Date:2010-04-24 17:34:29 (12 years 5 months ago)
Author:Lars C.
Commit:40ccfb2dbbfa8b89c7bef367fec2865ec4f17e14
Message:JZ4740 cache quicks

Files: arch/mips/include/asm/r4kcache.h (11 diffs)

Change Details

arch/mips/include/asm/r4kcache.h
1717#include <asm/cpu-features.h>
1818#include <asm/mipsmtregs.h>
1919
20#ifdef CONFIG_JZRISC
21
22#define K0_TO_K1() \
23do { \
24    unsigned long __k0_addr; \
25                        \
26    __asm__ __volatile__( \
27    "la %0, 1f\n\t" \
28    "or %0, %0, %1\n\t" \
29    "jr %0\n\t" \
30    "nop\n\t" \
31    "1: nop\n" \
32    : "=&r"(__k0_addr) \
33    : "r" (0x20000000) ); \
34} while(0)
35
36#define K1_TO_K0() \
37do { \
38    unsigned long __k0_addr; \
39    __asm__ __volatile__( \
40    "nop;nop;nop;nop;nop;nop;nop\n\t" \
41    "la %0, 1f\n\t" \
42    "jr %0\n\t" \
43    "nop\n\t" \
44    "1: nop\n" \
45    : "=&r" (__k0_addr)); \
46} while (0)
47
48#define INVALIDATE_BTB() \
49do { \
50    unsigned long tmp; \
51    __asm__ __volatile__( \
52    ".set mips32\n\t" \
53    "mfc0 %0, $16, 7\n\t" \
54    "nop\n\t" \
55    "ori %0, 2\n\t" \
56    "mtc0 %0, $16, 7\n\t" \
57    "nop\n\t" \
58    : "=&r" (tmp)); \
59} while (0)
60
61#define SYNC_WB() __asm__ __volatile__ ("sync")
62
63#else /* CONFIG_JZRISC */
64
65#define K0_TO_K1() do { } while (0)
66#define K1_TO_K0() do { } while (0)
67#define INVALIDATE_BTB() do { } while (0)
68#define SYNC_WB() do { } while (0)
69
70#endif /* CONFIG_JZRISC */
71
2072/*
2173 * This macro return a properly sign-extended address suitable as base address
2274 * for indexed cache operations. Two issues here:
...... 
144196{
145197    __iflush_prologue
146198    cache_op(Index_Invalidate_I, addr);
199    INVALIDATE_BTB();
147200    __iflush_epilogue
148201}
149202
...... 
151204{
152205    __dflush_prologue
153206    cache_op(Index_Writeback_Inv_D, addr);
207    SYNC_WB();
154208    __dflush_epilogue
155209}
156210
...... 
163217{
164218    __iflush_prologue
165219    cache_op(Hit_Invalidate_I, addr);
220    INVALIDATE_BTB();
166221    __iflush_epilogue
167222}
168223
...... 
170225{
171226    __dflush_prologue
172227    cache_op(Hit_Writeback_Inv_D, addr);
228    SYNC_WB();
173229    __dflush_epilogue
174230}
175231
...... 
177233{
178234    __dflush_prologue
179235    cache_op(Hit_Invalidate_D, addr);
236    SYNC_WB();
180237    __dflush_epilogue
181238}
182239
...... 
209266static inline void protected_flush_icache_line(unsigned long addr)
210267{
211268    protected_cache_op(Hit_Invalidate_I, addr);
269    INVALIDATE_BTB();
212270}
213271
214272/*
...... 
220278static inline void protected_writeback_dcache_line(unsigned long addr)
221279{
222280    protected_cache_op(Hit_Writeback_Inv_D, addr);
281    SYNC_WB();
223282}
224283
225284static inline void protected_writeback_scache_line(unsigned long addr)
...... 
396455__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
397456__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
398457__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
458#ifndef CONFIG_JZRISC
399459__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
400460__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
461#endif
401462__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
402463__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
403464__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
...... 
405466__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
406467
407468__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
469#ifndef CONFIG_JZRISC
408470__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
471#endif
409472__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
410473__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
411474__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
412475__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
413476
477#ifdef CONFIG_JZRISC
478
479static inline void blast_dcache32(void)
480{
481    unsigned long start = INDEX_BASE;
482    unsigned long end = start + current_cpu_data.dcache.waysize;
483    unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
484    unsigned long ws_end = current_cpu_data.dcache.ways <<
485                           current_cpu_data.dcache.waybit;
486    unsigned long ws, addr;
487
488    for (ws = 0; ws < ws_end; ws += ws_inc)
489        for (addr = start; addr < end; addr += 0x400)
490            cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
491
492    SYNC_WB();
493}
494
495static inline void blast_dcache32_page(unsigned long page)
496{
497    unsigned long start = page;
498    unsigned long end = page + PAGE_SIZE;
499
500    do {
501        cache32_unroll32(start,Hit_Writeback_Inv_D);
502        start += 0x400;
503    } while (start < end);
504
505    SYNC_WB();
506}
507
508static inline void blast_dcache32_page_indexed(unsigned long page)
509{
510    unsigned long indexmask = current_cpu_data.dcache.waysize - 1;
511    unsigned long start = INDEX_BASE + (page & indexmask);
512    unsigned long end = start + PAGE_SIZE;
513    unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
514    unsigned long ws_end = current_cpu_data.dcache.ways <<
515                           current_cpu_data.dcache.waybit;
516    unsigned long ws, addr;
517
518    for (ws = 0; ws < ws_end; ws += ws_inc)
519        for (addr = start; addr < end; addr += 0x400)
520            cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
521
522    SYNC_WB();
523}
524
525static inline void blast_icache32(void)
526{
527    unsigned long start = INDEX_BASE;
528    unsigned long end = start + current_cpu_data.icache.waysize;
529    unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
530    unsigned long ws_end = current_cpu_data.icache.ways <<
531                           current_cpu_data.icache.waybit;
532    unsigned long ws, addr;
533
534    K0_TO_K1();
535
536    for (ws = 0; ws < ws_end; ws += ws_inc)
537        for (addr = start; addr < end; addr += 0x400)
538            cache32_unroll32(addr|ws,Index_Invalidate_I);
539
540    INVALIDATE_BTB();
541
542    K1_TO_K0();
543}
544
545static inline void blast_icache32_page(unsigned long page)
546{
547    unsigned long start = page;
548    unsigned long end = page + PAGE_SIZE;
549
550    K0_TO_K1();
551
552    do {
553        cache32_unroll32(start,Hit_Invalidate_I);
554        start += 0x400;
555    } while (start < end);
556
557    INVALIDATE_BTB();
558
559    K1_TO_K0();
560}
561
562static inline void blast_icache32_page_indexed(unsigned long page)
563{
564    unsigned long indexmask = current_cpu_data.icache.waysize - 1;
565    unsigned long start = INDEX_BASE + (page & indexmask);
566    unsigned long end = start + PAGE_SIZE;
567    unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
568    unsigned long ws_end = current_cpu_data.icache.ways <<
569                           current_cpu_data.icache.waybit;
570    unsigned long ws, addr;
571
572    K0_TO_K1();
573
574    for (ws = 0; ws < ws_end; ws += ws_inc)
575        for (addr = start; addr < end; addr += 0x400)
576            cache32_unroll32(addr|ws,Index_Invalidate_I);
577
578    INVALIDATE_BTB();
579
580    K1_TO_K0();
581}
582
583#endif /* CONFIG_JZRISC */
584
414585/* build blast_xxx_range, protected_blast_xxx_range */
415586#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
416587static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
...... 
432603    __##pfx##flush_epilogue \
433604}
434605
606#ifndef CONFIG_JZRISC
435607__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
608#endif
436609__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
610#ifndef CONFIG_JZRISC
437611__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
438612__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
613#endif
439614__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
440615/* blast_inv_dcache_range */
441616__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
442617__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
443618
619#ifdef CONFIG_JZRISC
620
621static inline void protected_blast_dcache_range(unsigned long start,
622                        unsigned long end)
623{
624    unsigned long lsize = cpu_dcache_line_size();
625    unsigned long addr = start & ~(lsize - 1);
626    unsigned long aend = (end - 1) & ~(lsize - 1);
627
628    while (1) {
629        protected_cache_op(Hit_Writeback_Inv_D, addr);
630        if (addr == aend)
631            break;
632        addr += lsize;
633    }
634    SYNC_WB();
635}
636
637static inline void protected_blast_icache_range(unsigned long start,
638                        unsigned long end)
639{
640    unsigned long lsize = cpu_icache_line_size();
641    unsigned long addr = start & ~(lsize - 1);
642    unsigned long aend = (end - 1) & ~(lsize - 1);
643
644    K0_TO_K1();
645
646    while (1) {
647        protected_cache_op(Hit_Invalidate_I, addr);
648        if (addr == aend)
649            break;
650        addr += lsize;
651    }
652    INVALIDATE_BTB();
653
654    K1_TO_K0();
655}
656
657static inline void blast_dcache_range(unsigned long start,
658                      unsigned long end)
659{
660    unsigned long lsize = cpu_dcache_line_size();
661    unsigned long addr = start & ~(lsize - 1);
662    unsigned long aend = (end - 1) & ~(lsize - 1);
663
664    while (1) {
665        cache_op(Hit_Writeback_Inv_D, addr);
666        if (addr == aend)
667            break;
668        addr += lsize;
669    }
670    SYNC_WB();
671}
672
673#endif /* CONFIG_JZRISC */
674
444675#endif /* _ASM_R4KCACHE_H */

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