Date:2011-07-06 18:41:31 (9 years 2 months ago)
Author:Simon Guinot
Commit:659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5
Message:genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd)

This fixes a regression introduced by e59347a "arm: orion:
Use generic irq chip".

Depending on the device, interrupts acknowledgement is done by setting
or by clearing a dedicated register. Replace irq_gc_ack() with some
{set,clr}_bit variants allows to handle both cases.

Note that this patch affects the following SoCs: Davinci, Samsung and
Orion. Except for this last, the change is minor: irq_gc_ack() is just
renamed into irq_gc_ack_set_bit().

For the Orion SoCs, the edge GPIO interrupts support is currently
broken. irq_gc_ack() try to acknowledge a such interrupt by setting
the corresponding cause register bit. The Orion GPIO device expect the
opposite. To fix this issue, the irq_gc_ack_clr_bit() variant is used.

Tested on Network Space v2.

Reported-by: Joey Oravec <joravec@drewtech.com>
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Files: arch/arm/mach-davinci/irq.c (1 diff)
arch/arm/plat-orion/gpio.c (1 diff)
arch/arm/plat-s5p/irq-gpioint.c (1 diff)
arch/arm/plat-samsung/irq-uart.c (1 diff)
include/linux/irq.h (1 diff)
kernel/irq/generic-chip.c (2 diffs)

Change Details

arch/arm/mach-davinci/irq.c
5353
5454    gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
5555    ct = gc->chip_types;
56    ct->chip.irq_ack = irq_gc_ack;
56    ct->chip.irq_ack = irq_gc_ack_set_bit;
5757    ct->chip.irq_mask = irq_gc_mask_clr_bit;
5858    ct->chip.irq_unmask = irq_gc_mask_set_bit;
5959
arch/arm/plat-orion/gpio.c
432432    ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
433433    ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
434434    ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
435    ct->chip.irq_ack = irq_gc_ack;
435    ct->chip.irq_ack = irq_gc_ack_clr_bit;
436436    ct->chip.irq_mask = irq_gc_mask_clr_bit;
437437    ct->chip.irq_unmask = irq_gc_mask_set_bit;
438438    ct->chip.irq_set_type = gpio_irq_set_type;
arch/arm/plat-s5p/irq-gpioint.c
152152    if (!gc)
153153        return -ENOMEM;
154154    ct = gc->chip_types;
155    ct->chip.irq_ack = irq_gc_ack;
155    ct->chip.irq_ack = irq_gc_ack_set_bit;
156156    ct->chip.irq_mask = irq_gc_mask_set_bit;
157157    ct->chip.irq_unmask = irq_gc_mask_clr_bit;
158158    ct->chip.irq_set_type = s5p_gpioint_set_type,
arch/arm/plat-samsung/irq-uart.c
5555    gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
5656                    handle_level_irq);
5757    ct = gc->chip_types;
58    ct->chip.irq_ack = irq_gc_ack;
58    ct->chip.irq_ack = irq_gc_ack_set_bit;
5959    ct->chip.irq_mask = irq_gc_mask_set_bit;
6060    ct->chip.irq_unmask = irq_gc_mask_clr_bit;
6161    ct->regs.ack = S3C64XX_UINTP;
include/linux/irq.h
676676void irq_gc_mask_set_bit(struct irq_data *d);
677677void irq_gc_mask_clr_bit(struct irq_data *d);
678678void irq_gc_unmask_enable_reg(struct irq_data *d);
679void irq_gc_ack(struct irq_data *d);
679void irq_gc_ack_set_bit(struct irq_data *d);
680void irq_gc_ack_clr_bit(struct irq_data *d);
680681void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
681682void irq_gc_eoi(struct irq_data *d);
682683int irq_gc_set_wake(struct irq_data *d, unsigned int on);
kernel/irq/generic-chip.c
101101}
102102
103103/**
104 * irq_gc_ack - Ack pending interrupt
104 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
105105 * @d: irq_data
106106 */
107void irq_gc_ack(struct irq_data *d)
107void irq_gc_ack_set_bit(struct irq_data *d)
108108{
109109    struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
110110    u32 mask = 1 << (d->irq - gc->irq_base);
...... 
115115}
116116
117117/**
118 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
119 * @d: irq_data
120 */
121void irq_gc_ack_clr_bit(struct irq_data *d)
122{
123    struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
124    u32 mask = ~(1 << (d->irq - gc->irq_base));
125
126    irq_gc_lock(gc);
127    irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
128    irq_gc_unlock(gc);
129}
130
131/**
118132 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
119133 * @d: irq_data
120134 */

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