Date:2011-03-05 00:13:50 (9 years 3 months ago)
Author:Lars C.
Commit:6871d07cdbe9e01571c671687ac0a6189264901b
Message:Use common base address file for all sub-archs

The base addresses of the different IP-cores seem to be the same across SoCs, so
use a common header file for all of the SoCs.
Files: arch/mips/include/asm/mach-jz47xx/base.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/base.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4750/base.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4760/base.h (1 diff)
arch/mips/jz47xx/dma.c (2 diffs)
arch/mips/jz47xx/gpiov2.c (2 diffs)
arch/mips/jz47xx/irq.c (2 diffs)
arch/mips/jz47xx/jz4740/clock.c (2 diffs)
arch/mips/jz47xx/jz4740/platform.c (12 diffs)
arch/mips/jz47xx/jz4750/clock.c (2 diffs)
arch/mips/jz47xx/jz4750/platform.c (2 diffs)
arch/mips/jz47xx/jz4760/clock.c (2 diffs)
arch/mips/jz47xx/jz4760/platform.c (2 diffs)
arch/mips/jz47xx/prom.c (2 diffs)
arch/mips/jz47xx/reset.c (3 diffs)
arch/mips/jz47xx/timer.c (2 diffs)
arch/mips/jz47xx/timer.h (1 diff)

Change Details

arch/mips/include/asm/mach-jz47xx/base.h
1#ifndef __ASM_MACH_JZ4740_BASE_H__
2#define __ASM_MACH_JZ4740_BASE_H__
3
4#define JZ47XX_CPM_BASE_ADDR 0x10000000
5#define JZ47XX_INTC_BASE_ADDR 0x10001000
6#define JZ47XX_WDT_BASE_ADDR 0x10002000
7#define JZ47XX_TCU_BASE_ADDR 0x10002010
8#define JZ47XX_OST_BASE_ADDR 0x100020e0
9#define JZ47XX_RTC_BASE_ADDR 0x10003000
10#define JZ47XX_GPIO_BASE_ADDR 0x10010000
11#define JZ47XX_AIC_BASE_ADDR 0x10020000
12#define JZ47XX_MSC_BASE_ADDR 0x10021000
13#define JZ47XX_UART0_BASE_ADDR 0x10030000
14#define JZ47XX_UART1_BASE_ADDR 0x10031000
15#define JZ47XX_UART2_BASE_ADDR 0x10032000
16#define JZ47XX_UART3_BASE_ADDR 0x10033000
17#define JZ47XX_I2C_BASE_ADDR 0x10042000
18#define JZ47XX_SSI_BASE_ADDR 0x10043000
19#define JZ47XX_SADC_BASE_ADDR 0x10070000
20#define JZ47XX_EMC_BASE_ADDR 0x13010000
21#define JZ47XX_DMAC_BASE_ADDR 0x13020000
22#define JZ47XX_UHC_BASE_ADDR 0x13030000
23#define JZ47XX_UDC_BASE_ADDR 0x13040000
24#define JZ47XX_LCD_BASE_ADDR 0x13050000
25#define JZ47XX_SLCD_BASE_ADDR 0x13050000
26#define JZ47XX_CIM_BASE_ADDR 0x13060000
27#define JZ47XX_IPU_BASE_ADDR 0x13080000
28
29#endif
arch/mips/include/asm/mach-jz47xx/jz4740/base.h
1#ifndef __ASM_MACH_JZ4740_BASE_H__
2#define __ASM_MACH_JZ4740_BASE_H__
3
4#define JZ4740_CPM_BASE_ADDR 0x10000000
5#define JZ4740_INTC_BASE_ADDR 0x10001000
6#define JZ4740_WDT_BASE_ADDR 0x10002000
7#define JZ4740_TCU_BASE_ADDR 0x10002010
8#define JZ4740_RTC_BASE_ADDR 0x10003000
9#define JZ4740_GPIO_BASE_ADDR 0x10010000
10#define JZ4740_AIC_BASE_ADDR 0x10020000
11#define JZ4740_MSC_BASE_ADDR 0x10021000
12#define JZ4740_UART0_BASE_ADDR 0x10030000
13#define JZ4740_UART1_BASE_ADDR 0x10031000
14#define JZ4740_I2C_BASE_ADDR 0x10042000
15#define JZ4740_SSI_BASE_ADDR 0x10043000
16#define JZ4740_SADC_BASE_ADDR 0x10070000
17#define JZ4740_EMC_BASE_ADDR 0x13010000
18#define JZ4740_DMAC_BASE_ADDR 0x13020000
19#define JZ4740_UHC_BASE_ADDR 0x13030000
20#define JZ4740_UDC_BASE_ADDR 0x13040000
21#define JZ4740_LCD_BASE_ADDR 0x13050000
22#define JZ4740_SLCD_BASE_ADDR 0x13050000
23#define JZ4740_CIM_BASE_ADDR 0x13060000
24#define JZ4740_IPU_BASE_ADDR 0x13080000
25
26#endif
arch/mips/include/asm/mach-jz47xx/jz4750/base.h
1/*
2 * Copyright (C) 2011 Peter Zotov <whitequark@whitequark.org>
3 * JZ4750 base addresses
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4750_BASE_H__
17#define __ASM_MACH_JZ4750_BASE_H__
18
19#define JZ4750_CPM_BASE_ADDR 0x10000000
20#define JZ4750_INTC_BASE_ADDR 0x10001000
21#define JZ4750_WDT_BASE_ADDR 0x10002000
22#define JZ4750_TCU_BASE_ADDR 0x10002010
23#define JZ4750_RTC_BASE_ADDR 0x10003000
24#define JZ4750_GPIO_BASE_ADDR 0x10010000
25#define JZ4750_AIC_BASE_ADDR 0x10020000
26#define JZ4750_MSC_BASE_ADDR 0x10021000
27#define JZ4750_UART0_BASE_ADDR 0x10030000
28#define JZ4750_I2C_BASE_ADDR 0x10042000
29#define JZ4750_SSI_BASE_ADDR 0x10043000
30#define JZ4750_SADC_BASE_ADDR 0x10070000
31#define JZ4750_EMC_BASE_ADDR 0x13010000
32#define JZ4750_DMAC_BASE_ADDR 0x13020000
33#define JZ4750_UDC_BASE_ADDR 0x13040000
34#define JZ4750_LCD_BASE_ADDR 0x13050000
35#define JZ4750_SLCD_BASE_ADDR 0x13050000
36#define JZ4750_CIM_BASE_ADDR 0x13060000
37#define JZ4750_IPU_BASE_ADDR 0x13080000
38
39#endif
arch/mips/include/asm/mach-jz47xx/jz4760/base.h
1#ifndef __ASM_MACH_JZ4760_BASE_H__
2#define __ASM_MACH_JZ4760_BASE_H__
3
4#define JZ4740_CPM_BASE_ADDR 0x10000000
5#define JZ4740_INTC_BASE_ADDR 0x10001000
6#define JZ4740_WDT_BASE_ADDR 0x10002000
7#define JZ4740_TCU_BASE_ADDR 0x10002010
8#define JZ4740_RTC_BASE_ADDR 0x10003000
9#define JZ4740_GPIO_BASE_ADDR 0x10010000
10#define JZ4740_AIC_BASE_ADDR 0x10020000
11#define JZ4740_MSC_BASE_ADDR 0x10021000
12#define JZ4740_UART0_BASE_ADDR 0x10030000
13#define JZ4740_UART1_BASE_ADDR 0x10031000
14#define JZ4740_I2C_BASE_ADDR 0x10042000
15#define JZ4740_SSI_BASE_ADDR 0x10043000
16#define JZ4740_SADC_BASE_ADDR 0x10070000
17#define JZ4740_EMC_BASE_ADDR 0x13010000
18#define JZ4740_DMAC_BASE_ADDR 0x13020000
19#define JZ4740_UHC_BASE_ADDR 0x13030000
20#define JZ4740_UDC_BASE_ADDR 0x13040000
21#define JZ4740_LCD_BASE_ADDR 0x13050000
22#define JZ4740_SLCD_BASE_ADDR 0x13050000
23#define JZ4740_CIM_BASE_ADDR 0x13060000
24#define JZ4740_IPU_BASE_ADDR 0x13080000
25
26#endif
arch/mips/jz47xx/dma.c
2121#include <linux/dma-mapping.h>
2222
2323#include <jz4740/dma.h>
24#include <jz4740/base.h>
2524#include <jz4740/irq.h>
2625
26#include <asm/mach-jz47xx/base.h>
27
2728#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
2829#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
2930#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
...... 
274275{
275276    unsigned int ret;
276277
277    jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
278    jz4740_dma_base = ioremap(JZ47XX_DMAC_BASE_ADDR, 0x400);
278279
279280    if (!jz4740_dma_base)
280281        return -EBUSY;
arch/mips/jz47xx/gpiov2.c
2828#include <linux/debugfs.h>
2929#include <linux/seq_file.h>
3030
31#include <asm/mach-jz47xx/jz4740/base.h>
31#include <asm/mach-jz47xx/base.h>
3232#include <asm/mach-jz47xx/gpio.h>
3333
3434#define JZ_REG_GPIO_PIN 0x00
...... 
468468
469469    spin_lock_init(&chip->lock);
470470
471    chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
471    chip->base = ioremap(JZ47XX_GPIO_BASE_ADDR + (id * 0x100), 0x100);
472472    chip->gpio_chip.base = 32 * id;
473473
474474    chip->gpio_chip.set = jz_gpio_set_value;
arch/mips/jz47xx/irq.c
2929#include <asm/mipsregs.h>
3030#include <asm/irq_cpu.h>
3131
32#include <jz4740/base.h>
32#include <asm/mach-jz47xx/base.h>
3333
3434static unsigned int jz_intc_num_banks;
3535static void __iomem *jz_intc_base;
...... 
108108    int i;
109109    mips_cpu_irq_init();
110110
111    jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x20 * num_banks);
111    jz_intc_base = ioremap(JZ47XX_INTC_BASE_ADDR, 0x20 * num_banks);
112112    jz_intc_num_banks = num_banks;
113113
114114    /* Mask all irqs */
arch/mips/jz47xx/jz4740/clock.c
2323#include <linux/err.h>
2424
2525#include <jz4740/clock.h>
26#include <jz4740/base.h>
26#include <asm/mach-jz47xx/base.h>
2727
2828#include "../clock.h"
2929
...... 
893893{
894894    uint32_t val;
895895
896    jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
896    jz_clock_base = ioremap(JZ47XX_CPM_BASE_ADDR, 0x100);
897897    if (!jz_clock_base)
898898        return -EBUSY;
899899
arch/mips/jz47xx/jz4740/platform.c
2222#include <linux/dma-mapping.h>
2323
2424#include <jz4740/platform.h>
25#include <jz4740/base.h>
2625#include <jz4740/irq.h>
2726
27#include <asm/mach-jz47xx/base.h>
28
2829#include <linux/serial_core.h>
2930#include <linux/serial_8250.h>
3031
...... 
3435/* OHCI controller */
3536static struct resource jz4740_usb_ohci_resources[] = {
3637    {
37        .start = JZ4740_UHC_BASE_ADDR,
38        .end = JZ4740_UHC_BASE_ADDR + 0x1000 - 1,
38        .start = JZ47XX_UHC_BASE_ADDR,
39        .end = JZ47XX_UHC_BASE_ADDR + 0x1000 - 1,
3940        .flags = IORESOURCE_MEM,
4041    },
4142    {
...... 
5960/* UDC (USB gadget controller) */
6061static struct resource jz4740_usb_gdt_resources[] = {
6162    {
62        .start = JZ4740_UDC_BASE_ADDR,
63        .end = JZ4740_UDC_BASE_ADDR + 0x1000 - 1,
63        .start = JZ47XX_UDC_BASE_ADDR,
64        .end = JZ47XX_UDC_BASE_ADDR + 0x1000 - 1,
6465        .flags = IORESOURCE_MEM,
6566    },
6667    {
...... 
8485/* MMC/SD controller */
8586static struct resource jz4740_mmc_resources[] = {
8687    {
87        .start = JZ4740_MSC_BASE_ADDR,
88        .end = JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
88        .start = JZ47XX_MSC_BASE_ADDR,
89        .end = JZ47XX_MSC_BASE_ADDR + 0x1000 - 1,
8990        .flags = IORESOURCE_MEM,
9091    },
9192    {
...... 
109110/* RTC controller */
110111static struct resource jz4740_rtc_resources[] = {
111112    {
112        .start = JZ4740_RTC_BASE_ADDR,
113        .end = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
113        .start = JZ47XX_RTC_BASE_ADDR,
114        .end = JZ47XX_RTC_BASE_ADDR + 0x38 - 1,
114115        .flags = IORESOURCE_MEM,
115116    },
116117    {
...... 
130131/* I2C controller */
131132static struct resource jz4740_i2c_resources[] = {
132133    {
133        .start = JZ4740_I2C_BASE_ADDR,
134        .end = JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
134        .start = JZ47XX_I2C_BASE_ADDR,
135        .end = JZ47XX_I2C_BASE_ADDR + 0x1000 - 1,
135136        .flags = IORESOURCE_MEM,
136137    },
137138    {
...... 
152153static struct resource jz4740_nand_resources[] = {
153154    {
154155        .name = "mmio",
155        .start = JZ4740_EMC_BASE_ADDR,
156        .end = JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
156        .start = JZ47XX_EMC_BASE_ADDR,
157        .end = JZ47XX_EMC_BASE_ADDR + 0x1000 - 1,
157158        .flags = IORESOURCE_MEM,
158159    },
159160    {
...... 
173174/* LCD controller */
174175static struct resource jz4740_framebuffer_resources[] = {
175176    {
176        .start = JZ4740_LCD_BASE_ADDR,
177        .end = JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
177        .start = JZ47XX_LCD_BASE_ADDR,
178        .end = JZ47XX_LCD_BASE_ADDR + 0x1000 - 1,
178179        .flags = IORESOURCE_MEM,
179180    },
180181};
...... 
193194/* I2S controller */
194195static struct resource jz4740_i2s_resources[] = {
195196    {
196        .start = JZ4740_AIC_BASE_ADDR,
197        .end = JZ4740_AIC_BASE_ADDR + 0x38 - 1,
197        .start = JZ47XX_AIC_BASE_ADDR,
198        .end = JZ47XX_AIC_BASE_ADDR + 0x38 - 1,
198199        .flags = IORESOURCE_MEM,
199200    },
200201};
...... 
215216/* Codec */
216217static struct resource jz4740_codec_resources[] = {
217218    {
218        .start = JZ4740_AIC_BASE_ADDR + 0x80,
219        .end = JZ4740_AIC_BASE_ADDR + 0x88 - 1,
219        .start = JZ47XX_AIC_BASE_ADDR + 0x80,
220        .end = JZ47XX_AIC_BASE_ADDR + 0x88 - 1,
220221        .flags = IORESOURCE_MEM,
221222    },
222223};
...... 
231232/* ADC controller */
232233static struct resource jz4740_adc_resources[] = {
233234    {
234        .start = JZ4740_SADC_BASE_ADDR,
235        .end = JZ4740_SADC_BASE_ADDR + 0x30,
235        .start = JZ47XX_SADC_BASE_ADDR,
236        .end = JZ47XX_SADC_BASE_ADDR + 0x30,
236237        .flags = IORESOURCE_MEM,
237238    },
238239    {
...... 
262263        .regshift = 2, \
263264        .serial_out = jz4740_serial_out, \
264265        .type = PORT_16550, \
265        .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
266        .mapbase = JZ47XX_UART ## _id ## _BASE_ADDR, \
266267        .irq = JZ4740_IRQ_UART ## _id, \
267268    }
268269
arch/mips/jz47xx/jz4750/clock.c
2323#include <linux/err.h>
2424
2525#include <jz4740/clock.h>
26#include <jz4740/base.h>
26
27#include <asm/mach-jz47xx/base.h>
2728
2829#include "../clock.h"
2930
...... 
893894{
894895    uint32_t val;
895896
896    jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
897    jz_clock_base = ioremap(JZ47XX_CPM_BASE_ADDR, 0x100);
897898    if (!jz_clock_base)
898899        return -EBUSY;
899900
arch/mips/jz47xx/jz4750/platform.c
2222#include <linux/dma-mapping.h>
2323
2424#include <jz4750/platform.h>
25#include <jz4750/base.h>
2625#include <jz4750/irq.h>
2726
27#include <asm/mach-jz47xx/base.h>
28
2829#include <linux/serial_core.h>
2930#include <linux/serial_8250.h>
3031
...... 
3940        .regshift = 2, \
4041        .serial_out = jz4740_serial_out, \
4142        .type = PORT_16550, \
42        .mapbase = JZ4750_UART ## _id ## _BASE_ADDR, \
43        .mapbase = JZ47XX_UART ## _id ## _BASE_ADDR, \
4344        .irq = JZ4750_IRQ_UART ## _id, \
4445    }
4546
arch/mips/jz47xx/jz4760/clock.c
2323#include <linux/err.h>
2424
2525#include <jz4740/clock.h>
26#include <jz4740/base.h>
26
27#include <asm/mach-jz47xx/base.h>
2728
2829#include "../clock.h"
2930
...... 
893894{
894895    uint32_t val;
895896
896    jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
897    jz_clock_base = ioremap(JZ47XX_CPM_BASE_ADDR, 0x100);
897898    if (!jz_clock_base)
898899        return -EBUSY;
899900
arch/mips/jz47xx/jz4760/platform.c
2222#include <linux/dma-mapping.h>
2323
2424#include <jz4760/platform.h>
25#include <jz4760/base.h>
2625#include <jz4760/irq.h>
2726
27#include <asm/mach-jz47xx/base.h>
28
2829#include <linux/serial_core.h>
2930#include <linux/serial_8250.h>
3031
...... 
3940        .regshift = 2, \
4041        .serial_out = jz4740_serial_out, \
4142        .type = PORT_16550, \
42        .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
43        .mapbase = JZ47XX_UART ## _id ## _BASE_ADDR, \
4344        .irq = JZ4760_IRQ_UART ## _id, \
4445    }
4546
arch/mips/jz47xx/prom.c
2121#include <linux/serial_reg.h>
2222
2323#include <asm/bootinfo.h>
24#include <jz4740/base.h>
24#include <asm/mach-jz47xx/base.h>
2525
2626static __init void jz4740_init_cmdline(int argc, char *argv[])
2727{
...... 
5454{
5555}
5656
57#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
57#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ47XX_UART0_BASE_ADDR + (_reg << 2)))
5858
5959void prom_putchar(char c)
6060{
arch/mips/jz47xx/reset.c
1818
1919#include <asm/reboot.h>
2020
21#include <jz4740/base.h>
2221#include <jz4740/timer.h>
2322
23#include <asm/mach-jz47xx/base.h>
24
2425static void jz4740_halt(void)
2526{
2627    while (1) {
...... 
3940
4041static void jz4740_restart(char *command)
4142{
42    void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f);
43    void __iomem *wdt_base = ioremap(JZ47XX_WDT_BASE_ADDR, 0x0f);
4344
4445    jz4740_timer_enable_watchdog();
4546
...... 
6061
6162static void jz4740_power_off(void)
6263{
63    void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
64    void __iomem *rtc_base = ioremap(JZ47XX_RTC_BASE_ADDR, 0x24);
6465    uint32_t ctrl;
6566
6667    do {
arch/mips/jz47xx/timer.c
1919
2020#include "timer.h"
2121
22#include <jz4740/base.h>
22#include <asm/mach-jz47xx/base.h>
2323
2424void __iomem *jz4740_timer_base;
2525
...... 
3535
3636void __init jz4740_timer_init(void)
3737{
38    jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
38    jz4740_timer_base = ioremap(JZ47XX_TCU_BASE_ADDR, 0xd0);
3939
4040    if (!jz4740_timer_base)
4141        panic("Failed to ioremap timer registers");
arch/mips/jz47xx/timer.h
7373
7474static inline bool jz4740_timer_is_enabled(unsigned int timer)
7575{
76    return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
76    return readw(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
7777}
7878
7979static inline void jz4740_timer_enable(unsigned int timer)
8080{
81    writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
81    writew(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
8282}
8383
8484static inline void jz4740_timer_disable(unsigned int timer)
8585{
86    writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
86    writew(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
8787}
8888
8989

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