Date: | 2011-03-04 18:28:36 (13 years 23 days ago) |
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Author: | Lars C. |
Commit: | 7437e228a82b3fcf28d79e79c3c2fa2d8c9977fe |
Message: | Add support for more then one irq bank and move initialization into
sub-archs. |
Files: |
arch/mips/include/asm/mach-jz47xx/irq.h (1 diff) arch/mips/jz47xx/irq.c (5 diffs) arch/mips/jz47xx/jz4740/Makefile (1 diff) arch/mips/jz47xx/jz4740/irq.c (1 diff) |
Change Details
arch/mips/include/asm/mach-jz47xx/irq.h | ||
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22 | 22 | /* 1st-level interrupts */ |
23 | 23 | #define JZ47XX_IRQ(x) (JZ47XX_IRQ_BASE + (x)) |
24 | 24 | |
25 | extern void __init jz47xx_intc_init(unsigned int num_banks); | |
26 | ||
25 | 27 | #endif |
arch/mips/jz47xx/irq.c | ||
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31 | 31 | |
32 | 32 | #include <jz4740/base.h> |
33 | 33 | |
34 | static unsigned int jz_intc_num_banks; | |
34 | 35 | static void __iomem *jz_intc_base; |
35 | static uint32_t jz_intc_wakeup; | |
36 | static uint32_t jz_intc_saved; | |
36 | static uint32_t jz_intc_wakeup[2]; | |
37 | static uint32_t jz_intc_saved[2]; | |
37 | 38 | |
38 | 39 | #define JZ_REG_INTC_STATUS 0x00 |
39 | 40 | #define JZ_REG_INTC_MASK 0x04 |
... | ... | |
41 | 42 | #define JZ_REG_INTC_CLEAR_MASK 0x0c |
42 | 43 | #define JZ_REG_INTC_PENDING 0x10 |
43 | 44 | |
44 | #define IRQ_BIT(x) BIT((x) - JZ47XX_IRQ_BASE) | |
45 | #define IRQ_BIT(x) BIT(((x) - JZ47XX_IRQ_BASE) & 0x1f) | |
45 | 46 | |
46 | static inline unsigned long intc_irq_bit(struct irq_data *data) | |
47 | static inline unsigned int intc_irq_bit(struct irq_data *data) | |
47 | 48 | { |
48 | return (unsigned long)irq_data_get_irq_chip_data(data); | |
49 | return (unsigned int)irq_data_get_irq_chip_data(data); | |
49 | 50 | } |
50 | 51 | |
51 | 52 | static void intc_irq_unmask(struct irq_data *data) |
52 | 53 | { |
53 | writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); | |
54 | unsigned int offset = (data->irq - JZ47XX_IRQ_BASE) & ~0x1f; | |
55 | ||
56 | writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK + offset); | |
54 | 57 | } |
55 | 58 | |
56 | 59 | static void intc_irq_mask(struct irq_data *data) |
57 | 60 | { |
58 | writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK); | |
61 | unsigned int offset = (data->irq - JZ47XX_IRQ_BASE) & ~0x1f; | |
62 | writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK + offset); | |
59 | 63 | } |
60 | 64 | |
61 | 65 | static int intc_irq_set_wake(struct irq_data *data, unsigned int on) |
62 | 66 | { |
67 | unsigned int bank = (data->irq - JZ47XX_IRQ_BASE) >> 5; | |
63 | 68 | if (on) |
64 | jz_intc_wakeup |= intc_irq_bit(data); | |
69 | jz_intc_wakeup[bank] |= intc_irq_bit(data); | |
65 | 70 | else |
66 | jz_intc_wakeup &= ~intc_irq_bit(data); | |
71 | jz_intc_wakeup[bank] &= ~intc_irq_bit(data); | |
67 | 72 | |
68 | 73 | return 0; |
69 | 74 | } |
... | ... | |
79 | 84 | static irqreturn_t jz4740_cascade(int irq, void *data) |
80 | 85 | { |
81 | 86 | uint32_t irq_reg; |
87 | unsigned int i; | |
82 | 88 | |
83 | irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING); | |
89 | for (i = 0; i < jz_intc_num_banks; ++i) { | |
90 | irq_reg = readl(jz_intc_base + i * 0x20 + JZ_REG_INTC_PENDING); | |
84 | 91 | |
85 | if (irq_reg) | |
86 | generic_handle_irq(__fls(irq_reg) + JZ47XX_IRQ_BASE); | |
92 | if (irq_reg) { | |
93 | generic_handle_irq(__fls(irq_reg) + JZ47XX_IRQ_BASE + i * 0x20); | |
94 | break; | |
95 | } | |
96 | } | |
87 | 97 | |
88 | 98 | return IRQ_HANDLED; |
89 | 99 | } |
... | ... | |
93 | 103 | .name = "JZ4740 cascade interrupt", |
94 | 104 | }; |
95 | 105 | |
96 | void __init arch_init_irq(void) | |
106 | void __init jz47xx_intc_init(unsigned int num_banks) | |
97 | 107 | { |
98 | 108 | int i; |
99 | 109 | mips_cpu_irq_init(); |
100 | 110 | |
101 | jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); | |
111 | jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x20 * num_banks); | |
112 | jz_intc_num_banks = num_banks; | |
102 | 113 | |
103 | 114 | /* Mask all irqs */ |
104 | writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); | |
115 | for (i = 0; i < num_banks; ++i) { | |
116 | writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK + i * 0x20); | |
117 | } | |
105 | 118 | |
106 | for (i = JZ47XX_IRQ_BASE; i < JZ47XX_IRQ_BASE + 32; i++) { | |
119 | for (i = JZ47XX_IRQ_BASE; i < JZ47XX_IRQ_BASE + 32 * num_banks; i++) { | |
107 | 120 | set_irq_chip_data(i, (void *)IRQ_BIT(i)); |
108 | 121 | set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); |
109 | 122 | } |
... | ... | |
124 | 137 | |
125 | 138 | void jz4740_intc_suspend(void) |
126 | 139 | { |
127 | jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK); | |
128 | writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK); | |
129 | writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK); | |
140 | unsigned int offset; | |
141 | unsigned int i; | |
142 | ||
143 | for (i = 0; i < jz_intc_num_banks; ++i) { | |
144 | offset = i * 0x20; | |
145 | ||
146 | jz_intc_saved[i] = readl(jz_intc_base + JZ_REG_INTC_MASK + offset); | |
147 | writel(~jz_intc_wakeup[i], jz_intc_base + JZ_REG_INTC_SET_MASK + offset); | |
148 | writel(jz_intc_wakeup[i], jz_intc_base + JZ_REG_INTC_CLEAR_MASK + offset); | |
149 | } | |
130 | 150 | } |
131 | 151 | |
132 | 152 | void jz4740_intc_resume(void) |
133 | 153 | { |
134 | writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK); | |
135 | writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK); | |
154 | unsigned int offset; | |
155 | unsigned int i; | |
156 | ||
157 | for (i = 0; i < jz_intc_num_banks; ++i) { | |
158 | offset = i * 0x20; | |
159 | ||
160 | writel(~jz_intc_saved[i], jz_intc_base + JZ_REG_INTC_CLEAR_MASK + offset); | |
161 | writel(jz_intc_saved[i], jz_intc_base + JZ_REG_INTC_SET_MASK + offset); | |
162 | } | |
136 | 163 | } |
137 | 164 | |
138 | 165 | #ifdef CONFIG_DEBUG_FS |
arch/mips/jz47xx/jz4740/Makefile | ||
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1 | 1 | |
2 | obj-y += clock.o platform.o time.o gpio.o | |
2 | obj-y += clock.o platform.o time.o gpio.o irq.o | |
3 | 3 | |
4 | 4 | obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o |
5 | 5 | obj-$(CONFIG_JZ4740_N516) += board-n516.o board-n516-display.o |
arch/mips/jz47xx/jz4740/irq.c | ||
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1 | #include <linux/init.h> | |
2 | #include <asm/mach-jz47xx/irq.h> | |
3 | ||
4 | void __init arch_init_irq(void) | |
5 | { | |
6 | jz47xx_intc_init(1); | |
7 | } |
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
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