Date:2011-06-19 10:49:19 (9 years 3 months ago)
Author:Maarten ter Huurne
Commit:821be157b6c88c78d08b1416bd6ae48a6107e715
Message:MIPS: JZ4740: cpufreq: Set CE bit after PLL freq change.

This fixes I/O errors when reading from SD card.
I guess this is a hardware quirk: I even tried writing the current value
with the same routine and that had no effect, so it is not some side effect
that avoids the I/O errors, it is actually the CE bit that matters.
Files: arch/mips/jz4740/clock.c (1 diff)

Change Details

arch/mips/jz4740/clock.c
366366        :
367367        : "r" (jz_clock_base + JZ_REG_CLOCK_PLL), "r" (plcr1));
368368
369    /* MtH: For some reason the MSC will have problems if this flag is not
370            restored, even though the MSC is supposedly the only divider
371            that is not affected by this flag. */
372    jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_CHANGE_ENABLE);
373
369374    return 0;
370375}
371376

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