Date:2010-06-22 12:05:16 (13 years 6 months ago)
Author:Lars C.
Commit:902fdf0a9843b0f4c7c4e93ad43a2706c19b2ff0
Message:jz4740: clock: Fix setting parents for spi and i2s clock

Some clocks are later accessed by index. Make sure the index stays correct.
Files: arch/mips/jz4740/clock.c (5 diffs)

Change Details

arch/mips/jz4740/clock.c
598598};
599599
600600static struct divided_clk jz4740_clock_divided_clks[] = {
601    {
602        .clk = {
603            .name = "lcd_pclk",
604            .parent = &jz_clk_pll_half,
605            .gate_bit = JZ4740_CLK_NOT_GATED,
606            .ops = &jz_clk_divided_ops,
607        },
608        .reg = JZ_REG_CLOCK_LCD,
609        .mask = JZ_CLOCK_LCD_DIV_MASK,
610    },
611    {
601    [0] = {
612602        .clk = {
613603            .name = "i2s",
614604            .parent = &jz_clk_ext.clk,
...... 
618608        .reg = JZ_REG_CLOCK_I2S,
619609        .mask = JZ_CLOCK_I2S_DIV_MASK,
620610    },
621    {
611    [1] = {
622612        .clk = {
623613            .name = "spi",
624614            .parent = &jz_clk_ext.clk,
...... 
628618        .reg = JZ_REG_CLOCK_SPI,
629619        .mask = JZ_CLOCK_SPI_DIV_MASK,
630620    },
631    {
621    [2] = {
622        .clk = {
623            .name = "lcd_pclk",
624            .parent = &jz_clk_pll_half,
625            .gate_bit = JZ4740_CLK_NOT_GATED,
626            .ops = &jz_clk_divided_ops,
627        },
628        .reg = JZ_REG_CLOCK_LCD,
629        .mask = JZ_CLOCK_LCD_DIV_MASK,
630    },
631    [3] = {
632632        .clk = {
633633            .name = "mmc",
634634            .parent = &jz_clk_pll_half,
...... 
638638        .reg = JZ_REG_CLOCK_MMC,
639639        .mask = JZ_CLOCK_MMC_DIV_MASK,
640640    },
641    {
641    [4] = {
642642        .clk = {
643643            .name = "uhc",
644644            .parent = &jz_clk_pll_half,
...... 
666666};
667667
668668static struct clk jz4740_clock_simple_clks[] = {
669    {
669    [0] = {
670670        .name = "udc",
671671        .parent = &jz_clk_ext.clk,
672672        .ops = &jz_clk_udc_ops,
673673    },
674    {
674    [1] = {
675675        .name = "uart0",
676676        .parent = &jz_clk_ext.clk,
677677        .gate_bit = JZ_CLOCK_GATE_UART0,
678678        .ops = &jz_clk_simple_ops,
679679    },
680    {
680    [2] = {
681681        .name = "uart1",
682682        .parent = &jz_clk_ext.clk,
683683        .gate_bit = JZ_CLOCK_GATE_UART1,
684684        .ops = &jz_clk_simple_ops,
685685    },
686    {
686    [3] = {
687687        .name = "dma",
688688        .parent = &jz_clk_high_speed_peripheral.clk,
689689        .gate_bit = JZ_CLOCK_GATE_UART0,
690690        .ops = &jz_clk_simple_ops,
691691    },
692    {
692    [4] = {
693693        .name = "ipu",
694694        .parent = &jz_clk_high_speed_peripheral.clk,
695695        .gate_bit = JZ_CLOCK_GATE_IPU,
696696        .ops = &jz_clk_simple_ops,
697697    },
698    {
698    [5] = {
699699        .name = "adc",
700700        .parent = &jz_clk_ext.clk,
701701        .gate_bit = JZ_CLOCK_GATE_ADC,
702702        .ops = &jz_clk_simple_ops,
703703    },
704    {
704    [6] = {
705705        .name = "i2c",
706706        .parent = &jz_clk_ext.clk,
707707        .gate_bit = JZ_CLOCK_GATE_I2C,
708708        .ops = &jz_clk_simple_ops,
709709    },
710    {
710    [7] = {
711711        .name = "aic",
712712        .parent = &jz_clk_ext.clk,
713713        .gate_bit = JZ_CLOCK_GATE_AIC,

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