Date:2011-03-25 14:41:31 (3 years 8 months ago)
Author:Lars C.
Commit:9a83f481a49cf9337a0aaed749c631572dddb950
Message:stash

Files: arch/mips/Kconfig (1 diff)
arch/mips/boot/compressed/Makefile (1 diff)
arch/mips/boot/compressed/uart-16550.c (1 diff)
arch/mips/jz47xx/dma.c (1 diff)
arch/mips/jz47xx/jz4760/board-lepus.c (2 diffs)
drivers/input/touchscreen/jz4740-ts.c (9 diffs)
drivers/mfd/Kconfig (1 diff)
drivers/mfd/jz4740-adc.c (3 diffs)
drivers/mtd/nand/Kconfig (1 diff)
drivers/mtd/nand/jz4750_nand.c (4 diffs)
drivers/video/jz4740_fb.c (4 diffs)

Change Details

arch/mips/Kconfig
211211    select HAVE_PWM
212212    select HAVE_CLK
213213    select CLKDEV_LOOKUP
214    select SYS_SUPPORTS_ZBOOT_UART16550
214215
215216config LASAT
216217    bool "LASAT Networks platforms"
arch/mips/boot/compressed/Makefile
5858# Calculate the load address of the compressed kernel image
5959hostprogs-y := calc_vmlinuz_load_addr
6060
61VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
62        $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
61#VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
62# $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
63VMLINUZ_LOAD_ADDRESS:=0x80600000
64
6365
6466vmlinuzobjs-y += $(obj)/piggy.o
6567
arch/mips/boot/compressed/uart-16550.c
1818#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
1919#endif
2020
21#ifdef CONFIG_MACH_JZ4760
22#define UART1_BASE 0xB0031000
23#define PORT(offset) (UART1_BASE + (4 * offset))
24#endif
25
2126#ifndef PORT
2227#error please define the serial port address for your own machine
2328#endif
arch/mips/jz47xx/dma.c
289289
290290    return ret;
291291}
292arch_initcall(jz4740_dma_init);
arch/mips/jz47xx/jz4760/board-lepus.c
169169    .num_modes = ARRAY_SIZE(lepus_video_modes),
170170    .modes = lepus_video_modes,
171171    .bpp = 24,
172    .lcd_type = JZ_LCD_TYPE_GENERIC_24_BIT,
173    .pixclk_falling_edge = 1,
172    .lcd_type = JZ_LCD_TYPE_GENERIC_18_BIT,
174173
175174    .gpio_reset = JZ_GPIO_PORTF(10),
176175    .reset_active_low = 1,
...... 
214213    for (i = 20; i < 30; ++i)
215214        jz_gpio_disable_pullup(JZ_GPIO_PORTE(i));
216215
216    for (i = 0; i < 28; ++i)
217        jz_gpio_disable_pullup(JZ_GPIO_PORTC(i));
218
219
220    gpio_direction_output(JZ_GPIO_PORTB(31), 1);
221
217222    if (lepus_init_platform_devices())
218223        panic("Failed to initalize platform devices\n");
219224
drivers/input/touchscreen/jz4740-ts.c
11/*
22 * Touchscreen driver for Ingenic JZ SoCs.
33 *
4 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * Copyright (C) 2010-2011, Lars-Peter Clausen <lars@metafoo.de>
55 *
66 * This program is free software; you can redistribute it and/or modify
77 * it under the terms of the GNU General Public License version 2 as
...... 
2121#include <linux/bitops.h>
2222#include <linux/jz4740-adc.h>
2323
24#define JZ_REG_TS_SAME 0x00
25#define JZ_REG_TS_WAIT 0x04
26#define JZ_REG_TS_DATA 0x08
27
2428struct jz4740_ts {
2529    struct platform_device *pdev;
2630
...... 
2832    void __iomem *base;
2933
3034    int irq_penup;
31    int irq_pendown;
3235    int irq_data_ready;
3336
3437    struct mfd_cell *cell;
3538    struct input_dev *input;
3639
3740    bool is_open;
41
42    struct completion penup_completion;
43    unsigned int penup_count;
3844};
3945
4046static irqreturn_t jz4740_ts_data_ready_irq_handler(int irq, void *devid)
4147{
4248    struct jz4740_ts *jz4740_ts = devid;
4349    uint32_t data;
44    unsigned long x, y, z1, z2, pressure;
50    unsigned long pressure, x, y, z1, z2;
4551
46    data = readl(jz4740_ts->base + 0x08);
52    data = readl(jz4740_ts->base + JZ_REG_TS_DATA);
4753    x = data & 0xfff;
4854    y = (data >> 16) & 0xfff;
4955
50    data = readl(jz4740_ts->base + 0x08);
56    data = readl(jz4740_ts->base + JZ_REG_TS_DATA);
5157    z1 = data & 0xfff;
5258    z2 = (data >> 16) & 0xfff;
5359    if (z1 == 0) {
...... 
5662        pressure = 0;
5763    } else {
5864        if (data & 0x8000)
59            pressure = (((480UL * x * z2) / z1) - 480UL * x) / 4096UL;
65            pressure = ((((480UL * z2) / z1) * x) - 480UL * x) / 4096UL;
6066        else
61            pressure = (((272UL * y * z2) / z1) - 272UL * y) / 4096UL;
67            pressure = ((((272UL * z2) / z1) * y) - 272UL * y) / 4096UL;
6268        if (pressure >= 4096UL)
6369            pressure = 4095UL;
6470        pressure = 4095UL - pressure;
6571    }
6672
67    input_report_abs(jz4740_ts->input, ABS_X, y);
68    input_report_abs(jz4740_ts->input, ABS_Y, 4095 - x);
73    input_report_abs(jz4740_ts->input, ABS_X, x);
74    input_report_abs(jz4740_ts->input, ABS_Y, y);
6975    input_report_abs(jz4740_ts->input, ABS_PRESSURE, pressure);
7076    input_report_key(jz4740_ts->input, BTN_TOUCH, 1);
7177    input_sync(jz4740_ts->input);
7278
79    jz4740_ts->penup_count = 0;
80    complete(&jz4740_ts->penup_completion);
81
7382    return IRQ_HANDLED;
7483}
7584
76static irqreturn_t jz4740_ts_pen_irq_handler(int irq, void *devid)
85static irqreturn_t jz4740_ts_pen_up_irq_handler(int irq, void *devid)
7786{
7887    struct jz4740_ts *jz4740_ts = devid;
79    int is_pressed;
8088
81    if (irq == jz4740_ts->irq_penup) {
82        enable_irq(jz4740_ts->irq_pendown);
83        is_pressed = 0;
84    } else {
85        enable_irq(jz4740_ts->irq_penup);
86        is_pressed = 1;
87    }
88    disable_irq_nosync(irq);
89    /* Filter out sparse penup IRQs */
90    if (++jz4740_ts->penup_count < 5)
91        return IRQ_HANDLED;
8992
90    printk("pen irq: %d\n", irq);
91    input_report_key(jz4740_ts->input, BTN_TOUCH, is_pressed);
92    if (is_pressed == 0)
93        input_report_abs(jz4740_ts->input, ABS_PRESSURE, 0);
93    input_report_key(jz4740_ts->input, BTN_TOUCH, 0);
94    input_report_abs(jz4740_ts->input, ABS_PRESSURE, 0);
9495    input_sync(jz4740_ts->input);
9596
97    INIT_COMPLETION(jz4740_ts->penup_completion);
98    wait_for_completion(&jz4740_ts->penup_completion);
99
96100    return IRQ_HANDLED;
97101}
98102
...... 
129133    jz4740_ts->pdev = pdev;
130134    jz4740_ts->cell = pdev->dev.platform_data;
131135
136    init_completion(&jz4740_ts->penup_completion);
137
132138    jz4740_ts->irq_data_ready = platform_get_irq(pdev, 0);
133139    if (jz4740_ts->irq_data_ready < 0) {
134140        ret = jz4740_ts->irq_data_ready;
...... 
143149        goto err_free;
144150    }
145151
146    jz4740_ts->irq_pendown = platform_get_irq(pdev, 2);
147    if (jz4740_ts->irq_pendown < 0) {
148        ret = jz4740_ts->irq_pendown;
149        dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
150        goto err_free;
151    }
152
153152    jz4740_ts->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
154153    if (!jz4740_ts->mem) {
155154        ret = -ENOENT;
...... 
183182    input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
184183    __set_bit(BTN_TOUCH, input->keybit);
185184
186    input_set_abs_params(input, ABS_X, 150, 3920, 0, 0);
187    input_set_abs_params(input, ABS_Y, 270, 3700, 0, 0);
185    input_set_abs_params(input, ABS_X, 0, 4096, 0, 0);
186    input_set_abs_params(input, ABS_Y, 0, 4096, 0, 0);
188187    input_set_abs_params(input, ABS_PRESSURE, 0, 4096, 0, 0);
189188
190189    input->name = pdev->name;
...... 
211210        dev_err(&pdev->dev, "Failed to request irq %d\n", ret);
212211        goto err_input_unregister_device;
213212    }
214    ret = request_irq(jz4740_ts->irq_penup, jz4740_ts_pen_irq_handler, 0, pdev->name,
213    ret = request_threaded_irq(jz4740_ts->irq_penup, NULL,
214            jz4740_ts_pen_up_irq_handler, IRQF_ONESHOT, pdev->name,
215215            jz4740_ts);
216216    if (ret) {
217217        dev_err(&pdev->dev, "Failed to request irq %d\n", ret);
218218        goto err_free_irq_data_ready;
219219    }
220    disable_irq(jz4740_ts->irq_penup);
221    ret = request_irq(jz4740_ts->irq_pendown, jz4740_ts_pen_irq_handler, 0, pdev->name,
222            jz4740_ts);
223    if (ret) {
224        dev_err(&pdev->dev, "Failed to request irq %d\n", ret);
225        goto err_free_irq_penup;
226    }
227220    platform_set_drvdata(pdev, jz4740_ts);
228221
229222    jz4740_adc_set_config(pdev->dev.parent,
230        JZ_ADC_CONFIG_EX_IN | JZ_ADC_CONFIG_XYZ_OFFSET(2) | JZ_ADC_CONFIG_DNUM(7),
231        JZ_ADC_CONFIG_EX_IN | JZ_ADC_CONFIG_XYZ_MASK | JZ_ADC_CONFIG_DNUM_MASK);
223        JZ_ADC_CONFIG_SPZZ | JZ_ADC_CONFIG_XYZ_OFFSET(2) | JZ_ADC_CONFIG_DNUM(7)
224        | (5 << 10),
225        JZ_ADC_CONFIG_SPZZ | JZ_ADC_CONFIG_XYZ_MASK | JZ_ADC_CONFIG_DNUM_MASK |
226        (0x7 << 10));
232227
233
234    writel(0x15e, jz4740_ts->base);
235    writel(0x32, jz4740_ts->base + 0x04);
228    writel(0x1, jz4740_ts->base + JZ_REG_TS_SAME);
229    writel(500, jz4740_ts->base + JZ_REG_TS_WAIT);
236230
237231    return 0;
238232
...... 
256250{
257251    struct jz4740_ts *jz4740_ts = platform_get_drvdata(pdev);
258252
259
260    free_irq(jz4740_ts->irq_pendown, jz4740_ts);
261253    free_irq(jz4740_ts->irq_penup, jz4740_ts);
262254    free_irq(jz4740_ts->irq_data_ready, jz4740_ts);
263255
drivers/mfd/Kconfig
586586config MFD_JZ4740_ADC
587587    tristate "Support for the JZ4740 SoC ADC core"
588588    select MFD_CORE
589    depends on MACH_JZ4740 || MACH_JZ4750L
589    depends on MACH_JZ4740 || MACH_JZ4750L || MACH_JZ4760
590590    help
591591      Say yes here if you want support for the ADC unit in the JZ4740 SoC.
592592      This driver is necessary for jz4740-battery and jz4740-hwmon driver.
drivers/mfd/jz4740-adc.c
2929
3030#include <linux/jz4740-adc.h>
3131
32#include <asm/mach-jz47xx/soc.h>
33
3234
3335#define JZ_REG_ADC_ENABLE 0x00
3436#define JZ_REG_ADC_CFG 0x04
3537#define JZ_REG_ADC_CTRL 0x08
3638#define JZ_REG_ADC_STATUS 0x0c
39#define JZ_REG_ADC_CLKDIV 0x28
3740
3841#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10
3942#define JZ_REG_ADC_BATTERY_BASE 0x1c
...... 
358361    set_irq_data(adc->irq, adc);
359362    set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux);
360363
364    jz4740_adc_clk_enable(adc);
361365    writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
362366    writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
363367
368    if (soc_is_jz4760()) {
369        unsigned int div;
370        div = clk_get_rate(adc->clk) / 100000 - 1;
371        printk("clk div: %u\n", div);
372        writel(div | (1 << 12) | (1 << 18), adc->base + JZ_REG_ADC_CLKDIV);
373    }
374
364375    ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
365376        ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base);
366377    if (ret < 0)
...... 
368379
369380    /* In JZ4750, enabling a clock and issuing a request immediately
370381     * misses an irq. So keep clock running all the time. */
371    jz4740_adc_clk_enable(adc);
372382
373383    return 0;
374384
drivers/mtd/nand/Kconfig
528528
529529config MTD_NAND_JZ4750
530530    tristate "Support for JZ4750 SoC NAND controller"
531    depends on MACH_JZ4750L
531    depends on MACH_JZ4750L || MACH_JZ4760
532532    help
533533        Enables support for NAND Flash on JZ4750 SoC based boards.
534534
drivers/mtd/nand/jz4750_nand.c
3737#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
3838#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
3939
40#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
41#define JZ_NAND_MEM_CMD_OFFSET 0x08000
40#define JZ_NAND_MEM_ADDR_OFFSET 0x800000
41#define JZ_NAND_MEM_CMD_OFFSET 0x400000
4242
4343#define JZ_REG_BCH_CR 0x00
4444#define JZ_REG_BCH_CR_SET 0x04
...... 
4646#define JZ_REG_BCH_CNT 0x0C
4747#define JZ_REG_BCH_DR 0x10
4848#define JZ_REG_BCH_PAR(i) (0x14 + (i))
49#define JZ_REG_BCH_STATUS 0x24
50#define JZ_REG_BCH_ERR(i) (0x28 + ((i) << 2))
49#define JZ_REG_BCH_STATUS 0x6C
50#define JZ_REG_BCH_STATUS_SET 0x74
51#define JZ_REG_BCH_STATUS_CLR 0x78
52#define JZ_REG_BCH_ERR(i) (0x3C + ((i) << 2))
5153
5254#define JZ_BCH_ENABLE BIT(0)
5355#define JZ_BCH_RESET BIT(1)
54#define JZ_BCH_8BIT BIT(2)
55#define JZ_BCH_ENCODE BIT(3)
56#define JZ_BCH_8BIT BIT(3)
57#define JZ_BCH_ENCODE BIT(2)
5658#define JZ_BCH_USE_DMA BIT(4)
5759
5860#define JZ_BCH_STATUS_ERROR BIT(0)
...... 
158160    int size = nand->chip.ecc.size,
159161        bytes = nand->chip.ecc.bytes;
160162
163    return 0;
164
161165    if (nand->is_reading)
162166        return 0;
163167
164    writel(JZ_BCH_ENABLE, nand->bch_base + JZ_REG_BCH_CR_SET);
165    writel(JZ_BCH_RESET, nand->bch_base + JZ_REG_BCH_CR_SET);
168    writel(JZ_BCH_ENABLE | JZ_BCH_RESET, nand->bch_base + JZ_REG_BCH_CR_SET);
166169
167    writel(size & 0xffff, nand->bch_base + JZ_REG_BCH_CNT);
170    writel((size << 1) & 0xffff, nand->bch_base + JZ_REG_BCH_CNT);
168171
169172    for(i = 0; i < size; i++)
170173        writeb(dat[i], nand->bch_base + JZ_REG_BCH_DR);
...... 
196199    int size = nand->chip.ecc.size,
197200        bytes = nand->chip.ecc.bytes;
198201
199    writel(JZ_BCH_ENABLE, nand->bch_base + JZ_REG_BCH_CR_SET);
200    writel(JZ_BCH_RESET, nand->bch_base + JZ_REG_BCH_CR_SET);
202    return 0;
203
204    writel(JZ_BCH_ENABLE | JZ_BCH_RESET, nand->bch_base + JZ_REG_BCH_CR_SET);
201205
202206    /* Clear status bits */
203    writel(0xff, nand->bch_base + JZ_REG_BCH_STATUS);
207    writel(0xff, nand->bch_base + JZ_REG_BCH_STATUS_CLR);
204208
205    writel((size + bytes) << 16, nand->bch_base + JZ_REG_BCH_CNT);
209    writel((size + bytes) << 17, nand->bch_base + JZ_REG_BCH_CNT);
206210
207211    for (i = 0; i < size; i++)
208212        writeb(dat[i], nand->bch_base + JZ_REG_BCH_DR);
drivers/video/jz4740_fb.c
173173
174174#ifdef CONFIG_MACH_JZ4760
175175static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
176    { JZ_GPIO_PORTC(0), "LCD_B0", JZ4760_GPIO_C00_FUNC_LCD_B0 },
177    { JZ_GPIO_PORTC(1), "LCD_B1", JZ4760_GPIO_C01_FUNC_LCD_B1 },
178    { JZ_GPIO_PORTC(2), "LCD_B2", JZ4760_GPIO_C02_FUNC_LCD_B2 },
179176    { JZ_GPIO_PORTC(3), "LCD_B3", JZ4760_GPIO_C03_FUNC_LCD_B3 },
180177    { JZ_GPIO_PORTC(4), "LCD_B4", JZ4760_GPIO_C04_FUNC_LCD_B4 },
181    { JZ_GPIO_PORTC(10), "LCD_G0", JZ4760_GPIO_C10_FUNC_LCD_G0 },
182    { JZ_GPIO_PORTC(11), "LCD_G1", JZ4760_GPIO_C11_FUNC_LCD_G1 },
178    { JZ_GPIO_PORTC(5), "LCD_B5", JZ4760_GPIO_C05_FUNC_LCD_B5 },
179    { JZ_GPIO_PORTC(6), "LCD_B6", JZ4760_GPIO_C06_FUNC_LCD_B6 },
180    { JZ_GPIO_PORTC(7), "LCD_B7", JZ4760_GPIO_C07_FUNC_LCD_B7 },
183181    { JZ_GPIO_PORTC(12), "LCD_G2", JZ4760_GPIO_C12_FUNC_LCD_G2 },
184182    { JZ_GPIO_PORTC(13), "LCD_G3", JZ4760_GPIO_C13_FUNC_LCD_G3 },
185183    { JZ_GPIO_PORTC(14), "LCD_G4", JZ4760_GPIO_C14_FUNC_LCD_G4 },
186184    { JZ_GPIO_PORTC(15), "LCD_G5", JZ4760_GPIO_C15_FUNC_LCD_G5 },
187    { JZ_GPIO_PORTC(20), "LCD_R0", JZ4760_GPIO_C20_FUNC_LCD_R0 },
188    { JZ_GPIO_PORTC(21), "LCD_R1", JZ4760_GPIO_C21_FUNC_LCD_R1 },
189    { JZ_GPIO_PORTC(22), "LCD_R2", JZ4760_GPIO_C22_FUNC_LCD_R2 },
185    { JZ_GPIO_PORTC(16), "LCD_G6", JZ4760_GPIO_C16_FUNC_LCD_G6 },
186    { JZ_GPIO_PORTC(17), "LCD_G7", JZ4760_GPIO_C17_FUNC_LCD_G7 },
190187    { JZ_GPIO_PORTC(23), "LCD_R3", JZ4760_GPIO_C23_FUNC_LCD_R3 },
191188    { JZ_GPIO_PORTC(24), "LCD_R4", JZ4760_GPIO_C24_FUNC_LCD_R4 },
192
193    { JZ_GPIO_PORTC(5), "LCD_B5", JZ4760_GPIO_C05_FUNC_LCD_B5 },
194189    { JZ_GPIO_PORTC(25), "LCD_R5", JZ4760_GPIO_C25_FUNC_LCD_R5 },
195
196    { JZ_GPIO_PORTC(6), "LCD_B6", JZ4760_GPIO_C06_FUNC_LCD_B6 },
197    { JZ_GPIO_PORTC(7), "LCD_B7", JZ4760_GPIO_C07_FUNC_LCD_B7 },
198    { JZ_GPIO_PORTC(16), "LCD_G6", JZ4760_GPIO_C16_FUNC_LCD_G6 },
199    { JZ_GPIO_PORTC(17), "LCD_G7", JZ4760_GPIO_C17_FUNC_LCD_G7 },
200190    { JZ_GPIO_PORTC(26), "LCD_R6", JZ4760_GPIO_C26_FUNC_LCD_R6 },
201191    { JZ_GPIO_PORTC(27), "LCD_R7", JZ4760_GPIO_C27_FUNC_LCD_R7 },
192
193    { JZ_GPIO_PORTC(2), "LCD_B2", JZ4760_GPIO_C02_FUNC_LCD_B2 },
194    { JZ_GPIO_PORTC(22), "LCD_R2", JZ4760_GPIO_C22_FUNC_LCD_R2 },
195
196    { JZ_GPIO_PORTC(0), "LCD_B0", JZ4760_GPIO_C00_FUNC_LCD_B0 },
197    { JZ_GPIO_PORTC(1), "LCD_B1", JZ4760_GPIO_C01_FUNC_LCD_B1 },
198    { JZ_GPIO_PORTC(10), "LCD_G0", JZ4760_GPIO_C10_FUNC_LCD_G0 },
199    { JZ_GPIO_PORTC(11), "LCD_G1", JZ4760_GPIO_C11_FUNC_LCD_G1 },
200    { JZ_GPIO_PORTC(20), "LCD_R0", JZ4760_GPIO_C20_FUNC_LCD_R0 },
201    { JZ_GPIO_PORTC(21), "LCD_R1", JZ4760_GPIO_C21_FUNC_LCD_R1 },
202202};
203203#else
204204static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
...... 
229229
230230    switch (jzfb->pdata->lcd_type) {
231231    case JZ_LCD_TYPE_GENERIC_16_BIT:
232        num = 4;
233        break;
234232    case JZ_LCD_TYPE_GENERIC_18_BIT:
233    case JZ_LCD_TYPE_GENERIC_24_BIT:
235234        num = 4;
236235        break;
237236    case JZ_LCD_TYPE_8BIT_SERIAL:
...... 
259258        break;
260259    case JZ_LCD_TYPE_GENERIC_18_BIT:
261260        num = 18;
262    break;
261        break;
263262    case JZ_LCD_TYPE_GENERIC_24_BIT:
264263        num = 24;
265264        break;
...... 
376375        var->blue.length = 6;
377376        var->bits_per_pixel = 32;
378377        break;
379    case 32:
380378    case 24:
379    case 32:
381380        var->transp.offset = 24;
382381        var->transp.length = 8;
383382        var->red.offset = 16;

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