Date:2011-03-03 17:53:52 (9 years 3 months ago)
Author:Peter Zotov
Commit:ac7a6e48373a3c56e727b4224a33afd24fd05cea
Message:MIPS: JZ47xx: Moved jz4740 headers to a subdirectory of mach-jz47xx/.

Files: arch/mips/include/asm/mach-jz4740/base.h (1 diff)
arch/mips/include/asm/mach-jz4740/board-n516.h (1 diff)
arch/mips/include/asm/mach-jz4740/clock.h (1 diff)
arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h (1 diff)
arch/mips/include/asm/mach-jz4740/dma.h (1 diff)
arch/mips/include/asm/mach-jz4740/gpio.h (1 diff)
arch/mips/include/asm/mach-jz4740/irq.h (1 diff)
arch/mips/include/asm/mach-jz4740/jz4740_fb.h (1 diff)
arch/mips/include/asm/mach-jz4740/jz4740_mmc.h (1 diff)
arch/mips/include/asm/mach-jz4740/jz4740_nand.h (1 diff)
arch/mips/include/asm/mach-jz4740/platform.h (1 diff)
arch/mips/include/asm/mach-jz4740/timer.h (1 diff)
arch/mips/include/asm/mach-jz4740/war.h (1 diff)
arch/mips/include/asm/mach-jz47xx/cpu-feature-overrides.h (1 diff)
arch/mips/include/asm/mach-jz47xx/gpio.h (1 diff)
arch/mips/include/asm/mach-jz47xx/irq.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/base.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/board-n516.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/clock.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/dma.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/gpio.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/irq.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/platform.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/timer.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740_fb.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740_mmc.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740_nand.h (1 diff)
arch/mips/include/asm/mach-jz47xx/war.h (1 diff)
arch/mips/jz47xx/Platform (1 diff)
arch/mips/jz47xx/clock-debugfs.c (1 diff)
arch/mips/jz47xx/dma.c (1 diff)
arch/mips/jz47xx/gpiov2.c (6 diffs)
arch/mips/jz47xx/irq.c (4 diffs)
arch/mips/jz47xx/jz4740/board-id800wt.c (2 diffs)
arch/mips/jz47xx/jz4740/board-n516-display.c (1 diff)
arch/mips/jz47xx/jz4740/board-n516.c (1 diff)
arch/mips/jz47xx/jz4740/board-n526.c (1 diff)
arch/mips/jz47xx/jz4740/board-qi_lb60.c (1 diff)
arch/mips/jz47xx/jz4740/clock.c (1 diff)
arch/mips/jz47xx/jz4740/platform.c (1 diff)
arch/mips/jz47xx/prom.c (1 diff)
arch/mips/jz47xx/pwm.c (1 diff)
arch/mips/jz47xx/reset.c (1 diff)
arch/mips/jz47xx/time.c (1 diff)
arch/mips/jz47xx/timer.c (1 diff)

Change Details

arch/mips/include/asm/mach-jz4740/base.h
1#ifndef __ASM_MACH_JZ4740_BASE_H__
2#define __ASM_MACH_JZ4740_BASE_H__
3
4#define JZ4740_CPM_BASE_ADDR 0x10000000
5#define JZ4740_INTC_BASE_ADDR 0x10001000
6#define JZ4740_WDT_BASE_ADDR 0x10002000
7#define JZ4740_TCU_BASE_ADDR 0x10002010
8#define JZ4740_RTC_BASE_ADDR 0x10003000
9#define JZ4740_GPIO_BASE_ADDR 0x10010000
10#define JZ4740_AIC_BASE_ADDR 0x10020000
11#define JZ4740_MSC_BASE_ADDR 0x10021000
12#define JZ4740_UART0_BASE_ADDR 0x10030000
13#define JZ4740_UART1_BASE_ADDR 0x10031000
14#define JZ4740_I2C_BASE_ADDR 0x10042000
15#define JZ4740_SSI_BASE_ADDR 0x10043000
16#define JZ4740_SADC_BASE_ADDR 0x10070000
17#define JZ4740_EMC_BASE_ADDR 0x13010000
18#define JZ4740_DMAC_BASE_ADDR 0x13020000
19#define JZ4740_UHC_BASE_ADDR 0x13030000
20#define JZ4740_UDC_BASE_ADDR 0x13040000
21#define JZ4740_LCD_BASE_ADDR 0x13050000
22#define JZ4740_SLCD_BASE_ADDR 0x13050000
23#define JZ4740_CIM_BASE_ADDR 0x13060000
24#define JZ4740_IPU_BASE_ADDR 0x13080000
25
26#endif
arch/mips/include/asm/mach-jz4740/board-n516.h
1/*
2 * linux/include/asm-mips/mach-jz4740/board-n516.h
3 *
4 * JZ4730-based N516 board definition.
5 *
6 * Copyright (C) 2009, Yauhen Kharuzhy <jekhor@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __ASM_JZ4740_N516_H__
15#define __ASM_JZ4740_N516_H__
16
17#include <asm/mach-jz4740/gpio.h>
18
19/*
20 * GPIO
21 */
22#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(17)
23#define GPIO_SD_CD_N JZ_GPIO_PORTD(7)
24#define GPIO_SD_WP JZ_GPIO_PORTD(15)
25#define GPIO_USB_DETECT JZ_GPIO_PORTD(19)
26#define GPIO_CHARG_STAT_N JZ_GPIO_PORTD(16)
27#define GPIO_LED_ENABLE JZ_GPIO_PORTD(28)
28#define GPIO_LPC_INT JZ_GPIO_PORTD(14)
29#define GPIO_HPHONE_DETECT JZ_GPIO_PORTD(20)
30#define GPIO_SPEAKER_ENABLE JZ_GPIO_PORTD(21)
31
32/* Display */
33#define GPIO_DISPLAY_RST_L JZ_GPIO_PORTB(18)
34#define GPIO_DISPLAY_RDY JZ_GPIO_PORTB(17)
35#define GPIO_DISPLAY_STBY JZ_GPIO_PORTC(22)
36#define GPIO_DISPLAY_ERR JZ_GPIO_PORTC(23)
37#define GPIO_DISPLAY_OFF_N JZ_GPIO_PORTD(1)
38
39#endif /* __ASM_JZ4740_N516_H__ */
arch/mips/include/asm/mach-jz4740/clock.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __ASM_JZ4740_CLOCK_H__
16#define __ASM_JZ4740_CLOCK_H__
17
18enum jz4740_wait_mode {
19    JZ4740_WAIT_MODE_IDLE,
20    JZ4740_WAIT_MODE_SLEEP,
21};
22
23void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
24
25void jz4740_clock_udc_enable_auto_suspend(void);
26void jz4740_clock_udc_disable_auto_suspend(void);
27
28#endif
arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 */
7#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
8#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
9
10#define cpu_has_tlb 1
11#define cpu_has_4kex 1
12#define cpu_has_3k_cache 0
13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0
16#define cpu_has_32fpr 0
17#define cpu_has_counter 0
18#define cpu_has_watch 1
19#define cpu_has_divec 1
20#define cpu_has_vce 0
21#define cpu_has_cache_cdex_p 0
22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
24#define cpu_has_mcheck 1
25#define cpu_has_ejtag 1
26#define cpu_has_llsc 1
27#define cpu_has_mips16 0
28#define cpu_has_mdmx 0
29#define cpu_has_mips3d 0
30#define cpu_has_smartmips 0
31#define kernel_uses_llsc 1
32#define cpu_has_vtag_icache 1
33#define cpu_has_dc_aliases 0
34#define cpu_has_ic_fills_f_dc 0
35#define cpu_has_pindexed_dcache 0
36#define cpu_has_mips32r1 1
37#define cpu_has_mips32r2 0
38#define cpu_has_mips64r1 0
39#define cpu_has_mips64r2 0
40#define cpu_has_dsp 0
41#define cpu_has_mipsmt 0
42#define cpu_has_userlocal 0
43#define cpu_has_nofpuex 0
44#define cpu_has_64bits 0
45#define cpu_has_64bit_zero_reg 0
46#define cpu_has_inclusive_pcaches 0
47
48#define cpu_dcache_line_size() 32
49#define cpu_icache_line_size() 32
50
51#endif
arch/mips/include/asm/mach-jz4740/dma.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 DMA definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_DMA_H__
17#define __ASM_MACH_JZ4740_DMA_H__
18
19struct jz4740_dma_chan;
20
21enum jz4740_dma_request_type {
22    JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
23    JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
24    JZ4740_DMA_TYPE_UART_RECEIVE = 21,
25    JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
26    JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
27    JZ4740_DMA_TYPE_AIC_TRANSMIT = 24,
28    JZ4740_DMA_TYPE_AIC_RECEIVE = 25,
29    JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
30    JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
31    JZ4740_DMA_TYPE_TCU = 28,
32    JZ4740_DMA_TYPE_SADC = 29,
33    JZ4740_DMA_TYPE_SLCD = 30,
34};
35
36enum jz4740_dma_width {
37    JZ4740_DMA_WIDTH_32BIT = 0,
38    JZ4740_DMA_WIDTH_8BIT = 1,
39    JZ4740_DMA_WIDTH_16BIT = 2,
40};
41
42enum jz4740_dma_transfer_size {
43    JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
44    JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
45    JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
46    JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
47    JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
48};
49
50enum jz4740_dma_flags {
51    JZ4740_DMA_SRC_AUTOINC = 0x2,
52    JZ4740_DMA_DST_AUTOINC = 0x1,
53};
54
55enum jz4740_dma_mode {
56    JZ4740_DMA_MODE_SINGLE = 0,
57    JZ4740_DMA_MODE_BLOCK = 1,
58};
59
60struct jz4740_dma_config {
61    enum jz4740_dma_width src_width;
62    enum jz4740_dma_width dst_width;
63    enum jz4740_dma_transfer_size transfer_size;
64    enum jz4740_dma_request_type request_type;
65    enum jz4740_dma_flags flags;
66    enum jz4740_dma_mode mode;
67};
68
69typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
70
71struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
72void jz4740_dma_free(struct jz4740_dma_chan *dma);
73
74void jz4740_dma_configure(struct jz4740_dma_chan *dma,
75    const struct jz4740_dma_config *config);
76
77
78void jz4740_dma_enable(struct jz4740_dma_chan *dma);
79void jz4740_dma_disable(struct jz4740_dma_chan *dma);
80
81void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
82void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
83void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
84
85uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
86
87void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
88    jz4740_dma_complete_callback_t cb);
89
90#endif /* __ASM_JZ4740_DMA_H__ */
arch/mips/include/asm/mach-jz4740/gpio.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 GPIO pin definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef _JZ_GPIO_H
17#define _JZ_GPIO_H
18
19#include <linux/types.h>
20
21enum jz_gpio_function {
22    JZ_GPIO_FUNC_NONE,
23    JZ_GPIO_FUNC1,
24    JZ_GPIO_FUNC2,
25    JZ_GPIO_FUNC3,
26};
27
28
29/*
30 Usually a driver for a SoC component has to request several gpio pins and
31 configure them as funcion pins.
32 jz_gpio_bulk_request can be used to ease this process.
33 Usually one would do something like:
34
35 const static struct jz_gpio_bulk_request i2c_pins[] = {
36    JZ_GPIO_BULK_PIN(I2C_SDA),
37    JZ_GPIO_BULK_PIN(I2C_SCK),
38 };
39
40 inside the probe function:
41
42    ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
43    if (ret) {
44    ...
45
46 inside the remove function:
47
48    jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
49
50
51*/
52struct jz_gpio_bulk_request {
53    int gpio;
54    const char *name;
55    enum jz_gpio_function function;
56};
57
58#define JZ_GPIO_BULK_PIN(pin) { \
59    .gpio = JZ_GPIO_ ## pin, \
60    .name = #pin, \
61    .function = JZ_GPIO_FUNC_ ## pin \
62}
63
64int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
65void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
66void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
67void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
68void jz_gpio_enable_pullup(unsigned gpio);
69void jz_gpio_disable_pullup(unsigned gpio);
70int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
71
72int jz_gpio_port_direction_input(int port, uint32_t mask);
73int jz_gpio_port_direction_output(int port, uint32_t mask);
74void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
75uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
76
77#include <asm/mach-generic/gpio.h>
78
79#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
80#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
81#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
82#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
83
84/* Port A function pins */
85#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
86#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
87#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
88#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
89#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
90#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
91#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
92#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
93#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
94#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
95#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
96#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
97#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
98#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
99#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
100#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
101#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
102#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
103#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
104#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
105#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
106#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
107#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
108#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
109#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
110#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
111#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
112#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
113#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
114#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
115#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
116#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
117
118#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
119#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
120#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
121#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
122#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
123#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
124#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
125#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
126#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
127#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
128#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
129#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
130#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
131#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
132#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
133#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
134#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
135#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
136#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
137#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
138#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
139#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
140#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
141#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
142#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
143#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
144#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
145#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
146#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
147#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
148#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
149#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
150
151/* Port B function pins */
152#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
153#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
154#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
155#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
156#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
157#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
158#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
159#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
160#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
161#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
162#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
163#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
164#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
165#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
166#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
167#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
168#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
169#define JZ_GPIO_LCD_CLS JZ_GPIO_PORTB(17)
170#define JZ_GPIO_LCD_SPL JZ_GPIO_PORTB(18)
171#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
172#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
173#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
174#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
175#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
176#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
177#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
178#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
179#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
180#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
181#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
182#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
183#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
184
185#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
186#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
187#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
188#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
189#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
190#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
191#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
192#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
193#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
194#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
195#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
196#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
197#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
198#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
199#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
200#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
201#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
202#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1
203#define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1
204#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
205#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
206#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
207#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
208#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
209#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
210#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
211#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
212#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
213#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
214#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
215#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
216#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
217
218
219#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
220#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
221
222#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
223#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
224
225/* Port C function pins */
226#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
227#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
228#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
229#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
230#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
231#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
232#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
233#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
234#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
235#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
236#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
237#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
238#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
239#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
240#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
241#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
242#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
243#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
244#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
245#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
246#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
247#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
248#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
249#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
250#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
251#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
252#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
253#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
254#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
255#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
256
257#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
258#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
259#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
260#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
261#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
262#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
263#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
264#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
265#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
266#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
267#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
268#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
269#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
270#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
271#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
272#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
273#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
274#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
275#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
276#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
277#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
278#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
279#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
280#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
281#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
282#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
283#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
284#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
285#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
286#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
287
288
289#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
290#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
291
292#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
293#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
294
295/* Port D function pins */
296#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
297#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
298#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
299#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
300#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
301#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
302#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
303#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
304#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
305#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
306#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
307#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
308#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
309#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
310#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
311#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
312#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
313#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
314#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
315#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
316#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
317#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
318#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
319#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
320#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
321#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
322#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
323#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
324#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
325#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
326#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
327
328#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1
329#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA
330#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA
331#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA
332#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA
333#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA
334#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA
335#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA
336#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA
337#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
338#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
339#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1
340#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA
341#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA
342#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA
343#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA
344#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
345#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
346#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
347#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
348#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
349#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
350#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
351#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
352#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
353
354#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1
355#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM
356#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM
357#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM
358#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM
359#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM
360#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM
361#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM
362#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM
363
364#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
365#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
366#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
367#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
368#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
369#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
370#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
371#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
372#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
373#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
374#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
375#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
376#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
377
378#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
379#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
380#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
381#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
382#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
383#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
384#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
385#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
386#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
387#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
388#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
389#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
390#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
391
392#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
393#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
394
395#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
396#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
397
398#endif
arch/mips/include/asm/mach-jz4740/irq.h
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 IRQ definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_IRQ_H__
17#define __ASM_MACH_JZ4740_IRQ_H__
18
19#define MIPS_CPU_IRQ_BASE 0
20#define JZ4740_IRQ_BASE 8
21
22/* 1st-level interrupts */
23#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
24#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
25#define JZ4740_IRQ_UHC JZ4740_IRQ(3)
26#define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
27#define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
28#define JZ4740_IRQ_SADC JZ4740_IRQ(12)
29#define JZ4740_IRQ_MSC JZ4740_IRQ(14)
30#define JZ4740_IRQ_RTC JZ4740_IRQ(15)
31#define JZ4740_IRQ_SSI JZ4740_IRQ(16)
32#define JZ4740_IRQ_CIM JZ4740_IRQ(17)
33#define JZ4740_IRQ_AIC JZ4740_IRQ(18)
34#define JZ4740_IRQ_ETH JZ4740_IRQ(19)
35#define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
36#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
37#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
38#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
39#define JZ4740_IRQ_UDC JZ4740_IRQ(24)
40#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
41#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
42#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
43#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
44#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
45#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
46
47/* 2nd-level interrupts */
48#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X))
49
50#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
51#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x))
52
53#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(176)
54
55#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
56
57#endif
arch/mips/include/asm/mach-jz4740/jz4740_fb.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__
16#define __ASM_MACH_JZ4740_JZ4740_FB_H__
17
18#include <linux/fb.h>
19
20enum jz4740_fb_lcd_type {
21    JZ_LCD_TYPE_GENERIC_16_BIT = 0,
22    JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4),
23    JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
24    JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
25    JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
26    JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
27    JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
28    JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
29    JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
30    JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
31    JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11,
32    JZ_LCD_TYPE_8BIT_SERIAL = 12,
33};
34
35#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop))
36
37/*
38* width: width of the lcd display in mm
39* height: height of the lcd display in mm
40* num_modes: size of modes
41* modes: list of valid video modes
42* bpp: bits per pixel for the lcd
43* lcd_type: lcd type
44*/
45
46struct jz4740_fb_platform_data {
47    unsigned int width;
48    unsigned int height;
49
50    size_t num_modes;
51    struct fb_videomode *modes;
52
53    unsigned int bpp;
54    enum jz4740_fb_lcd_type lcd_type;
55
56    struct {
57        uint32_t spl;
58        uint32_t cls;
59        uint32_t ps;
60        uint32_t rev;
61    } special_tft_config;
62
63    unsigned pixclk_falling_edge:1;
64    unsigned date_enable_active_low:1;
65};
66
67#endif
arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
1#ifndef __LINUX_MMC_JZ4740_MMC
2#define __LINUX_MMC_JZ4740_MMC
3
4struct jz4740_mmc_platform_data {
5    int gpio_power;
6    int gpio_card_detect;
7    int gpio_read_only;
8    unsigned card_detect_active_low:1;
9    unsigned read_only_active_low:1;
10    unsigned power_active_low:1;
11
12    unsigned data_1bit:1;
13};
14
15#endif
arch/mips/include/asm/mach-jz4740/jz4740_nand.h
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC NAND controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
17#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
18
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21
22struct jz_nand_platform_data {
23    int num_partitions;
24    struct mtd_partition *partitions;
25
26    struct nand_ecclayout *ecc_layout;
27
28    unsigned int busy_gpio;
29
30    void (*ident_callback)(struct platform_device *, struct nand_chip *,
31                struct mtd_partition **, int *num_partitions);
32};
33
34#endif
arch/mips/include/asm/mach-jz4740/platform.h
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform device definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16
17#ifndef __JZ4740_PLATFORM_H
18#define __JZ4740_PLATFORM_H
19
20#include <linux/platform_device.h>
21
22extern struct platform_device jz4740_usb_ohci_device;
23extern struct platform_device jz4740_udc_device;
24extern struct platform_device jz4740_mmc_device;
25extern struct platform_device jz4740_rtc_device;
26extern struct platform_device jz4740_i2c_device;
27extern struct platform_device jz4740_nand_device;
28extern struct platform_device jz4740_framebuffer_device;
29extern struct platform_device jz4740_i2s_device;
30extern struct platform_device jz4740_pcm_device;
31extern struct platform_device jz4740_codec_device;
32extern struct platform_device jz4740_adc_device;
33
34void jz4740_serial_device_register(void);
35
36#endif
arch/mips/include/asm/mach-jz4740/timer.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_TIMER
17#define __ASM_MACH_JZ4740_TIMER
18
19void jz4740_timer_enable_watchdog(void);
20void jz4740_timer_disable_watchdog(void);
21
22#endif
arch/mips/include/asm/mach-jz4740/war.h
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
9#define __ASM_MIPS_MACH_JZ4740_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
arch/mips/include/asm/mach-jz47xx/cpu-feature-overrides.h
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 */
7#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
8#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
9
10#define cpu_has_tlb 1
11#define cpu_has_4kex 1
12#define cpu_has_3k_cache 0
13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0
16#define cpu_has_32fpr 0
17#define cpu_has_counter 0
18#define cpu_has_watch 1
19#define cpu_has_divec 1
20#define cpu_has_vce 0
21#define cpu_has_cache_cdex_p 0
22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
24#define cpu_has_mcheck 1
25#define cpu_has_ejtag 1
26#define cpu_has_llsc 1
27#define cpu_has_mips16 0
28#define cpu_has_mdmx 0
29#define cpu_has_mips3d 0
30#define cpu_has_smartmips 0
31#define kernel_uses_llsc 1
32#define cpu_has_vtag_icache 1
33#define cpu_has_dc_aliases 0
34#define cpu_has_ic_fills_f_dc 0
35#define cpu_has_pindexed_dcache 0
36#define cpu_has_mips32r1 1
37#define cpu_has_mips32r2 0
38#define cpu_has_mips64r1 0
39#define cpu_has_mips64r2 0
40#define cpu_has_dsp 0
41#define cpu_has_mipsmt 0
42#define cpu_has_userlocal 0
43#define cpu_has_nofpuex 0
44#define cpu_has_64bits 0
45#define cpu_has_64bit_zero_reg 0
46#define cpu_has_inclusive_pcaches 0
47
48#define cpu_dcache_line_size() 32
49#define cpu_icache_line_size() 32
50
51#endif
arch/mips/include/asm/mach-jz47xx/gpio.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 GPIO pin definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ47XX_GPIO_H__
17#define __ASM_MACH_JZ47XX_GPIO_H__
18
19#include <linux/types.h>
20
21enum jz_gpio_function {
22    JZ_GPIO_FUNC_NONE,
23    JZ_GPIO_FUNC1,
24    JZ_GPIO_FUNC2,
25    JZ_GPIO_FUNC3,
26};
27
28/*
29 Usually a driver for a SoC component has to request several gpio pins and
30 configure them as funcion pins.
31 jz_gpio_bulk_request can be used to ease this process.
32 Usually one would do something like:
33
34 const static struct jz_gpio_bulk_request i2c_pins[] = {
35    JZ_GPIO_BULK_PIN(I2C_SDA),
36    JZ_GPIO_BULK_PIN(I2C_SCK),
37 };
38
39 inside the probe function:
40
41    ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
42    if (ret) {
43    ...
44
45 inside the remove function:
46
47    jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
48
49
50*/
51struct jz_gpio_bulk_request {
52    int gpio;
53    const char *name;
54    enum jz_gpio_function function;
55};
56
57#define JZ_GPIO_BULK_PIN(pin) { \
58    .gpio = JZ_GPIO_ ## pin, \
59    .name = #pin, \
60    .function = JZ_GPIO_FUNC_ ## pin \
61}
62
63int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
64void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
65void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
66void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
67void jz_gpio_enable_pullup(unsigned gpio);
68void jz_gpio_disable_pullup(unsigned gpio);
69int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
70
71int jz_gpio_port_direction_input(int port, uint32_t mask);
72int jz_gpio_port_direction_output(int port, uint32_t mask);
73void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
74uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
75
76#include <asm/mach-generic/gpio.h>
77
78#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
79#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
80#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
81#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
82
83#endif
arch/mips/include/asm/mach-jz47xx/irq.h
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ47xx IRQ definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ47XX_IRQ_H__
17#define __ASM_MACH_JZ47XX_IRQ_H__
18
19#define MIPS_CPU_IRQ_BASE 0
20#define JZ47XX_IRQ_BASE 8
21
22/* 1st-level interrupts */
23#define JZ47XX_IRQ(x) (JZ47XX_IRQ_BASE + (x))
24
25/* 2nd-level interrupts */
26#define JZ47XX_IRQ_DMA(x) (JZ47XX_IRQ(32) + (x))
27
28#define JZ47XX_IRQ_INTC_GPIO(x) (JZ47XX_IRQ_GPIO(0) - (x))
29#define JZ47XX_IRQ_GPIO(x) (JZ47XX_IRQ(48) + (x))
30
31#define NR_IRQS 182
32
33#endif
arch/mips/include/asm/mach-jz47xx/jz4740/base.h
1#ifndef __ASM_MACH_JZ4740_BASE_H__
2#define __ASM_MACH_JZ4740_BASE_H__
3
4#define JZ4740_CPM_BASE_ADDR 0x10000000
5#define JZ4740_INTC_BASE_ADDR 0x10001000
6#define JZ4740_WDT_BASE_ADDR 0x10002000
7#define JZ4740_TCU_BASE_ADDR 0x10002010
8#define JZ4740_RTC_BASE_ADDR 0x10003000
9#define JZ4740_GPIO_BASE_ADDR 0x10010000
10#define JZ4740_AIC_BASE_ADDR 0x10020000
11#define JZ4740_MSC_BASE_ADDR 0x10021000
12#define JZ4740_UART0_BASE_ADDR 0x10030000
13#define JZ4740_UART1_BASE_ADDR 0x10031000
14#define JZ4740_I2C_BASE_ADDR 0x10042000
15#define JZ4740_SSI_BASE_ADDR 0x10043000
16#define JZ4740_SADC_BASE_ADDR 0x10070000
17#define JZ4740_EMC_BASE_ADDR 0x13010000
18#define JZ4740_DMAC_BASE_ADDR 0x13020000
19#define JZ4740_UHC_BASE_ADDR 0x13030000
20#define JZ4740_UDC_BASE_ADDR 0x13040000
21#define JZ4740_LCD_BASE_ADDR 0x13050000
22#define JZ4740_SLCD_BASE_ADDR 0x13050000
23#define JZ4740_CIM_BASE_ADDR 0x13060000
24#define JZ4740_IPU_BASE_ADDR 0x13080000
25
26#endif
arch/mips/include/asm/mach-jz47xx/jz4740/board-n516.h
1/*
2 * linux/include/asm-mips/mach-jz4740/board-n516.h
3 *
4 * JZ4730-based N516 board definition.
5 *
6 * Copyright (C) 2009, Yauhen Kharuzhy <jekhor@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __ASM_JZ4740_N516_H__
15#define __ASM_JZ4740_N516_H__
16
17#include <asm/mach-jz4740/gpio.h>
18
19/*
20 * GPIO
21 */
22#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(17)
23#define GPIO_SD_CD_N JZ_GPIO_PORTD(7)
24#define GPIO_SD_WP JZ_GPIO_PORTD(15)
25#define GPIO_USB_DETECT JZ_GPIO_PORTD(19)
26#define GPIO_CHARG_STAT_N JZ_GPIO_PORTD(16)
27#define GPIO_LED_ENABLE JZ_GPIO_PORTD(28)
28#define GPIO_LPC_INT JZ_GPIO_PORTD(14)
29#define GPIO_HPHONE_DETECT JZ_GPIO_PORTD(20)
30#define GPIO_SPEAKER_ENABLE JZ_GPIO_PORTD(21)
31
32/* Display */
33#define GPIO_DISPLAY_RST_L JZ_GPIO_PORTB(18)
34#define GPIO_DISPLAY_RDY JZ_GPIO_PORTB(17)
35#define GPIO_DISPLAY_STBY JZ_GPIO_PORTC(22)
36#define GPIO_DISPLAY_ERR JZ_GPIO_PORTC(23)
37#define GPIO_DISPLAY_OFF_N JZ_GPIO_PORTD(1)
38
39#endif /* __ASM_JZ4740_N516_H__ */
arch/mips/include/asm/mach-jz47xx/jz4740/clock.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __ASM_JZ4740_CLOCK_H__
16#define __ASM_JZ4740_CLOCK_H__
17
18enum jz4740_wait_mode {
19    JZ4740_WAIT_MODE_IDLE,
20    JZ4740_WAIT_MODE_SLEEP,
21};
22
23void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
24
25void jz4740_clock_udc_enable_auto_suspend(void);
26void jz4740_clock_udc_disable_auto_suspend(void);
27
28#endif
arch/mips/include/asm/mach-jz47xx/jz4740/dma.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 DMA definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_DMA_H__
17#define __ASM_MACH_JZ4740_DMA_H__
18
19struct jz4740_dma_chan;
20
21enum jz4740_dma_request_type {
22    JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
23    JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
24    JZ4740_DMA_TYPE_UART_RECEIVE = 21,
25    JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
26    JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
27    JZ4740_DMA_TYPE_AIC_TRANSMIT = 24,
28    JZ4740_DMA_TYPE_AIC_RECEIVE = 25,
29    JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
30    JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
31    JZ4740_DMA_TYPE_TCU = 28,
32    JZ4740_DMA_TYPE_SADC = 29,
33    JZ4740_DMA_TYPE_SLCD = 30,
34};
35
36enum jz4740_dma_width {
37    JZ4740_DMA_WIDTH_32BIT = 0,
38    JZ4740_DMA_WIDTH_8BIT = 1,
39    JZ4740_DMA_WIDTH_16BIT = 2,
40};
41
42enum jz4740_dma_transfer_size {
43    JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
44    JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
45    JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
46    JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
47    JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
48};
49
50enum jz4740_dma_flags {
51    JZ4740_DMA_SRC_AUTOINC = 0x2,
52    JZ4740_DMA_DST_AUTOINC = 0x1,
53};
54
55enum jz4740_dma_mode {
56    JZ4740_DMA_MODE_SINGLE = 0,
57    JZ4740_DMA_MODE_BLOCK = 1,
58};
59
60struct jz4740_dma_config {
61    enum jz4740_dma_width src_width;
62    enum jz4740_dma_width dst_width;
63    enum jz4740_dma_transfer_size transfer_size;
64    enum jz4740_dma_request_type request_type;
65    enum jz4740_dma_flags flags;
66    enum jz4740_dma_mode mode;
67};
68
69typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
70
71struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
72void jz4740_dma_free(struct jz4740_dma_chan *dma);
73
74void jz4740_dma_configure(struct jz4740_dma_chan *dma,
75    const struct jz4740_dma_config *config);
76
77
78void jz4740_dma_enable(struct jz4740_dma_chan *dma);
79void jz4740_dma_disable(struct jz4740_dma_chan *dma);
80
81void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
82void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
83void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
84
85uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
86
87void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
88    jz4740_dma_complete_callback_t cb);
89
90#endif /* __ASM_JZ4740_DMA_H__ */
arch/mips/include/asm/mach-jz47xx/jz4740/gpio.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 GPIO pin definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_GPIO_H__
17#define __ASM_MACH_JZ4740_GPIO_H__
18
19#include <asm/mach-jz47xx/gpio.h>
20
21/* Port A function pins */
22#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
23#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
24#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
25#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
26#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
27#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
28#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
29#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
30#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
31#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
32#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
33#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
34#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
35#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
36#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
37#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
38#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
39#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
40#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
41#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
42#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
43#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
44#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
45#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
46#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
47#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
48#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
49#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
50#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
51#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
52#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
53#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
54
55#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
56#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
57#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
58#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
59#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
60#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
61#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
62#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
63#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
64#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
65#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
66#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
67#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
68#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
69#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
70#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
71#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
72#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
73#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
74#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
75#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
76#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
77#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
78#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
79#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
80#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
81#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
82#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
83#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
84#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
85#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
86#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
87
88/* Port B function pins */
89#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
90#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
91#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
92#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
93#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
94#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
95#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
96#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
97#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
98#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
99#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
100#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
101#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
102#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
103#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
104#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
105#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
106#define JZ_GPIO_LCD_CLS JZ_GPIO_PORTB(17)
107#define JZ_GPIO_LCD_SPL JZ_GPIO_PORTB(18)
108#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
109#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
110#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
111#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
112#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
113#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
114#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
115#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
116#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
117#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
118#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
119#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
120#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
121
122#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
123#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
124#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
125#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
126#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
127#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
128#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
129#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
130#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
131#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
132#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
133#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
134#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
135#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
136#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
137#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
138#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
139#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1
140#define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1
141#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
142#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
143#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
144#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
145#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
146#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
147#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
148#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
149#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
150#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
151#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
152#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
153#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
154
155
156#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
157#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
158
159#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
160#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
161
162/* Port C function pins */
163#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
164#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
165#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
166#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
167#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
168#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
169#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
170#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
171#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
172#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
173#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
174#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
175#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
176#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
177#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
178#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
179#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
180#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
181#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
182#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
183#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
184#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
185#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
186#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
187#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
188#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
189#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
190#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
191#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
192#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
193
194#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
195#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
196#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
197#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
198#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
199#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
200#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
201#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
202#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
203#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
204#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
205#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
206#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
207#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
208#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
209#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
210#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
211#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
212#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
213#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
214#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
215#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
216#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
217#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
218#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
219#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
220#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
221#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
222#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
223#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
224
225
226#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
227#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
228
229#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
230#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
231
232/* Port D function pins */
233#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
234#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
235#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
236#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
237#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
238#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
239#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
240#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
241#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
242#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
243#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
244#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
245#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
246#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
247#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
248#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
249#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
250#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
251#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
252#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
253#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
254#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
255#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
256#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
257#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
258#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
259#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
260#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
261#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
262#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
263#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
264
265#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1
266#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA
267#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA
268#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA
269#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA
270#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA
271#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA
272#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA
273#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA
274#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
275#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
276#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1
277#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA
278#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA
279#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA
280#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA
281#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
282#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
283#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
284#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
285#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
286#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
287#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
288#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
289#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
290
291#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1
292#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM
293#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM
294#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM
295#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM
296#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM
297#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM
298#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM
299#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM
300
301#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
302#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
303#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
304#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
305#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
306#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
307#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
308#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
309#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
310#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
311#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
312#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
313#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
314
315#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
316#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
317#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
318#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
319#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
320#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
321#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
322#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
323#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
324#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
325#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
326#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
327#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
328
329#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
330#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
331
332#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
333#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
334
335#endif
arch/mips/include/asm/mach-jz47xx/jz4740/irq.h
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 IRQ definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_IRQ_H__
17#define __ASM_MACH_JZ4740_IRQ_H__
18
19#include <asm/mach-jz47xx/irq.h>
20
21/* 1st-level interrupts */
22#define JZ4740_IRQ_I2C JZ47XX_IRQ(1)
23#define JZ4740_IRQ_UHC JZ47XX_IRQ(3)
24#define JZ4740_IRQ_UART1 JZ47XX_IRQ(8)
25#define JZ4740_IRQ_UART0 JZ47XX_IRQ(9)
26#define JZ4740_IRQ_SADC JZ47XX_IRQ(12)
27#define JZ4740_IRQ_MSC JZ47XX_IRQ(14)
28#define JZ4740_IRQ_RTC JZ47XX_IRQ(15)
29#define JZ4740_IRQ_SSI JZ47XX_IRQ(16)
30#define JZ4740_IRQ_CIM JZ47XX_IRQ(17)
31#define JZ4740_IRQ_AIC JZ47XX_IRQ(18)
32#define JZ4740_IRQ_ETH JZ47XX_IRQ(19)
33#define JZ4740_IRQ_DMAC JZ47XX_IRQ(20)
34#define JZ4740_IRQ_TCU2 JZ47XX_IRQ(21)
35#define JZ4740_IRQ_TCU1 JZ47XX_IRQ(22)
36#define JZ4740_IRQ_TCU0 JZ47XX_IRQ(23)
37#define JZ4740_IRQ_UDC JZ47XX_IRQ(24)
38#define JZ4740_IRQ_GPIO3 JZ47XX_IRQ(25)
39#define JZ4740_IRQ_GPIO2 JZ47XX_IRQ(26)
40#define JZ4740_IRQ_GPIO1 JZ47XX_IRQ(27)
41#define JZ4740_IRQ_GPIO0 JZ47XX_IRQ(28)
42#define JZ4740_IRQ_IPU JZ47XX_IRQ(29)
43#define JZ4740_IRQ_LCD JZ47XX_IRQ(30)
44
45/* 2nd-level interrupts */
46#define JZ4740_IRQ_ADC_BASE JZ47XX_IRQ(176)
47
48#endif
arch/mips/include/asm/mach-jz47xx/jz4740/platform.h
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform device definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16
17#ifndef __JZ4740_PLATFORM_H
18#define __JZ4740_PLATFORM_H
19
20#include <linux/platform_device.h>
21
22extern struct platform_device jz4740_usb_ohci_device;
23extern struct platform_device jz4740_udc_device;
24extern struct platform_device jz4740_mmc_device;
25extern struct platform_device jz4740_rtc_device;
26extern struct platform_device jz4740_i2c_device;
27extern struct platform_device jz4740_nand_device;
28extern struct platform_device jz4740_framebuffer_device;
29extern struct platform_device jz4740_i2s_device;
30extern struct platform_device jz4740_pcm_device;
31extern struct platform_device jz4740_codec_device;
32extern struct platform_device jz4740_adc_device;
33
34void jz4740_serial_device_register(void);
35
36#endif
arch/mips/include/asm/mach-jz47xx/jz4740/timer.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_TIMER
17#define __ASM_MACH_JZ4740_TIMER
18
19void jz4740_timer_enable_watchdog(void);
20void jz4740_timer_disable_watchdog(void);
21
22#endif
arch/mips/include/asm/mach-jz47xx/jz4740_fb.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__
16#define __ASM_MACH_JZ4740_JZ4740_FB_H__
17
18#include <linux/fb.h>
19
20enum jz4740_fb_lcd_type {
21    JZ_LCD_TYPE_GENERIC_16_BIT = 0,
22    JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4),
23    JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
24    JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
25    JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
26    JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
27    JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
28    JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
29    JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
30    JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
31    JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11,
32    JZ_LCD_TYPE_8BIT_SERIAL = 12,
33};
34
35#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop))
36
37/*
38* width: width of the lcd display in mm
39* height: height of the lcd display in mm
40* num_modes: size of modes
41* modes: list of valid video modes
42* bpp: bits per pixel for the lcd
43* lcd_type: lcd type
44*/
45
46struct jz4740_fb_platform_data {
47    unsigned int width;
48    unsigned int height;
49
50    size_t num_modes;
51    struct fb_videomode *modes;
52
53    unsigned int bpp;
54    enum jz4740_fb_lcd_type lcd_type;
55
56    struct {
57        uint32_t spl;
58        uint32_t cls;
59        uint32_t ps;
60        uint32_t rev;
61    } special_tft_config;
62
63    unsigned pixclk_falling_edge:1;
64    unsigned date_enable_active_low:1;
65};
66
67#endif
arch/mips/include/asm/mach-jz47xx/jz4740_mmc.h
1#ifndef __LINUX_MMC_JZ4740_MMC
2#define __LINUX_MMC_JZ4740_MMC
3
4struct jz4740_mmc_platform_data {
5    int gpio_power;
6    int gpio_card_detect;
7    int gpio_read_only;
8    unsigned card_detect_active_low:1;
9    unsigned read_only_active_low:1;
10    unsigned power_active_low:1;
11
12    unsigned data_1bit:1;
13};
14
15#endif
arch/mips/include/asm/mach-jz47xx/jz4740_nand.h
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC NAND controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
17#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
18
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21
22struct jz_nand_platform_data {
23    int num_partitions;
24    struct mtd_partition *partitions;
25
26    struct nand_ecclayout *ecc_layout;
27
28    unsigned int busy_gpio;
29
30    void (*ident_callback)(struct platform_device *, struct nand_chip *,
31                struct mtd_partition **, int *num_partitions);
32};
33
34#endif
arch/mips/include/asm/mach-jz47xx/war.h
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
9#define __ASM_MIPS_MACH_JZ4740_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
arch/mips/jz47xx/Platform
11platform-$(CONFIG_MACH_JZ4740) += jz47xx/jz4740/
2cflags-$(CONFIG_MACH_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
32
43platform-$(CONFIG_MACH_JZ47XX) += jz47xx/
4cflags-$(CONFIG_MACH_JZ47XX) += -I$(srctree)/arch/mips/include/asm/mach-jz47xx
55load-$(CONFIG_MACH_JZ47XX) += 0xffffffff80010000
arch/mips/jz47xx/clock-debugfs.c
2121#include <linux/debugfs.h>
2222#include <linux/uaccess.h>
2323
24#include <asm/mach-jz4740/clock.h>
24#include <jz4740/clock.h>
2525#include "clock.h"
2626
2727static struct dentry *jz4740_clock_debugfs;
arch/mips/jz47xx/dma.c
1919#include <linux/interrupt.h>
2020
2121#include <linux/dma-mapping.h>
22#include <asm/mach-jz4740/dma.h>
23#include <asm/mach-jz4740/base.h>
22
23#include <jz4740/dma.h>
24#include <jz4740/base.h>
25#include <jz4740/irq.h>
2426
2527#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
2628#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
arch/mips/jz47xx/gpiov2.c
2828#include <linux/debugfs.h>
2929#include <linux/seq_file.h>
3030
31#include <asm/mach-jz4740/base.h>
31#include <jz4740/base.h>
32#include <jz4740/irq.h>
33#include <jz4740/gpio.h>
3234
3335#define JZ4740_GPIO_BASE_A (32*0)
3436#define JZ4740_GPIO_BASE_B (32*1)
...... 
4042#define JZ4740_GPIO_NUM_C 31
4143#define JZ4740_GPIO_NUM_D 32
4244
43#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
44#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
45#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
46#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
45#define JZ4740_IRQ_GPIO_BASE_A (JZ47XX_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
46#define JZ4740_IRQ_GPIO_BASE_B (JZ47XX_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
47#define JZ4740_IRQ_GPIO_BASE_C (JZ47XX_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
48#define JZ4740_IRQ_GPIO_BASE_D (JZ47XX_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
4749
4850#define JZ_REG_GPIO_PIN 0x00
4951#define JZ_REG_GPIO_DATA 0x10
...... 
269271
270272int gpio_to_irq(unsigned gpio)
271273{
272    return JZ4740_IRQ_GPIO(0) + gpio;
274    return JZ47XX_IRQ_GPIO(0) + gpio;
273275}
274276EXPORT_SYMBOL_GPL(gpio_to_irq);
275277
276278int irq_to_gpio(unsigned irq)
277279{
278    return irq - JZ4740_IRQ_GPIO(0);
280    return irq - JZ47XX_IRQ_GPIO(0);
279281}
280282EXPORT_SYMBOL_GPL(irq_to_gpio);
281283
...... 
308310    unsigned int gpio_bank;
309311    struct jz_gpio_chip *chip = get_irq_desc_data(desc);
310312
311    gpio_bank = JZ4740_IRQ_GPIO0 - irq;
313    gpio_bank = JZ47XX_IRQ_GPIO(0) - irq;
312314
313315    flag = readl(chip->base + JZ_REG_GPIO_FLAG);
314316
...... 
319321
320322    jz_gpio_check_trigger_both(chip, irq);
321323
322    gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
324    gpio_irq += (gpio_bank << 5) + JZ47XX_IRQ_GPIO(0);
323325
324326    generic_handle_irq(gpio_irq);
325327};
...... 
522524
523525    gpiochip_add(&chip->gpio_chip);
524526
525    chip->irq = JZ4740_IRQ_INTC_GPIO(id);
527    chip->irq = JZ47XX_IRQ_INTC_GPIO(id);
526528    set_irq_data(chip->irq, chip);
527529    set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
528530
arch/mips/jz47xx/irq.c
2929#include <asm/mipsregs.h>
3030#include <asm/irq_cpu.h>
3131
32#include <asm/mach-jz4740/base.h>
32#include <jz4740/base.h>
3333
3434static void __iomem *jz_intc_base;
3535static uint32_t jz_intc_wakeup;
...... 
4141#define JZ_REG_INTC_CLEAR_MASK 0x0c
4242#define JZ_REG_INTC_PENDING 0x10
4343
44#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
44#define IRQ_BIT(x) BIT((x) - JZ47XX_IRQ_BASE)
4545
4646static inline unsigned long intc_irq_bit(struct irq_data *data)
4747{
...... 
8383    irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
8484
8585    if (irq_reg)
86        generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
86        generic_handle_irq(__fls(irq_reg) + JZ47XX_IRQ_BASE);
8787
8888    return IRQ_HANDLED;
8989}
...... 
103103    /* Mask all irqs */
104104    writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
105105
106    for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
106    for (i = JZ47XX_IRQ_BASE; i < JZ47XX_IRQ_BASE + 32; i++) {
107107        set_irq_chip_data(i, (void *)IRQ_BIT(i));
108108        set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
109109    }
arch/mips/jz47xx/jz4740/board-id800wt.c
1010#include <linux/init.h>
1111#include <linux/gpio.h>
1212
13#include <asm/mach-jz4740/platform.h>
13#include <jz4740/platform.h>
1414
1515#include <linux/input.h>
1616#include <linux/power_supply.h>
...... 
1818
1919#include "../clock.h"
2020
21#include <asm/mach-jz4740/jz4740_fb.h>
22#include <asm/mach-jz4740/jz4740_nand.h>
21#include <jz4740_fb.h>
22#include <jz4740_nand.h>
2323
2424/* NAND */
2525static struct nand_ecclayout id800wt_ecclayout = {
arch/mips/jz47xx/jz4740/board-n516-display.c
2020#include <linux/irq.h>
2121#include <linux/gpio.h>
2222
23#include <asm/mach-jz4740/jz4740_fb.h>
23#include <jz4740/jz4740_fb.h>
2424
25#include <asm/mach-jz4740/platform.h>
26#include <asm/mach-jz4740/board-n516.h>
25#include <jz4740/platform.h>
26#include <jz4740/board-n516.h>
2727
2828#include <video/metronomefb.h>
2929#include <linux/console.h>
arch/mips/jz47xx/jz4740/board-n516.c
2727
2828#include <linux/i2c.h>
2929
30#include <asm/mach-jz4740/jz4740_mmc.h>
31#include <asm/mach-jz4740/jz4740_nand.h>
30#include <jz4740/jz4740_mmc.h>
31#include <jz4740/jz4740_nand.h>
3232
33#include <asm/mach-jz4740/board-n516.h>
34#include <asm/mach-jz4740/platform.h>
33#include <jz4740/board-n516.h>
34#include <jz4740/platform.h>
3535
3636#include "../clock.h"
3737
arch/mips/jz47xx/jz4740/board-n526.c
3030
3131#include "../clock.h"
3232
33#include <asm/mach-jz4740/jz4740_mmc.h>
34#include <asm/mach-jz4740/jz4740_nand.h>
35#include <asm/mach-jz4740/jz4740_fb.h>
33#include <jz4740/jz4740_mmc.h>
34#include <jz4740/jz4740_nand.h>
35#include <jz4740/jz4740_fb.h>
3636
37#include <asm/mach-jz4740/platform.h>
37#include <jz4740/platform.h>
3838
3939/* NAND */
4040static struct nand_ecclayout n526_ecclayout = {
arch/mips/jz47xx/jz4740/board-qi_lb60.c
2525#include <linux/power/jz4740-battery.h>
2626#include <linux/power/gpio-charger.h>
2727
28#include <asm/mach-jz4740/jz4740_fb.h>
29#include <asm/mach-jz4740/jz4740_mmc.h>
30#include <asm/mach-jz4740/jz4740_nand.h>
28#include <jz4740_fb.h>
29#include <jz4740_mmc.h>
30#include <jz4740_nand.h>
3131
3232#include <linux/regulator/fixed.h>
3333#include <linux/regulator/machine.h>
3434
3535#include <linux/leds_pwm.h>
3636
37#include <asm/mach-jz4740/platform.h>
37#include <jz4740/platform.h>
3838
3939#include "../clock.h"
4040
arch/mips/jz47xx/jz4740/clock.c
2222#include <linux/list.h>
2323#include <linux/err.h>
2424
25#include <asm/mach-jz4740/clock.h>
26#include <asm/mach-jz4740/base.h>
25#include <jz4740/clock.h>
26#include <jz4740/base.h>
2727
2828#include "../clock.h"
2929
arch/mips/jz47xx/jz4740/platform.c
2121
2222#include <linux/dma-mapping.h>
2323
24#include <asm/mach-jz4740/platform.h>
25#include <asm/mach-jz4740/base.h>
26#include <asm/mach-jz4740/irq.h>
24#include <jz4740/platform.h>
25#include <jz4740/base.h>
26#include <jz4740/irq.h>
2727
2828#include <linux/serial_core.h>
2929#include <linux/serial_8250.h>
arch/mips/jz47xx/prom.c
2121#include <linux/serial_reg.h>
2222
2323#include <asm/bootinfo.h>
24#include <asm/mach-jz4740/base.h>
24#include <jz4740/base.h>
2525
2626static __init void jz4740_init_cmdline(int argc, char *argv[])
2727{
arch/mips/jz47xx/pwm.c
2020#include <linux/pwm.h>
2121#include <linux/gpio.h>
2222
23#include <asm/mach-jz4740/gpio.h>
23#include <jz4740/gpio.h>
2424#include "timer.h"
2525
2626static struct clk *jz4740_pwm_clk;
arch/mips/jz47xx/reset.c
1818
1919#include <asm/reboot.h>
2020
21#include <asm/mach-jz4740/base.h>
22#include <asm/mach-jz4740/timer.h>
21#include <jz4740/base.h>
22#include <jz4740/timer.h>
2323
2424static void jz4740_halt(void)
2525{
arch/mips/jz47xx/time.c
1919
2020#include <linux/clockchips.h>
2121
22#include <asm/mach-jz4740/irq.h>
22#include <jz4740/irq.h>
2323#include <asm/time.h>
2424
2525#include "clock.h"
arch/mips/jz47xx/timer.c
1919
2020#include "timer.h"
2121
22#include <asm/mach-jz4740/base.h>
22#include <jz4740/base.h>
2323
2424void __iomem *jz4740_timer_base;
2525

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