| Date: | 2012-03-30 15:47:30 (9 years 14 days ago) |
|---|---|
| Author: | Maarten ter Huurne |
| Commit: | b386be689295730688885552666ea40b2e639b14 |
| Message: | Revert "MIPS: JZ4740: reset: Initialize hibernate wakeup
counters." This reverts commit 9fe93785649cf0a8db58da462d6cfaca8aa50278. The patch will be improved to get it accepted upstream. |
| Files: |
arch/mips/jz4740/reset.c (2 diffs) |
Change Details
| arch/mips/jz4740/reset.c | ||
|---|---|---|
| 21 | 21 | #include <asm/mach-jz4740/base.h> |
| 22 | 22 | #include <asm/mach-jz4740/timer.h> |
| 23 | 23 | |
| 24 | #include "reset.h" | |
| 25 | #include "clock.h" | |
| 26 | ||
| 27 | 24 | static void jz4740_halt(void) |
| 28 | 25 | { |
| 29 | 26 | while (1) { |
| ... | ... | |
| 56 | 53 | jz4740_halt(); |
| 57 | 54 | } |
| 58 | 55 | |
| 59 | #define JZ_REG_RTC_CTRL 0x00 | |
| 60 | #define JZ_REG_RTC_HIBERNATE 0x20 | |
| 61 | #define JZ_REG_RTC_WAKEUP_FILTER 0x24 | |
| 62 | #define JZ_REG_RTC_RESET_COUNTER 0x28 | |
| 56 | #define JZ_REG_RTC_CTRL 0x00 | |
| 57 | #define JZ_REG_RTC_HIBERNATE 0x20 | |
| 63 | 58 | |
| 64 | #define JZ_RTC_CTRL_WRDY BIT(7) | |
| 65 | #define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0 | |
| 66 | #define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0 | |
| 59 | #define JZ_RTC_CTRL_WRDY BIT(7) | |
| 67 | 60 | |
| 68 | static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base) | |
| 61 | static void jz4740_power_off(void) | |
| 69 | 62 | { |
| 63 | void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24); | |
| 70 | 64 | uint32_t ctrl; |
| 65 | ||
| 71 | 66 | do { |
| 72 | 67 | ctrl = readl(rtc_base + JZ_REG_RTC_CTRL); |
| 73 | 68 | } while (!(ctrl & JZ_RTC_CTRL_WRDY)); |
| 74 | } | |
| 75 | 69 | |
| 76 | static void jz4740_power_off(void) | |
| 77 | { | |
| 78 | void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38); | |
| 79 | unsigned long long wakeup_filter_ticks; | |
| 80 | unsigned long long reset_counter_ticks; | |
| 81 | ||
| 82 | /* Set minimum wakeup pin assertion time: 100 ms. | |
| 83 | Range is 0 to 2 sec if RTC is clocked at 32 kHz. */ | |
| 84 | wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000; | |
| 85 | if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK) | |
| 86 | wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK; | |
| 87 | else | |
| 88 | wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK; | |
| 89 | jz4740_rtc_wait_ready(rtc_base); | |
| 90 | writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER); | |
| 91 | ||
| 92 | /* Set reset pin low-level assertion time after wakeup: 60 ms. | |
| 93 | Range is 0 to 125 ms if RTC is clocked at 32 kHz. */ | |
| 94 | reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000; | |
| 95 | if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK) | |
| 96 | reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK; | |
| 97 | else | |
| 98 | reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK; | |
| 99 | jz4740_rtc_wait_ready(rtc_base); | |
| 100 | writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER); | |
| 101 | ||
| 102 | jz4740_rtc_wait_ready(rtc_base); | |
| 103 | 70 | writel(1, rtc_base + JZ_REG_RTC_HIBERNATE); |
| 104 | ||
| 105 | 71 | jz4740_halt(); |
| 106 | 72 | } |
| 107 | 73 | |
Branches:
ben-wpan
ben-wpan-stefan
5396a9238205f20f811ea57898980d3ca82df0b6
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9
