Date:2010-03-27 22:42:13 (12 years 6 months ago)
Author:Uwe Kleine-König
Commit:b7d41d6d580743b1fed1b9560d948c9ef58564bd
Message:V4L/DVB: mx1-camera: compile fix

This fixes a regression of

7d58289 (mx1: prefix SOC specific defines with MX1_ and deprecate old names)

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Files: arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h (1 diff)
drivers/media/video/mx1_camera.c (3 diffs)

Change Details

arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
3131#define DMA_MODE_WRITE 1
3232#define DMA_MODE_MASK 1
3333
34#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
34#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
35
36/* DMA Interrupt Mask Register */
37#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
38
39/* Channel Control Register */
40#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
3541
3642#define IMX_DMA_MEMSIZE_32 (0 << 4)
3743#define IMX_DMA_MEMSIZE_8 (1 << 4)
drivers/media/video/mx1_camera.c
4949/*
5050 * CSI registers
5151 */
52#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
53#define DMA_DIMR 0x08 /* Interrupt mask Register */
5452#define CSICR1 0x00 /* CSI Control Register 1 */
5553#define CSISR 0x08 /* CSI Status Register */
5654#define CSIRXR 0x10 /* CSI RxFIFO Register */
...... 
784782                   pcdev);
785783
786784    imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO,
787                   IMX_DMA_MEMSIZE_32, DMA_REQ_CSI_R, 0);
785                   IMX_DMA_MEMSIZE_32, MX1_DMA_REQ_CSI_R, 0);
788786    /* burst length : 16 words = 64 bytes */
789787    imx_dma_config_burstlen(pcdev->dma_chan, 0);
790788
...... 
798796    set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end -
799797                           &mx1_camera_sof_fiq_start);
800798
801    regs.ARM_r8 = DMA_BASE + DMA_DIMR;
802    regs.ARM_r9 = DMA_BASE + DMA_CCR(pcdev->dma_chan);
799    regs.ARM_r8 = (long)MX1_DMA_DIMR;
800    regs.ARM_r9 = (long)MX1_DMA_CCR(pcdev->dma_chan);
803801    regs.ARM_r10 = (long)pcdev->base + CSICR1;
804802    regs.ARM_fp = (long)pcdev->base + CSISR;
805803    regs.ARM_sp = 1 << pcdev->dma_chan;

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