Kernel Commit Details
|Date:||2010-09-08 01:23:50 (13 years 2 months ago)|
|Author:||Maarten ter Huurne|
|Message:||MIPS: JZ4740: Round PLL frequency down to a multiple of 24 MHz.
This is required to make the color encoding of the TV-out signal work on the Dingoo.
However, clock.c should not contain Dingoo specific code, but that's something to solve later.
arch/mips/jz4740/clock.c (1 diff)
|268||268||static unsigned long jz_clk_pll_round_rate(struct clk *clk, unsigned long rate)|
|270||270||unsigned int in_div, feedback, out_div;|
|272||jz_clk_pll_calc_dividers(rate, &in_div, &feedback, &out_div);|
|271||/* The PLL frequency must be a multiple of 24 MHz, since the LCD pixel|
|272||* clock must be exactly 12 MHz for the TV-out to work.|
|273||* TODO: A multiple of 12 MHz for the PLL would work if the PLL would|
|274||* not be divided by 2 before being passed to the set of derived|
|275||* clocks that includes the LCD pixel clock.|
|276||* TODO: Systemwide decisions like this should be made by the board|
|277||* support code, so add some kind of hook for that.|
|279||unsigned long rate24 = (rate / 24000000) * 24000000;|
|281||jz_clk_pll_calc_dividers(rate24, &in_div, &feedback, &out_div);|
|273||282||return jz_clk_pll_calc_rate(in_div, feedback, out_div);|