| Date: | 2010-09-08 01:23:50 (13 years 2 months ago) |
|---|---|
| Author: | Maarten ter Huurne |
| Commit: | b95a25ae613c1d9b978c44b18fbb45cc21e66794 |
| Message: | MIPS: JZ4740: Round PLL frequency down to a multiple of 24 MHz. This is required to make the color encoding of the TV-out signal work on the Dingoo. However, clock.c should not contain Dingoo specific code, but that's something to solve later. |
| Files: |
arch/mips/jz4740/clock.c (1 diff) |
Change Details
| arch/mips/jz4740/clock.c | ||
|---|---|---|
| 268 | 268 | static unsigned long jz_clk_pll_round_rate(struct clk *clk, unsigned long rate) |
| 269 | 269 | { |
| 270 | 270 | unsigned int in_div, feedback, out_div; |
| 271 | ||
| 272 | jz_clk_pll_calc_dividers(rate, &in_div, &feedback, &out_div); | |
| 271 | /* The PLL frequency must be a multiple of 24 MHz, since the LCD pixel | |
| 272 | * clock must be exactly 12 MHz for the TV-out to work. | |
| 273 | * TODO: A multiple of 12 MHz for the PLL would work if the PLL would | |
| 274 | * not be divided by 2 before being passed to the set of derived | |
| 275 | * clocks that includes the LCD pixel clock. | |
| 276 | * TODO: Systemwide decisions like this should be made by the board | |
| 277 | * support code, so add some kind of hook for that. | |
| 278 | */ | |
| 279 | unsigned long rate24 = (rate / 24000000) * 24000000; | |
| 280 | ||
| 281 | jz_clk_pll_calc_dividers(rate24, &in_div, &feedback, &out_div); | |
| 273 | 282 | return jz_clk_pll_calc_rate(in_div, feedback, out_div); |
| 274 | 283 | } |
| 275 | 284 | |
Branches:
ben-wpan
ben-wpan-stefan
5396a9238205f20f811ea57898980d3ca82df0b6
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9
