Date:2010-09-08 01:23:50 (12 years 27 days ago)
Author:Maarten ter Huurne
Commit:b95a25ae613c1d9b978c44b18fbb45cc21e66794
Message:MIPS: JZ4740: Round PLL frequency down to a multiple of 24 MHz.

This is required to make the color encoding of the TV-out signal work on the Dingoo.
However, clock.c should not contain Dingoo specific code, but that's something to solve later.
Files: arch/mips/jz4740/clock.c (1 diff)

Change Details

arch/mips/jz4740/clock.c
268268static unsigned long jz_clk_pll_round_rate(struct clk *clk, unsigned long rate)
269269{
270270    unsigned int in_div, feedback, out_div;
271
272    jz_clk_pll_calc_dividers(rate, &in_div, &feedback, &out_div);
271    /* The PLL frequency must be a multiple of 24 MHz, since the LCD pixel
272     * clock must be exactly 12 MHz for the TV-out to work.
273     * TODO: A multiple of 12 MHz for the PLL would work if the PLL would
274     * not be divided by 2 before being passed to the set of derived
275     * clocks that includes the LCD pixel clock.
276     * TODO: Systemwide decisions like this should be made by the board
277     * support code, so add some kind of hook for that.
278     */
279    unsigned long rate24 = (rate / 24000000) * 24000000;
280
281    jz_clk_pll_calc_dividers(rate24, &in_div, &feedback, &out_div);
273282    return jz_clk_pll_calc_rate(in_div, feedback, out_div);
274283}
275284

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