Date:2011-02-05 22:16:25 (11 years 7 months ago)
Author:Lars C.
Commit:bd61961fa87b34b60945c18b7a006cce427712e8
Message:MIPS: JZ4740: GPIO: Use common irq chip for all gpios

Currently there is one irq_chip per gpio_chip with the only difference being the
name.
Since the information whether the irq belong to GPIO bank A, B, C or D is not
that important rewrite the code to simply use a single irq_chip for all
gpio_chips.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Files: arch/mips/jz4740/gpio.c (4 diffs)

Change Details

arch/mips/jz4740/gpio.c
8686    spinlock_t lock;
8787
8888    struct gpio_chip gpio_chip;
89    struct irq_chip irq_chip;
9089    struct sys_device sysdev;
9190};
9291
...... 
435434    return 0;
436435}
437436
437static struct irq_chip jz_gpio_irq_chip = {
438    .name = "GPIO",
439    .irq_mask = jz_gpio_irq_mask,
440    .irq_unmask = jz_gpio_irq_unmask,
441    .irq_ack = jz_gpio_irq_ack,
442    .irq_startup = jz_gpio_irq_startup,
443    .irq_shutdown = jz_gpio_irq_shutdown,
444    .irq_set_type = jz_gpio_irq_set_type,
445    .irq_set_wake = jz_gpio_irq_set_wake,
446};
447
438448/*
439449 * This lock class tells lockdep that GPIO irqs are in a different
440450 * category than their parents, so it won't report false recursion.
...... 
453463        .base = JZ4740_GPIO_BASE_ ## _bank, \
454464        .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
455465    }, \
456    .irq_chip = { \
457        .name = "GPIO Bank " # _bank, \
458        .irq_mask = jz_gpio_irq_mask, \
459        .irq_unmask = jz_gpio_irq_unmask, \
460        .irq_ack = jz_gpio_irq_ack, \
461        .irq_startup = jz_gpio_irq_startup, \
462        .irq_shutdown = jz_gpio_irq_shutdown, \
463        .irq_set_type = jz_gpio_irq_set_type, \
464        .irq_set_wake = jz_gpio_irq_set_wake, \
465    }, \
466466}
467467
468468static struct jz_gpio_chip jz4740_gpio_chips[] = {
...... 
529529    for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
530530        lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
531531        set_irq_chip_data(irq, chip);
532        set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
532        set_irq_chip_and_handler(irq, &jz_gpio_irq_chip, handle_level_irq);
533533    }
534534
535535    return 0;

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