Date:2012-01-29 22:44:48 (8 years 7 months ago)
Author:Paul Cercueil
Commit:d42e289e19821de2491b8451a593203eddd446fc
Message:MIPS: JZ4740: Drop support for LG LGDP4551 and SPFD5420A Smart LCD panels.

Files: drivers/video/Kconfig (1 diff)
drivers/video/jz4740_slcd_panels.c (2 diffs)

Change Details

drivers/video/Kconfig
24112411    bool "ILI9338 Smart LCD panel"
24122412    depends on FB_JZ4740_SLCD
24132413
2414config JZ_SLCD_LGDP4551
2415    bool "LG LGDP4551 Smart LCD panel"
2416    depends on FB_JZ4740_SLCD
2417
2418config JZ_SLCD_SPFD5420A
2419    bool "SPFD5420A Smart LCD panel"
2420    depends on FB_JZ4740_SLCD
2421
24222414config FB_MXS
24232415    tristate "MXS LCD framebuffer support"
24242416    depends on FB && ARCH_MXS
drivers/video/jz4740_slcd_panels.c
450450    /* Keep RESET active */
451451    gpio_set_value(ILI9338_GPIO_RESET_N, 0);
452452}
453
454#endif
455
456#ifdef CONFIG_JZ_SLCD_LGDP4551
457
458#define LGDP4551_GPIO_CS_N JZ_GPIO_PORTC(18) /* Chip select */
459#define LGDP4551_GPIO_RESET_N JZ_GPIO_PORTC(21) /* LCD reset */
460
461/* Set the start address of screen, for example (0, 0) */
462static void lgdp4551_set_addr(struct jzfb *jzfb, u16 x, u16 y)
463{
464    set_panel_reg(jzfb, 0x20, x);
465    udelay(1);
466    set_panel_reg(jzfb, 0x21, y);
467    udelay(1);
468    send_panel_command(jzfb, 0x22);
469}
470
471static int lgdp4551_init(struct jzfb *jzfb)
472{
473    struct device *dev = &jzfb->pdev->dev;
474    int ret;
475
476    ret = gpio_request(LGDP4551_GPIO_CS_N, dev_name(dev));
477    if (ret)
478        goto err_cs;
479    gpio_direction_output(LGDP4551_GPIO_CS_N, 0);
480
481    ret = gpio_request(LGDP4551_GPIO_RESET_N, dev_name(dev));
482    if (ret)
483        goto err_reset;
484    gpio_direction_output(LGDP4551_GPIO_RESET_N, 1);
485
486    mdelay(100);
487    return 0;
488
489err_reset:
490    gpio_free(LGDP4551_GPIO_CS_N);
491err_cs:
492    dev_err(dev, "Could not reserve GPIO pins for LGDP4551 panel\n");
493    return ret;
494}
495
496static void lgdp4551_exit(struct jzfb *jzfb)
497{
498    gpio_free(LGDP4551_GPIO_CS_N);
499    gpio_free(LGDP4551_GPIO_RESET_N);
500}
501
502static void lgdp4551_enable(struct jzfb *jzfb)
503{
504    /* RESET# */
505    gpio_set_value(LGDP4551_GPIO_RESET_N, 1);
506    mdelay(10);
507    gpio_set_value(LGDP4551_GPIO_RESET_N, 0);
508    mdelay(10);
509    gpio_set_value(LGDP4551_GPIO_RESET_N, 1);
510    mdelay(100);
511    set_panel_reg(jzfb, 0x0015, 0x0050);
512    set_panel_reg(jzfb, 0x0011, 0x0000);
513    set_panel_reg(jzfb, 0x0010, 0x3628);
514    set_panel_reg(jzfb, 0x0012, 0x0002);
515    set_panel_reg(jzfb, 0x0013, 0x0E47);
516    udelay(100);
517    set_panel_reg(jzfb, 0x0012, 0x0012);
518    udelay(100);
519    set_panel_reg(jzfb, 0x0010, 0x3620);
520    set_panel_reg(jzfb, 0x0013, 0x2E47);
521    udelay(50);
522    set_panel_reg(jzfb, 0x0030, 0x0000);
523    set_panel_reg(jzfb, 0x0031, 0x0502);
524    set_panel_reg(jzfb, 0x0032, 0x0307);
525    set_panel_reg(jzfb, 0x0033, 0x0304);
526    set_panel_reg(jzfb, 0x0034, 0x0004);
527    set_panel_reg(jzfb, 0x0035, 0x0401);
528    set_panel_reg(jzfb, 0x0036, 0x0707);
529    set_panel_reg(jzfb, 0x0037, 0x0303);
530    set_panel_reg(jzfb, 0x0038, 0x1E02);
531    set_panel_reg(jzfb, 0x0039, 0x1E02);
532    set_panel_reg(jzfb, 0x0001, 0x0000);
533    set_panel_reg(jzfb, 0x0002, 0x0300);
534    if (jzfb->pdata->bpp == 16)
535        set_panel_reg(jzfb, 0x0003, 0x10B8); /*8-bit system interface two transfers
536                          up:0x10B8 down:0x1088 left:0x1090 right:0x10a0*/
537    else if (jzfb->pdata->bpp == 32)
538        set_panel_reg(jzfb, 0x0003, 0xD0B8);/*8-bit system interface three transfers,666
539                           up:0xD0B8 down:0xD088 left:0xD090 right:0xD0A0*/
540    set_panel_reg(jzfb, 0x0008, 0x0204);
541    set_panel_reg(jzfb, 0x000A, 0x0008);
542    set_panel_reg(jzfb, 0x0060, 0x3100);
543    set_panel_reg(jzfb, 0x0061, 0x0001);
544    set_panel_reg(jzfb, 0x0090, 0x0052);
545    set_panel_reg(jzfb, 0x0092, 0x000F);
546    set_panel_reg(jzfb, 0x0093, 0x0001);
547    set_panel_reg(jzfb, 0x009A, 0x0008);
548    set_panel_reg(jzfb, 0x00A3, 0x0010);
549    set_panel_reg(jzfb, 0x0050, 0x0000);
550    set_panel_reg(jzfb, 0x0051, 0x00EF);
551    set_panel_reg(jzfb, 0x0052, 0x0000);
552    set_panel_reg(jzfb, 0x0053, 0x018F);
553    /*===Display_On_Function=== */
554    set_panel_reg(jzfb, 0x0007, 0x0001);
555    set_panel_reg(jzfb, 0x0007, 0x0021);
556    set_panel_reg(jzfb, 0x0007, 0x0023);
557    set_panel_reg(jzfb, 0x0007, 0x0033);
558    set_panel_reg(jzfb, 0x0007, 0x0133);
559    send_panel_command(jzfb, 0x0022); /* Write Data to GRAM. */
560    udelay(1);
561    lgdp4551_set_addr(jzfb, 0, 0);
562    mdelay(100);
563}
564
565static void lgdp4551_disable(struct jzfb *jzfb)
566{
567}
568
569#endif
570
571#ifdef CONFIG_JZ_SLCD_SPFD5420A
572
573#define SPFD5420A_GPIO_CS_N JZ_GPIO_PORTC(22) /* Chip select */
574#define SPFD5420A_GPIO_RESET_N JZ_GPIO_PORTB(18) /* LCD reset */
575#define SPFD5420A_GPIO_POWER_N JZ_GPIO_PORTD(0) /* Power off */
576#define SPFD5420A_GPIO_FMARK_N JZ_GPIO_PORTD(1) /* fmark */
577
578/* Set the start address of screen, for example (0, 0) */
579static void spfd5420a_set_addr(struct jzfb *jzfb, u32 x, u32 y)
580{
581    set_panel_reg(jzfb, 0x200, x);
582    udelay(1);
583    set_panel_reg(jzfb, 0x201, y);
584    udelay(1);
585    send_panel_command(jzfb, 0x202);
586}
587
588static int spfd5420a_init(struct jzfb *jzfb)
589{
590    struct device *dev = &jzfb->pdev->dev;
591    int ret;
592
593    ret = gpio_request(SPFD5420A_GPIO_CS_N, dev_name(dev));
594    if (ret)
595        goto err_cs;
596    gpio_direction_output(SPFD5420A_GPIO_CS_N, 0);
597
598    ret = gpio_request(SPFD5420A_GPIO_RESET_N, dev_name(dev));
599    if (ret)
600        goto err_reset;
601    gpio_direction_output(SPFD5420A_GPIO_RESET_N, 1);
602
603    ret = gpio_request(SPFD5420A_GPIO_POWER_N, dev_name(dev));
604    if (ret)
605        goto err_power;
606    gpio_direction_output(SPFD5420A_GPIO_POWER_N, 0);
607
608    mdelay(100);
609    return 0;
610
611err_power:
612    gpio_free(SPFD5420A_GPIO_RESET_N);
613err_reset:
614    gpio_free(SPFD5420A_GPIO_CS_N);
615err_cs:
616    dev_err(dev, "Could not reserve GPIO pins for SPFD5420A panel\n");
617    return ret;
618}
619
620static void spfd5420a_exit(struct jzfb *jzfb)
621{
622    gpio_free(SPFD5420A_GPIO_CS_N);
623    gpio_free(SPFD5420A_GPIO_RESET_N);
624    gpio_free(SPFD5420A_GPIO_POWER_N);
625}
626
627static void spfd5420a_init_gamma(struct jzfb *jzfb)
628{
629    set_panel_reg(jzfb, 0x0300, 0x0101);
630    set_panel_reg(jzfb, 0x0301, 0x0b27);
631    set_panel_reg(jzfb, 0x0302, 0x132a);
632    set_panel_reg(jzfb, 0x0303, 0x2a13);
633    set_panel_reg(jzfb, 0x0304, 0x270b);
634    set_panel_reg(jzfb, 0x0305, 0x0101);
635    set_panel_reg(jzfb, 0x0306, 0x1205);
636    set_panel_reg(jzfb, 0x0307, 0x0512);
637    set_panel_reg(jzfb, 0x0308, 0x0005);
638    set_panel_reg(jzfb, 0x0309, 0x0003);
639    set_panel_reg(jzfb, 0x030a, 0x0f04);
640    set_panel_reg(jzfb, 0x030b, 0x0f00);
641    set_panel_reg(jzfb, 0x030c, 0x000f);
642    set_panel_reg(jzfb, 0x030d, 0x040f);
643    set_panel_reg(jzfb, 0x030e, 0x0300);
644    set_panel_reg(jzfb, 0x030f, 0x0500);
645    /*** secorrect gamma2 ***/
646    set_panel_reg(jzfb, 0x0400, 0x3500);
647    set_panel_reg(jzfb, 0x0401, 0x0001);
648    set_panel_reg(jzfb, 0x0404, 0x0000);
649    set_panel_reg(jzfb, 0x0500, 0x0000);
650    set_panel_reg(jzfb, 0x0501, 0x0000);
651    set_panel_reg(jzfb, 0x0502, 0x0000);
652    set_panel_reg(jzfb, 0x0503, 0x0000);
653    set_panel_reg(jzfb, 0x0504, 0x0000);
654    set_panel_reg(jzfb, 0x0505, 0x0000);
655    set_panel_reg(jzfb, 0x0600, 0x0000);
656    set_panel_reg(jzfb, 0x0606, 0x0000);
657    set_panel_reg(jzfb, 0x06f0, 0x0000);
658    set_panel_reg(jzfb, 0x07f0, 0x5420);
659    set_panel_reg(jzfb, 0x07f3, 0x288a);
660    set_panel_reg(jzfb, 0x07f4, 0x0022);
661    set_panel_reg(jzfb, 0x07f5, 0x0001);
662    set_panel_reg(jzfb, 0x07f0, 0x0000);
663}
664
665static void spfd5420a_enable(struct jzfb *jzfb)
666{
667    gpio_set_value(SPFD5420A_GPIO_RESET_N, 1);
668    mdelay(10);
669    gpio_set_value(SPFD5420A_GPIO_RESET_N, 0);
670    mdelay(10);
671    gpio_set_value(SPFD5420A_GPIO_RESET_N, 1);
672    mdelay(100);
673    if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_SMART_PARALLEL_18_BIT) {
674        set_panel_reg(jzfb, 0x0606, 0x0000);
675        udelay(10);
676        set_panel_reg(jzfb, 0x0007, 0x0001);
677        udelay(10);
678        set_panel_reg(jzfb, 0x0110, 0x0001);
679        udelay(10);
680        set_panel_reg(jzfb, 0x0100, 0x17b0);
681        set_panel_reg(jzfb, 0x0101, 0x0147);
682        set_panel_reg(jzfb, 0x0102, 0x019d);
683        set_panel_reg(jzfb, 0x0103, 0x8600);
684        set_panel_reg(jzfb, 0x0281, 0x0010);
685        udelay(10);
686        set_panel_reg(jzfb, 0x0102, 0x01bd);
687        udelay(10);
688        /************initial************/
689        set_panel_reg(jzfb, 0x0000, 0x0000);
690        set_panel_reg(jzfb, 0x0001, 0x0000);
691        set_panel_reg(jzfb, 0x0002, 0x0400);
692        set_panel_reg(jzfb, 0x0003, 0x1288); /*up:0x1288 down:0x12B8 left:0x1290 right:0x12A0*/
693        set_panel_reg(jzfb, 0x0006, 0x0000);
694        set_panel_reg(jzfb, 0x0008, 0x0503);
695        set_panel_reg(jzfb, 0x0009, 0x0001);
696        set_panel_reg(jzfb, 0x000b, 0x0010);
697        set_panel_reg(jzfb, 0x000c, 0x0000);
698        set_panel_reg(jzfb, 0x000f, 0x0000);
699        set_panel_reg(jzfb, 0x0007, 0x0001);
700        set_panel_reg(jzfb, 0x0010, 0x0010);
701        set_panel_reg(jzfb, 0x0011, 0x0202);
702        set_panel_reg(jzfb, 0x0012, 0x0300);
703        set_panel_reg(jzfb, 0x0020, 0x021e);
704        set_panel_reg(jzfb, 0x0021, 0x0202);
705        set_panel_reg(jzfb, 0x0022, 0x0100);
706        set_panel_reg(jzfb, 0x0090, 0x0000);
707        set_panel_reg(jzfb, 0x0092, 0x0000);
708        set_panel_reg(jzfb, 0x0100, 0x16b0);
709        set_panel_reg(jzfb, 0x0101, 0x0147);
710        set_panel_reg(jzfb, 0x0102, 0x01bd);
711        set_panel_reg(jzfb, 0x0103, 0x2c00);
712        set_panel_reg(jzfb, 0x0107, 0x0000);
713        set_panel_reg(jzfb, 0x0110, 0x0001);
714        set_panel_reg(jzfb, 0x0210, 0x0000);
715        set_panel_reg(jzfb, 0x0211, 0x00ef);
716        set_panel_reg(jzfb, 0x0212, 0x0000);
717        set_panel_reg(jzfb, 0x0213, 0x018f);
718        set_panel_reg(jzfb, 0x0280, 0x0000);
719        set_panel_reg(jzfb, 0x0281, 0x0001);
720        set_panel_reg(jzfb, 0x0282, 0x0000);
721        spfd5420a_init_gamma(jzfb);
722        set_panel_reg(jzfb, 0x0007, 0x0173);
723    } else {
724        set_panel_reg(jzfb, 0x0600, 0x0001); /*soft reset*/
725        mdelay(10);
726        set_panel_reg(jzfb, 0x0600, 0x0000); /*soft reset*/
727        mdelay(10);
728        set_panel_reg(jzfb, 0x0606, 0x0000); /*i80-i/F Endian Control*/
729        /*===User setting=== */
730        set_panel_reg(jzfb, 0x0001, 0x0000);/* Driver Output Control-----0x0100 SM(bit10) | 0x400*/
731        set_panel_reg(jzfb, 0x0002, 0x0100); /*LCD Driving Wave Control 0x0100 */
732        if (jzfb->pdata->bpp == 16)
733            set_panel_reg(jzfb, 0x0003, 0x50A8);/*Entry Mode 0x1030*/
734        else /*bpp = 18*/
735            set_panel_reg(jzfb, 0x0003, 0x1010 | 0xC8); /*Entry Mode 0x1030*/
736        set_panel_reg(jzfb, 0x0006, 0x0000); /*Outline Sharpening Control*/
737        set_panel_reg(jzfb, 0x0008, 0x0808); /*Sets the number of lines for front/back porch period*/
738        set_panel_reg(jzfb, 0x0009, 0x0001); /*Display Control 3 */
739        set_panel_reg(jzfb, 0x000B, 0x0010); /*Low Power Control*/
740        set_panel_reg(jzfb, 0x000C, 0x0000); /*External Display Interface Control 1 0x0001 */
741        set_panel_reg(jzfb, 0x000F, 0x0000); /*External Display Interface Control 2 */
742        set_panel_reg(jzfb, 0x0400, 0xB104); /*Base Image Number of Line---GS(bit15) | 0x8000*/
743        set_panel_reg(jzfb, 0x0401, 0x0001); /*Base Image Display 0x0001*/
744        set_panel_reg(jzfb, 0x0404, 0x0000); /*Base Image Vertical Scroll Control 0x0000*/
745        set_panel_reg(jzfb, 0x0500, 0x0000); /*Partial Image 1: Display Position*/
746        set_panel_reg(jzfb, 0x0501, 0x0000); /*RAM Address (Start Line Address) */
747        set_panel_reg(jzfb, 0x0502, 0x018f); /*RAM Address (End Line Address) */
748        set_panel_reg(jzfb, 0x0503, 0x0000); /*Partial Image 2: Display Position RAM Address*/
749        set_panel_reg(jzfb, 0x0504, 0x0000); /*RAM Address (Start Line Address) */
750        set_panel_reg(jzfb, 0x0505, 0x0000); /*RAM Address (End Line Address)*/
751        /*Panel interface control===*/
752        set_panel_reg(jzfb, 0x0010, 0x0011); /*Division Ratio,Clocks per Line 14 */
753        mdelay(10);
754        set_panel_reg(jzfb, 0x0011, 0x0202); /*Division Ratio,Clocks per Line*/
755        set_panel_reg(jzfb, 0x0012, 0x0300); /*Sets low power VCOM drive period. */
756        mdelay(10);
757        set_panel_reg(jzfb, 0x0020, 0x021e); /*Panel Interface Control 4 */
758        set_panel_reg(jzfb, 0x0021, 0x0202); /*Panel Interface Control 5 */
759        set_panel_reg(jzfb, 0x0022, 0x0100); /*Panel Interface Control 6*/
760        set_panel_reg(jzfb, 0x0090, 0x0000); /*Frame Marker Control */
761        set_panel_reg(jzfb, 0x0092, 0x0000); /*MDDI Sub-display Control */
762        /*===Gamma setting=== */
763        set_panel_reg(jzfb, 0x0300, 0x0101); /*γ Control*/
764        set_panel_reg(jzfb, 0x0301, 0x0000); /*γ Control*/
765        set_panel_reg(jzfb, 0x0302, 0x0016); /*γ Control*/
766        set_panel_reg(jzfb, 0x0303, 0x2913); /*γ Control*/
767        set_panel_reg(jzfb, 0x0304, 0x260B); /*γ Control*/
768        set_panel_reg(jzfb, 0x0305, 0x0101); /*γ Control*/
769        set_panel_reg(jzfb, 0x0306, 0x1204); /*γ Control*/
770        set_panel_reg(jzfb, 0x0307, 0x0415); /*γ Control*/
771        set_panel_reg(jzfb, 0x0308, 0x0205); /*γ Control*/
772        set_panel_reg(jzfb, 0x0309, 0x0303); /*γ Control*/
773        set_panel_reg(jzfb, 0x030a, 0x0E05); /*γ Control*/
774        set_panel_reg(jzfb, 0x030b, 0x0D01); /*γ Control*/
775        set_panel_reg(jzfb, 0x030c, 0x010D); /*γ Control*/
776        set_panel_reg(jzfb, 0x030d, 0x050E); /*γ Control*/
777        set_panel_reg(jzfb, 0x030e, 0x0303); /*γ Control*/
778        set_panel_reg(jzfb, 0x030f, 0x0502); /*γ Control*/
779        /*===Power on sequence===*/
780        set_panel_reg(jzfb, 0x0007, 0x0001); /*Display Control 1*/
781        set_panel_reg(jzfb, 0x0110, 0x0001); /*Power supply startup enable bit*/
782        set_panel_reg(jzfb, 0x0112, 0x0060); /*Power Control 7*/
783        set_panel_reg(jzfb, 0x0100, 0x16B0); /*Power Control 1 */
784        set_panel_reg(jzfb, 0x0101, 0x0115); /*Power Control 2*/
785        set_panel_reg(jzfb, 0x0102, 0x0119); /*Starts VLOUT3,Sets the VREG1OUT.*/
786        mdelay(50);
787        set_panel_reg(jzfb, 0x0103, 0x2E00); /*set the amplitude of VCOM*/
788        mdelay(50);
789        set_panel_reg(jzfb, 0x0282, 0x0093); /*VCOMH voltage, alt: 0x008E, 0x0093*/
790        set_panel_reg(jzfb, 0x0281, 0x000A); /*Selects the factor of VREG1OUT to generate VCOMH. */
791        set_panel_reg(jzfb, 0x0102, 0x01BE); /*Starts VLOUT3,Sets the VREG1OUT.*/
792        mdelay(10);
793        /*Address */
794        set_panel_reg(jzfb, 0x0210, 0x0000); /*Window Horizontal RAM Address Start*/
795        set_panel_reg(jzfb, 0x0211, 0x00ef); /*Window Horizontal RAM Address End*/
796        set_panel_reg(jzfb, 0x0212, 0x0000); /*Window Vertical RAM Address Start*/
797        set_panel_reg(jzfb, 0x0213, 0x018f); /*Window Vertical RAM Address End */
798        set_panel_reg(jzfb, 0x0200, 0x0000); /*RAM Address Set (Horizontal Address)*/
799        set_panel_reg(jzfb, 0x0201, 0x018f); /*RAM Address Set (Vertical Address)*/
800        /*===Display_On_Function===*/
801        set_panel_reg(jzfb, 0x0007, 0x0021); /*Display Control 1 */
802        mdelay(50); /*40*/
803        set_panel_reg(jzfb, 0x0007, 0x0061); /*Display Control 1 */
804        mdelay(50); /*100*/
805        set_panel_reg(jzfb, 0x0007, 0x0173); /*Display Control 1 */
806        mdelay(50); /*300*/
807    }
808    send_panel_command(jzfb, 0x0202); /*Write Data to GRAM */
809    udelay(10);
810    spfd5420a_set_addr(jzfb, 0, 0);
811    udelay(100);
812}
813
814static void spfd5420a_disable(struct jzfb *jzfb)
815{
816}
817
818453#endif
819454
820455static const struct jz_slcd_panel jz_slcd_panels[] = {
...... 
839474        "ili9338",
840475    },
841476#endif
842#ifdef CONFIG_JZ_SLCD_LGDP4551
843    {
844        lgdp4551_init, lgdp4551_exit,
845        lgdp4551_enable, lgdp4551_disable,
846        "lgdp4551",
847    },
848#endif
849#ifdef CONFIG_JZ_SLCD_SPFD5420A
850    {
851        spfd5420a_init, spfd5420a_exit,
852        spfd5420a_enable, spfd5420a_disable,
853        "spfd5420a",
854    },
855#endif
856477};
857478
858479static int __init jz_slcd_panels_setup(char *this_opt)

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