Date:2012-09-02 11:52:29 (8 years 2 months ago)
Author:Thierry Reding
Commit:e92c37116eabe2cb75f6325c2bc794b3f0457672
Message:MIPS: JZ4740: Export timer API

This is a prerequisite for allowing the PWM driver to be converted to
the PWM framework.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Files: arch/mips/include/asm/mach-jz4740/timer.h (1 diff)
arch/mips/jz4740/time.c (1 diff)
arch/mips/jz4740/timer.c (2 diffs)
arch/mips/jz4740/timer.h (1 diff)

Change Details

arch/mips/include/asm/mach-jz4740/timer.h
1616#ifndef __ASM_MACH_JZ4740_TIMER
1717#define __ASM_MACH_JZ4740_TIMER
1818
19#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
20#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
21#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
22#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
23#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
24#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
25#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
26#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
27#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
28#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
29#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
30
31#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
32
33#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
34#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
35#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
36
37void __init jz4740_timer_init(void);
38
39void jz4740_timer_stop(unsigned int timer);
40void jz4740_timer_start(unsigned int timer);
41bool jz4740_timer_is_enabled(unsigned int timer);
42void jz4740_timer_enable(unsigned int timer);
43void jz4740_timer_disable(unsigned int timer);
44void jz4740_timer_set_period(unsigned int timer, uint16_t period);
45void jz4740_timer_set_duty(unsigned int timer, uint16_t duty);
46void jz4740_timer_set_count(unsigned int timer, uint16_t count);
47uint16_t jz4740_timer_get_count(unsigned int timer);
48void jz4740_timer_ack_full(unsigned int timer);
49void jz4740_timer_irq_full_enable(unsigned int timer);
50void jz4740_timer_irq_full_disable(unsigned int timer);
51uint16_t jz4740_timer_get_ctrl(unsigned int timer);
52void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl);
53
1954void jz4740_timer_enable_watchdog(void);
2055void jz4740_timer_disable_watchdog(void);
2156
arch/mips/jz4740/time.c
2020#include <linux/clockchips.h>
2121
2222#include <asm/mach-jz4740/irq.h>
23#include <asm/mach-jz4740/timer.h>
2324#include <asm/time.h>
2425
2526#include "clock.h"
26#include "timer.h"
2727
2828#define TIMER_CLOCKEVENT 0
2929#define TIMER_CLOCKSOURCE 1
arch/mips/jz4740/timer.c
2121
2222#include <asm/mach-jz4740/base.h>
2323
24void __iomem *jz4740_timer_base;
24#define JZ_REG_TIMER_STOP 0x0C
25#define JZ_REG_TIMER_STOP_SET 0x1C
26#define JZ_REG_TIMER_STOP_CLEAR 0x2C
27#define JZ_REG_TIMER_ENABLE 0x00
28#define JZ_REG_TIMER_ENABLE_SET 0x04
29#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
30#define JZ_REG_TIMER_FLAG 0x10
31#define JZ_REG_TIMER_FLAG_SET 0x14
32#define JZ_REG_TIMER_FLAG_CLEAR 0x18
33#define JZ_REG_TIMER_MASK 0x20
34#define JZ_REG_TIMER_MASK_SET 0x24
35#define JZ_REG_TIMER_MASK_CLEAR 0x28
2536
26void jz4740_timer_enable_watchdog(void)
27{
28    writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
29}
30EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog);
37#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
38#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
39#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
40#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
3141
32void jz4740_timer_disable_watchdog(void)
33{
34    writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
35}
36EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog);
42#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
43#define JZ_TIMER_IRQ_FULL(x) BIT(x)
44
45void __iomem *jz4740_timer_base;
3746
3847void __init jz4740_timer_init(void)
3948{
...... 
4857    /* Timer irqs are unmasked by default, mask them */
4958    writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
5059}
60
61void jz4740_timer_stop(unsigned int timer)
62{
63    writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
64}
65EXPORT_SYMBOL_GPL(jz4740_timer_stop);
66
67void jz4740_timer_start(unsigned int timer)
68{
69    writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
70}
71EXPORT_SYMBOL_GPL(jz4740_timer_start);
72
73bool jz4740_timer_is_enabled(unsigned int timer)
74{
75    return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
76}
77EXPORT_SYMBOL_GPL(jz4740_timer_is_enabled);
78
79void jz4740_timer_enable(unsigned int timer)
80{
81    writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
82}
83EXPORT_SYMBOL_GPL(jz4740_timer_enable);
84
85void jz4740_timer_disable(unsigned int timer)
86{
87    writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
88}
89EXPORT_SYMBOL_GPL(jz4740_timer_disable);
90
91void jz4740_timer_set_period(unsigned int timer, uint16_t period)
92{
93    writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
94}
95EXPORT_SYMBOL_GPL(jz4740_timer_set_period);
96
97void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
98{
99    writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
100}
101EXPORT_SYMBOL_GPL(jz4740_timer_set_duty);
102
103void jz4740_timer_set_count(unsigned int timer, uint16_t count)
104{
105    writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
106}
107EXPORT_SYMBOL_GPL(jz4740_timer_set_count);
108
109uint16_t jz4740_timer_get_count(unsigned int timer)
110{
111    return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
112}
113EXPORT_SYMBOL_GPL(jz4740_timer_get_count);
114
115void jz4740_timer_ack_full(unsigned int timer)
116{
117    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
118}
119EXPORT_SYMBOL_GPL(jz4740_timer_ack_full);
120
121void jz4740_timer_irq_full_enable(unsigned int timer)
122{
123    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
124    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
125}
126EXPORT_SYMBOL_GPL(jz4740_timer_irq_full_enable);
127
128void jz4740_timer_irq_full_disable(unsigned int timer)
129{
130    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
131}
132EXPORT_SYMBOL_GPL(jz4740_timer_irq_full_disable);
133
134void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
135{
136    writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
137}
138EXPORT_SYMBOL_GPL(jz4740_timer_set_ctrl);
139
140uint16_t jz4740_timer_get_ctrl(unsigned int timer)
141{
142    return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
143}
144EXPORT_SYMBOL_GPL(jz4740_timer_get_ctrl);
145
146void jz4740_timer_enable_watchdog(void)
147{
148    writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
149}
150EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog);
151
152void jz4740_timer_disable_watchdog(void)
153{
154    writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
155}
156EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog);
arch/mips/jz4740/timer.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __MIPS_JZ4740_TIMER_H__
17#define __MIPS_JZ4740_TIMER_H__
18
19#include <linux/module.h>
20#include <linux/io.h>
21
22#define JZ_REG_TIMER_STOP 0x0C
23#define JZ_REG_TIMER_STOP_SET 0x1C
24#define JZ_REG_TIMER_STOP_CLEAR 0x2C
25#define JZ_REG_TIMER_ENABLE 0x00
26#define JZ_REG_TIMER_ENABLE_SET 0x04
27#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
28#define JZ_REG_TIMER_FLAG 0x10
29#define JZ_REG_TIMER_FLAG_SET 0x14
30#define JZ_REG_TIMER_FLAG_CLEAR 0x18
31#define JZ_REG_TIMER_MASK 0x20
32#define JZ_REG_TIMER_MASK_SET 0x24
33#define JZ_REG_TIMER_MASK_CLEAR 0x28
34
35#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
36#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
37#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
38#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
39
40#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
41#define JZ_TIMER_IRQ_FULL(x) BIT(x)
42
43#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
44#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
45#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
46#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
47#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
48#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
49#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
50#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
51#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
52#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
53#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
54
55#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
56
57#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
58#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
59#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
60
61extern void __iomem *jz4740_timer_base;
62void __init jz4740_timer_init(void);
63
64static inline void jz4740_timer_stop(unsigned int timer)
65{
66    writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
67}
68
69static inline void jz4740_timer_start(unsigned int timer)
70{
71    writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
72}
73
74static inline bool jz4740_timer_is_enabled(unsigned int timer)
75{
76    return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
77}
78
79static inline void jz4740_timer_enable(unsigned int timer)
80{
81    writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
82}
83
84static inline void jz4740_timer_disable(unsigned int timer)
85{
86    writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
87}
88
89
90static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
91{
92    writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
93}
94
95static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
96{
97    writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
98}
99
100static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
101{
102    writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
103}
104
105static inline uint16_t jz4740_timer_get_count(unsigned int timer)
106{
107    return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
108}
109
110static inline void jz4740_timer_ack_full(unsigned int timer)
111{
112    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
113}
114
115static inline void jz4740_timer_irq_full_enable(unsigned int timer)
116{
117    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
118    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
119}
120
121static inline void jz4740_timer_irq_full_disable(unsigned int timer)
122{
123    writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
124}
125
126static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
127{
128    writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
129}
130
131static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
132{
133    return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
134}
135
136#endif

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