Date:2010-04-24 12:18:01 (10 years 4 months ago)
Author:Lars C.
Commit:eee7787c6db1fe8df2da02a0b4917fb3c5c8c5d4
Message:Add jz4740 adc driver

Files: drivers/misc/Kconfig (1 diff)
drivers/misc/Makefile (1 diff)
drivers/misc/jz4740-adc.c (1 diff)
include/linux/jz4740-adc.h (1 diff)

Change Details

drivers/misc/Kconfig
327327      To compile this driver as a module, choose M here: the
328328      module will be called vmware_balloon.
329329
330config JZ4740_ADC
331    tristate "Ingenic JZ4720/JZ4740 SoC ADC driver"
332    depends on SOC_JZ4740
333    help
334      If you say yes here you get support for the Ingenic JZ4720/JZ4740 SoC ADC
335      core. It is required for the JZ4720/JZ4740 battery and touchscreen driver
336      and is used to synchronize access to the adc core between those two.
337
338      This driver can also be build as a module. If so, the module will be
339      called jz4740-adc.
340
330341source "drivers/misc/c2port/Kconfig"
331342source "drivers/misc/eeprom/Kconfig"
332343source "drivers/misc/cb710/Kconfig"
drivers/misc/Makefile
2727obj-$(CONFIG_TI_DAC7512) += ti_dac7512.o
2828obj-$(CONFIG_C2PORT) += c2port/
2929obj-$(CONFIG_IWMC3200TOP) += iwmc3200top/
30obj-$(CONFIG_JZ4740_ADC) += jz4740-adc.o
3031obj-y += eeprom/
3132obj-y += cb710/
3233obj-$(CONFIG_VMWARE_BALLOON) += vmware_balloon.o
drivers/misc/jz4740-adc.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC ADC driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 * This driver is meant to synchronize access to the adc core for the battery
15 * and touchscreen driver. Thus these drivers should use the adc driver as a
16 * parent.
17 */
18
19#include <linux/err.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/spinlock.h>
25#include <linux/interrupt.h>
26
27#include <linux/clk.h>
28
29#include <linux/jz4740-adc.h>
30
31#define JZ_REG_ADC_ENABLE 0x00
32#define JZ_REG_ADC_CFG 0x04
33#define JZ_REG_ADC_CTRL 0x08
34#define JZ_REG_ADC_STATUS 0x0C
35#define JZ_REG_ADC_SAME 0x10
36#define JZ_REG_ADC_WAIT 0x14
37#define JZ_REG_ADC_TOUCH 0x18
38#define JZ_REG_ADC_BATTERY 0x1C
39#define JZ_REG_ADC_ADCIN 0x20
40
41#define JZ_ADC_ENABLE_TOUCH BIT(2)
42#define JZ_ADC_ENABLE_BATTERY BIT(1)
43#define JZ_ADC_ENABLE_ADCIN BIT(0)
44
45#define JZ_ADC_CFG_SPZZ BIT(31)
46#define JZ_ADC_CFG_EX_IN BIT(30)
47#define JZ_ADC_CFG_DNUM_MASK (0x7 << 16)
48#define JZ_ADC_CFG_DMA_ENABLE BIT(15)
49#define JZ_ADC_CFG_XYZ_MASK (0x2 << 13)
50#define JZ_ADC_CFG_SAMPLE_NUM_MASK (0x7 << 10)
51#define JZ_ADC_CFG_CLKDIV (0xf << 5)
52#define JZ_ADC_CFG_BAT_MB BIT(4)
53
54#define JZ_ADC_CFG_DNUM_OFFSET 16
55#define JZ_ADC_CFG_XYZ_OFFSET 13
56#define JZ_ADC_CFG_SAMPLE_NUM_OFFSET 10
57#define JZ_ADC_CFG_CLKDIV_OFFSET 5
58
59#define JZ_ADC_IRQ_PENDOWN BIT(4)
60#define JZ_ADC_IRQ_PENUP BIT(3)
61#define JZ_ADC_IRQ_TOUCH BIT(2)
62#define JZ_ADC_IRQ_BATTERY BIT(1)
63#define JZ_ADC_IRQ_ADCIN BIT(0)
64
65#define JZ_ADC_TOUCH_TYPE1 BIT(31)
66#define JZ_ADC_TOUCH_DATA1_MASK 0xfff
67#define JZ_ADC_TOUCH_TYPE0 BIT(15)
68#define JZ_ADC_TOUCH_DATA0_MASK 0xfff
69
70#define JZ_ADC_BATTERY_MASK 0xfff
71
72#define JZ_ADC_ADCIN_MASK 0xfff
73
74struct jz4740_adc {
75    struct resource *mem;
76    void __iomem *base;
77
78    int irq;
79
80    struct clk *clk;
81    unsigned int clk_ref;
82
83    struct completion bat_completion;
84    struct completion adc_completion;
85
86    spinlock_t lock;
87};
88
89static irqreturn_t jz4740_adc_irq(int irq, void *data)
90{
91    struct jz4740_adc *adc = data;
92    uint8_t status;
93
94    status = readb(adc->base + JZ_REG_ADC_STATUS);
95
96    if (status & JZ_ADC_IRQ_BATTERY)
97        complete(&adc->bat_completion);
98    if (status & JZ_ADC_IRQ_ADCIN)
99        complete(&adc->adc_completion);
100
101    writeb(0xff, adc->base + JZ_REG_ADC_STATUS);
102
103    return IRQ_HANDLED;
104}
105
106static void jz4740_adc_enable_irq(struct jz4740_adc *adc, int irq)
107{
108    unsigned long flags;
109    uint8_t val;
110
111    spin_lock_irqsave(&adc->lock, flags);
112
113    val = readb(adc->base + JZ_REG_ADC_CTRL);
114    val &= ~irq;
115    writeb(val, adc->base + JZ_REG_ADC_CTRL);
116
117    spin_unlock_irqrestore(&adc->lock, flags);
118}
119
120static void jz4740_adc_disable_irq(struct jz4740_adc *adc, int irq)
121{
122    unsigned long flags;
123    uint8_t val;
124
125    spin_lock_irqsave(&adc->lock, flags);
126
127    val = readb(adc->base + JZ_REG_ADC_CTRL);
128    val |= irq;
129    writeb(val, adc->base + JZ_REG_ADC_CTRL);
130
131    spin_unlock_irqrestore(&adc->lock, flags);
132}
133
134static void jz4740_adc_enable_adc(struct jz4740_adc *adc, int engine)
135{
136    unsigned long flags;
137    uint8_t val;
138
139    spin_lock_irqsave(&adc->lock, flags);
140
141    val = readb(adc->base + JZ_REG_ADC_ENABLE);
142    val |= engine;
143    writeb(val, adc->base + JZ_REG_ADC_ENABLE);
144
145    spin_unlock_irqrestore(&adc->lock, flags);
146}
147
148static void jz4740_adc_disable_adc(struct jz4740_adc *adc, int engine)
149{
150    unsigned long flags;
151    uint8_t val;
152
153    spin_lock_irqsave(&adc->lock, flags);
154
155    val = readb(adc->base + JZ_REG_ADC_ENABLE);
156    val &= ~engine;
157    writeb(val, adc->base + JZ_REG_ADC_ENABLE);
158
159    spin_unlock_irqrestore(&adc->lock, flags);
160}
161
162static inline void jz4740_adc_set_cfg(struct jz4740_adc *adc, uint32_t mask,
163uint32_t val)
164{
165    unsigned long flags;
166    uint32_t cfg;
167
168    spin_lock_irqsave(&adc->lock, flags);
169
170    cfg = readl(adc->base + JZ_REG_ADC_CFG);
171
172    cfg &= ~mask;
173    cfg |= val;
174
175    writel(cfg, adc->base + JZ_REG_ADC_CFG);
176
177    spin_unlock_irqrestore(&adc->lock, flags);
178}
179
180static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
181{
182    unsigned long flags;
183
184    spin_lock_irqsave(&adc->lock, flags);
185    if (adc->clk_ref++ == 0)
186        clk_enable(adc->clk);
187    spin_unlock_irqrestore(&adc->lock, flags);
188}
189
190static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
191{
192    unsigned long flags;
193
194    spin_lock_irqsave(&adc->lock, flags);
195    if (--adc->clk_ref == 0)
196        clk_disable(adc->clk);
197    spin_unlock_irqrestore(&adc->lock, flags);
198}
199
200long jz4740_adc_read_battery_voltage(struct device *dev,
201                        enum jz_adc_battery_scale scale)
202{
203    struct jz4740_adc *adc = dev_get_drvdata(dev);
204    unsigned long t;
205    long long voltage;
206    uint16_t val;
207
208    if (!adc)
209        return -ENODEV;
210
211    jz4740_adc_clk_enable(adc);
212
213    if (scale == JZ_ADC_BATTERY_SCALE_2V5)
214        jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, JZ_ADC_CFG_BAT_MB);
215    else
216        jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, 0);
217
218    jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_BATTERY);
219    jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_BATTERY);
220
221    t = wait_for_completion_interruptible_timeout(&adc->bat_completion,
222                            HZ);
223
224    jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_BATTERY);
225
226    if (t <= 0) {
227        jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_BATTERY);
228        return t ? t : -ETIMEDOUT;
229    }
230
231    val = readw(adc->base + JZ_REG_ADC_BATTERY);
232
233    jz4740_adc_clk_disable(adc);
234
235    if (scale == JZ_ADC_BATTERY_SCALE_2V5)
236        voltage = (((long long)val) * 2500000LL) >> 12LL;
237    else
238        voltage = ((((long long)val) * 7395000LL) >> 12LL) + 33000LL;
239
240    return voltage;
241}
242EXPORT_SYMBOL_GPL(jz4740_adc_read_battery_voltage);
243
244static ssize_t jz4740_adc_read_adcin(struct device *dev,
245                    struct device_attribute *dev_attr,
246                    char *buf)
247{
248    struct jz4740_adc *adc = dev_get_drvdata(dev);
249    unsigned long t;
250    uint16_t val;
251
252    jz4740_adc_clk_enable(adc);
253
254    jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_ADCIN);
255    jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_ADCIN);
256
257    t = wait_for_completion_interruptible_timeout(&adc->adc_completion,
258                            HZ);
259
260    jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_ADCIN);
261
262    if (t <= 0) {
263        jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_ADCIN);
264        return t ? t : -ETIMEDOUT;
265    }
266
267    val = readw(adc->base + JZ_REG_ADC_ADCIN);
268    jz4740_adc_clk_disable(adc);
269
270    return sprintf(buf, "%d\n", val);
271}
272
273static DEVICE_ATTR(adcin, S_IRUGO, jz4740_adc_read_adcin, NULL);
274
275static int __devinit jz4740_adc_probe(struct platform_device *pdev)
276{
277    int ret;
278    struct jz4740_adc *adc;
279
280    adc = kmalloc(sizeof(*adc), GFP_KERNEL);
281
282    adc->irq = platform_get_irq(pdev, 0);
283
284    if (adc->irq < 0) {
285        ret = adc->irq;
286        dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
287        goto err_free;
288    }
289
290    adc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
291
292    if (!adc->mem) {
293        ret = -ENOENT;
294        dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
295        goto err_free;
296    }
297
298    adc->mem = request_mem_region(adc->mem->start, resource_size(adc->mem),
299                    pdev->name);
300
301    if (!adc->mem) {
302        ret = -EBUSY;
303        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
304        goto err_free;
305    }
306
307    adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
308
309    if (!adc->base) {
310        ret = -EBUSY;
311        dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
312        goto err_release_mem_region;
313    }
314
315    adc->clk = clk_get(&pdev->dev, "adc");
316
317    if (IS_ERR(adc->clk)) {
318        ret = PTR_ERR(adc->clk);
319        dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
320        goto err_iounmap;
321    }
322
323    init_completion(&adc->bat_completion);
324    init_completion(&adc->adc_completion);
325
326    spin_lock_init(&adc->lock);
327
328    adc->clk_ref = 0;
329
330    platform_set_drvdata(pdev, adc);
331
332    ret = request_irq(adc->irq, jz4740_adc_irq, 0, pdev->name, adc);
333
334    if (ret) {
335        dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
336        goto err_clk_put;
337    }
338
339    ret = device_create_file(&pdev->dev, &dev_attr_adcin);
340    if (ret) {
341        dev_err(&pdev->dev, "Failed to create sysfs file: %d\n", ret);
342        goto err_free_irq;
343    }
344
345    writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
346    writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
347
348    return 0;
349
350err_free_irq:
351    free_irq(adc->irq, adc);
352err_clk_put:
353    clk_put(adc->clk);
354err_iounmap:
355    platform_set_drvdata(pdev, NULL);
356    iounmap(adc->base);
357err_release_mem_region:
358    release_mem_region(adc->mem->start, resource_size(adc->mem));
359err_free:
360    kfree(adc);
361
362    return ret;
363}
364
365static int __devexit jz4740_adc_remove(struct platform_device *pdev)
366{
367    struct jz4740_adc *adc = platform_get_drvdata(pdev);
368
369    device_remove_file(&pdev->dev, &dev_attr_adcin);
370
371    free_irq(adc->irq, adc);
372
373    iounmap(adc->base);
374    release_mem_region(adc->mem->start, resource_size(adc->mem));
375
376    clk_put(adc->clk);
377
378    platform_set_drvdata(pdev, NULL);
379
380    kfree(adc);
381
382    return 0;
383}
384
385struct platform_driver jz4740_adc_driver = {
386    .probe = jz4740_adc_probe,
387    .remove = jz4740_adc_remove,
388    .driver = {
389        .name = "jz4740-adc",
390        .owner = THIS_MODULE,
391    },
392};
393
394static int __init jz4740_adc_init(void)
395{
396    return platform_driver_register(&jz4740_adc_driver);
397}
398module_init(jz4740_adc_init);
399
400static void __exit jz4740_adc_exit(void)
401{
402    platform_driver_unregister(&jz4740_adc_driver);
403}
404module_exit(jz4740_adc_exit);
405
406MODULE_DESCRIPTION("JZ4720/JZ4740 SoC ADC driver");
407MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
408MODULE_LICENSE("GPL");
409MODULE_ALIAS("platform:jz4740-adc");
410MODULE_ALIAS("platform:jz4720-adc");
include/linux/jz4740-adc.h
1
2#ifndef __LINUX_JZ4740_ADC
3#define __LINUX_JZ4740_ADC
4
5#include <linux/device.h>
6
7enum jz_adc_battery_scale {
8    JZ_ADC_BATTERY_SCALE_2V5, /* Mesures voltages up to 2.5V */
9    JZ_ADC_BATTERY_SCALE_7V5, /* Mesures voltages up to 7.5V */
10};
11
12/*
13 * jz4740_adc_read_battery_voltage - Read battery voltage from the ADC PBAT pin
14 * @dev: Pointer to a jz4740-adc device
15 * @scale: Whether to use 2.5V or 7.5V scale
16 *
17 * Returns: Battery voltage in mircovolts
18 *
19 * Context: Process
20*/
21long jz4740_adc_read_battery_voltage(struct device *dev,
22                    enum jz_adc_battery_scale scale);
23
24
25#endif

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