Date:2009-12-01 07:54:55 (14 years 3 months ago)
Author:xiangfu
Commit:ef60fc3200a68f7ebd2a5a9fff585073f233bb5e
Message:file

Files: arch/mips/boot/compressed/Makefile (1 diff)
arch/mips/boot/compressed/dummy.c (1 diff)
arch/mips/boot/compressed/head.S (1 diff)
arch/mips/boot/compressed/ld.script (1 diff)
arch/mips/boot/compressed/misc.c (1 diff)
arch/mips/boot/tools/entry (1 diff)
arch/mips/boot/tools/filesize (1 diff)
arch/mips/include/asm/mach-jz4740/board-qi_lb60.h (1 diff)
arch/mips/include/asm/mach-jz4740/clock.h (1 diff)
arch/mips/include/asm/mach-jz4740/dma.h (1 diff)
arch/mips/include/asm/mach-jz4740/gpio.h (1 diff)
arch/mips/include/asm/mach-jz4740/irq.h (1 diff)
arch/mips/include/asm/mach-jz4740/jz4740.h (1 diff)
arch/mips/include/asm/mach-jz4740/ops.h (1 diff)
arch/mips/include/asm/mach-jz4740/platform.h (1 diff)
arch/mips/include/asm/mach-jz4740/regs.h (1 diff)
arch/mips/include/asm/mach-jz4740/serial.h (1 diff)
arch/mips/include/asm/mach-jz4740/war.h (1 diff)
arch/mips/jz4740/Kconfig (1 diff)
arch/mips/jz4740/Makefile (1 diff)
arch/mips/jz4740/board-qi_lb60.c (1 diff)
arch/mips/jz4740/clock.c (1 diff)
arch/mips/jz4740/cpufreq.c (1 diff)
arch/mips/jz4740/dma.c (1 diff)
arch/mips/jz4740/gpio.c (1 diff)
arch/mips/jz4740/irq.c (1 diff)
arch/mips/jz4740/platform.c (1 diff)
arch/mips/jz4740/pm.c (1 diff)
arch/mips/jz4740/proc.c (1 diff)
arch/mips/jz4740/prom.c (1 diff)
arch/mips/jz4740/reset.c (1 diff)
arch/mips/jz4740/setup.c (1 diff)
arch/mips/jz4740/time.c (1 diff)
drivers/misc/jz4740-adc.c (1 diff)
drivers/mmc/host/jz_mmc.c (1 diff)
drivers/mtd/nand/jz4740_nand.c (1 diff)
drivers/power/jz4740-battery.c (1 diff)
drivers/rtc/rtc-jz4740.c (1 diff)
drivers/usb/gadget/jz4740_udc.c (1 diff)
drivers/usb/gadget/jz4740_udc.h (1 diff)
drivers/usb/gadget/udc_hotplug.h (1 diff)
drivers/usb/gadget/udc_hotplug_core.c (1 diff)
drivers/video/backlight/gpm940b0.c (1 diff)
drivers/video/jz4740_fb.c (1 diff)
include/linux/jz4740-adc.h (1 diff)
include/linux/jz4740_fb.h (1 diff)
include/linux/mmc/jz4740_mmc.h (1 diff)
include/linux/mtd/jz4740_nand.h (1 diff)
include/linux/power/jz4740-battery.h (1 diff)
sound/soc/codecs/jzcodec.c (1 diff)
sound/soc/codecs/jzcodec.h (1 diff)
sound/soc/jz4740/Kconfig (1 diff)
sound/soc/jz4740/Makefile (1 diff)
sound/soc/jz4740/jz4740-i2s.c (1 diff)
sound/soc/jz4740/jz4740-i2s.h (1 diff)
sound/soc/jz4740/jz4740-pcm.c (1 diff)
sound/soc/jz4740/jz4740-pcm.h (1 diff)
sound/soc/jz4740/qi_lb60.c (1 diff)

Change Details

arch/mips/boot/compressed/Makefile
1#
2# linux/arch/mips/boot/compressed/Makefile
3#
4# create a compressed zImage from the original vmlinux
5#
6
7targets := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o
8
9OBJS := $(obj)/head.o $(obj)/misc.o
10
11LD_ARGS := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic
12OBJCOPY_ARGS := -O elf32-tradlittlemips
13
14ENTRY := $(obj)/../tools/entry
15FILESIZE := $(obj)/../tools/filesize
16
17drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
18strip-flags = $(addprefix --remove-section=,$(drop-sections))
19
20
21$(obj)/vmlinux.bin.gz: vmlinux
22    rm -f $(obj)/vmlinux.bin.gz
23    $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin
24    gzip -v9f $(obj)/vmlinux.bin
25
26$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux
27    $(CC) $(KBUILD_AFLAGS) \
28    -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \
29    -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \
30    -DLOADADDR=$(loadaddr) \
31    -c -o $(obj)/head.o $<
32
33$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o
34    $(OBJCOPY) \
35        --add-section=.image=$(obj)/vmlinux.bin.gz \
36        --set-section-flags=.image=contents,alloc,load,readonly,data \
37        $(obj)/dummy.o $(obj)/piggy.o
38    $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o
39    $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap
40
41zImage: $(obj)/vmlinuz
42    $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage
arch/mips/boot/compressed/dummy.c
1int main(void)
2{
3    return 0;
4}
arch/mips/boot/compressed/head.S
1/*
2 * linux/arch/mips/boot/compressed/head.S
3 *
4 * Copyright (C) 2005-2008 Ingenic Semiconductor Inc.
5 */
6
7#include <asm/asm.h>
8#include <asm/cacheops.h>
9#include <asm/cachectl.h>
10#include <asm/regdef.h>
11
12#define IndexInvalidate_I 0x00
13#define IndexWriteBack_D 0x01
14
15    .set noreorder
16    LEAF(startup)
17startup:
18    move s0, a0 /* Save the boot loader transfered args */
19    move s1, a1
20    move s2, a2
21    move s3, a3
22
23    la a0, _edata
24    la a1, _end
251: sw zero, 0(a0) /* Clear BSS section */
26    bne a1, a0, 1b
27    addu a0, 4
28
29    la sp, (.stack + 8192)
30
31    la a0, __image_begin
32    la a1, IMAGESIZE
33    la a2, LOADADDR
34    la ra, 1f
35    la k0, decompress_kernel
36    jr k0
37    nop
381:
39
40    move a0, s0
41    move a1, s1
42    move a2, s2
43    move a3, s3
44    li k0, KERNEL_ENTRY
45    jr k0
46    nop
472:
48    b 32
49    END(startup)
50
51
52    LEAF(flushcaches)
53    la t0, 1f
54    la t1, 0xa0000000
55    or t0, t0, t1
56    jr t0
57    nop
581:
59    li k0, 0x80000000 # start address
60    li k1, 0x80004000 # end address (16KB I-Cache)
61    subu k1, 128
62
632:
64    .set mips3
65    cache IndexWriteBack_D, 0(k0)
66    cache IndexWriteBack_D, 32(k0)
67    cache IndexWriteBack_D, 64(k0)
68    cache IndexWriteBack_D, 96(k0)
69    cache IndexInvalidate_I, 0(k0)
70    cache IndexInvalidate_I, 32(k0)
71    cache IndexInvalidate_I, 64(k0)
72    cache IndexInvalidate_I, 96(k0)
73    .set mips0
74
75    bne k0, k1, 2b
76    addu k0, k0, 128
77    la t0, 3f
78    jr t0
79    nop
803:
81    jr ra
82    nop
83    END(flushcaches)
84
85    .comm .stack,4096*2,4
arch/mips/boot/compressed/ld.script
1OUTPUT_ARCH(mips)
2ENTRY(startup)
3SECTIONS
4{
5  /* Read-only sections, merged into text segment: */
6
7  .init : { *(.init) } =0
8  .text :
9  {
10    _ftext = . ;
11    *(.text)
12    *(.rodata)
13    *(.rodata1)
14    /* .gnu.warning sections are handled specially by elf32.em. */
15    *(.gnu.warning)
16  } =0
17  .kstrtab : { *(.kstrtab) }
18
19  . = ALIGN(16); /* Exception table */
20  __start___ex_table = .;
21  __ex_table : { *(__ex_table) }
22  __stop___ex_table = .;
23
24  __start___dbe_table = .; /* Exception table for data bus errors */
25  __dbe_table : { *(__dbe_table) }
26  __stop___dbe_table = .;
27
28  __start___ksymtab = .; /* Kernel symbol table */
29  __ksymtab : { *(__ksymtab) }
30  __stop___ksymtab = .;
31
32  _etext = .;
33
34  . = ALIGN(8192);
35  .data.init_task : { *(.data.init_task) }
36
37  /* Startup code */
38  . = ALIGN(4096);
39  __init_begin = .;
40  .text.init : { *(.text.init) }
41  .data.init : { *(.data.init) }
42  . = ALIGN(16);
43  __setup_start = .;
44  .setup.init : { *(.setup.init) }
45  __setup_end = .;
46  __initcall_start = .;
47  .initcall.init : { *(.initcall.init) }
48  __initcall_end = .;
49  . = ALIGN(4096); /* Align double page for init_task_union */
50  __init_end = .;
51
52  . = ALIGN(4096);
53  .data.page_aligned : { *(.data.idt) }
54
55  . = ALIGN(32);
56  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
57
58  .fini : { *(.fini) } =0
59  .reginfo : { *(.reginfo) }
60  /* Adjust the address for the data segment. We want to adjust up to
61     the same address within the page on the next page up. It would
62     be more correct to do this:
63       . = .;
64     The current expression does not correctly handle the case of a
65     text segment ending precisely at the end of a page; it causes the
66     data segment to skip a page. The above expression does not have
67     this problem, but it will currently (2/95) cause BFD to allocate
68     a single segment, combining both text and data, for this case.
69     This will prevent the text segment from being shared among
70     multiple executions of the program; I think that is more
71     important than losing a page of the virtual address space (note
72     that no actual memory is lost; the page which is skipped can not
73     be referenced). */
74  . = .;
75  .data :
76  {
77    _fdata = . ;
78    *(.data)
79
80   /* Put the compressed image here, so bss is on the end. */
81   __image_begin = .;
82   *(.image)
83   __image_end = .;
84   /* Align the initial ramdisk image (INITRD) on page boundaries. */
85   . = ALIGN(4096);
86   __ramdisk_begin = .;
87   *(.initrd)
88   __ramdisk_end = .;
89   . = ALIGN(4096);
90
91    CONSTRUCTORS
92  }
93  .data1 : { *(.data1) }
94  _gp = . + 0x8000;
95  .lit8 : { *(.lit8) }
96  .lit4 : { *(.lit4) }
97  .ctors : { *(.ctors) }
98  .dtors : { *(.dtors) }
99  .got : { *(.got.plt) *(.got) }
100  .dynamic : { *(.dynamic) }
101  /* We want the small data sections together, so single-instruction offsets
102     can access them all, and initialized data all before uninitialized, so
103     we can shorten the on-disk segment size. */
104  .sdata : { *(.sdata) }
105  . = ALIGN(4);
106  _edata = .;
107  PROVIDE (edata = .);
108
109  __bss_start = .;
110  _fbss = .;
111  .sbss : { *(.sbss) *(.scommon) }
112  .bss :
113  {
114   *(.dynbss)
115   *(.bss)
116   *(COMMON)
117   . = ALIGN(4);
118  _end = . ;
119  PROVIDE (end = .);
120  }
121
122  /* Sections to be discarded */
123  /DISCARD/ :
124  {
125        *(.text.exit)
126        *(.data.exit)
127        *(.exitcall.exit)
128  }
129
130  /* This is the MIPS specific mdebug section. */
131  .mdebug : { *(.mdebug) }
132  /* These are needed for ELF backends which have not yet been
133     converted to the new style linker. */
134  .stab 0 : { *(.stab) }
135  .stabstr 0 : { *(.stabstr) }
136  /* DWARF debug sections.
137     Symbols in the .debug DWARF section are relative to the beginning of the
138     section so we begin .debug at 0. It's not clear yet what needs to happen
139     for the others. */
140  .debug 0 : { *(.debug) }
141  .debug_srcinfo 0 : { *(.debug_srcinfo) }
142  .debug_aranges 0 : { *(.debug_aranges) }
143  .debug_pubnames 0 : { *(.debug_pubnames) }
144  .debug_sfnames 0 : { *(.debug_sfnames) }
145  .line 0 : { *(.line) }
146  /* These must appear regardless of . */
147  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
148  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
149  .comment : { *(.comment) }
150  .note : { *(.note) }
151}
arch/mips/boot/compressed/misc.c
1/*
2 * linux/arch/mips/boot/compressed/misc.c
3 *
4 * This is a collection of several routines from gzip-1.0.3
5 * adapted for Linux.
6 *
7 * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
8 *
9 * Adapted for JZSOC by Peter Wei, 2008
10 *
11 */
12
13#define size_t int
14#define NULL 0
15
16/*
17 * gzip declarations
18 */
19
20#define OF(args) args
21#define STATIC static
22
23#undef memset
24#undef memcpy
25#define memzero(s, n) memset ((s), 0, (n))
26
27typedef unsigned char uch;
28typedef unsigned short ush;
29typedef unsigned long ulg;
30
31#define WSIZE 0x8000 /* Window size must be at least 32k, */
32                /* and a power of two */
33
34static uch *inbuf; /* input buffer */
35static uch window[WSIZE]; /* Sliding window buffer */
36
37static unsigned insize = 0; /* valid bytes in inbuf */
38static unsigned inptr = 0; /* index of next byte to be processed in inbuf */
39static unsigned outcnt = 0; /* bytes in output buffer */
40
41/* gzip flag byte */
42#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
43#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
44#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
45#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
46#define COMMENT 0x10 /* bit 4 set: file comment present */
47#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
48#define RESERVED 0xC0 /* bit 6,7: reserved */
49
50#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
51
52/* Diagnostic functions */
53#ifdef DEBUG
54# define Assert(cond,msg) {if(!(cond)) error(msg);}
55# define Trace(x) fprintf x
56# define Tracev(x) {if (verbose) fprintf x ;}
57# define Tracevv(x) {if (verbose>1) fprintf x ;}
58# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
59# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
60#else
61# define Assert(cond,msg)
62# define Trace(x)
63# define Tracev(x)
64# define Tracevv(x)
65# define Tracec(c,x)
66# define Tracecv(c,x)
67#endif
68
69static int fill_inbuf(void);
70static void flush_window(void);
71static void error(char *m);
72static void gzip_mark(void **);
73static void gzip_release(void **);
74
75void* memset(void* s, int c, size_t n);
76void* memcpy(void* __dest, __const void* __src, size_t __n);
77
78extern void flushcaches(void); /* defined in head.S */
79
80char *input_data;
81int input_len;
82
83static long bytes_out = 0;
84static uch *output_data;
85static unsigned long output_ptr = 0;
86
87
88static void *malloc(int size);
89static void free(void *where);
90static void error(char *m);
91static void gzip_mark(void **);
92static void gzip_release(void **);
93
94static void puts(const char *str)
95{
96}
97
98extern unsigned char _end[];
99static unsigned long free_mem_ptr;
100static unsigned long free_mem_end_ptr;
101
102#define HEAP_SIZE 0x10000
103
104#include "../../../../lib/inflate.c"
105
106static void *malloc(int size)
107{
108    void *p;
109
110    if (size <0) error("Malloc error\n");
111    if (free_mem_ptr == 0) error("Memory error\n");
112
113    free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */
114
115    p = (void *)free_mem_ptr;
116    free_mem_ptr += size;
117
118    if (free_mem_ptr >= free_mem_end_ptr)
119        error("\nOut of memory\n");
120
121    return p;
122}
123
124static void free(void *where)
125{ /* Don't care */
126}
127
128static void gzip_mark(void **ptr)
129{
130    *ptr = (void *) free_mem_ptr;
131}
132
133static void gzip_release(void **ptr)
134{
135    free_mem_ptr = (long) *ptr;
136}
137
138void* memset(void* s, int c, size_t n)
139{
140    int i;
141    char *ss = (char*)s;
142
143    for (i=0;i<n;i++) ss[i] = c;
144    return s;
145}
146
147void* memcpy(void* __dest, __const void* __src, size_t __n)
148{
149    int i = 0;
150    unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
151
152    for (i = __n >> 3; i > 0; i--) {
153        *d++ = *s++;
154        *d++ = *s++;
155        *d++ = *s++;
156        *d++ = *s++;
157        *d++ = *s++;
158        *d++ = *s++;
159        *d++ = *s++;
160        *d++ = *s++;
161    }
162
163    if (__n & 1 << 2) {
164        *d++ = *s++;
165        *d++ = *s++;
166        *d++ = *s++;
167        *d++ = *s++;
168    }
169
170    if (__n & 1 << 1) {
171        *d++ = *s++;
172        *d++ = *s++;
173    }
174
175    if (__n & 1)
176        *d++ = *s++;
177
178    return __dest;
179}
180
181/* ===========================================================================
182 * Fill the input buffer. This is called only when the buffer is empty
183 * and at least one byte is really needed.
184 */
185static int fill_inbuf(void)
186{
187    if (insize != 0) {
188        error("ran out of input data\n");
189    }
190
191    inbuf = input_data;
192    insize = input_len;
193    inptr = 1;
194    return inbuf[0];
195}
196
197/* ===========================================================================
198 * Write the output window window[0..outcnt-1] and update crc and bytes_out.
199 * (Used for the decompressed data only.)
200 */
201static void flush_window(void)
202{
203    ulg c = crc; /* temporary variable */
204    unsigned n;
205    uch *in, *out, ch;
206
207    in = window;
208    out = &output_data[output_ptr];
209    for (n = 0; n < outcnt; n++) {
210        ch = *out++ = *in++;
211        c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
212    }
213    crc = c;
214    bytes_out += (ulg)outcnt;
215    output_ptr += (ulg)outcnt;
216    outcnt = 0;
217}
218
219static void error(char *x)
220{
221    puts("\n\n");
222    puts(x);
223    puts("\n\n -- System halted");
224
225    while(1); /* Halt */
226}
227
228void decompress_kernel(unsigned int imageaddr, unsigned int imagesize, unsigned int loadaddr)
229{
230    input_data = (char *)imageaddr;
231    input_len = imagesize;
232    output_ptr = 0;
233    output_data = (uch *)loadaddr;
234    free_mem_ptr = (unsigned long)_end;
235    free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
236
237    makecrc();
238    puts("Uncompressing Linux...");
239    gunzip();
240    flushcaches();
241    puts("Ok, booting the kernel.");
242}
arch/mips/boot/tools/entry
1#!/bin/sh
2
3# grab the kernel_entry address from the vmlinux elf image
4entry=`$1 $2 | grep kernel_entry`
5
6fs=`echo $entry | grep ffffffff` # check toolchain output
7
8if [ -n "$fs" ]; then
9    echo "0x"`$1 $2 | grep kernel_entry | cut -c9- | awk '{print $1}'`
10else
11    echo "0x"`$1 $2 | grep kernel_entry | cut -c1- | awk '{print $1}'`
12fi
arch/mips/boot/tools/filesize
1#!/bin/sh
2HOSTNAME=`uname`
3if [ "$HOSTNAME" = "Linux" ]; then
4echo `ls -l $1 | awk '{print $5}'`
5else
6echo `ls -l $1 | awk '{print $6}'`
7fi
arch/mips/include/asm/mach-jz4740/board-qi_lb60.h
1/*
2 * Copyright (c) 2009 Qi Hardware Inc.,
3 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
4 *
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __ASM_JZ4740_QI_LB60_H__
20#define __ASM_JZ4740_QI_LB60_H__
21
22#include <linux/gpio.h>
23/*
24 * Frequencies of on-board oscillators
25 */
26#define JZ_EXTAL 12000000 /* Main extal freq: 12 MHz */
27#define JZ_EXTAL_RTC 32768 /* RTC extal freq: 32.768 KHz */
28
29/*
30 * GPIO
31 */
32#define GPIO_DC_DETE_N JZ_GPIO_PORTC(26)
33#define GPIO_CHARG_STAT_N JZ_GPIO_PORTC(27)
34#define GPIO_LED_EN JZ_GPIO_PORTC(28)
35#define GPIO_LCD_CS JZ_GPIO_PORTC(21)
36#define GPIO_DISP_OFF_N JZ_GPIO_PORTD(21)
37#define GPIO_PWM JZ_GPIO_PORTD(27)
38#define GPIO_WAKEUP_N JZ_GPIO_PORTD(29)
39
40#define GPIO_AMP_EN JZ_GPIO_PORTD(4)
41
42#define GPIO_SD_CD_N JZ_GPIO_PORTD(0)
43#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2)
44#define GPIO_SD_WP JZ_GPIO_PORTD(16)
45
46#define GPIO_USB_DETE JZ_GPIO_PORTD(28)
47#define GPIO_BUZZ_PWM JZ_GPIO_PORTD(27)
48#define GPIO_UDC_HOTPLUG GPIO_USB_DETE
49
50#define GPIO_AUDIO_POP JZ_GPIO_PORTB(29)
51#define GPIO_COB_TEST JZ_GPIO_PORTB(30)
52
53#define GPIO_KEYOUT_BASE JZ_GPIO_PORTC(10)
54#define GPIO_KEYIN_BASE JZ_GPIO_PORTD(18)
55#define GPIO_KEYIN_8 JZ_GPIO_PORTD(26)
56
57/*
58 * MMC/SD
59 */
60#define MSC_WP_PIN GPIO_SD_WP
61#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
62#define MSC_HOTPLUG_IRQ (JZ_IRQ_GPIO(GPIO_SD_CD_N))
63
64#define __msc_init_io() \
65do { \
66    __gpio_as_output(GPIO_SD_VCC_EN_N); \
67    __gpio_as_input(GPIO_SD_CD_N); \
68} while (0)
69
70#define __msc_enable_power() \
71do { \
72    __gpio_clear_pin(GPIO_SD_VCC_EN_N); \
73} while (0)
74
75#define __msc_disable_power() \
76do { \
77    __gpio_set_pin(GPIO_SD_VCC_EN_N); \
78} while (0)
79
80#define __msc_card_detected(s) \
81({ \
82    int detected = 1; \
83    if (!__gpio_get_pin(GPIO_SD_CD_N)) \
84        detected = 0; \
85    detected; \
86})
87
88#endif /* __ASM_JZ4740_QI_LB60_H__ */
arch/mips/include/asm/mach-jz4740/clock.h
1/*
2 * linux/include/asm-mips/mach-jz4740/clock.h
3 *
4 * JZ4740 clocks definition.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <lhhuang@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_JZ4740_CLOCK_H__
16#define __ASM_JZ4740_CLOCK_H__
17
18#include <asm/mach-jz4740/ops.h>
19
20#ifndef JZ_EXTAL
21//#define JZ_EXTAL 3686400 /* 3.6864 MHz */
22#define JZ_EXTAL 12000000 /* 3.6864 MHz */
23#endif
24#ifndef JZ_EXTAL2
25#define JZ_EXTAL2 32768 /* 32.768 KHz */
26#endif
27
28/*
29 * JZ4740 clocks structure
30 */
31typedef struct {
32    unsigned int cclk; /* CPU clock */
33    unsigned int hclk; /* System bus clock */
34    unsigned int pclk; /* Peripheral bus clock */
35    unsigned int mclk; /* Flash/SRAM/SDRAM clock */
36    unsigned int lcdclk; /* LCDC module clock */
37    unsigned int pixclk; /* LCD pixel clock */
38    unsigned int i2sclk; /* AIC module clock */
39    unsigned int usbclk; /* USB module clock */
40    unsigned int mscclk; /* MSC module clock */
41    unsigned int extalclk; /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
42    unsigned int rtcclk; /* RTC clock for CPM,INTC,RTC,TCU,WDT */
43} jz_clocks_t;
44
45extern jz_clocks_t jz_clocks;
46
47
48/* PLL output frequency */
49static __inline__ unsigned int __cpm_get_pllout(void)
50{
51    unsigned long m, n, no, pllout;
52    unsigned long cppcr = REG_CPM_CPPCR;
53    unsigned long od[4] = {1, 2, 2, 4};
54    if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
55        m = __cpm_get_pllm() + 2;
56        n = __cpm_get_plln() + 2;
57        no = od[__cpm_get_pllod()];
58        pllout = ((JZ_EXTAL) / (n * no)) * m;
59    } else
60        pllout = JZ_EXTAL;
61    return pllout;
62}
63
64/* PLL output frequency for MSC/I2S/LCD/USB */
65static __inline__ unsigned int __cpm_get_pllout2(void)
66{
67    if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
68        return __cpm_get_pllout();
69    else
70        return __cpm_get_pllout()/2;
71}
72
73/* CPU core clock */
74static __inline__ unsigned int __cpm_get_cclk(void)
75{
76    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
77
78    return __cpm_get_pllout() / div[__cpm_get_cdiv()];
79}
80
81/* AHB system bus clock */
82static __inline__ unsigned int __cpm_get_hclk(void)
83{
84    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
85
86    return __cpm_get_pllout() / div[__cpm_get_hdiv()];
87}
88
89/* Memory bus clock */
90static __inline__ unsigned int __cpm_get_mclk(void)
91{
92    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
93
94    return __cpm_get_pllout() / div[__cpm_get_mdiv()];
95}
96
97/* APB peripheral bus clock */
98static __inline__ unsigned int __cpm_get_pclk(void)
99{
100    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
101
102    return __cpm_get_pllout() / div[__cpm_get_pdiv()];
103}
104
105/* LCDC module clock */
106static __inline__ unsigned int __cpm_get_lcdclk(void)
107{
108    return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
109}
110
111/* LCD pixel clock */
112static __inline__ unsigned int __cpm_get_pixclk(void)
113{
114    return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
115}
116
117/* I2S clock */
118static __inline__ unsigned int __cpm_get_i2sclk(void)
119{
120    if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
121        return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
122    }
123    else {
124        return JZ_EXTAL;
125    }
126}
127
128/* USB clock */
129static __inline__ unsigned int __cpm_get_usbclk(void)
130{
131    if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
132        return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
133    }
134    else {
135        return JZ_EXTAL;
136    }
137}
138
139/* MSC clock */
140static __inline__ unsigned int __cpm_get_mscclk(void)
141{
142    return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
143}
144
145/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
146static __inline__ unsigned int __cpm_get_extalclk(void)
147{
148    return JZ_EXTAL;
149}
150
151/* RTC clock for CPM,INTC,RTC,TCU,WDT */
152static __inline__ unsigned int __cpm_get_rtcclk(void)
153{
154    return JZ_EXTAL2;
155}
156
157/*
158 * Output 24MHz for SD and 16MHz for MMC.
159 */
160static inline void __cpm_select_msc_clk(int sd)
161{
162    unsigned int pllout2 = __cpm_get_pllout2();
163    unsigned int div = 0;
164
165    if (sd) {
166        div = pllout2 / 24000000;
167    }
168    else {
169        div = pllout2 / 16000000;
170    }
171
172    REG_CPM_MSCCDR = div - 1;
173}
174
175int jz_init_clocks(unsigned long ext_rate);
176
177#endif /* __ASM_JZ4740_CLOCK_H__ */
arch/mips/include/asm/mach-jz4740/dma.h
1/*
2 * linux/include/asm-mips/mach-jz4740/dma.h
3 *
4 * JZ4740 DMA definition.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <lhhuang@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_JZ4740_DMA_H__
16#define __ASM_JZ4740_DMA_H__
17
18#include <linux/interrupt.h>
19#include <asm/io.h> /* need byte IO */
20#include <linux/spinlock.h> /* And spinlocks */
21#include <linux/delay.h>
22#include <asm/mach-jz4740/regs.h>
23#include <asm/mach-jz4740/ops.h>
24
25/*
26 * Descriptor structure for JZ4740 DMA engine
27 * Note: this structure must always be aligned to a 16-bytes boundary.
28 */
29
30typedef struct {
31    volatile u32 dcmd; /* DCMD value for the current transfer */
32    volatile u32 dsadr; /* DSAR value for the current transfer */
33    volatile u32 dtadr; /* DTAR value for the current transfer */
34    volatile u32 ddadr; /* Points to the next descriptor + transfer count */
35} jz_dma_desc;
36
37
38/* DMA Device ID's follow */
39enum {
40    DMA_ID_UART0_TX = 0,
41    DMA_ID_UART0_RX,
42    DMA_ID_SSI_TX,
43    DMA_ID_SSI_RX,
44    DMA_ID_AIC_TX,
45    DMA_ID_AIC_RX,
46    DMA_ID_MSC_TX,
47    DMA_ID_MSC_RX,
48    DMA_ID_TCU_OVERFLOW,
49    DMA_ID_AUTO,
50    DMA_ID_RAW_SET,
51    DMA_ID_MAX
52};
53
54/* DMA modes, simulated by sw */
55#define DMA_MODE_READ 0x0 /* I/O to memory, no autoinit, increment, single mode */
56#define DMA_MODE_WRITE 0x1 /* memory to I/O, no autoinit, increment, single mode */
57#define DMA_AUTOINIT 0x2
58#define DMA_MODE_MASK 0x3
59
60struct jz_dma_chan {
61    int dev_id; /* DMA ID: this channel is allocated if >=0, free otherwise */
62    unsigned int io; /* DMA channel number */
63    const char *dev_str; /* string describes the DMA channel */
64    int irq; /* DMA irq number */
65    void *irq_dev; /* DMA private device structure */
66    unsigned int fifo_addr; /* physical fifo address of the requested device */
67    unsigned int cntl; /* DMA controll */
68    unsigned int mode; /* DMA configuration */
69    unsigned int source; /* DMA request source */
70};
71
72extern struct jz_dma_chan jz_dma_table[];
73
74
75#define DMA_8BIT_RX_CMD \
76    DMAC_DCMD_DAI | \
77    DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
78    DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
79
80#define DMA_8BIT_TX_CMD \
81    DMAC_DCMD_SAI | \
82    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
83    DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
84
85#define DMA_16BIT_RX_CMD \
86    DMAC_DCMD_DAI | \
87    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_32 | \
88    DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
89
90#define DMA_16BIT_TX_CMD \
91    DMAC_DCMD_SAI | \
92    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16 | \
93    DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
94
95#define DMA_32BIT_RX_CMD \
96    DMAC_DCMD_DAI | \
97    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
98    DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
99
100#define DMA_32BIT_TX_CMD \
101    DMAC_DCMD_SAI | \
102    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
103    DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
104
105#define DMA_16BYTE_RX_CMD \
106    DMAC_DCMD_DAI | \
107    DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
108    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
109
110#define DMA_16BYTE_TX_CMD \
111    DMAC_DCMD_SAI | \
112    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
113    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
114
115#define DMA_32BYTE_RX_CMD \
116    DMAC_DCMD_DAI | \
117    DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
118    DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
119
120#define DMA_32BYTE_TX_CMD \
121    DMAC_DCMD_SAI | \
122    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
123    DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
124
125#define DMA_AIC_32_16BYTE_TX_CMD \
126    DMAC_DCMD_SAI | \
127    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
128    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
129
130#define DMA_AIC_32_16BYTE_RX_CMD \
131    DMAC_DCMD_DAI | \
132    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
133    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
134
135#define DMA_AIC_16BIT_TX_CMD \
136    DMAC_DCMD_SAI | \
137    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
138    DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
139
140#define DMA_AIC_16BIT_RX_CMD \
141    DMAC_DCMD_DAI | \
142    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
143    DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
144
145#define DMA_AIC_16BYTE_RX_CMD \
146    DMAC_DCMD_DAI | \
147    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
148    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
149
150#define DMA_AIC_16BYTE_TX_CMD \
151    DMAC_DCMD_SAI | \
152    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
153    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
154
155extern int jz_request_dma(int dev_id,
156              const char *dev_str,
157              irqreturn_t (*irqhandler)(int, void *),
158              unsigned long irqflags,
159              void *irq_dev_id);
160extern void jz_free_dma(unsigned int dmanr);
161
162extern int jz_dma_read_proc(char *buf, char **start, off_t fpos,
163                  int length, int *eof, void *data);
164extern void dump_jz_dma_channel(unsigned int dmanr);
165
166extern void enable_dma(unsigned int dmanr);
167extern void disable_dma(unsigned int dmanr);
168extern void set_dma_addr(unsigned int dmanr, unsigned int phyaddr);
169extern void set_dma_count(unsigned int dmanr, unsigned int bytecnt);
170extern void set_dma_mode(unsigned int dmanr, unsigned int mode);
171extern void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
172extern unsigned int get_dma_residue(unsigned int dmanr);
173
174extern spinlock_t dma_spin_lock;
175
176static __inline__ unsigned long claim_dma_lock(void)
177{
178    unsigned long flags;
179    spin_lock_irqsave(&dma_spin_lock, flags);
180    return flags;
181}
182
183static __inline__ void release_dma_lock(unsigned long flags)
184{
185    spin_unlock_irqrestore(&dma_spin_lock, flags);
186}
187
188/* Clear the 'DMA Pointer Flip Flop'.
189 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
190 */
191#define clear_dma_ff(channel)
192
193static __inline__ struct jz_dma_chan *get_dma_chan(unsigned int dmanr)
194{
195    if (dmanr > MAX_DMA_NUM
196        || jz_dma_table[dmanr].dev_id < 0)
197        return NULL;
198    return &jz_dma_table[dmanr];
199}
200
201static __inline__ int dma_halted(unsigned int dmanr)
202{
203    struct jz_dma_chan *chan = get_dma_chan(dmanr);
204    if (!chan)
205        return 1;
206    return __dmac_channel_transmit_halt_detected(dmanr) ? 1 : 0;
207}
208
209static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
210{
211    struct jz_dma_chan *chan = get_dma_chan(dmanr);
212    if (!chan)
213        return 0;
214    return chan->mode;
215}
216
217static __inline__ void clear_dma_done(unsigned int dmanr)
218{
219    struct jz_dma_chan *chan = get_dma_chan(dmanr);
220    if (!chan)
221        return;
222    REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
223}
224
225static __inline__ void clear_dma_halt(unsigned int dmanr)
226{
227    struct jz_dma_chan *chan = get_dma_chan(dmanr);
228    if (!chan)
229        return;
230    REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT);
231    REG_DMAC_DMACR &= ~(DMAC_DMACR_HLT);
232}
233
234static __inline__ void clear_dma_flag(unsigned int dmanr)
235{
236    struct jz_dma_chan *chan = get_dma_chan(dmanr);
237    if (!chan)
238        return;
239    REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
240    REG_DMAC_DMACR &= ~(DMAC_DMACR_HLT | DMAC_DMACR_AR);
241}
242
243static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
244{
245}
246
247static __inline__ unsigned int get_dma_done_status(unsigned int dmanr)
248{
249    unsigned long dccsr;
250    struct jz_dma_chan *chan = get_dma_chan(dmanr);
251    if (!chan)
252        return 0;
253    dccsr = REG_DMAC_DCCSR(chan->io);
254    return dccsr & (DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
255}
256
257static __inline__ int get_dma_done_irq(unsigned int dmanr)
258{
259    struct jz_dma_chan *chan = get_dma_chan(dmanr);
260    if (!chan)
261        return -1;
262    return chan->irq;
263}
264
265#endif /* __ASM_JZ4740_DMA_H__ */
arch/mips/include/asm/mach-jz4740/gpio.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 GPIO pin definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef _JZ_GPIO_H
17#define _JZ_GPIO_H
18
19#include <linux/types.h>
20
21enum jz_gpio_function {
22    JZ_GPIO_FUNC_NONE,
23    JZ_GPIO_FUNC1,
24    JZ_GPIO_FUNC2,
25    JZ_GPIO_FUNC3,
26};
27
28
29/*
30 Usually a driver for a SoC component has to request several gpio pins and
31 configure them as funcion pins.
32 jz_gpio_bulk_request can be used to ease this process.
33 Usually one would do something like:
34
35 const static struct jz_gpio_bulk_request i2c_pins[] = {
36    JZ_GPIO_BULK_PIN(I2C_SDA),
37    JZ_GPIO_BULK_PIN(I2C_SCK),
38 };
39
40 inside the probe function:
41
42    ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
43    if (ret) {
44    ...
45
46 inside the remove function:
47
48    jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
49
50
51*/
52struct jz_gpio_bulk_request {
53    int gpio;
54    const char *name;
55    enum jz_gpio_function function;
56};
57
58#define JZ_GPIO_BULK_PIN(pin) { \
59    .gpio = JZ_GPIO_ ## pin, \
60    .name = #pin, \
61    .function = JZ_GPIO_FUNC_ ## pin \
62}
63
64int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
65void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
66void jz_gpio_enable_pullup(unsigned gpio);
67void jz_gpio_disable_pullup(unsigned gpio);
68int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
69
70#include <asm/mach-generic/gpio.h>
71
72#define JZ_GPIO_PORTA(x) (x + 32 * 0)
73#define JZ_GPIO_PORTB(x) (x + 32 * 1)
74#define JZ_GPIO_PORTC(x) (x + 32 * 2)
75#define JZ_GPIO_PORTD(x) (x + 32 * 3)
76
77/* Port A function pins */
78#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
79#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
80#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
81#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
82#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
83#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
84#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
85#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
86#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
87#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
88#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
89#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
90#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
91#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
92#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
93#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
94#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
95#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
96#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
97#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
98#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
99#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
100#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
101#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
102#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
103#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
104#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
105#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
106#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
107#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
108#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
109#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
110
111#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
112#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
113#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
114#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
115#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
116#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
117#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
118#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
119#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
120#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
121#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
122#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
123#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
124#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
125#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
126#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
127#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
128#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
129#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
130#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
131#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
132#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
133#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
134#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
135#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
136#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
137#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
138#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
139#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
140#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
141#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
142#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
143
144/* Port B function pins */
145#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
146#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
147#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
148#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
149#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
150#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
151#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
152#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
153#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
154#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
155#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
156#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
157#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
158#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
159#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
160#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
161#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
162#define JZ_GPIO_MEM_CLS JZ_GPIO_PORTB(17)
163#define JZ_GPIO_MEM_SPL JZ_GPIO_PORTB(18)
164#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
165#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
166#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
167#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
168#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
169#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
170#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
171#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
172#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
173#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
174#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
175#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
176#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
177
178#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
179#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
180#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
181#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
182#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
183#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
184#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
185#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
186#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
187#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
188#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
189#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
190#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
191#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
192#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
193#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
194#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
195#define JZ_GPIO_FUNC_MEM_CLS JZ_GPIO_FUNC1
196#define JZ_GPIO_FUNC_MEM_SPL JZ_GPIO_FUNC1
197#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
198#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
199#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
200#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
201#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
202#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
203#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
204#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
205#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
206#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
207#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
208#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
209#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
210
211
212#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
213#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
214
215#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
216#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
217
218/* Port C function pins */
219#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
220#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
221#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
222#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
223#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
224#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
225#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
226#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
227#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
228#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
229#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
230#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
231#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
232#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
233#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
234#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
235#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
236#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
237#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
238#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
239#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
240#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
241#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
242#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
243#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
244#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
245#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
246#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
247#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
248#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
249
250#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
251#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
252#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
253#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
254#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
255#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
256#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
257#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
258#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
259#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
260#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
261#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
262#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
263#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
264#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
265#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
266#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
267#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
268#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
269#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
270#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
271#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
272#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
273#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
274#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
275#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
276#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
277#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
278#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
279#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
280
281
282#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
283#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
284
285#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
286#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
287
288/* Port D function pins */
289#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
290#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
291#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
292#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
293#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
294#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
295#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
296#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
297#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
298#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
299#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
300#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
301#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
302#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
303#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
304#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
305#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
306#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
307#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
308#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
309#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
310#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
311#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
312#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
313#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
314#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
315#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
316#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
317#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
318#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
319#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
320
321#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC1
322#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC1
323#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC1
324#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC1
325#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC1
326#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC1
327#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC1
328#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC1
329#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
330#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
331#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC1
332#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC1
333#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC1
334#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC1
335#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
336#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
337#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
338#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
339#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
340#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
341#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
342#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
343#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
344#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC1
345#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC1
346#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC1
347#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC1
348#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC1
349#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC1
350#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC1
351
352#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
353#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
354#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
355#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
356#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
357#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
358#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
359#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
360#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
361#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
362#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
363#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
364#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
365
366#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
367#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
368#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
369#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
370#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
371#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
372#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
373#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
374#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
375#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
376#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
377#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
378#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
379
380#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
381#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
382
383#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
384#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
385
386#endif
arch/mips/include/asm/mach-jz4740/irq.h
1#ifndef __JZ4740_IRQ_H__
2#define __JZ4740_IRQ_H__
3
4#define MIPS_CPU_IRQ_BASE 0
5#define JZ_IRQ_BASE 8
6
7// 1st-level interrupts
8#define JZ_IRQ(x) (JZ_IRQ_BASE + (x))
9#define JZ_IRQ_I2C JZ_IRQ(1)
10#define JZ_IRQ_UHC JZ_IRQ(3)
11#define JZ_IRQ_UART1 JZ_IRQ(8)
12#define JZ_IRQ_UART0 JZ_IRQ(9)
13#define JZ_IRQ_SADC JZ_IRQ(12)
14#define JZ_IRQ_MSC JZ_IRQ(14)
15#define JZ_IRQ_RTC JZ_IRQ(15)
16#define JZ_IRQ_SSI JZ_IRQ(16)
17#define JZ_IRQ_CIM JZ_IRQ(17)
18#define JZ_IRQ_AIC JZ_IRQ(18)
19#define JZ_IRQ_ETH JZ_IRQ(19)
20#define JZ_IRQ_DMAC JZ_IRQ(20)
21#define JZ_IRQ_TCU2 JZ_IRQ(21)
22#define JZ_IRQ_TCU1 JZ_IRQ(22)
23#define JZ_IRQ_TCU0 JZ_IRQ(23)
24#define JZ_IRQ_UDC JZ_IRQ(24)
25#define JZ_IRQ_GPIO3 JZ_IRQ(25)
26#define JZ_IRQ_GPIO2 JZ_IRQ(26)
27#define JZ_IRQ_GPIO1 JZ_IRQ(27)
28#define JZ_IRQ_GPIO0 JZ_IRQ(28)
29#define JZ_IRQ_IPU JZ_IRQ(29)
30#define JZ_IRQ_LCD JZ_IRQ(30)
31
32/* 2nd-level interrupts */
33#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
34
35#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
36#define JZ_IRQ_GPIO(x) (JZ_IRQ(48) + (x))
37
38#define NR_IRQS (JZ_IRQ_GPIO(127) + 1)
39
40#endif
arch/mips/include/asm/mach-jz4740/jz4740.h
1/*
2 * linux/include/asm-mips/mach-jz4740/jz4740.h
3 *
4 * JZ4740 common definition.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <lhhuang@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_JZ4740_H__
16#define __ASM_JZ4740_H__
17
18#include <asm/mach-jz4740/regs.h>
19#include <asm/mach-jz4740/ops.h>
20#include <asm/mach-jz4740/dma.h>
21
22/*------------------------------------------------------------------
23 * Platform definitions
24 */
25
26#ifdef CONFIG_JZ4740_QI_LB60
27#include <asm/mach-jz4740/board-qi_lb60.h>
28#endif
29
30/* Add other platform definition here ... */
31
32
33/*------------------------------------------------------------------
34 * Follows are related to platform definitions
35 */
36
37#include <asm/mach-jz4740/clock.h>
38#include <asm/mach-jz4740/serial.h>
39
40#endif /* __ASM_JZ4740_H__ */
arch/mips/include/asm/mach-jz4740/ops.h
1/*
2 * linux/include/asm-mips/mach-jz4740/ops.h
3 *
4 * Ingenic's JZ4740 common include.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <yliu@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15
16#ifndef __JZ4740_OPS_H__
17#define __JZ4740_OPS_H__
18
19#include <asm/mach-jz4740/regs.h>
20
21/*
22 * Definition of Module Operations
23 */
24
25/***************************************************************************
26 * GPIO
27 ***************************************************************************/
28
29//------------------------------------------------------
30// GPIO Pins Description
31//
32// PORT 0:
33//
34// PIN/BIT N FUNC0 FUNC1
35// 0 D0 -
36// 1 D1 -
37// 2 D2 -
38// 3 D3 -
39// 4 D4 -
40// 5 D5 -
41// 6 D6 -
42// 7 D7 -
43// 8 D8 -
44// 9 D9 -
45// 10 D10 -
46// 11 D11 -
47// 12 D12 -
48// 13 D13 -
49// 14 D14 -
50// 15 D15 -
51// 16 D16 -
52// 17 D17 -
53// 18 D18 -
54// 19 D19 -
55// 20 D20 -
56// 21 D21 -
57// 22 D22 -
58// 23 D23 -
59// 24 D24 -
60// 25 D25 -
61// 26 D26 -
62// 27 D27 -
63// 28 D28 -
64// 29 D29 -
65// 30 D30 -
66// 31 D31 -
67//
68//------------------------------------------------------
69// PORT 1:
70//
71// PIN/BIT N FUNC0 FUNC1
72// 0 A0 -
73// 1 A1 -
74// 2 A2 -
75// 3 A3 -
76// 4 A4 -
77// 5 A5 -
78// 6 A6 -
79// 7 A7 -
80// 8 A8 -
81// 9 A9 -
82// 10 A10 -
83// 11 A11 -
84// 12 A12 -
85// 13 A13 -
86// 14 A14 -
87// 15 A15/CL -
88// 16 A16/AL -
89// 17 LCD_CLS A21
90// 18 LCD_SPL A22
91// 19 DCS# -
92// 20 RAS# -
93// 21 CAS# -
94// 22 RDWE#/BUFD# -
95// 23 CKE -
96// 24 CKO -
97// 25 CS1# -
98// 26 CS2# -
99// 27 CS3# -
100// 28 CS4# -
101// 29 RD# -
102// 30 WR# -
103// 31 WE0# -
104//
105// Note: PIN15&16 are CL&AL when connecting to NAND flash.
106//------------------------------------------------------
107// PORT 2:
108//
109// PIN/BIT N FUNC0 FUNC1
110// 0 LCD_D0 -
111// 1 LCD_D1 -
112// 2 LCD_D2 -
113// 3 LCD_D3 -
114// 4 LCD_D4 -
115// 5 LCD_D5 -
116// 6 LCD_D6 -
117// 7 LCD_D7 -
118// 8 LCD_D8 -
119// 9 LCD_D9 -
120// 10 LCD_D10 -
121// 11 LCD_D11 -
122// 12 LCD_D12 -
123// 13 LCD_D13 -
124// 14 LCD_D14 -
125// 15 LCD_D15 -
126// 16 LCD_D16 -
127// 17 LCD_D17 -
128// 18 LCD_PCLK -
129// 19 LCD_HSYNC -
130// 20 LCD_VSYNC -
131// 21 LCD_DE -
132// 22 LCD_PS A19
133// 23 LCD_REV A20
134// 24 WE1# -
135// 25 WE2# -
136// 26 WE3# -
137// 27 WAIT# -
138// 28 FRE# -
139// 29 FWE# -
140// 30(NOTE:FRB#) - -
141// 31 - -
142//
143// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
144//------------------------------------------------------
145// PORT 3:
146//
147// PIN/BIT N FUNC0 FUNC1
148// 0 CIM_D0 -
149// 1 CIM_D1 -
150// 2 CIM_D2 -
151// 3 CIM_D3 -
152// 4 CIM_D4 -
153// 5 CIM_D5 -
154// 6 CIM_D6 -
155// 7 CIM_D7 -
156// 8 MSC_CMD -
157// 9 MSC_CLK -
158// 10 MSC_D0 -
159// 11 MSC_D1 -
160// 12 MSC_D2 -
161// 13 MSC_D3 -
162// 14 CIM_MCLK -
163// 15 CIM_PCLK -
164// 16 CIM_VSYNC -
165// 17 CIM_HSYNC -
166// 18 SSI_CLK SCLK_RSTN
167// 19 SSI_CE0# BIT_CLK(AIC)
168// 20 SSI_DT SDATA_OUT(AIC)
169// 21 SSI_DR SDATA_IN(AIC)
170// 22 SSI_CE1#&GPC SYNC(AIC)
171// 23 PWM0 I2C_SDA
172// 24 PWM1 I2C_SCK
173// 25 PWM2 UART0_TxD
174// 26 PWM3 UART0_RxD
175// 27 PWM4 A17
176// 28 PWM5 A18
177// 29 - -
178// 30 PWM6 UART0_CTS/UART1_RxD
179// 31 PWM7 UART0_RTS/UART1_TxD
180//
181//////////////////////////////////////////////////////////
182
183/*
184 * p is the port number (0,1,2,3)
185 * o is the pin offset (0-31) inside the port
186 * n is the absolute number of a pin (0-127), regardless of the port
187 */
188
189//-------------------------------------------
190// Function Pins Mode
191
192#define __gpio_as_func0(n) \
193do { \
194    unsigned int p, o; \
195    p = (n) / 32; \
196    o = (n) % 32; \
197    REG_GPIO_PXFUNS(p) = (1 << o); \
198    REG_GPIO_PXSELC(p) = (1 << o); \
199} while (0)
200
201#define __gpio_as_func1(n) \
202do { \
203    unsigned int p, o; \
204    p = (n) / 32; \
205    o = (n) % 32; \
206    REG_GPIO_PXFUNS(p) = (1 << o); \
207    REG_GPIO_PXSELS(p) = (1 << o); \
208} while (0)
209
210/*
211 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
212 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
213 */
214#define __gpio_as_sdram_32bit() \
215do { \
216    REG_GPIO_PXFUNS(0) = 0xffffffff; \
217    REG_GPIO_PXSELC(0) = 0xffffffff; \
218    REG_GPIO_PXPES(0) = 0xffffffff; \
219    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
220    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
221    REG_GPIO_PXPES(1) = 0x81f9ffff; \
222    REG_GPIO_PXFUNS(2) = 0x07000000; \
223    REG_GPIO_PXSELC(2) = 0x07000000; \
224    REG_GPIO_PXPES(2) = 0x07000000; \
225} while (0)
226
227/*
228 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
229 * RDWE#, CKO#, WE0#, WE1#
230 */
231#define __gpio_as_sdram_16bit() \
232do { \
233    REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
234    REG_GPIO_PXSELC(0) = 0x5442bfaa; \
235    REG_GPIO_PXPES(0) = 0x5442bfaa; \
236    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
237    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
238    REG_GPIO_PXPES(1) = 0x81f9ffff; \
239    REG_GPIO_PXFUNS(2) = 0x01000000; \
240    REG_GPIO_PXSELC(2) = 0x01000000; \
241    REG_GPIO_PXPES(2) = 0x01000000; \
242} while (0)
243
244/*
245 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
246 */
247#define __gpio_as_nand() \
248do { \
249    REG_GPIO_PXFUNS(1) = 0x02018000; \
250    REG_GPIO_PXSELC(1) = 0x02018000; \
251    REG_GPIO_PXPES(1) = 0x02018000; \
252    REG_GPIO_PXFUNS(2) = 0x30000000; \
253    REG_GPIO_PXSELC(2) = 0x30000000; \
254    REG_GPIO_PXPES(2) = 0x30000000; \
255    REG_GPIO_PXFUNC(2) = 0x40000000; \
256    REG_GPIO_PXSELC(2) = 0x40000000; \
257    REG_GPIO_PXDIRC(2) = 0x40000000; \
258    REG_GPIO_PXPES(2) = 0x40000000; \
259    REG_GPIO_PXFUNS(1) = 0x00400000; \
260    REG_GPIO_PXSELC(1) = 0x00400000; \
261} while (0)
262
263/*
264 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
265 */
266#define __gpio_as_nor_8bit() \
267do { \
268    REG_GPIO_PXFUNS(0) = 0x000000ff; \
269    REG_GPIO_PXSELC(0) = 0x000000ff; \
270    REG_GPIO_PXPES(0) = 0x000000ff; \
271    REG_GPIO_PXFUNS(1) = 0x7041ffff; \
272    REG_GPIO_PXSELC(1) = 0x7041ffff; \
273    REG_GPIO_PXPES(1) = 0x7041ffff; \
274    REG_GPIO_PXFUNS(1) = 0x00060000; \
275    REG_GPIO_PXSELS(1) = 0x00060000; \
276    REG_GPIO_PXPES(1) = 0x00060000; \
277    REG_GPIO_PXFUNS(2) = 0x08000000; \
278    REG_GPIO_PXSELC(2) = 0x08000000; \
279    REG_GPIO_PXPES(2) = 0x08000000; \
280    REG_GPIO_PXFUNS(2) = 0x00c00000; \
281    REG_GPIO_PXSELS(2) = 0x00c00000; \
282    REG_GPIO_PXPES(2) = 0x00c00000; \
283    REG_GPIO_PXFUNS(3) = 0x18000000; \
284    REG_GPIO_PXSELS(3) = 0x18000000; \
285    REG_GPIO_PXPES(3) = 0x18000000; \
286} while (0)
287
288/*
289 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
290 */
291#define __gpio_as_nor_16bit() \
292do { \
293    REG_GPIO_PXFUNS(0) = 0x0000ffff; \
294    REG_GPIO_PXSELC(0) = 0x0000ffff; \
295    REG_GPIO_PXPES(0) = 0x0000ffff; \
296    REG_GPIO_PXFUNS(1) = 0x7041ffff; \
297    REG_GPIO_PXSELC(1) = 0x7041ffff; \
298    REG_GPIO_PXPES(1) = 0x7041ffff; \
299    REG_GPIO_PXFUNS(1) = 0x00060000; \
300    REG_GPIO_PXSELS(1) = 0x00060000; \
301    REG_GPIO_PXPES(1) = 0x00060000; \
302    REG_GPIO_PXFUNS(2) = 0x08000000; \
303    REG_GPIO_PXSELC(2) = 0x08000000; \
304    REG_GPIO_PXPES(2) = 0x08000000; \
305    REG_GPIO_PXFUNS(2) = 0x00c00000; \
306    REG_GPIO_PXSELS(2) = 0x00c00000; \
307    REG_GPIO_PXPES(2) = 0x00c00000; \
308    REG_GPIO_PXFUNS(3) = 0x18000000; \
309    REG_GPIO_PXSELS(3) = 0x18000000; \
310    REG_GPIO_PXPES(3) = 0x18000000; \
311} while (0)
312
313/*
314 * UART0_TxD, UART_RxD0
315 */
316#define __gpio_as_uart0() \
317do { \
318    REG_GPIO_PXFUNS(3) = 0x06000000; \
319    REG_GPIO_PXSELS(3) = 0x06000000; \
320    REG_GPIO_PXPES(3) = 0x06000000; \
321} while (0)
322
323/*
324 * UART0_CTS, UART0_RTS
325 */
326#define __gpio_as_ctsrts() \
327do { \
328    REG_GPIO_PXFUNS(3) = 0xc0000000; \
329    REG_GPIO_PXSELS(3) = 0xc0000000; \
330    REG_GPIO_PXTRGC(3) = 0xc0000000; \
331    REG_GPIO_PXPES(3) = 0xc0000000; \
332} while (0)
333
334/*
335 * UART1_TxD, UART1_RxD1
336 */
337#define __gpio_as_uart1() \
338do { \
339    REG_GPIO_PXFUNS(3) = 0xc0000000; \
340    REG_GPIO_PXSELC(3) = 0xc0000000; \
341    REG_GPIO_PXTRGS(3) = 0xc0000000; \
342    REG_GPIO_PXPES(3) = 0xc0000000; \
343} while (0)
344
345/*
346 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
347 */
348#define __gpio_as_lcd_16bit() \
349do { \
350    REG_GPIO_PXFUNS(2) = 0x003cffff; \
351    REG_GPIO_PXSELC(2) = 0x003cffff; \
352    REG_GPIO_PXPES(2) = 0x003cffff; \
353} while (0)
354
355/*
356 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
357 */
358#define __gpio_as_lcd_18bit() \
359do { \
360    REG_GPIO_PXFUNS(2) = 0x003fffff; \
361    REG_GPIO_PXSELC(2) = 0x003fffff; \
362    REG_GPIO_PXPES(2) = 0x003fffff; \
363} while (0)
364
365/*
366 * LCD_PS, LCD_REV, LCD_CLS, LCD_SPL
367 */
368#define __gpio_as_lcd_special() \
369do { \
370    REG_GPIO_PXFUNS(1) = 0x00060000; \
371    REG_GPIO_PXSELC(1) = 0x00060000; \
372    REG_GPIO_PXPES(1) = 0x00060000; \
373    REG_GPIO_PXFUNS(2) = 0x00c00000; \
374    REG_GPIO_PXSELC(2) = 0x00c00000; \
375    REG_GPIO_PXPES(2) = 0x00c00000; \
376} while (0)
377
378/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
379#define __gpio_as_slcd_8bit() \
380do { \
381    REG_GPIO_PXFUNS(2) = 0x001800ff; \
382    REG_GPIO_PXSELC(2) = 0x001800ff; \
383} while (0)
384
385/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
386#define __gpio_as_slcd_9bit() \
387do { \
388    REG_GPIO_PXFUNS(2) = 0x001801ff; \
389    REG_GPIO_PXSELC(2) = 0x001801ff; \
390} while (0)
391
392/* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */
393#define __gpio_as_slcd_16bit() \
394do { \
395    REG_GPIO_PXFUNS(2) = 0x0018ffff; \
396    REG_GPIO_PXSELC(2) = 0x0018ffff; \
397} while (0)
398
399/* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */
400#define __gpio_as_slcd_18bit() \
401do { \
402    REG_GPIO_PXFUNS(2) = 0x001bffff; \
403    REG_GPIO_PXSELC(2) = 0x001bffff; \
404} while (0)
405
406/*
407 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
408 */
409#define __gpio_as_cim() \
410do { \
411    REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
412    REG_GPIO_PXSELC(3) = 0x0003c0ff; \
413    REG_GPIO_PXPES(3) = 0x0003c0ff; \
414} while (0)
415
416/*
417 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
418 */
419#define __gpio_as_aic() \
420do { \
421    REG_GPIO_PXFUNS(3) = 0x007c0000; \
422    REG_GPIO_PXSELS(3) = 0x007c0000; \
423    REG_GPIO_PXPES(3) = 0x007c0000; \
424} while (0)
425
426/*
427 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
428 */
429#define __gpio_as_msc() \
430do { \
431    REG_GPIO_PXFUNS(3) = 0x00003f00; \
432    REG_GPIO_PXSELC(3) = 0x00003f00; \
433    REG_GPIO_PXPES(3) = 0x00003f00; \
434} while (0)
435
436/*
437 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
438 */
439#define __gpio_as_ssi() \
440do { \
441    REG_GPIO_PXFUNS(3) = 0x003c0000; \
442    REG_GPIO_PXSELC(3) = 0x003c0000; \
443    REG_GPIO_PXPES(3) = 0x003c0000; \
444} while (0)
445
446/*
447 * I2C_SCK, I2C_SDA
448 */
449#define __gpio_as_i2c() \
450do { \
451    REG_GPIO_PXFUNS(3) = 0x01800000; \
452    REG_GPIO_PXSELS(3) = 0x01800000; \
453    REG_GPIO_PXPES(3) = 0x01800000; \
454} while (0)
455
456/*
457 * PWM0
458 */
459#define __gpio_as_pwm0() \
460do { \
461    REG_GPIO_PXFUNS(3) = 0x00800000; \
462    REG_GPIO_PXSELC(3) = 0x00800000; \
463    REG_GPIO_PXPES(3) = 0x00800000; \
464} while (0)
465
466/*
467 * PWM1
468 */
469#define __gpio_as_pwm1() \
470do { \
471    REG_GPIO_PXFUNS(3) = 0x01000000; \
472    REG_GPIO_PXSELC(3) = 0x01000000; \
473    REG_GPIO_PXPES(3) = 0x01000000; \
474} while (0)
475
476/*
477 * PWM2
478 */
479#define __gpio_as_pwm2() \
480do { \
481    REG_GPIO_PXFUNS(3) = 0x02000000; \
482    REG_GPIO_PXSELC(3) = 0x02000000; \
483    REG_GPIO_PXPES(3) = 0x02000000; \
484} while (0)
485
486/*
487 * PWM3
488 */
489#define __gpio_as_pwm3() \
490do { \
491    REG_GPIO_PXFUNS(3) = 0x04000000; \
492    REG_GPIO_PXSELC(3) = 0x04000000; \
493    REG_GPIO_PXPES(3) = 0x04000000; \
494} while (0)
495
496/*
497 * PWM4
498 */
499#define __gpio_as_pwm4() \
500do { \
501    REG_GPIO_PXFUNS(3) = 0x08000000; \
502    REG_GPIO_PXSELC(3) = 0x08000000; \
503    REG_GPIO_PXPES(3) = 0x08000000; \
504} while (0)
505
506/*
507 * PWM5
508 */
509#define __gpio_as_pwm5() \
510do { \
511    REG_GPIO_PXFUNS(3) = 0x10000000; \
512    REG_GPIO_PXSELC(3) = 0x10000000; \
513    REG_GPIO_PXPES(3) = 0x10000000; \
514} while (0)
515
516/*
517 * PWM6
518 */
519#define __gpio_as_pwm6() \
520do { \
521    REG_GPIO_PXFUNS(3) = 0x40000000; \
522    REG_GPIO_PXSELC(3) = 0x40000000; \
523    REG_GPIO_PXPES(3) = 0x40000000; \
524} while (0)
525
526/*
527 * PWM7
528 */
529#define __gpio_as_pwm7() \
530do { \
531    REG_GPIO_PXFUNS(3) = 0x80000000; \
532    REG_GPIO_PXSELC(3) = 0x80000000; \
533    REG_GPIO_PXPES(3) = 0x80000000; \
534} while (0)
535
536/*
537 * n = 0 ~ 7
538 */
539#define __gpio_as_pwm(n) __gpio_as_pwm##n()
540
541//-------------------------------------------
542// GPIO or Interrupt Mode
543
544#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
545
546#define __gpio_port_as_output(p, o) \
547do { \
548    REG_GPIO_PXFUNC(p) = (1 << (o)); \
549    REG_GPIO_PXSELC(p) = (1 << (o)); \
550    REG_GPIO_PXDIRS(p) = (1 << (o)); \
551} while (0)
552
553#define __gpio_port_as_input(p, o) \
554do { \
555    REG_GPIO_PXFUNC(p) = (1 << (o)); \
556    REG_GPIO_PXSELC(p) = (1 << (o)); \
557    REG_GPIO_PXDIRC(p) = (1 << (o)); \
558} while (0)
559
560#define __gpio_as_output(n) \
561do { \
562    unsigned int p, o; \
563    p = (n) / 32; \
564    o = (n) % 32; \
565    __gpio_port_as_output(p, o); \
566} while (0)
567
568#define __gpio_as_input(n) \
569do { \
570    unsigned int p, o; \
571    p = (n) / 32; \
572    o = (n) % 32; \
573    __gpio_port_as_input(p, o); \
574} while (0)
575
576#define __gpio_set_pin(n) \
577do { \
578    unsigned int p, o; \
579    p = (n) / 32; \
580    o = (n) % 32; \
581    REG_GPIO_PXDATS(p) = (1 << o); \
582} while (0)
583
584#define __gpio_clear_pin(n) \
585do { \
586    unsigned int p, o; \
587    p = (n) / 32; \
588    o = (n) % 32; \
589    REG_GPIO_PXDATC(p) = (1 << o); \
590} while (0)
591
592#define __gpio_get_pin(n) \
593({ \
594    unsigned int p, o, v; \
595    p = (n) / 32; \
596    o = (n) % 32; \
597    if (__gpio_get_port(p) & (1 << o)) \
598        v = 1; \
599    else \
600        v = 0; \
601    v; \
602})
603
604#define __gpio_as_irq_high_level(n) \
605do { \
606    unsigned int p, o; \
607    p = (n) / 32; \
608    o = (n) % 32; \
609    REG_GPIO_PXIMS(p) = (1 << o); \
610    REG_GPIO_PXTRGC(p) = (1 << o); \
611    REG_GPIO_PXFUNC(p) = (1 << o); \
612    REG_GPIO_PXSELS(p) = (1 << o); \
613    REG_GPIO_PXDIRS(p) = (1 << o); \
614    REG_GPIO_PXFLGC(p) = (1 << o); \
615    REG_GPIO_PXIMC(p) = (1 << o); \
616} while (0)
617
618#define __gpio_as_irq_low_level(n) \
619do { \
620    unsigned int p, o; \
621    p = (n) / 32; \
622    o = (n) % 32; \
623    REG_GPIO_PXIMS(p) = (1 << o); \
624    REG_GPIO_PXTRGC(p) = (1 << o); \
625    REG_GPIO_PXFUNC(p) = (1 << o); \
626    REG_GPIO_PXSELS(p) = (1 << o); \
627    REG_GPIO_PXDIRC(p) = (1 << o); \
628    REG_GPIO_PXFLGC(p) = (1 << o); \
629    REG_GPIO_PXIMC(p) = (1 << o); \
630} while (0)
631
632#define __gpio_as_irq_rise_edge(n) \
633do { \
634    unsigned int p, o; \
635    p = (n) / 32; \
636    o = (n) % 32; \
637    REG_GPIO_PXIMS(p) = (1 << o); \
638    REG_GPIO_PXTRGS(p) = (1 << o); \
639    REG_GPIO_PXFUNC(p) = (1 << o); \
640    REG_GPIO_PXSELS(p) = (1 << o); \
641    REG_GPIO_PXDIRS(p) = (1 << o); \
642    REG_GPIO_PXFLGC(p) = (1 << o); \
643    REG_GPIO_PXIMC(p) = (1 << o); \
644} while (0)
645
646#define __gpio_as_irq_fall_edge(n) \
647do { \
648    unsigned int p, o; \
649    p = (n) / 32; \
650    o = (n) % 32; \
651    REG_GPIO_PXIMS(p) = (1 << o); \
652    REG_GPIO_PXTRGS(p) = (1 << o); \
653    REG_GPIO_PXFUNC(p) = (1 << o); \
654    REG_GPIO_PXSELS(p) = (1 << o); \
655    REG_GPIO_PXDIRC(p) = (1 << o); \
656    REG_GPIO_PXFLGC(p) = (1 << o); \
657    REG_GPIO_PXIMC(p) = (1 << o); \
658} while (0)
659
660#define __gpio_mask_irq(n) \
661do { \
662    unsigned int p, o; \
663    p = (n) / 32; \
664    o = (n) % 32; \
665    REG_GPIO_PXIMS(p) = (1 << o); \
666} while (0)
667
668#define __gpio_unmask_irq(n) \
669do { \
670    unsigned int p, o; \
671    p = (n) / 32; \
672    o = (n) % 32; \
673    REG_GPIO_PXIMC(p) = (1 << o); \
674} while (0)
675
676#define __gpio_ack_irq(n) \
677do { \
678    unsigned int p, o; \
679    p = (n) / 32; \
680    o = (n) % 32; \
681    REG_GPIO_PXFLGC(p) = (1 << o); \
682} while (0)
683
684#define __gpio_get_irq() \
685({ \
686    unsigned int p, i, tmp, v = 0; \
687    for (p = 3; p >= 0; p--) { \
688        tmp = REG_GPIO_PXFLG(p); \
689        for (i = 0; i < 32; i++) \
690            if (tmp & (1 << i)) \
691                v = (32*p + i); \
692    } \
693    v; \
694})
695
696#define __gpio_group_irq(n) \
697({ \
698    register int tmp, i; \
699    tmp = REG_GPIO_PXFLG((n)); \
700    for (i=31;i>=0;i--) \
701        if (tmp & (1 << i)) \
702            break; \
703    i; \
704})
705
706#define __gpio_enable_pull(n) \
707do { \
708    unsigned int p, o; \
709    p = (n) / 32; \
710    o = (n) % 32; \
711    REG_GPIO_PXPEC(p) = (1 << o); \
712} while (0)
713
714#define __gpio_disable_pull(n) \
715do { \
716    unsigned int p, o; \
717    p = (n) / 32; \
718    o = (n) % 32; \
719    REG_GPIO_PXPES(p) = (1 << o); \
720} while (0)
721
722
723/***************************************************************************
724 * CPM
725 ***************************************************************************/
726#define __cpm_get_pllm() \
727    ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
728#define __cpm_get_plln() \
729    ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
730#define __cpm_get_pllod() \
731    ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
732
733#define __cpm_get_cdiv() \
734    ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
735#define __cpm_get_hdiv() \
736    ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
737#define __cpm_get_pdiv() \
738    ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
739#define __cpm_get_mdiv() \
740    ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
741#define __cpm_get_ldiv() \
742    ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
743#define __cpm_get_udiv() \
744    ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
745#define __cpm_get_i2sdiv() \
746    ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
747#define __cpm_get_pixdiv() \
748    ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
749#define __cpm_get_mscdiv() \
750    ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
751#define __cpm_get_uhcdiv() \
752    ((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT)
753#define __cpm_get_ssidiv() \
754    ((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
755
756#define __cpm_set_cdiv(v) \
757    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
758#define __cpm_set_hdiv(v) \
759    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
760#define __cpm_set_pdiv(v) \
761    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
762#define __cpm_set_mdiv(v) \
763    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
764#define __cpm_set_ldiv(v) \
765    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
766#define __cpm_set_udiv(v) \
767    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
768#define __cpm_set_i2sdiv(v) \
769    (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
770#define __cpm_set_pixdiv(v) \
771    (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
772#define __cpm_set_mscdiv(v) \
773    (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
774#define __cpm_set_uhcdiv(v) \
775    (REG_CPM_UHCCDR = (REG_CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | ((v) << (CPM_UHCCDR_UHCDIV_BIT)))
776#define __cpm_ssiclk_select_exclk() \
777    (REG_CPM_SSICDR &= ~CPM_SSICDR_SCS)
778#define __cpm_ssiclk_select_pllout() \
779    (REG_CPM_SSICDR |= CPM_SSICDR_SCS)
780#define __cpm_set_ssidiv(v) \
781    (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
782
783#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
784#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
785#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
786#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
787#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
788#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
789#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
790#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
791
792#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
793#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
794#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
795
796#define __cpm_get_cclk_doze_duty() \
797    ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
798#define __cpm_set_cclk_doze_duty(v) \
799    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
800
801#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
802#define __cpm_idle_mode() \
803    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
804#define __cpm_sleep_mode() \
805    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
806
807#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
808#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
809#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
810#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
811#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
812#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
813#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
814#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
815#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
816#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
817#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
818#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
819#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
820#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
821#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
822#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
823#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
824
825#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
826#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
827#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
828#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
829#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
830#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
831#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
832#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
833#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
834#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
835#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
836#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
837#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
838#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
839#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
840#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
841#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
842
843#define __cpm_get_o1st() \
844    ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
845#define __cpm_set_o1st(v) \
846    (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
847#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
848#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
849
850
851/***************************************************************************
852 * TCU
853 ***************************************************************************/
854// where 'n' is the TCU channel
855#define __tcu_select_extalclk(n) \
856    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
857#define __tcu_select_rtcclk(n) \
858    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
859#define __tcu_select_pclk(n) \
860    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
861
862#define __tcu_select_clk_div1(n) \
863    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
864#define __tcu_select_clk_div4(n) \
865    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
866#define __tcu_select_clk_div16(n) \
867    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
868#define __tcu_select_clk_div64(n) \
869    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
870#define __tcu_select_clk_div256(n) \
871    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
872#define __tcu_select_clk_div1024(n) \
873    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
874
875#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
876#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
877
878#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
879#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
880
881#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
882#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
883
884#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
885#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
886
887#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
888#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
889#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
890#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
891#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
892#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
893#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
894#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
895#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
896#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
897
898#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
899#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
900
901#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
902#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
903
904#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
905#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
906
907#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
908#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
909#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
910#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
911
912
913/***************************************************************************
914 * WDT
915 ***************************************************************************/
916#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
917#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
918#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
919#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
920
921#define __wdt_select_extalclk() \
922    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
923#define __wdt_select_rtcclk() \
924    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
925#define __wdt_select_pclk() \
926    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
927
928#define __wdt_select_clk_div1() \
929    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
930#define __wdt_select_clk_div4() \
931    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
932#define __wdt_select_clk_div16() \
933    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
934#define __wdt_select_clk_div64() \
935    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
936#define __wdt_select_clk_div256() \
937    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
938#define __wdt_select_clk_div1024() \
939    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
940
941
942/***************************************************************************
943 * UART
944 ***************************************************************************/
945
946#define __uart_enable(n) \
947  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE )
948#define __uart_disable(n) \
949  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE )
950
951#define __uart_enable_transmit_irq(n) \
952  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE )
953#define __uart_disable_transmit_irq(n) \
954  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE )
955
956#define __uart_enable_receive_irq(n) \
957  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
958#define __uart_disable_receive_irq(n) \
959  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
960
961#define __uart_enable_loopback(n) \
962  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP )
963#define __uart_disable_loopback(n) \
964  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP )
965
966#define __uart_set_8n1(n) \
967  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 )
968
969#define __uart_set_baud(n, devclk, baud) \
970  do { \
971    REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \
972    REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \
973    REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
974    REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \
975  } while (0)
976
977#define __uart_parity_error(n) \
978  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 )
979
980#define __uart_clear_errors(n) \
981  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
982
983#define __uart_transmit_fifo_empty(n) \
984  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 )
985
986#define __uart_transmit_end(n) \
987  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 )
988
989#define __uart_transmit_char(n, ch) \
990  REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch)
991
992#define __uart_receive_fifo_full(n) \
993  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
994
995#define __uart_receive_ready(n) \
996  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
997
998#define __uart_receive_char(n) \
999  REG8(UART_BASE + UART_OFF*(n) + OFF_RDR)
1000
1001#define __uart_disable_irda() \
1002  ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
1003#define __uart_enable_irda() \
1004  /* Tx high pulse as 0, Rx low pulse as 0 */ \
1005  ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
1006
1007
1008/***************************************************************************
1009 * DMAC
1010 ***************************************************************************/
1011
1012/* n is the DMA channel (0 - 5) */
1013
1014#define __dmac_enable_module() \
1015  ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
1016#define __dmac_disable_module() \
1017  ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
1018
1019/* p=0,1,2,3 */
1020#define __dmac_set_priority(p) \
1021do { \
1022    REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
1023    REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
1024} while (0)
1025
1026#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
1027#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
1028
1029#define __dmac_enable_descriptor(n) \
1030  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
1031#define __dmac_disable_descriptor(n) \
1032  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
1033
1034#define __dmac_enable_channel(n) \
1035  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
1036#define __dmac_disable_channel(n) \
1037  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
1038#define __dmac_channel_enabled(n) \
1039  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
1040
1041#define __dmac_channel_enable_irq(n) \
1042  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
1043#define __dmac_channel_disable_irq(n) \
1044  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
1045
1046#define __dmac_channel_transmit_halt_detected(n) \
1047  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
1048#define __dmac_channel_transmit_end_detected(n) \
1049  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
1050#define __dmac_channel_address_error_detected(n) \
1051  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
1052#define __dmac_channel_count_terminated_detected(n) \
1053  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
1054#define __dmac_channel_descriptor_invalid_detected(n) \
1055  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
1056
1057#define __dmac_channel_clear_transmit_halt(n) \
1058  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
1059#define __dmac_channel_clear_transmit_end(n) \
1060  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
1061#define __dmac_channel_clear_address_error(n) \
1062  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
1063#define __dmac_channel_clear_count_terminated(n) \
1064  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
1065#define __dmac_channel_clear_descriptor_invalid(n) \
1066  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
1067
1068#define __dmac_channel_set_single_mode(n) \
1069  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
1070#define __dmac_channel_set_block_mode(n) \
1071  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
1072
1073#define __dmac_channel_set_transfer_unit_32bit(n) \
1074do { \
1075    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1076    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
1077} while (0)
1078
1079#define __dmac_channel_set_transfer_unit_16bit(n) \
1080do { \
1081    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1082    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
1083} while (0)
1084
1085#define __dmac_channel_set_transfer_unit_8bit(n) \
1086do { \
1087    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1088    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
1089} while (0)
1090
1091#define __dmac_channel_set_transfer_unit_16byte(n) \
1092do { \
1093    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1094    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
1095} while (0)
1096
1097#define __dmac_channel_set_transfer_unit_32byte(n) \
1098do { \
1099    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1100    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
1101} while (0)
1102
1103/* w=8,16,32 */
1104#define __dmac_channel_set_dest_port_width(n,w) \
1105do { \
1106    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
1107    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
1108} while (0)
1109
1110/* w=8,16,32 */
1111#define __dmac_channel_set_src_port_width(n,w) \
1112do { \
1113    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
1114    REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
1115} while (0)
1116
1117/* v=0-15 */
1118#define __dmac_channel_set_rdil(n,v) \
1119do { \
1120    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
1121    REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
1122} while (0)
1123
1124#define __dmac_channel_dest_addr_fixed(n) \
1125  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
1126#define __dmac_channel_dest_addr_increment(n) \
1127  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
1128
1129#define __dmac_channel_src_addr_fixed(n) \
1130  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
1131#define __dmac_channel_src_addr_increment(n) \
1132  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
1133
1134#define __dmac_channel_set_doorbell(n) \
1135  ( REG_DMAC_DMADBSR = (1 << (n)) )
1136
1137#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
1138#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
1139
1140static __inline__ int __dmac_get_irq(void)
1141{
1142    int i;
1143    for (i = 0; i < MAX_DMA_NUM; i++)
1144        if (__dmac_channel_irq_detected(i))
1145            return i;
1146    return -1;
1147}
1148
1149
1150/***************************************************************************
1151 * AIC (AC'97 & I2S Controller)
1152 ***************************************************************************/
1153
1154#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
1155#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
1156
1157#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
1158#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
1159
1160#define __aic_play_zero() ( REG_AIC_FR &= ~AIC_FR_LSMP )
1161#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
1162
1163#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
1164#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
1165#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
1166
1167#define __aic_reset() \
1168do { \
1169        REG_AIC_FR |= AIC_FR_RST; \
1170} while(0)
1171
1172
1173#define __aic_set_transmit_trigger(n) \
1174do { \
1175    REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
1176    REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
1177} while(0)
1178
1179#define __aic_set_receive_trigger(n) \
1180do { \
1181    REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
1182    REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
1183} while(0)
1184
1185#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
1186#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
1187#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
1188#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
1189#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
1190#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
1191
1192#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
1193#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
1194
1195#define __aic_enable_transmit_intr() \
1196  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
1197#define __aic_disable_transmit_intr() \
1198  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
1199#define __aic_enable_receive_intr() \
1200  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
1201#define __aic_disable_receive_intr() \
1202  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
1203
1204#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
1205#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
1206#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
1207#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
1208
1209#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
1210#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
1211#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
1212#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
1213#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
1214#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
1215
1216#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
1217#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
1218#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
1219#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
1220#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
1221#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
1222
1223#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
1224#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
1225#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
1226#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
1227#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
1228#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
1229
1230#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
1231#define __ac97_set_xs_mono() \
1232do { \
1233    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
1234    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
1235} while(0)
1236#define __ac97_set_xs_stereo() \
1237do { \
1238    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
1239    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
1240} while(0)
1241
1242/* In fact, only stereo is support now. */
1243#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
1244#define __ac97_set_rs_mono() \
1245do { \
1246    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
1247    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
1248} while(0)
1249#define __ac97_set_rs_stereo() \
1250do { \
1251    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
1252    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
1253} while(0)
1254
1255#define __ac97_warm_reset_codec() \
1256 do { \
1257    REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
1258    REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
1259    udelay(2); \
1260    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
1261    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
1262 } while (0)
1263
1264#define __ac97_cold_reset_codec() \
1265 do { \
1266    REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
1267    udelay(2); \
1268    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
1269 } while (0)
1270
1271/* n=8,16,18,20 */
1272#define __ac97_set_iass(n) \
1273 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
1274#define __ac97_set_oass(n) \
1275 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
1276
1277#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
1278#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
1279
1280/* n=8,16,18,20,24 */
1281/*#define __i2s_set_sample_size(n) \
1282 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
1283
1284#define __i2s_set_oss_sample_size(n) \
1285 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
1286#define __i2s_set_iss_sample_size(n) \
1287 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
1288
1289#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
1290#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
1291
1292#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
1293#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
1294#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
1295#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
1296
1297#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
1298
1299#define __aic_get_transmit_resident() \
1300  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
1301#define __aic_get_receive_count() \
1302  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
1303
1304#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
1305#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
1306#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
1307#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
1308#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
1309#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
1310#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
1311
1312#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
1313
1314#define CODEC_READ_CMD (1 << 19)
1315#define CODEC_WRITE_CMD (0 << 19)
1316#define CODEC_REG_INDEX_BIT 12
1317#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
1318#define CODEC_REG_DATA_BIT 4
1319#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
1320
1321#define __ac97_out_rcmd_addr(reg) \
1322do { \
1323    REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
1324} while (0)
1325
1326#define __ac97_out_wcmd_addr(reg) \
1327do { \
1328    REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
1329} while (0)
1330
1331#define __ac97_out_data(value) \
1332do { \
1333    REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
1334} while (0)
1335
1336#define __ac97_in_data() \
1337 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
1338
1339#define __ac97_in_status_addr() \
1340 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
1341
1342#define __i2s_set_sample_rate(i2sclk, sync) \
1343  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
1344
1345#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
1346#define __aic_read_rfifo() ( REG_AIC_DR )
1347
1348#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
1349#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
1350
1351//
1352// Define next ops for AC97 compatible
1353//
1354
1355#define AC97_ACSR AIC_ACSR
1356
1357#define __ac97_enable() __aic_enable(); __aic_select_ac97()
1358#define __ac97_disable() __aic_disable()
1359#define __ac97_reset() __aic_reset()
1360
1361#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
1362#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
1363
1364#define __ac97_enable_record() __aic_enable_record()
1365#define __ac97_disable_record() __aic_disable_record()
1366#define __ac97_enable_replay() __aic_enable_replay()
1367#define __ac97_disable_replay() __aic_disable_replay()
1368#define __ac97_enable_loopback() __aic_enable_loopback()
1369#define __ac97_disable_loopback() __aic_disable_loopback()
1370
1371#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
1372#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
1373#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
1374#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
1375
1376#define __ac97_transmit_request() __aic_transmit_request()
1377#define __ac97_receive_request() __aic_receive_request()
1378#define __ac97_transmit_underrun() __aic_transmit_underrun()
1379#define __ac97_receive_overrun() __aic_receive_overrun()
1380
1381#define __ac97_clear_errors() __aic_clear_errors()
1382
1383#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
1384#define __ac97_get_receive_count() __aic_get_receive_count()
1385
1386#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
1387#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
1388#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
1389#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
1390
1391#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
1392#define __ac97_read_rfifo() __aic_read_rfifo()
1393
1394//
1395// Define next ops for I2S compatible
1396//
1397
1398#define I2S_ACSR AIC_I2SSR
1399
1400#define __i2s_enable() __aic_enable(); __aic_select_i2s()
1401#define __i2s_disable() __aic_disable()
1402#define __i2s_reset() __aic_reset()
1403
1404#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
1405#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
1406
1407#define __i2s_enable_record() __aic_enable_record()
1408#define __i2s_disable_record() __aic_disable_record()
1409#define __i2s_enable_replay() __aic_enable_replay()
1410#define __i2s_disable_replay() __aic_disable_replay()
1411#define __i2s_enable_loopback() __aic_enable_loopback()
1412#define __i2s_disable_loopback() __aic_disable_loopback()
1413
1414#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
1415#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
1416#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
1417#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
1418
1419#define __i2s_transmit_request() __aic_transmit_request()
1420#define __i2s_receive_request() __aic_receive_request()
1421#define __i2s_transmit_underrun() __aic_transmit_underrun()
1422#define __i2s_receive_overrun() __aic_receive_overrun()
1423
1424#define __i2s_clear_errors() __aic_clear_errors()
1425
1426#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
1427#define __i2s_get_receive_count() __aic_get_receive_count()
1428
1429#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
1430#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
1431#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
1432#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
1433
1434#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
1435#define __i2s_read_rfifo() __aic_read_rfifo()
1436
1437#define __i2s_reset_codec() \
1438 do { \
1439 } while (0)
1440
1441
1442/***************************************************************************
1443 * ICDC
1444 ***************************************************************************/
1445#define __i2s_internal_codec() __aic_internal_codec()
1446#define __i2s_external_codec() __aic_external_codec()
1447
1448/***************************************************************************
1449 * INTC
1450 ***************************************************************************/
1451#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
1452#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
1453#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
1454
1455
1456/***************************************************************************
1457 * I2C
1458 ***************************************************************************/
1459
1460#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
1461#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
1462
1463#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
1464#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
1465#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
1466#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
1467
1468#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
1469#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
1470#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
1471
1472#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
1473#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
1474#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
1475
1476#define __i2c_set_clk(dev_clk, i2c_clk) \
1477  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
1478
1479#define __i2c_read() ( REG_I2C_DR )
1480#define __i2c_write(val) ( REG_I2C_DR = (val) )
1481
1482
1483/***************************************************************************
1484 * MSC
1485 ***************************************************************************/
1486
1487#define __msc_start_op() \
1488  ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
1489
1490#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
1491#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
1492#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
1493#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
1494#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
1495#define __msc_get_nob() ( REG_MSC_NOB )
1496#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
1497#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
1498#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
1499#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
1500
1501#define __msc_set_cmdat_bus_width1() \
1502do { \
1503    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
1504    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
1505} while(0)
1506
1507#define __msc_set_cmdat_bus_width4() \
1508do { \
1509    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
1510    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
1511} while(0)
1512
1513#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
1514#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
1515#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
1516#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
1517#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
1518#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
1519#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
1520#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
1521
1522/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
1523#define __msc_set_cmdat_res_format(r) \
1524do { \
1525    REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
1526    REG_MSC_CMDAT |= (r); \
1527} while(0)
1528
1529#define __msc_clear_cmdat() \
1530  REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
1531  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
1532  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
1533
1534#define __msc_get_imask() ( REG_MSC_IMASK )
1535#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
1536#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
1537#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
1538#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
1539#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
1540#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
1541#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
1542#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
1543#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
1544#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
1545#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
1546#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
1547
1548/* n=0,1,2,3,4,5,6,7 */
1549#define __msc_set_clkrt(n) \
1550do { \
1551    REG_MSC_CLKRT = n; \
1552} while(0)
1553
1554#define __msc_get_ireg() ( REG_MSC_IREG )
1555#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
1556#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
1557#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
1558#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
1559#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
1560#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
1561#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
1562#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
1563
1564#define __msc_get_stat() ( REG_MSC_STAT )
1565#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
1566#define __msc_stat_crc_err() \
1567  ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
1568#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
1569#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
1570#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
1571#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
1572#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
1573
1574#define __msc_rd_resfifo() ( REG_MSC_RES )
1575#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
1576#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
1577
1578#define __msc_reset() \
1579do { \
1580    REG_MSC_STRPCL = MSC_STRPCL_RESET; \
1581     while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
1582} while (0)
1583
1584#define __msc_start_clk() \
1585do { \
1586    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
1587} while (0)
1588
1589#define __msc_stop_clk() \
1590do { \
1591    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
1592} while (0)
1593
1594#define MMC_CLK 19169200
1595#define SD_CLK 24576000
1596
1597/* msc_clk should little than pclk and little than clk retrieve from card */
1598#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
1599do { \
1600    unsigned int rate, pclk, i; \
1601    pclk = dev_clk; \
1602    rate = type?SD_CLK:MMC_CLK; \
1603      if (msc_clk && msc_clk < pclk) \
1604            pclk = msc_clk; \
1605    i = 0; \
1606      while (pclk < rate) \
1607        { \
1608              i ++; \
1609              rate >>= 1; \
1610        } \
1611      lv = i; \
1612} while(0)
1613
1614/* divide rate to little than or equal to 400kHz */
1615#define __msc_calc_slow_clk_divisor(type, lv) \
1616do { \
1617    unsigned int rate, i; \
1618    rate = (type?SD_CLK:MMC_CLK)/1000/400; \
1619    i = 0; \
1620    while (rate > 0) \
1621        { \
1622              rate >>= 1; \
1623              i ++; \
1624        } \
1625      lv = i; \
1626} while(0)
1627
1628
1629/***************************************************************************
1630 * SSI
1631 ***************************************************************************/
1632
1633#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
1634#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
1635#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
1636
1637#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
1638
1639#define __ssi_select_ce2() \
1640do { \
1641    REG_SSI_CR0 |= SSI_CR0_FSEL; \
1642    REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
1643} while (0)
1644
1645#define __ssi_select_gpc() \
1646do { \
1647    REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
1648    REG_SSI_CR1 |= SSI_CR1_MULTS; \
1649} while (0)
1650
1651#define __ssi_enable_tx_intr() \
1652  ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
1653
1654#define __ssi_disable_tx_intr() \
1655  ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
1656
1657#define __ssi_enable_rx_intr() \
1658  ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
1659
1660#define __ssi_disable_rx_intr() \
1661  ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
1662
1663#define __ssi_enable_txfifo_half_empty_intr() \
1664    ( REG_SSI_CR0 |= SSI_CR0_TIE )
1665#define __ssi_disable_txfifo_half_empty_intr() \
1666    ( REG_SSI_CR0 &= ~SSI_CR0_TIE )
1667#define __ssi_enable_tx_error_intr() \
1668    ( REG_SSI_CR0 |= SSI_CR0_TEIE )
1669#define __ssi_disable_tx_error_intr() \
1670    ( REG_SSI_CR0 &= ~SSI_CR0_TEIE )
1671
1672#define __ssi_enable_rxfifo_half_full_intr() \
1673    ( REG_SSI_CR0 |= SSI_CR0_RIE )
1674#define __ssi_disable_rxfifo_half_full_intr() \
1675    ( REG_SSI_CR0 &= ~SSI_CR0_RIE )
1676#define __ssi_enable_rx_error_intr() \
1677    ( REG_SSI_CR0 |= SSI_CR0_REIE )
1678#define __ssi_disable_rx_error_intr() \
1679    ( REG_SSI_CR0 &= ~SSI_CR0_REIE )
1680
1681#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
1682#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
1683
1684#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
1685#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
1686
1687#define __ssi_finish_receive() \
1688  ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
1689
1690#define __ssi_disable_recvfinish() \
1691  ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
1692
1693#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
1694#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
1695
1696#define __ssi_flush_fifo() \
1697  ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
1698
1699#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
1700#define __ssi_wait_transmit() ( REG_SSI_CR1 |= SSI_CR1_UNFIN )
1701
1702#define __ssi_spi_format() \
1703do { \
1704    REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
1705    REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
1706    REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
1707    REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
1708} while (0)
1709
1710/* TI's SSP format, must clear SSI_CR1.UNFIN */
1711#define __ssi_ssp_format() \
1712do { \
1713    REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
1714    REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
1715} while (0)
1716
1717/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
1718#define __ssi_microwire_format() \
1719do { \
1720    REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
1721    REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
1722    REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
1723    REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
1724    REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
1725} while (0)
1726
1727/* CE# level (FRMHL), CE# in interval time (ITFRM),
1728   clock phase and polarity (PHA POL),
1729   interval time (SSIITR), interval characters/frame (SSIICR) */
1730
1731 /* frmhl,endian,mcom,flen,pha,pol MASK */
1732#define SSICR1_MISC_MASK \
1733    ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
1734    | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
1735
1736#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
1737do { \
1738    REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
1739    REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
1740         (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
1741             ((pha) << 1) | (pol); \
1742} while(0)
1743
1744/* Transfer with MSB or LSB first */
1745#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
1746#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
1747
1748#define __ssi_set_frame_length(n) \
1749    REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
1750
1751/* n = 1 - 16 */
1752#define __ssi_set_microwire_command_length(n) \
1753    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
1754
1755/* Set the clock phase for SPI */
1756#define __ssi_set_spi_clock_phase(n) \
1757    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | ((n&0x1)<< 1)))
1758
1759/* Set the clock polarity for SPI */
1760#define __ssi_set_spi_clock_polarity(n) \
1761    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
1762
1763/* n = ix8 */
1764#define __ssi_set_tx_trigger(n) \
1765do { \
1766    REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
1767    REG_SSI_CR1 |= (n/8)<<SSI_CR1_TTRG_BIT; \
1768} while (0)
1769
1770/* n = ix8 */
1771#define __ssi_set_rx_trigger(n) \
1772do { \
1773    REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
1774    REG_SSI_CR1 |= (n/8)<<SSI_CR1_RTRG_BIT; \
1775} while (0)
1776
1777#define __ssi_get_txfifo_count() \
1778    ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
1779
1780#define __ssi_get_rxfifo_count() \
1781    ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
1782
1783#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
1784#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
1785
1786#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
1787#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
1788#define __ssi_rxfifo_half_full() ( REG_SSI_SR & SSI_SR_RFHF )
1789#define __ssi_txfifo_half_empty() ( REG_SSI_SR & SSI_SR_TFHE )
1790#define __ssi_underrun() ( REG_SSI_SR & SSI_SR_UNDR )
1791#define __ssi_overrun() ( REG_SSI_SR & SSI_SR_OVER )
1792#define __ssi_clear_underrun() ( REG_SSI_SR = ~SSI_SR_UNDR )
1793#define __ssi_clear_overrun() ( REG_SSI_SR = ~SSI_SR_OVER )
1794#define __ssi_clear_errors() \
1795    ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
1796
1797
1798#define __ssi_set_clk(dev_clk, ssi_clk) \
1799  ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
1800
1801#define __ssi_receive_data() REG_SSI_DR
1802#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
1803
1804
1805/***************************************************************************
1806 * CIM
1807 ***************************************************************************/
1808
1809#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
1810#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
1811
1812#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
1813#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
1814
1815#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
1816#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
1817
1818#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
1819#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
1820
1821#define __cim_sample_data_at_pclk_falling_edge() \
1822  ( REG_CIM_CFG |= CIM_CFG_PCP )
1823#define __cim_sample_data_at_pclk_rising_edge() \
1824  ( REG_CIM_CFG &= ~CIM_CFG_PCP )
1825
1826#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
1827#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
1828
1829#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
1830#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
1831
1832/* n=0-7 */
1833#define __cim_set_data_packing_mode(n) \
1834do { \
1835    REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
1836    REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
1837} while (0)
1838
1839#define __cim_enable_ccir656_progressive_mode() \
1840do { \
1841    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1842    REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
1843} while (0)
1844
1845#define __cim_enable_ccir656_interlace_mode() \
1846do { \
1847    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1848    REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
1849} while (0)
1850
1851#define __cim_enable_gated_clock_mode() \
1852do { \
1853    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1854    REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
1855} while (0)
1856
1857#define __cim_enable_nongated_clock_mode() \
1858do { \
1859    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1860    REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
1861} while (0)
1862
1863/* sclk:system bus clock
1864 * mclk: CIM master clock
1865 */
1866#define __cim_set_master_clk(sclk, mclk) \
1867do { \
1868    REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
1869    REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
1870} while (0)
1871
1872#define __cim_enable_sof_intr() \
1873  ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
1874#define __cim_disable_sof_intr() \
1875  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
1876
1877#define __cim_enable_eof_intr() \
1878  ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
1879#define __cim_disable_eof_intr() \
1880  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
1881
1882#define __cim_enable_stop_intr() \
1883  ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
1884#define __cim_disable_stop_intr() \
1885  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
1886
1887#define __cim_enable_trig_intr() \
1888  ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
1889#define __cim_disable_trig_intr() \
1890  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
1891
1892#define __cim_enable_rxfifo_overflow_intr() \
1893  ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
1894#define __cim_disable_rxfifo_overflow_intr() \
1895  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
1896
1897/* n=1-16 */
1898#define __cim_set_frame_rate(n) \
1899do { \
1900    REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
1901    REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
1902} while (0)
1903
1904#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
1905#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
1906
1907#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
1908#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
1909
1910/* n=4,8,12,16,20,24,28,32 */
1911#define __cim_set_rxfifo_trigger(n) \
1912do { \
1913    REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
1914    REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
1915} while (0)
1916
1917#define __cim_clear_state() ( REG_CIM_STATE = 0 )
1918
1919#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
1920#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
1921#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
1922#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
1923#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
1924#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
1925#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
1926#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
1927
1928#define __cim_get_iid() ( REG_CIM_IID )
1929#define __cim_get_image_data() ( REG_CIM_RXFIFO )
1930#define __cim_get_dam_cmd() ( REG_CIM_CMD )
1931
1932#define __cim_set_da(a) ( REG_CIM_DA = (a) )
1933
1934/***************************************************************************
1935 * LCD
1936 ***************************************************************************/
1937#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
1938#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
1939
1940#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
1941#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
1942
1943#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
1944#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
1945
1946/* n=1,2,4,8,16 */
1947#define __lcd_set_bpp(n) \
1948  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
1949
1950/* n=4,8,16 */
1951#define __lcd_set_burst_length(n) \
1952do { \
1953    REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
1954    REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
1955} while (0)
1956
1957#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
1958#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
1959
1960#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
1961#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
1962
1963/* n=2,4,16 */
1964#define __lcd_set_stn_frc(n) \
1965do { \
1966    REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
1967    REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
1968} while (0)
1969
1970
1971#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
1972#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
1973
1974#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
1975#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
1976
1977#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
1978#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
1979
1980#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
1981#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
1982
1983#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
1984#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
1985
1986#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
1987#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
1988
1989#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
1990#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
1991
1992#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
1993#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
1994
1995#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
1996#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
1997
1998
1999/* LCD status register indication */
2000
2001#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
2002#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
2003#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
2004#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
2005#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
2006#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
2007#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
2008
2009#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
2010#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
2011#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
2012
2013#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
2014#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
2015
2016/* n=1,2,4,8 for single mono-STN
2017 * n=4,8 for dual mono-STN
2018 */
2019#define __lcd_set_panel_datawidth(n) \
2020do { \
2021    REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
2022    REG_LCD_CFG |= LCD_CFG_PDW_n##; \
2023} while (0)
2024
2025/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
2026#define __lcd_set_panel_mode(m) \
2027do { \
2028    REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
2029    REG_LCD_CFG |= (m); \
2030} while(0)
2031
2032/* n = 0-255 */
2033#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
2034#define __lcd_set_ac_bias(n) \
2035do { \
2036    REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
2037    REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
2038} while(0)
2039
2040#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
2041#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
2042
2043#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
2044#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
2045
2046#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
2047#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
2048
2049#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
2050#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
2051
2052#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
2053#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
2054
2055#define __lcd_vsync_get_vps() \
2056  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
2057
2058#define __lcd_vsync_get_vpe() \
2059  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
2060#define __lcd_vsync_set_vpe(n) \
2061do { \
2062    REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
2063    REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
2064} while (0)
2065
2066#define __lcd_hsync_get_hps() \
2067  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
2068#define __lcd_hsync_set_hps(n) \
2069do { \
2070    REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
2071    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
2072} while (0)
2073
2074#define __lcd_hsync_get_hpe() \
2075  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
2076#define __lcd_hsync_set_hpe(n) \
2077do { \
2078    REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
2079    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
2080} while (0)
2081
2082#define __lcd_vat_get_ht() \
2083  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
2084#define __lcd_vat_set_ht(n) \
2085do { \
2086    REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
2087    REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
2088} while (0)
2089
2090#define __lcd_vat_get_vt() \
2091  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
2092#define __lcd_vat_set_vt(n) \
2093do { \
2094    REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
2095    REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
2096} while (0)
2097
2098#define __lcd_dah_get_hds() \
2099  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
2100#define __lcd_dah_set_hds(n) \
2101do { \
2102    REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
2103    REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
2104} while (0)
2105
2106#define __lcd_dah_get_hde() \
2107  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
2108#define __lcd_dah_set_hde(n) \
2109do { \
2110    REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
2111    REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
2112} while (0)
2113
2114#define __lcd_dav_get_vds() \
2115  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
2116#define __lcd_dav_set_vds(n) \
2117do { \
2118    REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
2119    REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
2120} while (0)
2121
2122#define __lcd_dav_get_vde() \
2123  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
2124#define __lcd_dav_set_vde(n) \
2125do { \
2126    REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
2127    REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
2128} while (0)
2129
2130#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
2131#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
2132#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
2133#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
2134
2135#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
2136#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
2137#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
2138#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
2139
2140#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
2141#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
2142
2143#define __lcd_cmd0_get_len() \
2144  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
2145#define __lcd_cmd1_get_len() \
2146  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
2147
2148/*******************************************************
2149 * SMART LCD
2150 *******************************************************/
2151
2152#define __slcd_dma_enable() (REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN)
2153#define __slcd_dma_disable() \
2154do {\
2155    while (REG_SLCD_STATE & SLCD_STATE_BUSY); \
2156    REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; \
2157} while(0)
2158
2159/*******************************************************
2160 * SMART LCD
2161 *******************************************************/
2162
2163#define __slcd_dma_enable() (REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN)
2164#define __slcd_dma_disable() \
2165do {\
2166    while (REG_SLCD_STATE & SLCD_STATE_BUSY); \
2167    REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; \
2168} while(0)
2169
2170/***************************************************************************
2171 * RTC ops
2172 ***************************************************************************/
2173
2174#define __rtc_write_ready() ( (REG_RTC_RCR & RTC_RCR_WRDY) >> RTC_RCR_WRDY_BIT )
2175#define __rtc_enabled() ( REG_RTC_RCR |= RTC_RCR_RTCE )
2176#define __rtc_disabled() ( REG_RTC_RCR &= ~RTC_RCR_RTCE )
2177#define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE )
2178#define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE )
2179#define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE )
2180#define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE )
2181#define __rtc_enable_1Hz_irq() ( REG_RTC_RCR |= RTC_RCR_1HZIE )
2182#define __rtc_disable_1Hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_1HZIE )
2183
2184#define __rtc_get_1Hz_flag() ( (REG_RTC_RCR >> RTC_RCR_1HZ_BIT) & 0x1 )
2185#define __rtc_clear_1Hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_1HZ )
2186#define __rtc_get_alarm_flag() ( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 )
2187#define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF )
2188
2189#define __rtc_get_second() ( REG_RTC_RSR )
2190#define __rtc_set_second(v) ( REG_RTC_RSR = v )
2191
2192#define __rtc_get_alarm_second() ( REG_RTC_RSAR )
2193#define __rtc_set_alarm_second(v) ( REG_RTC_RSAR = v )
2194
2195#define __rtc_RGR_is_locked() ( (REG_RTC_RGR >> RTC_RGR_LOCK) )
2196#define __rtc_lock_RGR() ( REG_RTC_RGR |= RTC_RGR_LOCK )
2197#define __rtc_unlock_RGR() ( REG_RTC_RGR &= ~RTC_RGR_LOCK )
2198#define __rtc_get_adjc_val() ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT )
2199#define __rtc_set_adjc_val(v) \
2200       ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) ))
2201#define __rtc_get_nc1Hz_val() ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
2202#define __rtc_set_nc1Hz_val(v) \
2203       ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) ))
2204
2205#define __rtc_power_down() ( REG_RTC_HCR |= RTC_HCR_PD )
2206
2207#define __rtc_get_hwfcr_val() ( REG_RTC_HWFCR & RTC_HWFCR_MASK )
2208#define __rtc_set_hwfcr_val(v) ( REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK )
2209#define __rtc_get_hrcr_val() ( REG_RTC_HRCR & RTC_HRCR_MASK )
2210#define __rtc_set_hrcr_val(v) ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK )
2211
2212#define __rtc_enable_alarm_wakeup() ( REG_RTC_HWCR |= RTC_HWCR_EALM )
2213#define __rtc_disable_alarm_wakeup() ( REG_RTC_HWCR &= ~RTC_HWCR_EALM )
2214
2215#define __rtc_status_hib_reset_occur() ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 )
2216#define __rtc_status_ppr_reset_occur() ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 )
2217#define __rtc_status_wakeup_pin_waken_up() ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 )
2218#define __rtc_status_alarm_waken_up() ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 )
2219#define __rtc_clear_hib_stat_all() ( REG_RTC_HWRSR = 0 )
2220
2221#define __rtc_get_scratch_pattern() (REG_RTC_HSPR)
2222#define __rtc_set_scratch_pattern(n) (REG_RTC_HSPR = n )
2223
2224
2225
2226#endif /* __JZ4740_OPS_H__ */
arch/mips/include/asm/mach-jz4740/platform.h
1
2#ifndef __JZ4740_PLATFORM_H
3#define __JZ4740_PLATFORM_H
4
5#include <linux/platform_device.h>
6
7extern struct platform_device jz4740_usb_ohci_device;
8extern struct platform_device jz4740_usb_gdt_device;
9extern struct platform_device jz4740_mmc_device;
10extern struct platform_device jz4740_rtc_device;
11extern struct platform_device jz4740_i2c_device;
12extern struct platform_device jz4740_nand_device;
13extern struct platform_device jz4740_framebuffer_device;
14extern struct platform_device jz4740_i2s_device;
15extern struct platform_device jz4740_codec_device;
16extern struct platform_device jz4740_adc_device;
17extern struct platform_device jz4740_battery_device;
18
19#endif
arch/mips/include/asm/mach-jz4740/regs.h
1/*
2 * linux/include/asm-mips/mach-jz4740/regs.h
3 *
4 * Ingenic's JZ4740 common include.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <yliu@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __JZ4740_REGS_H__
16#define __JZ4740_REGS_H__
17
18#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)
19#define REG8(addr) (addr)
20#define REG16(addr) (addr)
21#define REG32(addr) (addr)
22#else
23#define REG8(addr) *((volatile unsigned char *)(addr))
24#define REG16(addr) *((volatile unsigned short *)(addr))
25#define REG32(addr) *((volatile unsigned int *)(addr))
26#endif
27
28/*
29 * Define the module base addresses
30 */
31#define CPM_BASE 0xB0000000
32#define INTC_BASE 0xB0001000
33#define TCU_BASE 0xB0002000
34#define WDT_BASE 0xB0002000
35#define RTC_BASE 0xB0003000
36#define GPIO_BASE 0xB0010000
37#define AIC_BASE 0xB0020000
38#define ICDC_BASE 0xB0020000
39#define MSC_BASE 0xB0021000
40#define UART0_BASE 0xB0030000
41#define UART1_BASE 0xB0031000
42#define I2C_BASE 0xB0042000
43#define SSI_BASE 0xB0043000
44#define SADC_BASE 0xB0070000
45#define EMC_BASE 0xB3010000
46#define DMAC_BASE 0xB3020000
47#define UHC_BASE 0xB3030000
48#define UDC_BASE 0xB3040000
49#define LCD_BASE 0xB3050000
50#define SLCD_BASE 0xB3050000
51#define CIM_BASE 0xB3060000
52#define IPU_BASE 0xB3080000
53#define ETH_BASE 0xB3100000
54
55
56/*************************************************************************
57 * INTC (Interrupt Controller)
58 *************************************************************************/
59#define INTC_ISR (INTC_BASE + 0x00)
60#define INTC_IMR (INTC_BASE + 0x04)
61#define INTC_IMSR (INTC_BASE + 0x08)
62#define INTC_IMCR (INTC_BASE + 0x0c)
63#define INTC_IPR (INTC_BASE + 0x10)
64
65#define REG_INTC_ISR REG32(INTC_ISR)
66#define REG_INTC_IMR REG32(INTC_IMR)
67#define REG_INTC_IMSR REG32(INTC_IMSR)
68#define REG_INTC_IMCR REG32(INTC_IMCR)
69#define REG_INTC_IPR REG32(INTC_IPR)
70
71#define NUM_DMA 6
72#define NUM_GPIO 128
73/*************************************************************************
74 * RTC
75 *************************************************************************/
76#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
77#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
78#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
79#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
80
81#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
82#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
83#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
84#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
85#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
86#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
87
88#define REG_RTC_RCR REG32(RTC_RCR)
89#define REG_RTC_RSR REG32(RTC_RSR)
90#define REG_RTC_RSAR REG32(RTC_RSAR)
91#define REG_RTC_RGR REG32(RTC_RGR)
92#define REG_RTC_HCR REG32(RTC_HCR)
93#define REG_RTC_HWFCR REG32(RTC_HWFCR)
94#define REG_RTC_HRCR REG32(RTC_HRCR)
95#define REG_RTC_HWCR REG32(RTC_HWCR)
96#define REG_RTC_HWRSR REG32(RTC_HWRSR)
97#define REG_RTC_HSPR REG32(RTC_HSPR)
98
99/* RTC Control Register */
100#define RTC_RCR_WRDY_BIT 7
101#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
102#define RTC_RCR_1HZ_BIT 6
103#define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */
104#define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */
105#define RTC_RCR_AF_BIT 4
106#define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */
107#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
108#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
109#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
110
111/* RTC Regulator Register */
112#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
113#define RTC_RGR_ADJC_BIT 16
114#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
115#define RTC_RGR_NC1HZ_BIT 0
116#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
117
118/* Hibernate Control Register */
119#define RTC_HCR_PD (1 << 0) /* Power Down */
120
121/* Hibernate Wakeup Filter Counter Register */
122#define RTC_HWFCR_BIT 5
123#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
124
125/* Hibernate Reset Counter Register */
126#define RTC_HRCR_BIT 5
127#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
128
129/* Hibernate Wakeup Control Register */
130#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
131
132/* Hibernate Wakeup Status Register */
133#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
134#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
135#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
136#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
137
138
139/*************************************************************************
140 * CPM (Clock reset and Power control Management)
141 *************************************************************************/
142#define CPM_CPCCR (CPM_BASE+0x00)
143#define CPM_CPPCR (CPM_BASE+0x10)
144#define CPM_I2SCDR (CPM_BASE+0x60)
145#define CPM_LPCDR (CPM_BASE+0x64)
146#define CPM_MSCCDR (CPM_BASE+0x68)
147#define CPM_UHCCDR (CPM_BASE+0x6C)
148#define CPM_SSICDR (CPM_BASE+0x74)
149
150#define CPM_LCR (CPM_BASE+0x04)
151#define CPM_CLKGR (CPM_BASE+0x20)
152#define CPM_SCR (CPM_BASE+0x24)
153
154#define CPM_HCR (CPM_BASE+0x30)
155#define CPM_HWFCR (CPM_BASE+0x34)
156#define CPM_HRCR (CPM_BASE+0x38)
157#define CPM_HWCR (CPM_BASE+0x3c)
158#define CPM_HWSR (CPM_BASE+0x40)
159#define CPM_HSPR (CPM_BASE+0x44)
160
161#define CPM_RSR (CPM_BASE+0x08)
162
163
164#define REG_CPM_CPCCR REG32(CPM_CPCCR)
165#define REG_CPM_CPPCR REG32(CPM_CPPCR)
166#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
167#define REG_CPM_LPCDR REG32(CPM_LPCDR)
168#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
169#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
170#define REG_CPM_SSICDR REG32(CPM_SSICDR)
171
172#define REG_CPM_LCR REG32(CPM_LCR)
173#define REG_CPM_CLKGR REG32(CPM_CLKGR)
174#define REG_CPM_SCR REG32(CPM_SCR)
175#define REG_CPM_HCR REG32(CPM_HCR)
176#define REG_CPM_HWFCR REG32(CPM_HWFCR)
177#define REG_CPM_HRCR REG32(CPM_HRCR)
178#define REG_CPM_HWCR REG32(CPM_HWCR)
179#define REG_CPM_HWSR REG32(CPM_HWSR)
180#define REG_CPM_HSPR REG32(CPM_HSPR)
181
182#define REG_CPM_RSR REG32(CPM_RSR)
183
184
185/* Clock Control Register */
186#define CPM_CPCCR_I2CS (1 << 31)
187#define CPM_CPCCR_CLKOEN (1 << 30)
188#define CPM_CPCCR_UCS (1 << 29)
189#define CPM_CPCCR_UDIV_BIT 23
190#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
191#define CPM_CPCCR_CE (1 << 22)
192#define CPM_CPCCR_PCS (1 << 21)
193#define CPM_CPCCR_LDIV_BIT 16
194#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
195#define CPM_CPCCR_MDIV_BIT 12
196#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
197#define CPM_CPCCR_PDIV_BIT 8
198#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
199#define CPM_CPCCR_HDIV_BIT 4
200#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
201#define CPM_CPCCR_CDIV_BIT 0
202#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
203
204/* I2S Clock Divider Register */
205#define CPM_I2SCDR_I2SDIV_BIT 0
206#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
207
208/* LCD Pixel Clock Divider Register */
209#define CPM_LPCDR_PIXDIV_BIT 0
210#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
211
212/* MSC Clock Divider Register */
213#define CPM_MSCCDR_MSCDIV_BIT 0
214#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
215
216/* UHC Clock Divider Register */
217#define CPM_UHCCDR_UHCDIV_BIT 0
218#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
219
220/* SSI Clock Divider Register */
221#define CPM_SSICDR_SCS (1<<31) /* SSI clock source selection, 0:EXCLK, 1: PLL */
222#define CPM_SSICDR_SSIDIV_BIT 0
223#define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT)
224
225/* PLL Control Register */
226#define CPM_CPPCR_PLLM_BIT 23
227#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
228#define CPM_CPPCR_PLLN_BIT 18
229#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
230#define CPM_CPPCR_PLLOD_BIT 16
231#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
232#define CPM_CPPCR_PLLS (1 << 10)
233#define CPM_CPPCR_PLLBP (1 << 9)
234#define CPM_CPPCR_PLLEN (1 << 8)
235#define CPM_CPPCR_PLLST_BIT 0
236#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
237
238/* Low Power Control Register */
239#define CPM_LCR_DOZE_DUTY_BIT 3
240#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
241#define CPM_LCR_DOZE_ON (1 << 2)
242#define CPM_LCR_LPM_BIT 0
243#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
244  #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
245  #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
246
247/* Clock Gate Register */
248#define CPM_CLKGR_UART1 (1 << 15)
249#define CPM_CLKGR_UHC (1 << 14)
250#define CPM_CLKGR_IPU (1 << 13)
251#define CPM_CLKGR_DMAC (1 << 12)
252#define CPM_CLKGR_UDC (1 << 11)
253#define CPM_CLKGR_LCD (1 << 10)
254#define CPM_CLKGR_CIM (1 << 9)
255#define CPM_CLKGR_SADC (1 << 8)
256#define CPM_CLKGR_MSC (1 << 7)
257#define CPM_CLKGR_AIC1 (1 << 6)
258#define CPM_CLKGR_AIC2 (1 << 5)
259#define CPM_CLKGR_SSI (1 << 4)
260#define CPM_CLKGR_I2C (1 << 3)
261#define CPM_CLKGR_RTC (1 << 2)
262#define CPM_CLKGR_TCU (1 << 1)
263#define CPM_CLKGR_UART0 (1 << 0)
264
265/* Sleep Control Register */
266#define CPM_SCR_O1ST_BIT 8
267#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
268#define CPM_SCR_USBPHY_ENABLE (1 << 6)
269#define CPM_SCR_OSC_ENABLE (1 << 4)
270
271/* Hibernate Control Register */
272#define CPM_HCR_PD (1 << 0)
273
274/* Wakeup Filter Counter Register in Hibernate Mode */
275#define CPM_HWFCR_TIME_BIT 0
276#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
277
278/* Reset Counter Register in Hibernate Mode */
279#define CPM_HRCR_TIME_BIT 0
280#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
281
282/* Wakeup Control Register in Hibernate Mode */
283#define CPM_HWCR_WLE_LOW (0 << 2)
284#define CPM_HWCR_WLE_HIGH (1 << 2)
285#define CPM_HWCR_PIN_WAKEUP (1 << 1)
286#define CPM_HWCR_RTC_WAKEUP (1 << 0)
287
288/* Wakeup Status Register in Hibernate Mode */
289#define CPM_HWSR_WSR_PIN (1 << 1)
290#define CPM_HWSR_WSR_RTC (1 << 0)
291
292/* Reset Status Register */
293#define CPM_RSR_HR (1 << 2)
294#define CPM_RSR_WR (1 << 1)
295#define CPM_RSR_PR (1 << 0)
296
297
298/*************************************************************************
299 * TCU (Timer Counter Unit)
300 *************************************************************************/
301#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
302#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
303#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
304#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
305#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
306#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
307#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
308#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
309#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
310#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
311#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
312#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
313#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
314#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
315#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
316#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
317#define TCU_TDFR1 (TCU_BASE + 0x50)
318#define TCU_TDHR1 (TCU_BASE + 0x54)
319#define TCU_TCNT1 (TCU_BASE + 0x58)
320#define TCU_TCSR1 (TCU_BASE + 0x5C)
321#define TCU_TDFR2 (TCU_BASE + 0x60)
322#define TCU_TDHR2 (TCU_BASE + 0x64)
323#define TCU_TCNT2 (TCU_BASE + 0x68)
324#define TCU_TCSR2 (TCU_BASE + 0x6C)
325#define TCU_TDFR3 (TCU_BASE + 0x70)
326#define TCU_TDHR3 (TCU_BASE + 0x74)
327#define TCU_TCNT3 (TCU_BASE + 0x78)
328#define TCU_TCSR3 (TCU_BASE + 0x7C)
329#define TCU_TDFR4 (TCU_BASE + 0x80)
330#define TCU_TDHR4 (TCU_BASE + 0x84)
331#define TCU_TCNT4 (TCU_BASE + 0x88)
332#define TCU_TCSR4 (TCU_BASE + 0x8C)
333#define TCU_TDFR5 (TCU_BASE + 0x90)
334#define TCU_TDHR5 (TCU_BASE + 0x94)
335#define TCU_TCNT5 (TCU_BASE + 0x98)
336#define TCU_TCSR5 (TCU_BASE + 0x9C)
337
338#define REG_TCU_TSR REG32(TCU_TSR)
339#define REG_TCU_TSSR REG32(TCU_TSSR)
340#define REG_TCU_TSCR REG32(TCU_TSCR)
341#define REG_TCU_TER REG8(TCU_TER)
342#define REG_TCU_TESR REG8(TCU_TESR)
343#define REG_TCU_TECR REG8(TCU_TECR)
344#define REG_TCU_TFR REG32(TCU_TFR)
345#define REG_TCU_TFSR REG32(TCU_TFSR)
346#define REG_TCU_TFCR REG32(TCU_TFCR)
347#define REG_TCU_TMR REG32(TCU_TMR)
348#define REG_TCU_TMSR REG32(TCU_TMSR)
349#define REG_TCU_TMCR REG32(TCU_TMCR)
350#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
351#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
352#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
353#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
354#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
355#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
356#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
357#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
358#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
359#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
360#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
361#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
362#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
363#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
364#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
365#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
366#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
367#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
368#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
369#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
370
371// n = 0,1,2,3,4,5
372#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
373#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
374#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
375#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
376
377#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
378#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
379#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
380#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
381
382// Register definitions
383#define TCU_TCSR_PWM_SD (1 << 9)
384#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
385#define TCU_TCSR_PWM_EN (1 << 7)
386#define TCU_TCSR_PRESCALE_BIT 3
387#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
388  #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
389  #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
390  #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
391  #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
392  #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
393  #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
394#define TCU_TCSR_EXT_EN (1 << 2)
395#define TCU_TCSR_RTC_EN (1 << 1)
396#define TCU_TCSR_PCK_EN (1 << 0)
397
398#define TCU_TER_TCEN5 (1 << 5)
399#define TCU_TER_TCEN4 (1 << 4)
400#define TCU_TER_TCEN3 (1 << 3)
401#define TCU_TER_TCEN2 (1 << 2)
402#define TCU_TER_TCEN1 (1 << 1)
403#define TCU_TER_TCEN0 (1 << 0)
404
405#define TCU_TESR_TCST5 (1 << 5)
406#define TCU_TESR_TCST4 (1 << 4)
407#define TCU_TESR_TCST3 (1 << 3)
408#define TCU_TESR_TCST2 (1 << 2)
409#define TCU_TESR_TCST1 (1 << 1)
410#define TCU_TESR_TCST0 (1 << 0)
411
412#define TCU_TECR_TCCL5 (1 << 5)
413#define TCU_TECR_TCCL4 (1 << 4)
414#define TCU_TECR_TCCL3 (1 << 3)
415#define TCU_TECR_TCCL2 (1 << 2)
416#define TCU_TECR_TCCL1 (1 << 1)
417#define TCU_TECR_TCCL0 (1 << 0)
418
419#define TCU_TFR_HFLAG5 (1 << 21)
420#define TCU_TFR_HFLAG4 (1 << 20)
421#define TCU_TFR_HFLAG3 (1 << 19)
422#define TCU_TFR_HFLAG2 (1 << 18)
423#define TCU_TFR_HFLAG1 (1 << 17)
424#define TCU_TFR_HFLAG0 (1 << 16)
425#define TCU_TFR_FFLAG5 (1 << 5)
426#define TCU_TFR_FFLAG4 (1 << 4)
427#define TCU_TFR_FFLAG3 (1 << 3)
428#define TCU_TFR_FFLAG2 (1 << 2)
429#define TCU_TFR_FFLAG1 (1 << 1)
430#define TCU_TFR_FFLAG0 (1 << 0)
431
432#define TCU_TFSR_HFLAG5 (1 << 21)
433#define TCU_TFSR_HFLAG4 (1 << 20)
434#define TCU_TFSR_HFLAG3 (1 << 19)
435#define TCU_TFSR_HFLAG2 (1 << 18)
436#define TCU_TFSR_HFLAG1 (1 << 17)
437#define TCU_TFSR_HFLAG0 (1 << 16)
438#define TCU_TFSR_FFLAG5 (1 << 5)
439#define TCU_TFSR_FFLAG4 (1 << 4)
440#define TCU_TFSR_FFLAG3 (1 << 3)
441#define TCU_TFSR_FFLAG2 (1 << 2)
442#define TCU_TFSR_FFLAG1 (1 << 1)
443#define TCU_TFSR_FFLAG0 (1 << 0)
444
445#define TCU_TFCR_HFLAG5 (1 << 21)
446#define TCU_TFCR_HFLAG4 (1 << 20)
447#define TCU_TFCR_HFLAG3 (1 << 19)
448#define TCU_TFCR_HFLAG2 (1 << 18)
449#define TCU_TFCR_HFLAG1 (1 << 17)
450#define TCU_TFCR_HFLAG0 (1 << 16)
451#define TCU_TFCR_FFLAG5 (1 << 5)
452#define TCU_TFCR_FFLAG4 (1 << 4)
453#define TCU_TFCR_FFLAG3 (1 << 3)
454#define TCU_TFCR_FFLAG2 (1 << 2)
455#define TCU_TFCR_FFLAG1 (1 << 1)
456#define TCU_TFCR_FFLAG0 (1 << 0)
457
458#define TCU_TMR_HMASK5 (1 << 21)
459#define TCU_TMR_HMASK4 (1 << 20)
460#define TCU_TMR_HMASK3 (1 << 19)
461#define TCU_TMR_HMASK2 (1 << 18)
462#define TCU_TMR_HMASK1 (1 << 17)
463#define TCU_TMR_HMASK0 (1 << 16)
464#define TCU_TMR_FMASK5 (1 << 5)
465#define TCU_TMR_FMASK4 (1 << 4)
466#define TCU_TMR_FMASK3 (1 << 3)
467#define TCU_TMR_FMASK2 (1 << 2)
468#define TCU_TMR_FMASK1 (1 << 1)
469#define TCU_TMR_FMASK0 (1 << 0)
470
471#define TCU_TMSR_HMST5 (1 << 21)
472#define TCU_TMSR_HMST4 (1 << 20)
473#define TCU_TMSR_HMST3 (1 << 19)
474#define TCU_TMSR_HMST2 (1 << 18)
475#define TCU_TMSR_HMST1 (1 << 17)
476#define TCU_TMSR_HMST0 (1 << 16)
477#define TCU_TMSR_FMST5 (1 << 5)
478#define TCU_TMSR_FMST4 (1 << 4)
479#define TCU_TMSR_FMST3 (1 << 3)
480#define TCU_TMSR_FMST2 (1 << 2)
481#define TCU_TMSR_FMST1 (1 << 1)
482#define TCU_TMSR_FMST0 (1 << 0)
483
484#define TCU_TMCR_HMCL5 (1 << 21)
485#define TCU_TMCR_HMCL4 (1 << 20)
486#define TCU_TMCR_HMCL3 (1 << 19)
487#define TCU_TMCR_HMCL2 (1 << 18)
488#define TCU_TMCR_HMCL1 (1 << 17)
489#define TCU_TMCR_HMCL0 (1 << 16)
490#define TCU_TMCR_FMCL5 (1 << 5)
491#define TCU_TMCR_FMCL4 (1 << 4)
492#define TCU_TMCR_FMCL3 (1 << 3)
493#define TCU_TMCR_FMCL2 (1 << 2)
494#define TCU_TMCR_FMCL1 (1 << 1)
495#define TCU_TMCR_FMCL0 (1 << 0)
496
497#define TCU_TSR_WDTS (1 << 16)
498#define TCU_TSR_STOP5 (1 << 5)
499#define TCU_TSR_STOP4 (1 << 4)
500#define TCU_TSR_STOP3 (1 << 3)
501#define TCU_TSR_STOP2 (1 << 2)
502#define TCU_TSR_STOP1 (1 << 1)
503#define TCU_TSR_STOP0 (1 << 0)
504
505#define TCU_TSSR_WDTSS (1 << 16)
506#define TCU_TSSR_STPS5 (1 << 5)
507#define TCU_TSSR_STPS4 (1 << 4)
508#define TCU_TSSR_STPS3 (1 << 3)
509#define TCU_TSSR_STPS2 (1 << 2)
510#define TCU_TSSR_STPS1 (1 << 1)
511#define TCU_TSSR_STPS0 (1 << 0)
512
513#define TCU_TSSR_WDTSC (1 << 16)
514#define TCU_TSSR_STPC5 (1 << 5)
515#define TCU_TSSR_STPC4 (1 << 4)
516#define TCU_TSSR_STPC3 (1 << 3)
517#define TCU_TSSR_STPC2 (1 << 2)
518#define TCU_TSSR_STPC1 (1 << 1)
519#define TCU_TSSR_STPC0 (1 << 0)
520
521
522/*************************************************************************
523 * WDT (WatchDog Timer)
524 *************************************************************************/
525#define WDT_TDR (WDT_BASE + 0x00)
526#define WDT_TCER (WDT_BASE + 0x04)
527#define WDT_TCNT (WDT_BASE + 0x08)
528#define WDT_TCSR (WDT_BASE + 0x0C)
529
530#define REG_WDT_TDR REG16(WDT_TDR)
531#define REG_WDT_TCER REG8(WDT_TCER)
532#define REG_WDT_TCNT REG16(WDT_TCNT)
533#define REG_WDT_TCSR REG16(WDT_TCSR)
534
535// Register definition
536#define WDT_TCSR_PRESCALE_BIT 3
537#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
538  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
539  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
540  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
541  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
542  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
543  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
544#define WDT_TCSR_EXT_EN (1 << 2)
545#define WDT_TCSR_RTC_EN (1 << 1)
546#define WDT_TCSR_PCK_EN (1 << 0)
547
548#define WDT_TCER_TCEN (1 << 0)
549
550
551/*************************************************************************
552 * DMAC (DMA Controller)
553 *************************************************************************/
554
555#define MAX_DMA_NUM 6 /* max 6 channels */
556
557#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
558#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
559#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
560#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
561#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
562#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
563#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
564#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
565#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
566#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
567#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
568
569// channel 0
570#define DMAC_DSAR0 DMAC_DSAR(0)
571#define DMAC_DTAR0 DMAC_DTAR(0)
572#define DMAC_DTCR0 DMAC_DTCR(0)
573#define DMAC_DRSR0 DMAC_DRSR(0)
574#define DMAC_DCCSR0 DMAC_DCCSR(0)
575#define DMAC_DCMD0 DMAC_DCMD(0)
576#define DMAC_DDA0 DMAC_DDA(0)
577
578// channel 1
579#define DMAC_DSAR1 DMAC_DSAR(1)
580#define DMAC_DTAR1 DMAC_DTAR(1)
581#define DMAC_DTCR1 DMAC_DTCR(1)
582#define DMAC_DRSR1 DMAC_DRSR(1)
583#define DMAC_DCCSR1 DMAC_DCCSR(1)
584#define DMAC_DCMD1 DMAC_DCMD(1)
585#define DMAC_DDA1 DMAC_DDA(1)
586
587// channel 2
588#define DMAC_DSAR2 DMAC_DSAR(2)
589#define DMAC_DTAR2 DMAC_DTAR(2)
590#define DMAC_DTCR2 DMAC_DTCR(2)
591#define DMAC_DRSR2 DMAC_DRSR(2)
592#define DMAC_DCCSR2 DMAC_DCCSR(2)
593#define DMAC_DCMD2 DMAC_DCMD(2)
594#define DMAC_DDA2 DMAC_DDA(2)
595
596// channel 3
597#define DMAC_DSAR3 DMAC_DSAR(3)
598#define DMAC_DTAR3 DMAC_DTAR(3)
599#define DMAC_DTCR3 DMAC_DTCR(3)
600#define DMAC_DRSR3 DMAC_DRSR(3)
601#define DMAC_DCCSR3 DMAC_DCCSR(3)
602#define DMAC_DCMD3 DMAC_DCMD(3)
603#define DMAC_DDA3 DMAC_DDA(3)
604
605// channel 4
606#define DMAC_DSAR4 DMAC_DSAR(4)
607#define DMAC_DTAR4 DMAC_DTAR(4)
608#define DMAC_DTCR4 DMAC_DTCR(4)
609#define DMAC_DRSR4 DMAC_DRSR(4)
610#define DMAC_DCCSR4 DMAC_DCCSR(4)
611#define DMAC_DCMD4 DMAC_DCMD(4)
612#define DMAC_DDA4 DMAC_DDA(4)
613
614// channel 5
615#define DMAC_DSAR5 DMAC_DSAR(5)
616#define DMAC_DTAR5 DMAC_DTAR(5)
617#define DMAC_DTCR5 DMAC_DTCR(5)
618#define DMAC_DRSR5 DMAC_DRSR(5)
619#define DMAC_DCCSR5 DMAC_DCCSR(5)
620#define DMAC_DCMD5 DMAC_DCMD(5)
621#define DMAC_DDA5 DMAC_DDA(5)
622
623#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
624#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
625#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
626#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
627#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
628#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
629#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
630#define REG_DMAC_DMACR REG32(DMAC_DMACR)
631#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
632#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
633#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
634
635// DMA request source register
636#define DMAC_DRSR_RS_BIT 0
637#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
638  #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
639  #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
640  #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
641  #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
642  #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
643  #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
644  #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
645  #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
646  #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
647  #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
648  #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
649  #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
650
651// DMA channel control/status register
652#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
653#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
654#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
655#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
656#define DMAC_DCCSR_AR (1 << 4) /* address error */
657#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
658#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
659#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
660#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
661
662// DMA channel command register
663#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
664#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
665#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
666#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
667  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
668  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
669  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
670  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
671  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
672  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
673  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
674  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
675  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
676  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
677  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
678  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
679  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
680  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
681  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
682  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
683#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
684#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
685  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
686  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
687  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
688#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
689#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
690  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
691  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
692  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
693#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
694#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
695  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
696  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
697  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
698  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
699  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
700#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
701#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
702#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
703#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
704#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
705#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
706
707// DMA descriptor address register
708#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
709#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
710#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
711#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
712
713// DMA control register
714#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
715#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
716  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
717  #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
718  #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
719  #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
720#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
721#define DMAC_DMACR_AR (1 << 2) /* address error flag */
722#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
723
724// DMA doorbell register
725#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
726#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
727#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
728#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
729#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
730#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
731
732// DMA doorbell set register
733#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
734#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
735#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
736#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
737#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
738#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
739
740// DMA interrupt pending register
741#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
742#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
743#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
744#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
745#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
746#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
747
748
749/*************************************************************************
750 * GPIO (General-Purpose I/O Ports)
751 *************************************************************************/
752#define MAX_GPIO_NUM 128
753
754//n = 0,1,2,3
755#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
756#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
757#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
758#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
759#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
760#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
761#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
762#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
763#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
764#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
765#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
766#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
767#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
768#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
769#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
770#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
771#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
772#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
773#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
774#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
775#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
776#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
777#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
778#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag Clear Register */
779
780#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
781#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
782#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
783#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
784#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
785#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
786#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
787#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
788#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
789#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
790#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
791#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
792#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
793#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
794#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
795#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
796#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
797#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
798#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
799#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
800#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
801#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
802#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
803#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
804
805
806/*************************************************************************
807 * UART
808 *************************************************************************/
809
810#define IRDA_BASE UART0_BASE
811#define UART_BASE UART0_BASE
812#define UART_OFF 0x1000
813
814/* Register Offset */
815#define OFF_RDR (0x00) /* R 8b H'xx */
816#define OFF_TDR (0x00) /* W 8b H'xx */
817#define OFF_DLLR (0x00) /* RW 8b H'00 */
818#define OFF_DLHR (0x04) /* RW 8b H'00 */
819#define OFF_IER (0x04) /* RW 8b H'00 */
820#define OFF_ISR (0x08) /* R 8b H'01 */
821#define OFF_FCR (0x08) /* W 8b H'00 */
822#define OFF_LCR (0x0C) /* RW 8b H'00 */
823#define OFF_MCR (0x10) /* RW 8b H'00 */
824#define OFF_LSR (0x14) /* R 8b H'00 */
825#define OFF_MSR (0x18) /* R 8b H'00 */
826#define OFF_SPR (0x1C) /* RW 8b H'00 */
827#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
828#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
829#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
830
831/* Register Address */
832#define UART0_RDR (UART0_BASE + OFF_RDR)
833#define UART0_TDR (UART0_BASE + OFF_TDR)
834#define UART0_DLLR (UART0_BASE + OFF_DLLR)
835#define UART0_DLHR (UART0_BASE + OFF_DLHR)
836#define UART0_IER (UART0_BASE + OFF_IER)
837#define UART0_ISR (UART0_BASE + OFF_ISR)
838#define UART0_FCR (UART0_BASE + OFF_FCR)
839#define UART0_LCR (UART0_BASE + OFF_LCR)
840#define UART0_MCR (UART0_BASE + OFF_MCR)
841#define UART0_LSR (UART0_BASE + OFF_LSR)
842#define UART0_MSR (UART0_BASE + OFF_MSR)
843#define UART0_SPR (UART0_BASE + OFF_SPR)
844#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
845#define UART0_UMR (UART0_BASE + OFF_UMR)
846#define UART0_UACR (UART0_BASE + OFF_UACR)
847
848/*
849 * Define macros for UARTIER
850 * UART Interrupt Enable Register
851 */
852#define UARTIER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
853#define UARTIER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
854#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
855#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
856#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
857
858/*
859 * Define macros for UARTISR
860 * UART Interrupt Status Register
861 */
862#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
863#define UARTISR_IID (7 << 1) /* Source of Interrupt */
864#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
865#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
866#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
867#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
868#define UARTISR_IID_RTO (6 << 1) /* Receive timeout */
869#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
870#define UARTISR_FFMS_NO_FIFO (0 << 6)
871#define UARTISR_FFMS_FIFO_MODE (3 << 6)
872
873/*
874 * Define macros for UARTFCR
875 * UART FIFO Control Register
876 */
877#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
878#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
879#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
880#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
881#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
882#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
883#define UARTFCR_RTRG_1 (0 << 6)
884#define UARTFCR_RTRG_4 (1 << 6)
885#define UARTFCR_RTRG_8 (2 << 6)
886#define UARTFCR_RTRG_15 (3 << 6)
887
888/*
889 * Define macros for UARTLCR
890 * UART Line Control Register
891 */
892#define UARTLCR_WLEN (3 << 0) /* word length */
893#define UARTLCR_WLEN_5 (0 << 0)
894#define UARTLCR_WLEN_6 (1 << 0)
895#define UARTLCR_WLEN_7 (2 << 0)
896#define UARTLCR_WLEN_8 (3 << 0)
897#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
898                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
899#define UARTLCR_STOP1 (0 << 2)
900#define UARTLCR_STOP2 (1 << 2)
901#define UARTLCR_PE (1 << 3) /* 0: parity disable */
902#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
903#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
904#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
905#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */
906
907/*
908 * Define macros for UARTLSR
909 * UART Line Status Register
910 */
911#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
912#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
913#define UARTLSR_PER (1 << 2) /* 0: no parity error */
914#define UARTLSR_FER (1 << 3) /* 0; no framing error */
915#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
916#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
917#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
918#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
919
920/*
921 * Define macros for UARTMCR
922 * UART Modem Control Register
923 */
924#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high, 1: RTS_ output low */
925#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
926#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
927
928/*
929 * Define macros for UARTMSR
930 * UART Modem Status Register
931 */
932#define UARTMSR_CCTS (1 << 0) /* 1: a change on CTS_ pin */
933#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
934
935/*
936 * Define macros for SIRCR
937 * Slow IrDA Control Register
938 */
939#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: SIR mode */
940#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: SIR mode */
941#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
942                       1: 0 pulse width is 1.6us for 115.2Kbps */
943#define SIRCR_TDPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
944#define SIRCR_RDPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
945
946
947/*************************************************************************
948 * AIC (AC97/I2S Controller)
949 *************************************************************************/
950#define AIC_FR (AIC_BASE + 0x000)
951#define AIC_CR (AIC_BASE + 0x004)
952#define AIC_ACCR1 (AIC_BASE + 0x008)
953#define AIC_ACCR2 (AIC_BASE + 0x00C)
954#define AIC_I2SCR (AIC_BASE + 0x010)
955#define AIC_SR (AIC_BASE + 0x014)
956#define AIC_ACSR (AIC_BASE + 0x018)
957#define AIC_I2SSR (AIC_BASE + 0x01C)
958#define AIC_ACCAR (AIC_BASE + 0x020)
959#define AIC_ACCDR (AIC_BASE + 0x024)
960#define AIC_ACSAR (AIC_BASE + 0x028)
961#define AIC_ACSDR (AIC_BASE + 0x02C)
962#define AIC_I2SDIV (AIC_BASE + 0x030)
963#define AIC_DR (AIC_BASE + 0x034)
964
965#define REG_AIC_FR REG32(AIC_FR)
966#define REG_AIC_CR REG32(AIC_CR)
967#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
968#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
969#define REG_AIC_I2SCR REG32(AIC_I2SCR)
970#define REG_AIC_SR REG32(AIC_SR)
971#define REG_AIC_ACSR REG32(AIC_ACSR)
972#define REG_AIC_I2SSR REG32(AIC_I2SSR)
973#define REG_AIC_ACCAR REG32(AIC_ACCAR)
974#define REG_AIC_ACCDR REG32(AIC_ACCDR)
975#define REG_AIC_ACSAR REG32(AIC_ACSAR)
976#define REG_AIC_ACSDR REG32(AIC_ACSDR)
977#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
978#define REG_AIC_DR REG32(AIC_DR)
979
980/* AIC Controller Configuration Register (AIC_FR) */
981
982#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
983#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
984#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
985#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
986#define AIC_FR_LSMP (1 << 6) /* Play Zero sample or last sample */
987#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
988#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
989#define AIC_FR_RST (1 << 3) /* AIC registers reset */
990#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
991#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
992#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
993
994/* AIC Controller Common Control Register (AIC_CR) */
995
996#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
997#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
998  #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
999  #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1000  #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1001  #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1002  #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1003#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1004#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1005  #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1006  #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1007  #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1008  #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1009  #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1010#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1011#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1012#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1013#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1014#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1015#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1016#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1017#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1018#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1019#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1020#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1021#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1022#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1023
1024/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1025
1026#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1027#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1028  #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1029  #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1030  #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1031  #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1032  #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1033  #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1034  #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1035  #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1036  #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1037  #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1038#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1039#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1040  #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1041  #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1042  #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1043  #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1044  #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1045  #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1046  #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1047  #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1048  #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1049  #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1050
1051/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1052
1053#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1054#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1055#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1056#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1057#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1058  #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1059  #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1060  #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1061  #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1062#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1063#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1064  #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1065  #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1066  #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1067  #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1068#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1069#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1070#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1071#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1072
1073/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1074
1075#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1076#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1077#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1078  #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1079  #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1080  #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1081  #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1082  #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1083#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1084
1085/* AIC Controller FIFO Status Register (AIC_SR) */
1086
1087#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1088#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1089#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1090#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1091#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1092#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1093#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1094#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1095
1096/* AIC Controller AC-link Status Register (AIC_ACSR) */
1097
1098#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1099#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1100#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1101#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1102#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1103#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1104
1105/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1106
1107#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1108
1109/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1110
1111#define AIC_ACCAR_CAR_BIT 0
1112#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1113
1114/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1115
1116#define AIC_ACCDR_CDR_BIT 0
1117#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1118
1119/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1120
1121#define AIC_ACSAR_SAR_BIT 0
1122#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1123
1124/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1125
1126#define AIC_ACSDR_SDR_BIT 0
1127#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1128
1129/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1130
1131#define AIC_I2SDIV_DIV_BIT 0
1132#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1133  #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1134  #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1135  #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1136  #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1137  #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1138  #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1139
1140
1141/*************************************************************************
1142 * ICDC (Internal CODEC)
1143 *************************************************************************/
1144#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1145#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1146#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1147#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1148#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1149#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1150#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1151
1152#define REG_ICDC_CR REG32(ICDC_CR)
1153#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1154#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1155#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1156#define REG_ICDC_APSR REG32(ICDC_APSR)
1157#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1158#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1159
1160/* ICDC Control Register */
1161#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1162#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1163#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1164#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1165  #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1166  #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1167  #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1168  #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1169  #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1170  #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1171  #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1172  #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1173  #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1174#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1175#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1176  #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1177  #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1178  #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1179  #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1180#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1181#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1182  #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1183  #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1184  #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1185  #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1186#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1187#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1188#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1189#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1190#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1191#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1192#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1193#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1194#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1195#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1196#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1197#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1198
1199/* Anti-Pop WAIT Stage Timing Control Register */
1200#define ICDC_APWAIT_WAITSN_BIT 0
1201#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1202
1203/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1204#define ICDC_APPRE_PRESN_BIT 0
1205#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1206
1207/* Anti-Pop HPEN Stage Timing Control Register */
1208#define ICDC_APHPEN_HPENSN_BIT 0
1209#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1210
1211/* Anti-Pop Status Register */
1212#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1213#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1214#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1215#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1216  #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1217#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1218  #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1219  #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1220  #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1221  #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1222#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1223#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1224
1225
1226/*************************************************************************
1227 * I2C
1228 *************************************************************************/
1229#define I2C_DR (I2C_BASE + 0x000)
1230#define I2C_CR (I2C_BASE + 0x004)
1231#define I2C_SR (I2C_BASE + 0x008)
1232#define I2C_GR (I2C_BASE + 0x00C)
1233
1234#define REG_I2C_DR REG8(I2C_DR)
1235#define REG_I2C_CR REG8(I2C_CR)
1236#define REG_I2C_SR REG8(I2C_SR)
1237#define REG_I2C_GR REG16(I2C_GR)
1238
1239/* I2C Control Register (I2C_CR) */
1240
1241#define I2C_CR_IEN (1 << 4)
1242#define I2C_CR_STA (1 << 3)
1243#define I2C_CR_STO (1 << 2)
1244#define I2C_CR_AC (1 << 1)
1245#define I2C_CR_I2CE (1 << 0)
1246
1247/* I2C Status Register (I2C_SR) */
1248
1249#define I2C_SR_STX (1 << 4)
1250#define I2C_SR_BUSY (1 << 3)
1251#define I2C_SR_TEND (1 << 2)
1252#define I2C_SR_DRF (1 << 1)
1253#define I2C_SR_ACKF (1 << 0)
1254
1255
1256/*************************************************************************
1257 * SSI
1258 *************************************************************************/
1259#define SSI_DR (SSI_BASE + 0x000)
1260#define SSI_CR0 (SSI_BASE + 0x004)
1261#define SSI_CR1 (SSI_BASE + 0x008)
1262#define SSI_SR (SSI_BASE + 0x00C)
1263#define SSI_ITR (SSI_BASE + 0x010)
1264#define SSI_ICR (SSI_BASE + 0x014)
1265#define SSI_GR (SSI_BASE + 0x018)
1266
1267#define REG_SSI_DR REG32(SSI_DR)
1268#define REG_SSI_CR0 REG16(SSI_CR0)
1269#define REG_SSI_CR1 REG32(SSI_CR1)
1270#define REG_SSI_SR REG32(SSI_SR)
1271#define REG_SSI_ITR REG16(SSI_ITR)
1272#define REG_SSI_ICR REG8(SSI_ICR)
1273#define REG_SSI_GR REG16(SSI_GR)
1274
1275/* SSI Data Register (SSI_DR) */
1276
1277#define SSI_DR_GPC_BIT 0
1278#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1279
1280/* SSI Control Register 0 (SSI_CR0) */
1281
1282#define SSI_CR0_SSIE (1 << 15)
1283#define SSI_CR0_TIE (1 << 14)
1284#define SSI_CR0_RIE (1 << 13)
1285#define SSI_CR0_TEIE (1 << 12)
1286#define SSI_CR0_REIE (1 << 11)
1287#define SSI_CR0_LOOP (1 << 10)
1288#define SSI_CR0_RFINE (1 << 9)
1289#define SSI_CR0_RFINC (1 << 8)
1290#define SSI_CR0_FSEL (1 << 6)
1291#define SSI_CR0_TFLUSH (1 << 2)
1292#define SSI_CR0_RFLUSH (1 << 1)
1293#define SSI_CR0_DISREV (1 << 0)
1294
1295/* SSI Control Register 1 (SSI_CR1) */
1296
1297#define SSI_CR1_FRMHL_BIT 30
1298#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1299  #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1300  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1301  #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1302  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1303#define SSI_CR1_TFVCK_BIT 28
1304#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1305  #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1306  #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1307  #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1308  #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1309#define SSI_CR1_TCKFI_BIT 26
1310#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1311  #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1312  #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1313  #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1314  #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1315#define SSI_CR1_LFST (1 << 25)
1316#define SSI_CR1_ITFRM (1 << 24)
1317#define SSI_CR1_UNFIN (1 << 23)
1318#define SSI_CR1_MULTS (1 << 22)
1319#define SSI_CR1_FMAT_BIT 20
1320#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1321  #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1322  #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1323  #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1324  #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1325#define SSI_CR1_TTRG_BIT 16
1326#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1327  #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1328  #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1329  #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1330  #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1331  #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1332  #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1333  #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1334  #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1335  #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1336  #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1337  #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1338  #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1339  #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1340  #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1341  #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1342  #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1343#define SSI_CR1_MCOM_BIT 12
1344#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1345  #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1346  #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1347  #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1348  #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1349  #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1350  #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1351  #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1352  #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1353  #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1354  #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1355  #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1356  #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1357  #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1358  #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1359  #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1360  #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1361#define SSI_CR1_RTRG_BIT 8
1362#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1363  #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1364  #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1365  #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1366  #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1367  #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1368  #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1369  #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1370  #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1371  #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1372  #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1373  #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1374  #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1375  #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1376  #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1377  #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1378  #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1379#define SSI_CR1_FLEN_BIT 4
1380#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1381  #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1382  #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1383  #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1384  #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1385  #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1386  #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1387  #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1388  #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1389  #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1390  #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1391  #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1392  #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1393  #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1394  #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1395  #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1396  #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1397#define SSI_CR1_PHA (1 << 1)
1398#define SSI_CR1_POL (1 << 0)
1399
1400/* SSI Status Register (SSI_SR) */
1401
1402#define SSI_SR_TFIFONUM_BIT 16
1403#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1404#define SSI_SR_RFIFONUM_BIT 8
1405#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1406#define SSI_SR_END (1 << 7)
1407#define SSI_SR_BUSY (1 << 6)
1408#define SSI_SR_TFF (1 << 5)
1409#define SSI_SR_RFE (1 << 4)
1410#define SSI_SR_TFHE (1 << 3)
1411#define SSI_SR_RFHF (1 << 2)
1412#define SSI_SR_UNDR (1 << 1)
1413#define SSI_SR_OVER (1 << 0)
1414
1415/* SSI Interval Time Control Register (SSI_ITR) */
1416
1417#define SSI_ITR_CNTCLK (1 << 15)
1418#define SSI_ITR_IVLTM_BIT 0
1419#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1420
1421
1422/*************************************************************************
1423 * MSC
1424 *************************************************************************/
1425#define MSC_STRPCL (MSC_BASE + 0x000)
1426#define MSC_STAT (MSC_BASE + 0x004)
1427#define MSC_CLKRT (MSC_BASE + 0x008)
1428#define MSC_CMDAT (MSC_BASE + 0x00C)
1429#define MSC_RESTO (MSC_BASE + 0x010)
1430#define MSC_RDTO (MSC_BASE + 0x014)
1431#define MSC_BLKLEN (MSC_BASE + 0x018)
1432#define MSC_NOB (MSC_BASE + 0x01C)
1433#define MSC_SNOB (MSC_BASE + 0x020)
1434#define MSC_IMASK (MSC_BASE + 0x024)
1435#define MSC_IREG (MSC_BASE + 0x028)
1436#define MSC_CMD (MSC_BASE + 0x02C)
1437#define MSC_ARG (MSC_BASE + 0x030)
1438#define MSC_RES (MSC_BASE + 0x034)
1439#define MSC_RXFIFO (MSC_BASE + 0x038)
1440#define MSC_TXFIFO (MSC_BASE + 0x03C)
1441
1442#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1443#define REG_MSC_STAT REG32(MSC_STAT)
1444#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1445#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1446#define REG_MSC_RESTO REG16(MSC_RESTO)
1447#define REG_MSC_RDTO REG16(MSC_RDTO)
1448#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1449#define REG_MSC_NOB REG16(MSC_NOB)
1450#define REG_MSC_SNOB REG16(MSC_SNOB)
1451#define REG_MSC_IMASK REG16(MSC_IMASK)
1452#define REG_MSC_IREG REG16(MSC_IREG)
1453#define REG_MSC_CMD REG8(MSC_CMD)
1454#define REG_MSC_ARG REG32(MSC_ARG)
1455#define REG_MSC_RES REG16(MSC_RES)
1456#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1457#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1458
1459/* MSC Clock and Control Register (MSC_STRPCL) */
1460
1461#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1462#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1463#define MSC_STRPCL_START_READWAIT (1 << 5)
1464#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1465#define MSC_STRPCL_RESET (1 << 3)
1466#define MSC_STRPCL_START_OP (1 << 2)
1467#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1468#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1469  #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1470  #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1471
1472/* MSC Status Register (MSC_STAT) */
1473
1474#define MSC_STAT_IS_RESETTING (1 << 15)
1475#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1476#define MSC_STAT_PRG_DONE (1 << 13)
1477#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1478#define MSC_STAT_END_CMD_RES (1 << 11)
1479#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1480#define MSC_STAT_IS_READWAIT (1 << 9)
1481#define MSC_STAT_CLK_EN (1 << 8)
1482#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1483#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1484#define MSC_STAT_CRC_RES_ERR (1 << 5)
1485#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1486#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1487#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1488  #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1489  #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1490  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1491#define MSC_STAT_TIME_OUT_RES (1 << 1)
1492#define MSC_STAT_TIME_OUT_READ (1 << 0)
1493
1494/* MSC Bus Clock Control Register (MSC_CLKRT) */
1495
1496#define MSC_CLKRT_CLK_RATE_BIT 0
1497#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1498  #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1499  #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1500  #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1501  #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1502  #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1503  #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1504  #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1505  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1506
1507/* MSC Command Sequence Control Register (MSC_CMDAT) */
1508
1509#define MSC_CMDAT_IO_ABORT (1 << 11)
1510#define MSC_CMDAT_BUS_WIDTH_BIT 9
1511#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1512  #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1513  #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1514  #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1515  #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1516#define MSC_CMDAT_DMA_EN (1 << 8)
1517#define MSC_CMDAT_INIT (1 << 7)
1518#define MSC_CMDAT_BUSY (1 << 6)
1519#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1520#define MSC_CMDAT_WRITE (1 << 4)
1521#define MSC_CMDAT_READ (0 << 4)
1522#define MSC_CMDAT_DATA_EN (1 << 3)
1523#define MSC_CMDAT_RESPONSE_BIT 0
1524#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1525  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1526  #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1527  #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1528  #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1529  #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1530  #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1531  #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1532
1533#define CMDAT_DMA_EN (1 << 8)
1534#define CMDAT_INIT (1 << 7)
1535#define CMDAT_BUSY (1 << 6)
1536#define CMDAT_STREAM (1 << 5)
1537#define CMDAT_WRITE (1 << 4)
1538#define CMDAT_DATA_EN (1 << 3)
1539
1540/* MSC Interrupts Mask Register (MSC_IMASK) */
1541
1542#define MSC_IMASK_SDIO (1 << 7)
1543#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1544#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1545#define MSC_IMASK_END_CMD_RES (1 << 2)
1546#define MSC_IMASK_PRG_DONE (1 << 1)
1547#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1548
1549
1550/* MSC Interrupts Status Register (MSC_IREG) */
1551
1552#define MSC_IREG_SDIO (1 << 7)
1553#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1554#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1555#define MSC_IREG_END_CMD_RES (1 << 2)
1556#define MSC_IREG_PRG_DONE (1 << 1)
1557#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1558
1559
1560/*************************************************************************
1561 * EMC (External Memory Controller)
1562 *************************************************************************/
1563#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1564#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1565#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1566#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1567#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1568#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1569#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1570#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1571#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1572#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1573
1574#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1575#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1576#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1577#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1578#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1579#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1580#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1581#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1582#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1583#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1584#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1585#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1586
1587#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1588#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1589#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1590#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1591#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1592#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1593
1594
1595#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1596#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1597#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1598#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1599#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1600#define REG_EMC_SACR0 REG32(EMC_SACR0)
1601#define REG_EMC_SACR1 REG32(EMC_SACR1)
1602#define REG_EMC_SACR2 REG32(EMC_SACR2)
1603#define REG_EMC_SACR3 REG32(EMC_SACR3)
1604#define REG_EMC_SACR4 REG32(EMC_SACR4)
1605
1606#define REG_EMC_NFCSR REG32(EMC_NFCSR)
1607#define REG_EMC_NFECR REG32(EMC_NFECR)
1608#define REG_EMC_NFECC REG32(EMC_NFECC)
1609#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1610#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1611#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1612#define REG_EMC_NFINTS REG32(EMC_NFINTS)
1613#define REG_EMC_NFINTE REG32(EMC_NFINTE)
1614#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1615#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1616#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1617#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1618
1619#define REG_EMC_DMCR REG32(EMC_DMCR)
1620#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1621#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1622#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1623#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1624
1625/* Static Memory Control Register */
1626#define EMC_SMCR_STRV_BIT 24
1627#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1628#define EMC_SMCR_TAW_BIT 20
1629#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1630#define EMC_SMCR_TBP_BIT 16
1631#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1632#define EMC_SMCR_TAH_BIT 12
1633#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1634#define EMC_SMCR_TAS_BIT 8
1635#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1636#define EMC_SMCR_BW_BIT 6
1637#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1638  #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1639  #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1640  #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1641#define EMC_SMCR_BCM (1 << 3)
1642#define EMC_SMCR_BL_BIT 1
1643#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1644  #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1645  #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1646  #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1647  #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1648#define EMC_SMCR_SMT (1 << 0)
1649
1650/* Static Memory Bank Addr Config Reg */
1651#define EMC_SACR_BASE_BIT 8
1652#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1653#define EMC_SACR_MASK_BIT 0
1654#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1655
1656/* NAND Flash Control/Status Register */
1657#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1658#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1659#define EMC_NFCSR_NFCE3 (1 << 5)
1660#define EMC_NFCSR_NFE3 (1 << 4)
1661#define EMC_NFCSR_NFCE2 (1 << 3)
1662#define EMC_NFCSR_NFE2 (1 << 2)
1663#define EMC_NFCSR_NFCE1 (1 << 1)
1664#define EMC_NFCSR_NFE1 (1 << 0)
1665
1666/* NAND Flash ECC Control Register */
1667#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1668#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1669#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1670#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1671#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1672#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1673#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1674
1675/* NAND Flash ECC Data Register */
1676#define EMC_NFECC_ECC2_BIT 16
1677#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1678#define EMC_NFECC_ECC1_BIT 8
1679#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1680#define EMC_NFECC_ECC0_BIT 0
1681#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1682
1683/* NAND Flash Interrupt Status Register */
1684#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1685#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1686#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1687#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1688#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1689#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1690#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1691
1692/* NAND Flash Interrupt Enable Register */
1693#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1694#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1695#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1696#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1697#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1698
1699/* NAND Flash RS Error Report Register */
1700#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1701#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1702#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1703#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1704
1705
1706/* DRAM Control Register */
1707#define EMC_DMCR_BW_BIT 31
1708#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1709#define EMC_DMCR_CA_BIT 26
1710#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1711  #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1712  #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1713  #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1714  #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1715  #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1716#define EMC_DMCR_RMODE (1 << 25)
1717#define EMC_DMCR_RFSH (1 << 24)
1718#define EMC_DMCR_MRSET (1 << 23)
1719#define EMC_DMCR_RA_BIT 20
1720#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1721  #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1722  #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1723  #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1724#define EMC_DMCR_BA_BIT 19
1725#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1726#define EMC_DMCR_PDM (1 << 18)
1727#define EMC_DMCR_EPIN (1 << 17)
1728#define EMC_DMCR_TRAS_BIT 13
1729#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1730#define EMC_DMCR_RCD_BIT 11
1731#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1732#define EMC_DMCR_TPC_BIT 8
1733#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1734#define EMC_DMCR_TRWL_BIT 5
1735#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1736#define EMC_DMCR_TRC_BIT 2
1737#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1738#define EMC_DMCR_TCL_BIT 0
1739#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1740
1741/* Refresh Time Control/Status Register */
1742#define EMC_RTCSR_CMF (1 << 7)
1743#define EMC_RTCSR_CKS_BIT 0
1744#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1745  #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1746  #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1747  #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1748  #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1749  #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1750  #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1751  #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1752  #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1753
1754/* SDRAM Bank Address Configuration Register */
1755#define EMC_DMAR_BASE_BIT 8
1756#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1757#define EMC_DMAR_MASK_BIT 0
1758#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1759
1760/* Mode Register of SDRAM bank 0 */
1761#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1762#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1763#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1764  #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1765#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1766#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1767  #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1768  #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1769  #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1770#define EMC_SDMR_BT_BIT 3 /* Burst Type */
1771#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1772  #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1773  #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1774#define EMC_SDMR_BL_BIT 0 /* Burst Length */
1775#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1776  #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1777  #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1778  #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1779  #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1780
1781#define EMC_SDMR_CAS2_16BIT \
1782  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1783#define EMC_SDMR_CAS2_32BIT \
1784  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1785#define EMC_SDMR_CAS3_16BIT \
1786  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1787#define EMC_SDMR_CAS3_32BIT \
1788  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1789
1790
1791/*************************************************************************
1792 * CIM
1793 *************************************************************************/
1794#define CIM_CFG (CIM_BASE + 0x0000)
1795#define CIM_CTRL (CIM_BASE + 0x0004)
1796#define CIM_STATE (CIM_BASE + 0x0008)
1797#define CIM_IID (CIM_BASE + 0x000C)
1798#define CIM_RXFIFO (CIM_BASE + 0x0010)
1799#define CIM_DA (CIM_BASE + 0x0020)
1800#define CIM_FA (CIM_BASE + 0x0024)
1801#define CIM_FID (CIM_BASE + 0x0028)
1802#define CIM_CMD (CIM_BASE + 0x002C)
1803
1804#define REG_CIM_CFG REG32(CIM_CFG)
1805#define REG_CIM_CTRL REG32(CIM_CTRL)
1806#define REG_CIM_STATE REG32(CIM_STATE)
1807#define REG_CIM_IID REG32(CIM_IID)
1808#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1809#define REG_CIM_DA REG32(CIM_DA)
1810#define REG_CIM_FA REG32(CIM_FA)
1811#define REG_CIM_FID REG32(CIM_FID)
1812#define REG_CIM_CMD REG32(CIM_CMD)
1813
1814/* CIM Configuration Register (CIM_CFG) */
1815
1816#define CIM_CFG_INV_DAT (1 << 15)
1817#define CIM_CFG_VSP (1 << 14)
1818#define CIM_CFG_HSP (1 << 13)
1819#define CIM_CFG_PCP (1 << 12)
1820#define CIM_CFG_DUMMY_ZERO (1 << 9)
1821#define CIM_CFG_EXT_VSYNC (1 << 8)
1822#define CIM_CFG_PACK_BIT 4
1823#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1824  #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1825  #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1826  #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1827  #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1828  #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1829  #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1830  #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1831  #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1832#define CIM_CFG_DSM_BIT 0
1833#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1834  #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1835  #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1836  #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1837  #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1838
1839/* CIM Control Register (CIM_CTRL) */
1840
1841#define CIM_CTRL_MCLKDIV_BIT 24
1842#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1843#define CIM_CTRL_FRC_BIT 16
1844#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1845  #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1846  #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1847  #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1848  #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1849  #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1850  #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1851  #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1852  #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1853  #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1854  #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1855  #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1856  #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1857  #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1858  #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1859  #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1860  #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1861#define CIM_CTRL_VDDM (1 << 13)
1862#define CIM_CTRL_DMA_SOFM (1 << 12)
1863#define CIM_CTRL_DMA_EOFM (1 << 11)
1864#define CIM_CTRL_DMA_STOPM (1 << 10)
1865#define CIM_CTRL_RXF_TRIGM (1 << 9)
1866#define CIM_CTRL_RXF_OFM (1 << 8)
1867#define CIM_CTRL_RXF_TRIG_BIT 4
1868#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1869  #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1870  #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1871  #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1872  #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1873  #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1874  #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1875  #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1876  #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1877#define CIM_CTRL_DMA_EN (1 << 2)
1878#define CIM_CTRL_RXF_RST (1 << 1)
1879#define CIM_CTRL_ENA (1 << 0)
1880
1881/* CIM State Register (CIM_STATE) */
1882
1883#define CIM_STATE_DMA_SOF (1 << 6)
1884#define CIM_STATE_DMA_EOF (1 << 5)
1885#define CIM_STATE_DMA_STOP (1 << 4)
1886#define CIM_STATE_RXF_OF (1 << 3)
1887#define CIM_STATE_RXF_TRIG (1 << 2)
1888#define CIM_STATE_RXF_EMPTY (1 << 1)
1889#define CIM_STATE_VDD (1 << 0)
1890
1891/* CIM DMA Command Register (CIM_CMD) */
1892
1893#define CIM_CMD_SOFINT (1 << 31)
1894#define CIM_CMD_EOFINT (1 << 30)
1895#define CIM_CMD_STOP (1 << 28)
1896#define CIM_CMD_LEN_BIT 0
1897#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
1898
1899
1900/*************************************************************************
1901 * SADC (Smart A/D Controller)
1902 *************************************************************************/
1903
1904#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
1905#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
1906#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
1907#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
1908#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
1909#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
1910#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
1911#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
1912#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
1913
1914#define REG_SADC_ENA REG8(SADC_ENA)
1915#define REG_SADC_CFG REG32(SADC_CFG)
1916#define REG_SADC_CTRL REG8(SADC_CTRL)
1917#define REG_SADC_STATE REG8(SADC_STATE)
1918#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
1919#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
1920#define REG_SADC_TSDAT REG32(SADC_TSDAT)
1921#define REG_SADC_BATDAT REG16(SADC_BATDAT)
1922#define REG_SADC_SADDAT REG16(SADC_SADDAT)
1923
1924/* ADC Enable Register */
1925#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
1926#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
1927#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
1928#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
1929
1930/* ADC Configure Register */
1931#define SADC_CFG_EXIN (1 << 30)
1932#define SADC_CFG_CLKOUT_NUM_BIT 16
1933#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
1934#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
1935#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
1936#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
1937  #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
1938  #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
1939  #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
1940#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
1941#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
1942  #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
1943  #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
1944  #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
1945  #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
1946  #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
1947  #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
1948  #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
1949  #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
1950#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
1951#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
1952#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
1953#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
1954#define SADC_CFG_CMD_BIT 0 /* ADC Command */
1955#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
1956  #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
1957  #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
1958  #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
1959  #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
1960  #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
1961  #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
1962  #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
1963  #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
1964  #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
1965  #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
1966  #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
1967  #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
1968  #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
1969
1970/* ADC Control Register */
1971#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
1972#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
1973#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
1974#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
1975#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
1976
1977/* ADC Status Register */
1978#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
1979#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
1980#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
1981#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
1982#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
1983#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
1984#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
1985#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
1986
1987/* ADC Touch Screen Data Register */
1988#define SADC_TSDAT_DATA0_BIT 0
1989#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
1990#define SADC_TSDAT_TYPE0 (1 << 15)
1991#define SADC_TSDAT_DATA1_BIT 16
1992#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
1993#define SADC_TSDAT_TYPE1 (1 << 31)
1994
1995
1996/*************************************************************************
1997 * SLCD (Smart LCD Controller)
1998 *************************************************************************/
1999
2000#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2001#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2002#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2003#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2004#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2005
2006#define REG_SLCD_CFG REG32(SLCD_CFG)
2007#define REG_SLCD_CTRL REG8(SLCD_CTRL)
2008#define REG_SLCD_STATE REG8(SLCD_STATE)
2009#define REG_SLCD_DATA REG32(SLCD_DATA)
2010#define REG_SLCD_FIFO REG32(SLCD_FIFO)
2011
2012/* SLCD Configure Register */
2013#define SLCD_CFG_BURST_BIT 14
2014#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2015  #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2016  #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2017#define SLCD_CFG_DWIDTH_BIT 10
2018#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2019  #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2020  #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2021  #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2022  #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2023  #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
2024  #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT)
2025#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2026#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2027#define SLCD_CFG_CWIDTH_18BIT (2 << 8)
2028#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2029#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2030#define SLCD_CFG_RS_CMD_LOW (0 << 3)
2031#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2032#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2033#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2034#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2035#define SLCD_CFG_TYPE_SERIAL (1 << 0)
2036
2037/* SLCD Control Register */
2038#define SLCD_CTRL_DMA_EN (1 << 0)
2039
2040/* SLCD Status Register */
2041#define SLCD_STATE_BUSY (1 << 0)
2042
2043/* SLCD Data Register */
2044#define SLCD_DATA_RS_DATA (0 << 31)
2045#define SLCD_DATA_RS_COMMAND (1 << 31)
2046
2047/* SLCD FIFO Register */
2048#define SLCD_FIFO_RS_DATA (0 << 31)
2049#define SLCD_FIFO_RS_COMMAND (1 << 31)
2050
2051
2052/*************************************************************************
2053 * LCD (LCD Controller)
2054 *************************************************************************/
2055#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2056#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2057#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2058#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2059#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2060#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2061#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2062#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2063#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2064#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2065#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2066#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2067#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2068#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2069#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2070#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2071#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2072#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2073#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2074#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2075#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2076
2077#define REG_LCD_CFG REG32(LCD_CFG)
2078#define REG_LCD_VSYNC REG32(LCD_VSYNC)
2079#define REG_LCD_HSYNC REG32(LCD_HSYNC)
2080#define REG_LCD_VAT REG32(LCD_VAT)
2081#define REG_LCD_DAH REG32(LCD_DAH)
2082#define REG_LCD_DAV REG32(LCD_DAV)
2083#define REG_LCD_PS REG32(LCD_PS)
2084#define REG_LCD_CLS REG32(LCD_CLS)
2085#define REG_LCD_SPL REG32(LCD_SPL)
2086#define REG_LCD_REV REG32(LCD_REV)
2087#define REG_LCD_CTRL REG32(LCD_CTRL)
2088#define REG_LCD_STATE REG32(LCD_STATE)
2089#define REG_LCD_IID REG32(LCD_IID)
2090#define REG_LCD_DA0 REG32(LCD_DA0)
2091#define REG_LCD_SA0 REG32(LCD_SA0)
2092#define REG_LCD_FID0 REG32(LCD_FID0)
2093#define REG_LCD_CMD0 REG32(LCD_CMD0)
2094#define REG_LCD_DA1 REG32(LCD_DA1)
2095#define REG_LCD_SA1 REG32(LCD_SA1)
2096#define REG_LCD_FID1 REG32(LCD_FID1)
2097#define REG_LCD_CMD1 REG32(LCD_CMD1)
2098
2099/* LCD Configure Register */
2100#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2101#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2102  #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2103  #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2104#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2105#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2106#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2107#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2108#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2109#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2110#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2111#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2112#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2113#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2114#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2115#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2116#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2117#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2118#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2119#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2120#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2121#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2122#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2123  #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2124  #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2125  #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2126#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2127#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2128  #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2129  #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2130  #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2131  #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2132  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2133  #define LCD_CFG_MODE_INTER_CCIR656 (6 << LCD_CFG_MODE_BIT)
2134  #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2135  #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2136  #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2137  #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2138  #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2139  /* JZ47XX defines */
2140  #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2141  #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2142  #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2143
2144
2145
2146/* Vertical Synchronize Register */
2147#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2148#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2149#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2150#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2151
2152/* Horizontal Synchronize Register */
2153#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2154#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2155#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2156#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2157
2158/* Virtual Area Setting Register */
2159#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2160#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2161#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2162#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2163
2164/* Display Area Horizontal Start/End Point Register */
2165#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2166#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2167#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2168#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2169
2170/* Display Area Vertical Start/End Point Register */
2171#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2172#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2173#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2174#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2175
2176/* PS Signal Setting */
2177#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2178#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2179#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2180#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2181
2182/* CLS Signal Setting */
2183#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2184#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2185#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2186#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2187
2188/* SPL Signal Setting */
2189#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2190#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2191#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2192#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2193
2194/* REV Signal Setting */
2195#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2196#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2197
2198/* LCD Control Register */
2199#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2200#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2201  #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2202  #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2203  #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2204#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2205#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2206#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2207#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2208#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2209  #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2210  #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2211  #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2212#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2213#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2214#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2215#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2216#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2217#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2218#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2219#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2220#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2221#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2222#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2223#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2224#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2225#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2226#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2227  #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2228  #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2229  #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2230  #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2231  #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2232  #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2233
2234/* LCD Status Register */
2235#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2236#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2237#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2238#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2239#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2240#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2241#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2242
2243/* DMA Command Register */
2244#define LCD_CMD_SOFINT (1 << 31)
2245#define LCD_CMD_EOFINT (1 << 30)
2246#define LCD_CMD_PAL (1 << 28)
2247#define LCD_CMD_LEN_BIT 0
2248#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2249
2250
2251/*************************************************************************
2252 * USB Device
2253 *************************************************************************/
2254#define USB_BASE UDC_BASE
2255
2256#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2257#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2258#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2259#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2260#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2261#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2262#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2263#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2264#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2265#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2266#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2267
2268#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2269#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2270#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2271#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2272#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2273#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2274#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2275#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2276
2277#define USB_FIFO_EP0 (USB_BASE + 0x20)
2278#define USB_FIFO_EP1 (USB_BASE + 0x24)
2279#define USB_FIFO_EP2 (USB_BASE + 0x28)
2280
2281#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2282#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2283
2284#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2285#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2286#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2287#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2288#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2289#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2290#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2291
2292
2293/* Power register bit masks */
2294#define USB_POWER_SUSPENDM 0x01
2295#define USB_POWER_RESUME 0x04
2296#define USB_POWER_HSMODE 0x10
2297#define USB_POWER_HSENAB 0x20
2298#define USB_POWER_SOFTCONN 0x40
2299
2300/* Interrupt register bit masks */
2301#define USB_INTR_SUSPEND 0x01
2302#define USB_INTR_RESUME 0x02
2303#define USB_INTR_RESET 0x04
2304
2305#define USB_INTR_EP0 0x0001
2306#define USB_INTR_INEP1 0x0002
2307#define USB_INTR_INEP2 0x0004
2308#define USB_INTR_OUTEP1 0x0002
2309
2310/* CSR0 bit masks */
2311#define USB_CSR0_OUTPKTRDY 0x01
2312#define USB_CSR0_INPKTRDY 0x02
2313#define USB_CSR0_SENTSTALL 0x04
2314#define USB_CSR0_DATAEND 0x08
2315#define USB_CSR0_SETUPEND 0x10
2316#define USB_CSR0_SENDSTALL 0x20
2317#define USB_CSR0_SVDOUTPKTRDY 0x40
2318#define USB_CSR0_SVDSETUPEND 0x80
2319
2320/* Endpoint CSR register bits */
2321#define USB_INCSRH_AUTOSET 0x80
2322#define USB_INCSRH_ISO 0x40
2323#define USB_INCSRH_MODE 0x20
2324#define USB_INCSRH_DMAREQENAB 0x10
2325#define USB_INCSRH_DMAREQMODE 0x04
2326#define USB_INCSR_CDT 0x40
2327#define USB_INCSR_SENTSTALL 0x20
2328#define USB_INCSR_SENDSTALL 0x10
2329#define USB_INCSR_FF 0x08
2330#define USB_INCSR_UNDERRUN 0x04
2331#define USB_INCSR_FFNOTEMPT 0x02
2332#define USB_INCSR_INPKTRDY 0x01
2333#define USB_OUTCSRH_AUTOCLR 0x80
2334#define USB_OUTCSRH_ISO 0x40
2335#define USB_OUTCSRH_DMAREQENAB 0x20
2336#define USB_OUTCSRH_DNYT 0x10
2337#define USB_OUTCSRH_DMAREQMODE 0x08
2338#define USB_OUTCSR_CDT 0x80
2339#define USB_OUTCSR_SENTSTALL 0x40
2340#define USB_OUTCSR_SENDSTALL 0x20
2341#define USB_OUTCSR_FF 0x10
2342#define USB_OUTCSR_DATAERR 0x08
2343#define USB_OUTCSR_OVERRUN 0x04
2344#define USB_OUTCSR_FFFULL 0x02
2345#define USB_OUTCSR_OUTPKTRDY 0x01
2346
2347/* Testmode register bits */
2348#define USB_TEST_SE0NAK 0x01
2349#define USB_TEST_J 0x02
2350#define USB_TEST_K 0x04
2351#define USB_TEST_PACKET 0x08
2352
2353/* DMA control bits */
2354#define USB_CNTL_ENA 0x01
2355#define USB_CNTL_DIR_IN 0x02
2356#define USB_CNTL_MODE_1 0x04
2357#define USB_CNTL_INTR_EN 0x08
2358#define USB_CNTL_EP(n) ((n) << 4)
2359#define USB_CNTL_BURST_0 (0 << 9)
2360#define USB_CNTL_BURST_4 (1 << 9)
2361#define USB_CNTL_BURST_8 (2 << 9)
2362#define USB_CNTL_BURST_16 (3 << 9)
2363
2364#endif /* __JZ4740_REGS_H__ */
arch/mips/include/asm/mach-jz4740/serial.h
1/*
2 * linux/include/asm-mips/mach-jz4740/serial.h
3 *
4 * Ingenic's JZ4740 common include.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <yliu@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_BOARD_SERIAL_H__
16#define __ASM_BOARD_SERIAL_H__
17
18#ifndef CONFIG_SERIAL_MANY_PORTS
19#undef RS_TABLE_SIZE
20#define RS_TABLE_SIZE 1
21#endif
22
23#define JZ_BASE_BAUD (12000000/16)
24
25#define JZ_SERIAL_PORT_DEFNS \
26    { .baud_base = JZ_BASE_BAUD, .irq = IRQ_UART0, \
27      .flags = STD_COM_FLAGS, .iomem_base = (u8 *)UART0_BASE, \
28      .iomem_reg_shift = 2, .io_type = SERIAL_IO_MEM },
29
30#endif /* __ASM_BORAD_SERIAL_H__ */
arch/mips/include/asm/mach-jz4740/war.h
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
9#define __ASM_MIPS_MACH_JZ4740_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
arch/mips/jz4740/Kconfig
1choice
2    prompt "Machine type"
3    depends on MACH_JZ
4    default JZ4740_QI_LB60
5
6config JZ4740_QI_LB60
7    bool "Qi Hardware Ben NanoNote"
8    select DMA_NONCOHERENT
9    select SOC_JZ4740
10
11endchoice
12
13config SOC_JZ4740
14    bool
15    select JZSOC
16    select GENERIC_GPIO
17    select ARCH_REQUIRE_GPIOLIB
18    select SYS_HAS_EARLY_PRINTK
19    select SYS_SUPPORTS_LITTLE_ENDIAN
20    select IRQ_CPU
21
22config JZSOC
23    bool
24    select JZRISC
25    select SYS_HAS_CPU_MIPS32_R1
26    select SYS_SUPPORTS_32BIT_KERNEL
27
28config JZRISC
29    bool
arch/mips/jz4740/Makefile
1#
2# Makefile for the Ingenic JZ4740.
3#
4
5# Object file lists.
6
7obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
8    gpio.o clock.o platform.o
9
10obj-$(CONFIG_PROC_FS) += proc.o
11
12# board specific support
13
14obj-$(CONFIG_JZ4740_PAVO) += board-pavo.o
15obj-$(CONFIG_JZ4740_LEO) += board-leo.o
16obj-$(CONFIG_JZ4740_LYRA) += board-lyra.o
17obj-$(CONFIG_JZ4725_DIPPER) += board-dipper.o
18obj-$(CONFIG_JZ4720_VIRGO) += board-virgo.o
19obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
20
21# PM support
22
23obj-$(CONFIG_PM) +=pm.o
24
25# CPU Frequency scaling support
26
27obj-$(CONFIG_CPU_FREQ_JZ) +=cpufreq.o
arch/mips/jz4740/board-qi_lb60.c
1/*
2 * linux/arch/mips/jz4740/board-qi_lb60.c
3 *
4 * QI_LB60 setup routines.
5 *
6 * Copyright (c) 2009 Qi Hardware inc.,
7 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 or later
11 * as published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/gpio.h>
17
18#include <asm/mach-jz4740/board-qi_lb60.h>
19#include <asm/mach-jz4740/platform.h>
20
21#include <linux/input.h>
22#include <linux/gpio_keys.h>
23#include <linux/mtd/jz4740_nand.h>
24#include <linux/jz4740_fb.h>
25#include <linux/input/matrix_keypad.h>
26#include <linux/mtd/jz4740_nand.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/spi_gpio.h>
29#include <linux/power_supply.h>
30#include <linux/power/jz4740-battery.h>
31#include <linux/mmc/jz4740_mmc.h>
32
33
34/* NAND */
35static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
36    .eccbytes = 36,
37    .eccpos = {
38        6, 7, 8, 9, 10, 11, 12, 13,
39        14, 15, 16, 17, 18, 19, 20, 21,
40        22, 23, 24, 25, 26, 27, 28, 29,
41        30, 31, 32, 33, 34, 35, 36, 37,
42        38, 39, 40, 41},
43    .oobfree = {
44        {.offset = 2,
45         .length = 4},
46        {.offset = 42,
47         .length = 22}}
48};
49
50static struct mtd_partition qi_lb60_partitions_1gb[] = {
51    { .name = "NAND BOOT partition",
52      .offset = 0 * 0x100000,
53      .size = 4 * 0x100000,
54     },
55    { .name = "NAND KERNEL partition",
56      .offset = 4 * 0x100000,
57      .size = 4 * 0x100000,
58     },
59    { .name = "NAND ROOTFS partition",
60      .offset = 8 * 0x100000,
61      .size = 504 * 0x100000,
62     },
63    { .name = "NAND DATA partition",
64      .offset = 512 * 0x100000,
65      .size = 512 * 0x100000,
66     },
67};
68
69static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
70    .eccbytes = 72,
71    .eccpos = {
72        12, 13, 14, 15, 16, 17, 18, 19,
73        20, 21, 22, 23, 24, 25, 26, 27,
74        28, 29, 30, 31, 32, 33, 34, 35,
75        36, 37, 38, 39, 40, 41, 42, 43,
76        44, 45, 46, 47, 48, 49, 50, 51,
77        52, 53, 54, 55, 56, 57, 58, 59,
78        60, 61, 62, 63, 64, 65, 66, 67,
79        68, 69, 70, 71, 72, 73, 74, 75,
80        76, 77, 78, 79, 80, 81, 82, 83},
81    .oobfree = {
82         {.offset = 2,
83         .length = 10},
84        {.offset = 84,
85         .length = 44}}
86};
87
88static struct mtd_partition qi_lb60_partitions_2gb[] = {
89    { .name = "NAND BOOT partition",
90      .offset = 0 * 0x100000,
91      .size = 4 * 0x100000,
92     },
93    { .name = "NAND KERNEL partition",
94      .offset = 4 * 0x100000,
95      .size = 4 * 0x100000,
96     },
97    { .name = "NAND ROOTFS partition",
98      .offset = 8 * 0x100000,
99      .size = 504 * 0x100000,
100     },
101    { .name = "NAND DATA partition",
102      .offset = 512 * 0x100000,
103      .size = (512 + 1024) * 0x100000,
104     },
105};
106
107static void qi_lb60_nand_ident(struct platform_device *pdev,
108                struct nand_chip *chip,
109                struct mtd_partition **partitions,
110                int *num_partitions)
111{
112    if (chip->page_shift == 12) {
113        chip->ecc.layout = &qi_lb60_ecclayout_2gb;
114        *partitions = qi_lb60_partitions_2gb;
115        *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb);
116    } else {
117        chip->ecc.layout = &qi_lb60_ecclayout_1gb;
118        *partitions = qi_lb60_partitions_1gb;
119        *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb);
120    }
121}
122
123static struct jz_nand_platform_data qi_lb60_nand_pdata = {
124    .ident_callback = qi_lb60_nand_ident,
125    .busy_gpio = 94,
126};
127
128
129/* Keyboard*/
130
131/* #define KEEP_UART_ALIVE
132 * don't define this. the keyboard and keyboard both work
133 */
134
135#define KEY_QI_QI KEY_F13
136#define KEY_QI_UPRED KEY_RIGHTSHIFT
137#define KEY_QI_VOLUP KEY_F15
138#define KEY_QI_VOLDOWN KEY_F16
139#define KEY_QI_FN KEY_RIGHTCTRL
140
141static const uint32_t qi_lb60_keymap[] = {
142    KEY(0, 0, KEY_F1), /* S2 */
143    KEY(0, 1, KEY_F2), /* S3 */
144    KEY(0, 2, KEY_F3), /* S4 */
145    KEY(0, 3, KEY_F4), /* S5 */
146    KEY(0, 4, KEY_F5), /* S6 */
147    KEY(0, 5, KEY_F6), /* S7 */
148    KEY(0, 6, KEY_F7), /* S8 */
149
150    KEY(1, 0, KEY_Q), /* S10 */
151    KEY(1, 1, KEY_W), /* S11 */
152    KEY(1, 2, KEY_E), /* S12 */
153    KEY(1, 3, KEY_R), /* S13 */
154    KEY(1, 4, KEY_T), /* S14 */
155    KEY(1, 5, KEY_Y), /* S15 */
156    KEY(1, 6, KEY_U), /* S16 */
157    KEY(1, 7, KEY_I), /* S17 */
158    KEY(2, 0, KEY_A), /* S18 */
159    KEY(2, 1, KEY_S), /* S19 */
160    KEY(2, 2, KEY_D), /* S20 */
161    KEY(2, 3, KEY_F), /* S21 */
162    KEY(2, 4, KEY_G), /* S22 */
163    KEY(2, 5, KEY_H), /* S23 */
164    KEY(2, 6, KEY_J), /* S24 */
165    KEY(2, 7, KEY_K), /* S25 */
166    KEY(3, 0, KEY_ESC), /* S26 */
167    KEY(3, 1, KEY_Z), /* S27 */
168    KEY(3, 2, KEY_X), /* S28 */
169    KEY(3, 3, KEY_C), /* S29 */
170    KEY(3, 4, KEY_V), /* S30 */
171    KEY(3, 5, KEY_B), /* S31 */
172    KEY(3, 6, KEY_N), /* S32 */
173    KEY(3, 7, KEY_M), /* S33 */
174    KEY(4, 0, KEY_TAB), /* S34 */
175    KEY(4, 1, KEY_CAPSLOCK), /* S35 */
176    KEY(4, 2, KEY_BACKSLASH), /* S36 */
177    KEY(4, 3, KEY_APOSTROPHE), /* S37 */
178    KEY(4, 4, KEY_COMMA), /* S38 */
179    KEY(4, 5, KEY_DOT), /* S39 */
180    KEY(4, 6, KEY_SLASH), /* S40 */
181    KEY(4, 7, KEY_UP), /* S41 */
182    KEY(5, 0, KEY_O), /* S42 */
183    KEY(5, 1, KEY_L), /* S43 */
184    KEY(5, 2, KEY_EQUAL), /* S44 */
185    KEY(5, 3, KEY_QI_UPRED), /* S45 */
186    KEY(5, 4, KEY_SPACE), /* S46 */
187    KEY(5, 5, KEY_QI_QI), /* S47 */
188    KEY(5, 6, KEY_LEFTCTRL), /* S48 */
189    KEY(5, 7, KEY_LEFT), /* S49 */
190    KEY(6, 0, KEY_F8), /* S50 */
191    KEY(6, 1, KEY_P), /* S51 */
192    KEY(6, 2, KEY_BACKSPACE),/* S52 */
193    KEY(6, 3, KEY_ENTER), /* S53 */
194    KEY(6, 4, KEY_QI_VOLUP), /* S54 */
195    KEY(6, 5, KEY_QI_VOLDOWN), /* S55 */
196    KEY(6, 6, KEY_DOWN), /* S56 */
197    KEY(6, 7, KEY_RIGHT), /* S57 */
198
199#ifndef KEEP_UART_ALIVE
200    KEY(7, 0, KEY_LEFTSHIFT), /* S58 */
201    KEY(7, 1, KEY_LEFTALT), /* S59 */
202    KEY(7, 2, KEY_QI_FN), /* S60 */
203#endif
204};
205
206static const struct matrix_keymap_data qi_lb60_keymap_data = {
207    .keymap = qi_lb60_keymap,
208    .keymap_size = ARRAY_SIZE(qi_lb60_keymap),
209};
210
211static const unsigned int qi_lb60_keypad_cols[] = {
212    74, 75, 76, 77, 78, 79, 80, 81,
213};
214
215static const unsigned int qi_lb60_keypad_rows[] = {
216    114, 115, 116, 117, 118, 119, 120,
217#ifndef KEEP_UART_ALIVE
218    122,
219#endif
220};
221
222static struct matrix_keypad_platform_data qi_lb60_pdata = {
223    .keymap_data = &qi_lb60_keymap_data,
224    .col_gpios = qi_lb60_keypad_cols,
225    .row_gpios = qi_lb60_keypad_rows,
226    .num_col_gpios = ARRAY_SIZE(qi_lb60_keypad_cols),
227    .num_row_gpios = ARRAY_SIZE(qi_lb60_keypad_rows),
228    .col_scan_delay_us = 10,
229    .debounce_ms = 10,
230    .wakeup = 1,
231    .active_low = 1,
232};
233
234static struct platform_device qi_lb60_keypad = {
235    .name = "matrix-keypad",
236    .id = -1,
237    .dev = {
238        .platform_data = &qi_lb60_pdata,
239    },
240};
241
242/* Display */
243static struct fb_videomode qi_lb60_video_modes[] = {
244    {
245        .name = "320x240",
246        .xres = 320,
247        .yres = 240,
248        .pixclock = 700000,
249        .left_margin = 140,
250        .right_margin = 273,
251        .upper_margin = 20,
252        .lower_margin = 2,
253        .hsync_len = 1,
254        .vsync_len = 1,
255        .sync = 0,
256        .vmode = FB_VMODE_NONINTERLACED,
257    },
258};
259
260static struct jz4740_fb_platform_data qi_lb60_fb_pdata = {
261    .width = 60,
262    .height = 45,
263    .num_modes = ARRAY_SIZE(qi_lb60_video_modes),
264    .modes = qi_lb60_video_modes,
265    .bpp = 24,
266    .lcd_type = JZ_LCD_TYPE_8BIT_SERIAL,
267};
268
269
270struct spi_gpio_platform_data spigpio_platform_data = {
271    .sck = JZ_GPIO_PORTC(23),
272    .mosi = JZ_GPIO_PORTC(22),
273    .miso = JZ_GPIO_PORTC(22),
274    .num_chipselect = 1,
275};
276
277static struct platform_device spigpio_device = {
278    .name = "spi_gpio",
279    .id = 1,
280    .dev = {
281        .platform_data = &spigpio_platform_data,
282    },
283};
284
285static struct spi_board_info qi_lb60_spi_board_info[] = {
286    {
287        .modalias = "gpm940b0",
288        .controller_data = (void*)JZ_GPIO_PORTC(21),
289        .chip_select = 0,
290        .bus_num = 1,
291        .max_speed_hz = 30 * 1000,
292    },
293};
294
295/* Battery */
296static struct jz_batt_info qi_lb60_battery_pdata = {
297    .dc_dect_gpio = GPIO_DC_DETE_N,
298    .usb_dect_gpio = GPIO_USB_DETE,
299    .charg_stat_gpio = GPIO_CHARG_STAT_N,
300
301    .min_voltag = 3600000,
302    .max_voltag = 4200000,
303    .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO,
304};
305
306/* GPIO Key: power */
307static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
308    [0] = {
309        .code = KEY_POWER,
310        .gpio = GPIO_WAKEUP_N,
311        .active_low = 1,
312        .desc = "Power",
313        .wakeup = 1,
314    },
315};
316
317static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
318    .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
319    .buttons = qi_lb60_gpio_keys_buttons,
320};
321
322static struct platform_device qi_lb60_gpio_keys = {
323    .name = "gpio-keys",
324    .id = -1,
325    .dev = {
326        .platform_data = &qi_lb60_gpio_keys_data,
327    }
328};
329
330static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
331    .gpio_card_detect = JZ_GPIO_PORTD(0),
332    .gpio_read_only = JZ_GPIO_PORTD(16),
333    .gpio_power = JZ_GPIO_PORTD(2),
334};
335
336static struct platform_device *jz_platform_devices[] __initdata = {
337    &jz4740_usb_ohci_device,
338    &jz4740_usb_gdt_device,
339    &jz4740_mmc_device,
340    &jz4740_nand_device,
341    &qi_lb60_keypad,
342    &spigpio_device,
343    &jz4740_framebuffer_device,
344    &jz4740_i2s_device,
345    &jz4740_codec_device,
346    &jz4740_rtc_device,
347    &jz4740_adc_device,
348    &jz4740_battery_device,
349    &qi_lb60_gpio_keys,
350};
351
352static void __init board_gpio_setup(void)
353{
354    /* We only need to enable/disable pullup here for pins used in generic
355     * drivers. Everything else is done by the drivers themselfs. */
356    jz_gpio_disable_pullup(GPIO_SD_VCC_EN_N);
357    jz_gpio_disable_pullup(GPIO_SD_CD_N);
358    jz_gpio_disable_pullup(GPIO_SD_WP);
359}
360
361static int __init qi_lb60_init_platform_devices(void)
362{
363    jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata;
364    jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata;
365    jz4740_battery_device.dev.platform_data = &qi_lb60_battery_pdata;
366/* jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata;*/
367
368    spi_register_board_info(qi_lb60_spi_board_info,
369                ARRAY_SIZE(qi_lb60_spi_board_info));
370
371    return platform_add_devices(jz_platform_devices,
372                    ARRAY_SIZE(jz_platform_devices));
373
374}
375extern int jz_gpiolib_init(void);
376extern int jz_init_clocks(unsigned long extal);
377
378static int __init qi_lb60_board_setup(void)
379{
380    printk("Qi Hardware JZ4740 QI_LB60 setup\n");
381    if (jz_gpiolib_init())
382        panic("Failed to initalize jz gpio\n");
383    jz_init_clocks(12000000);
384
385    board_gpio_setup();
386
387    if (qi_lb60_init_platform_devices())
388        panic("Failed to initalize platform devices\n");
389
390    return 0;
391}
392
393arch_initcall(qi_lb60_board_setup);
arch/mips/jz4740/clock.c
1
2#include <linux/kernel.h>
3#include <linux/errno.h>
4#include <linux/clk.h>
5#include <linux/spinlock.h>
6#include <linux/io.h>
7#include <linux/module.h>
8#include <linux/list.h>
9#include <linux/err.h>
10
11#define JZ_REG_CLOCK_CTRL 0x00
12#define JZ_REG_CLOCK_PLL 0x10
13#define JZ_REG_CLOCK_GATE 0x20
14#define JZ_REG_CLOCK_I2S 0x60
15#define JZ_REG_CLOCK_LCD 0x64
16#define JZ_REG_CLOCK_MMC 0x68
17#define JZ_REG_CLOCK_UHC 0x6C
18#define JZ_REG_CLOCK_SPI 0x74
19
20#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31)
21#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30)
22#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29)
23#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000
24#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22)
25#define JZ_CLOCK_CTRL_PLL_HALF BIT(21)
26#define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000
27#define JZ_CLOCK_CTRL_UDIV_OFFSET 23
28#define JZ_CLOCK_CTRL_LDIV_OFFSET 16
29#define JZ_CLOCK_CTRL_MDIV_OFFSET 12
30#define JZ_CLOCK_CTRL_PDIV_OFFSET 8
31#define JZ_CLOCK_CTRL_HDIV_OFFSET 4
32#define JZ_CLOCK_CTRL_CDIV_OFFSET 0
33
34#define JZ_CLOCK_GATE_UART0 BIT(0)
35#define JZ_CLOCK_GATE_TCU BIT(1)
36#define JZ_CLOCK_GATE_RTC BIT(2)
37#define JZ_CLOCK_GATE_I2C BIT(3)
38#define JZ_CLOCK_GATE_SPI BIT(4)
39#define JZ_CLOCK_GATE_AIC_PCLK BIT(5)
40#define JZ_CLOCK_GATE_AIC BIT(6)
41#define JZ_CLOCK_GATE_MMC BIT(7)
42#define JZ_CLOCK_GATE_ADC BIT(8)
43#define JZ_CLOCK_GATE_CIM BIT(9)
44#define JZ_CLOCK_GATE_LCD BIT(10)
45#define JZ_CLOCK_GATE_UDC BIT(11)
46#define JZ_CLOCK_GATE_DMAC BIT(12)
47#define JZ_CLOCK_GATE_IPU BIT(13)
48#define JZ_CLOCK_GATE_UHC BIT(14)
49#define JZ_CLOCK_GATE_UART1 BIT(15)
50
51#define JZ_CLOCK_I2S_DIV_MASK 0x01ff
52
53#define JZ_CLOCK_LCD_DIV_MASK 0x01ff
54
55#define JZ_CLOCK_MMC_DIV_MASK 0x001f
56
57#define JZ_CLOCK_UHC_DIV_MASK 0x000f
58
59#define JZ_CLOCK_SPI_SRC_PLL BIT(31)
60#define JZ_CLOCK_SPI_DIV_MASK 0x000f
61
62#define JZ_CLOCK_PLL_M_MASK 0x01ff
63#define JZ_CLOCK_PLL_N_MASK 0x001f
64#define JZ_CLOCK_PLL_OD_MASK 0x0003
65#define JZ_CLOCK_PLL_STABLE BIT(10)
66#define JZ_CLOCK_PLL_BYPASS BIT(9)
67#define JZ_CLOCK_PLL_ENABLED BIT(8)
68#define JZ_CLOCK_PLL_STABLIZE_MASK 0x000f
69#define JZ_CLOCK_PLL_M_OFFSET 23
70#define JZ_CLOCK_PLL_N_OFFSET 18
71#define JZ_CLOCK_PLL_OD_OFFSET 16
72
73static void __iomem *jz_clock_base;
74static spinlock_t jz_clock_lock;
75static LIST_HEAD(jz_clocks);
76
77struct clk {
78    const char *name;
79    struct clk* parent;
80
81    uint32_t gate_bit;
82
83    unsigned long (*get_rate)(struct clk* clk);
84    unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
85    int (*set_rate)(struct clk* clk, unsigned long rate);
86    int (*enable)(struct clk* clk);
87    int (*disable)(struct clk* clk);
88
89    int (*set_parent)(struct clk* clk, struct clk *parent);
90    struct list_head list;
91};
92
93struct main_clk {
94    struct clk clk;
95    uint32_t div_offset;
96};
97
98struct divided_clk {
99    struct clk clk;
100    uint32_t reg;
101    uint32_t mask;
102};
103
104struct static_clk {
105    struct clk clk;
106    unsigned long rate;
107};
108
109static uint32_t jz_clk_reg_read(int reg)
110{
111    return readl(jz_clock_base + reg);
112}
113
114static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
115{
116    uint32_t val2;
117
118    spin_lock(&jz_clock_lock);
119    val2 = readl(jz_clock_base + reg);
120    val2 &= ~mask;
121    val2 |= val;
122    writel(val2, jz_clock_base + reg);
123    spin_unlock(&jz_clock_lock);
124}
125
126static void jz_clk_reg_set_bits(int reg, uint32_t mask)
127{
128    uint32_t val;
129
130    spin_lock(&jz_clock_lock);
131    val = readl(jz_clock_base + reg);
132    val |= mask;
133    writel(val, jz_clock_base + reg);
134    spin_unlock(&jz_clock_lock);
135}
136
137static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
138{
139    uint32_t val;
140
141    spin_lock(&jz_clock_lock);
142    val = readl(jz_clock_base + reg);
143    val &= ~mask;
144    writel(val, jz_clock_base + reg);
145    spin_unlock(&jz_clock_lock);
146}
147
148static int jz_clk_enable_gating(struct clk *clk)
149{
150    jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
151    return 0;
152}
153
154static int jz_clk_disable_gating(struct clk *clk)
155{
156    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
157    return 0;
158}
159
160static unsigned long jz_clk_static_get_rate(struct clk *clk)
161{
162    return ((struct static_clk*)clk)->rate;
163}
164
165static int jz_clk_ko_enable(struct clk* clk)
166{
167    jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
168    return 0;
169}
170
171static int jz_clk_ko_disable(struct clk* clk)
172{
173    jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
174    return 0;
175}
176
177
178static const int pllno[] = {1, 2, 2, 4};
179
180static unsigned long jz_clk_pll_get_rate(struct clk *clk)
181{
182    uint32_t val;
183    int m;
184    int n;
185    int od;
186
187    val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
188
189    if (val & JZ_CLOCK_PLL_BYPASS)
190        return clk_get_rate(clk->parent);
191
192    m = ((val >> 23) & 0x1ff) + 2;
193    n = ((val >> 18) & 0x1f) + 2;
194    od = (val >> 16) & 0x3;
195
196    return clk_get_rate(clk->parent) * (m / n) / pllno[od];
197}
198
199static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
200{
201    uint32_t reg;
202
203    reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
204    if (reg & JZ_CLOCK_CTRL_PLL_HALF)
205        return jz_clk_pll_get_rate(clk->parent);
206    return jz_clk_pll_get_rate(clk->parent) >> 1;
207}
208
209
210
211static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
212
213static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
214{
215    unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
216    int div;
217
218    div = parent_rate / rate;
219    if (div > 32)
220        return parent_rate / 32;
221    else if (div < 1)
222        return parent_rate;
223
224    div &= (0x3 << (ffs(div) - 1));
225
226    return parent_rate / div;
227}
228
229static unsigned long jz_clk_main_get_rate(struct clk *clk) {
230    struct main_clk *mclk = (struct main_clk*)clk;
231    uint32_t div;
232
233    div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
234
235    div >>= mclk->div_offset;
236    div &= 0xf;
237
238    if (div >= ARRAY_SIZE(jz_clk_main_divs))
239        div = ARRAY_SIZE(jz_clk_main_divs) - 1;
240
241    return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
242}
243
244static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
245{
246    struct main_clk *mclk = (struct main_clk*)clk;
247    int i;
248    int div;
249    unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
250
251    rate = jz_clk_main_round_rate(clk, rate);
252
253    div = parent_rate / rate;
254
255    i = (ffs(div) - 1) << 1;
256    if (i > 0 && !(div & BIT(i-1)))
257        i -= 1;
258
259    jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
260                0xf << mclk->div_offset);
261
262    return 0;
263}
264
265
266static struct static_clk jz_clk_ext = {
267    .clk = {
268        .name = "ext",
269        .get_rate = jz_clk_static_get_rate,
270    },
271};
272
273static struct clk jz_clk_pll = {
274    .name = "pll",
275    .parent = &jz_clk_ext.clk,
276    .get_rate = jz_clk_pll_get_rate,
277};
278
279static struct clk jz_clk_pll_half = {
280    .name = "pll half",
281    .parent = &jz_clk_pll,
282    .get_rate = jz_clk_pll_half_get_rate,
283};
284
285static struct main_clk jz_clk_cpu = {
286    .clk = {
287        .name = "cclk",
288        .parent = &jz_clk_pll,
289        .get_rate = jz_clk_main_get_rate,
290        .set_rate = jz_clk_main_set_rate,
291        .round_rate = jz_clk_main_round_rate,
292    },
293    .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
294};
295
296static struct main_clk jz_clk_memory = {
297    .clk = {
298        .name = "mclk",
299        .parent = &jz_clk_pll,
300        .get_rate = jz_clk_main_get_rate,
301        .set_rate = jz_clk_main_set_rate,
302        .round_rate = jz_clk_main_round_rate,
303    },
304    .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
305};
306
307static struct main_clk jz_clk_high_speed_peripheral = {
308    .clk = {
309        .name = "hclk",
310        .parent = &jz_clk_pll,
311        .get_rate = jz_clk_main_get_rate,
312        .set_rate = jz_clk_main_set_rate,
313        .round_rate = jz_clk_main_round_rate,
314    },
315    .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
316};
317
318
319static struct main_clk jz_clk_low_speed_peripheral = {
320    .clk = {
321        .name = "pclk",
322        .parent = &jz_clk_pll,
323        .get_rate = jz_clk_main_get_rate,
324        .set_rate = jz_clk_main_set_rate,
325    },
326    .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
327};
328
329static struct clk jz_clk_ko = {
330    .name = "cko",
331    .parent = &jz_clk_memory.clk,
332    .enable = jz_clk_ko_enable,
333    .disable = jz_clk_ko_disable,
334};
335
336static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
337{
338    if (parent == &jz_clk_pll)
339        jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
340    else if(parent == &jz_clk_ext.clk)
341        jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
342    else
343        return -EINVAL;
344
345    clk->parent = parent;
346
347    return 0;
348}
349
350static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
351{
352    if (parent == &jz_clk_pll_half)
353        jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
354    else if(parent == &jz_clk_ext.clk)
355        jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
356    else
357        return -EINVAL;
358
359    clk->parent = parent;
360
361    return 0;
362}
363
364static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
365{
366    if (parent == &jz_clk_pll_half)
367        jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
368    else if(parent == &jz_clk_ext.clk)
369        jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
370    else
371        return -EINVAL;
372
373    clk->parent = parent;
374
375    return 0;
376}
377
378static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
379{
380    int div;
381
382    if (clk->parent == &jz_clk_ext.clk)
383        return -EINVAL;
384
385    div = clk_get_rate(clk->parent) / rate - 1;
386
387    if (div < 0)
388        div = 0;
389    else if (div > 63)
390        div = 63;
391
392    jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
393                JZ_CLOCK_CTRL_UDIV_MASK);
394    return 0;
395}
396
397static unsigned long jz_clk_udc_get_rate(struct clk *clk)
398{
399    int div;
400
401    if (clk->parent == &jz_clk_ext.clk)
402        return clk_get_rate(clk->parent);
403
404    div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
405    div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
406    div += 1;
407
408    return clk_get_rate(clk->parent) / div;
409}
410
411static unsigned long jz_clk_divided_get_rate(struct clk *clk)
412{
413    struct divided_clk *dclk = (struct divided_clk*)clk;
414    int div;
415
416    if (clk->parent == &jz_clk_ext.clk)
417        return clk_get_rate(clk->parent);
418
419    div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
420
421    return clk_get_rate(clk->parent) / div;
422}
423
424static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
425{
426    struct divided_clk *dclk = (struct divided_clk*)clk;
427    int div;
428
429    if (clk->parent == &jz_clk_ext.clk)
430        return -EINVAL;
431
432    div = clk_get_rate(clk->parent) / rate - 1;
433
434    if (div < 0)
435        div = 0;
436    else if(div > dclk->mask)
437        div = dclk->mask;
438
439    jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
440
441    return 0;
442}
443
444static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
445{
446    int div;
447    unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
448
449    if (rate > 150000000)
450        return 150000000;
451
452    div = parent_rate / rate;
453    if (div < 1)
454        div = 1;
455    else if(div > 32)
456        div = 32;
457
458    return parent_rate / div;
459}
460
461static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
462{
463    int div;
464
465    if (rate > 150000000)
466        return -EINVAL;
467
468    div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
469    if (div < 0)
470        div = 0;
471    else if(div > 31)
472        div = 31;
473
474    jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
475                JZ_CLOCK_CTRL_LDIV_MASK);
476
477    return 0;
478}
479
480static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
481{
482    int div;
483
484    div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
485    div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
486
487    return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
488}
489
490static struct clk jz_clk_ld = {
491    .name = "lcd",
492    .parent = &jz_clk_pll_half,
493    .set_rate = jz_clk_ldclk_set_rate,
494    .get_rate = jz_clk_ldclk_get_rate,
495    .round_rate = jz_clk_ldclk_round_rate,
496};
497
498static struct divided_clk jz_clk_lp = {
499    .clk = {
500        .name = "lcd_pclk",
501        .parent = &jz_clk_pll_half,
502    },
503    .reg = JZ_REG_CLOCK_LCD,
504    .mask = JZ_CLOCK_LCD_DIV_MASK,
505};
506
507static struct clk jz_clk_cim_mclk = {
508    .name = "cim_mclk",
509    .parent = &jz_clk_high_speed_peripheral.clk,
510};
511
512static struct static_clk jz_clk_cim_pclk = {
513    .clk = {
514        .name = "cim_pclk",
515        .gate_bit = JZ_CLOCK_GATE_CIM,
516        .get_rate = jz_clk_static_get_rate,
517        .enable = jz_clk_enable_gating,
518        .disable = jz_clk_disable_gating,
519    },
520};
521
522static struct divided_clk jz_clk_i2s = {
523    .clk = {
524        .name = "i2s",
525        .parent = &jz_clk_ext.clk,
526        .gate_bit = JZ_CLOCK_GATE_AIC,
527        .set_parent = jz_clk_i2s_set_parent,
528        .set_rate = jz_clk_divided_set_rate,
529        .get_rate = jz_clk_divided_get_rate,
530    },
531    .reg = JZ_REG_CLOCK_I2S,
532    .mask = JZ_CLOCK_I2S_DIV_MASK,
533};
534
535static struct divided_clk jz_clk_mmc = {
536    .clk = {
537        .name = "mmc",
538        .parent = &jz_clk_pll_half,
539        .gate_bit = JZ_CLOCK_GATE_MMC,
540        .set_rate = jz_clk_divided_set_rate,
541        .get_rate = jz_clk_divided_get_rate,
542        .enable = jz_clk_enable_gating,
543        .disable = jz_clk_disable_gating,
544    },
545    .reg = JZ_REG_CLOCK_MMC,
546    .mask = JZ_CLOCK_MMC_DIV_MASK,
547};
548
549static struct divided_clk jz_clk_uhc = {
550    .clk = {
551        .name = "uhc",
552        .parent = &jz_clk_pll_half,
553        .gate_bit = JZ_CLOCK_GATE_UHC,
554        .set_rate = jz_clk_divided_set_rate,
555        .get_rate = jz_clk_divided_get_rate,
556        .enable = jz_clk_enable_gating,
557        .disable = jz_clk_disable_gating,
558    },
559    .reg = JZ_REG_CLOCK_UHC,
560    .mask = JZ_CLOCK_UHC_DIV_MASK,
561};
562
563static struct clk jz_clk_udc = {
564    .name = "udc",
565    .parent = &jz_clk_ext.clk,
566    .set_parent = jz_clk_udc_set_parent,
567    .set_rate = jz_clk_udc_set_rate,
568    .get_rate = jz_clk_udc_get_rate,
569};
570
571static struct divided_clk jz_clk_spi = {
572    .clk = {
573        .name = "spi",
574        .parent = &jz_clk_ext.clk,
575        .gate_bit = JZ_CLOCK_GATE_SPI,
576        .set_rate = jz_clk_divided_set_rate,
577        .get_rate = jz_clk_divided_get_rate,
578        .enable = jz_clk_enable_gating,
579        .disable = jz_clk_disable_gating,
580        .set_parent = jz_clk_spi_set_parent,
581    },
582    .reg = JZ_REG_CLOCK_SPI,
583    .mask = JZ_CLOCK_SPI_DIV_MASK,
584};
585
586static struct clk jz_clk_uart0 = {
587    .name = "uart0",
588    .parent = &jz_clk_ext.clk,
589    .gate_bit = JZ_CLOCK_GATE_UART0,
590    .enable = jz_clk_enable_gating,
591    .disable = jz_clk_disable_gating,
592};
593
594static struct clk jz_clk_uart1 = {
595    .name = "uart1",
596    .parent = &jz_clk_ext.clk,
597    .gate_bit = JZ_CLOCK_GATE_UART1,
598    .enable = jz_clk_enable_gating,
599    .disable = jz_clk_disable_gating,
600};
601
602static struct clk jz_clk_dma = {
603    .name = "dma",
604    .parent = &jz_clk_high_speed_peripheral.clk,
605    .gate_bit = JZ_CLOCK_GATE_UART0,
606    .enable = jz_clk_enable_gating,
607    .disable = jz_clk_disable_gating,
608};
609
610static struct clk jz_clk_ipu = {
611    .name = "ipu",
612    .parent = &jz_clk_high_speed_peripheral.clk,
613    .gate_bit = JZ_CLOCK_GATE_IPU,
614    .enable = jz_clk_enable_gating,
615    .disable = jz_clk_disable_gating,
616};
617
618static struct clk jz_clk_adc = {
619    .name = "adc",
620    .parent = &jz_clk_ext.clk,
621    .gate_bit = JZ_CLOCK_GATE_ADC,
622    .enable = jz_clk_enable_gating,
623    .disable = jz_clk_disable_gating,
624};
625
626static struct clk jz_clk_i2c = {
627    .name = "i2c",
628    .parent = &jz_clk_ext.clk,
629    .gate_bit = JZ_CLOCK_GATE_I2C,
630    .enable = jz_clk_enable_gating,
631    .disable = jz_clk_disable_gating,
632};
633
634static struct static_clk jz_clk_rtc = {
635    .clk = {
636        .name = "rtc",
637        .gate_bit = JZ_CLOCK_GATE_RTC,
638        .enable = jz_clk_enable_gating,
639        .disable = jz_clk_disable_gating,
640    },
641    .rate = 32768,
642};
643
644int clk_enable(struct clk *clk)
645{
646    if (!clk->enable)
647        return -EINVAL;
648
649    return clk->enable(clk);
650}
651EXPORT_SYMBOL_GPL(clk_enable);
652
653void clk_disable(struct clk *clk)
654{
655    if (clk->disable)
656        clk->disable(clk);
657}
658EXPORT_SYMBOL_GPL(clk_disable);
659
660unsigned long clk_get_rate(struct clk *clk)
661{
662    if (clk->get_rate)
663        return clk->get_rate(clk);
664    if (clk->parent)
665        return clk_get_rate(clk->parent);
666
667    return -EINVAL;
668}
669EXPORT_SYMBOL_GPL(clk_get_rate);
670
671int clk_set_rate(struct clk *clk, unsigned long rate)
672{
673    if (!clk->set_rate)
674        return -EINVAL;
675    return clk->set_rate(clk, rate);
676}
677EXPORT_SYMBOL_GPL(clk_set_rate);
678
679long clk_round_rate(struct clk *clk, unsigned long rate)
680{
681    if (clk->round_rate)
682        return clk->round_rate(clk, rate);
683
684    return -EINVAL;
685}
686EXPORT_SYMBOL_GPL(clk_round_rate);
687
688int clk_set_parent(struct clk *clk, struct clk *parent)
689{
690    int ret;
691
692    if (!clk->set_parent)
693        return -EINVAL;
694
695    clk->disable(clk);
696    ret = clk->set_parent(clk, parent);
697    clk->enable(clk);
698
699    return ret;
700}
701EXPORT_SYMBOL_GPL(clk_set_parent);
702
703
704struct clk *clk_get(struct device *dev, const char *name)
705{
706    struct clk *clk;
707
708    list_for_each_entry(clk, &jz_clocks, list) {
709        if (strcmp(clk->name, name) == 0)
710            return clk;
711    }
712    return ERR_PTR(-ENOENT);
713}
714EXPORT_SYMBOL_GPL(clk_get);
715
716void clk_put(struct clk *clk)
717{
718}
719EXPORT_SYMBOL_GPL(clk_put);
720
721inline static void clk_add(struct clk *clk)
722{
723    list_add_tail(&clk->list, &jz_clocks);
724}
725
726static void clk_register_clks(void)
727{
728    clk_add(&jz_clk_ext.clk);
729    clk_add(&jz_clk_pll);
730    clk_add(&jz_clk_pll_half);
731    clk_add(&jz_clk_cpu.clk);
732    clk_add(&jz_clk_high_speed_peripheral.clk);
733    clk_add(&jz_clk_low_speed_peripheral.clk);
734    clk_add(&jz_clk_ko);
735    clk_add(&jz_clk_ld);
736    clk_add(&jz_clk_lp.clk);
737    clk_add(&jz_clk_cim_mclk);
738    clk_add(&jz_clk_cim_pclk.clk);
739    clk_add(&jz_clk_i2s.clk);
740    clk_add(&jz_clk_mmc.clk);
741    clk_add(&jz_clk_uhc.clk);
742    clk_add(&jz_clk_udc);
743    clk_add(&jz_clk_uart0);
744    clk_add(&jz_clk_uart1);
745    clk_add(&jz_clk_dma);
746    clk_add(&jz_clk_ipu);
747    clk_add(&jz_clk_adc);
748    clk_add(&jz_clk_i2c);
749    clk_add(&jz_clk_rtc.clk);
750}
751
752int jz_init_clocks(unsigned long ext_rate)
753{
754    uint32_t val;
755
756    jz_clock_base = ioremap(0x10000000, 0x100);
757    if (!jz_clock_base)
758        return -EBUSY;
759
760    jz_clk_ext.rate = ext_rate;
761
762    val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
763
764    if (val & JZ_CLOCK_SPI_SRC_PLL)
765        jz_clk_spi.clk.parent = &jz_clk_pll_half;
766
767    val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
768
769    if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
770        jz_clk_i2s.clk.parent = &jz_clk_pll_half;
771
772    if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
773        jz_clk_udc.parent = &jz_clk_pll_half;
774
775    clk_register_clks();
776
777    return 0;
778}
779EXPORT_SYMBOL_GPL(jz_init_clocks);
arch/mips/jz4740/cpufreq.c
1/*
2 * linux/arch/mips/jz4740/cpufreq.c
3 *
4 * cpufreq driver for JZ4740
5 *
6 * Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
7 * Author: <lhhuang@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17
18#include <linux/cpufreq.h>
19
20#include <asm/mach-jz4740/regs.h>
21#include <asm/mach-jz4740/clock.h>
22#include <asm/processor.h>
23
24#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
25                        "cpufreq-jz4740", msg)
26
27#undef CHANGE_PLL
28
29#define PLL_UNCHANGED 0
30#define PLL_GOES_UP 1
31#define PLL_GOES_DOWN 2
32
33#define PLL_WAIT_500NS (500*(__cpm_get_cclk()/1000000000))
34
35/* Saved the boot-time parameters */
36static struct {
37    /* SDRAM parameters */
38    unsigned int mclk; /* memory clock, KHz */
39    unsigned int tras; /* RAS pulse width, cycles of mclk */
40    unsigned int rcd; /* RAS to CAS Delay, cycles of mclk */
41    unsigned int tpc; /* RAS Precharge time, cycles of mclk */
42    unsigned int trwl; /* Write Precharge Time, cycles of mclk */
43    unsigned int trc; /* RAS Cycle Time, cycles of mclk */
44    unsigned int rtcor; /* Refresh Time Constant */
45    unsigned int sdram_initialized;
46
47    /* LCD parameters */
48    unsigned int lcd_clk; /* LCD clock, Hz */
49    unsigned int lcdpix_clk; /* LCD Pixel clock, Hz */
50    unsigned int lcd_clks_initialized;
51} boot_config;
52
53struct jz4740_freq_percpu_info {
54    struct cpufreq_frequency_table table[7];
55};
56
57static struct jz4740_freq_percpu_info jz4740_freq_table;
58
59/*
60 * This contains the registers value for an operating point.
61 * If only part of a register needs to change then there is
62 * a mask value for that register.
63 * When going to a new operating point the current register
64 * value is ANDed with the ~mask and ORed with the new value.
65 */
66struct dpm_regs {
67    u32 cpccr; /* Clock Freq Control Register */
68    u32 cpccr_mask; /* Clock Freq Control Register mask */
69    u32 cppcr; /* PLL1 Control Register */
70    u32 cppcr_mask; /* PLL1 Control Register mask */
71    u32 pll_up_flag; /* New PLL freq is higher than current or not */
72};
73
74static void
75jz_init_boot_config(void)
76{
77    if (!boot_config.lcd_clks_initialized) {
78        /* the first time to scale pll */
79        boot_config.lcd_clk = __cpm_get_lcdclk();
80        boot_config.lcdpix_clk = __cpm_get_pixclk();
81        boot_config.lcd_clks_initialized = 1;
82    }
83
84    if (!boot_config.sdram_initialized) {
85        /* the first time to scale frequencies */
86        unsigned int dmcr, rtcor;
87        unsigned int tras, rcd, tpc, trwl, trc;
88
89        dmcr = REG_EMC_DMCR;
90        rtcor = REG_EMC_RTCOR;
91
92        tras = (dmcr >> 13) & 0x7;
93        rcd = (dmcr >> 11) & 0x3;
94        tpc = (dmcr >> 8) & 0x7;
95        trwl = (dmcr >> 5) & 0x3;
96        trc = (dmcr >> 2) & 0x7;
97
98        boot_config.mclk = __cpm_get_mclk() / 1000;
99        boot_config.tras = tras + 4;
100        boot_config.rcd = rcd + 1;
101        boot_config.tpc = tpc + 1;
102        boot_config.trwl = trwl + 1;
103        boot_config.trc = trc * 2 + 1;
104        boot_config.rtcor = rtcor;
105
106        boot_config.sdram_initialized = 1;
107    }
108}
109
110static void jz_update_dram_rtcor(unsigned int new_mclk)
111{
112    unsigned int rtcor;
113
114    new_mclk /= 1000;
115    rtcor = boot_config.rtcor * new_mclk / boot_config.mclk;
116    rtcor--;
117
118    if (rtcor < 1) rtcor = 1;
119    if (rtcor > 255) rtcor = 255;
120
121    REG_EMC_RTCOR = rtcor;
122    REG_EMC_RTCNT = rtcor;
123}
124
125static void jz_update_dram_dmcr(unsigned int new_mclk)
126{
127    unsigned int dmcr;
128    unsigned int tras, rcd, tpc, trwl, trc;
129    unsigned int valid_time, new_time; /* ns */
130
131    new_mclk /= 1000;
132    tras = boot_config.tras * new_mclk / boot_config.mclk;
133    rcd = boot_config.rcd * new_mclk / boot_config.mclk;
134    tpc = boot_config.tpc * new_mclk / boot_config.mclk;
135    trwl = boot_config.trwl * new_mclk / boot_config.mclk;
136    trc = boot_config.trc * new_mclk / boot_config.mclk;
137
138    /* Validation checking */
139    valid_time = (boot_config.tras * 1000000) / boot_config.mclk;
140    new_time = (tras * 1000000) / new_mclk;
141    if (new_time < valid_time) tras += 1;
142
143    valid_time = (boot_config.rcd * 1000000) / boot_config.mclk;
144    new_time = (rcd * 1000000) / new_mclk;
145    if (new_time < valid_time) rcd += 1;
146
147    valid_time = (boot_config.tpc * 1000000) / boot_config.mclk;
148    new_time = (tpc * 1000000) / new_mclk;
149    if (new_time < valid_time) tpc += 1;
150
151    valid_time = (boot_config.trwl * 1000000) / boot_config.mclk;
152    new_time = (trwl * 1000000) / new_mclk;
153    if (new_time < valid_time) trwl += 1;
154
155    valid_time = (boot_config.trc * 1000000) / boot_config.mclk;
156    new_time = (trc * 1000000) / new_mclk;
157    if (new_time < valid_time) trc += 2;
158
159    tras = (tras < 4) ? 4: tras;
160    tras = (tras > 11) ? 11: tras;
161    tras -= 4;
162
163    rcd = (rcd < 1) ? 1: rcd;
164    rcd = (rcd > 4) ? 4: rcd;
165    rcd -= 1;
166
167    tpc = (tpc < 1) ? 1: tpc;
168    tpc = (tpc > 8) ? 8: tpc;
169    tpc -= 1;
170
171    trwl = (trwl < 1) ? 1: trwl;
172    trwl = (trwl > 4) ? 4: trwl;
173    trwl -= 1;
174
175    trc = (trc < 1) ? 1: trc;
176    trc = (trc > 15) ? 15: trc;
177    trc /= 2;
178
179    dmcr = REG_EMC_DMCR;
180
181    dmcr &= ~(EMC_DMCR_TRAS_MASK | EMC_DMCR_RCD_MASK | EMC_DMCR_TPC_MASK | EMC_DMCR_TRWL_MASK | EMC_DMCR_TRC_MASK);
182    dmcr |= ((tras << EMC_DMCR_TRAS_BIT) | (rcd << EMC_DMCR_RCD_BIT) | (tpc << EMC_DMCR_TPC_BIT) | (trwl << EMC_DMCR_TRWL_BIT) | (trc << EMC_DMCR_TRC_BIT));
183
184    REG_EMC_DMCR = dmcr;
185}
186
187static void jz_update_dram_prev(unsigned int cur_mclk, unsigned int new_mclk)
188{
189    /* No risk, no fun: run with interrupts on! */
190    if (new_mclk > cur_mclk) {
191        /* We're going FASTER, so first update TRAS, RCD, TPC, TRWL
192         * and TRC of DMCR before changing the frequency.
193         */
194        jz_update_dram_dmcr(new_mclk);
195    } else {
196        /* We're going SLOWER: first update RTCOR value
197         * before changing the frequency.
198         */
199        jz_update_dram_rtcor(new_mclk);
200    }
201}
202
203static void jz_update_dram_post(unsigned int cur_mclk, unsigned int new_mclk)
204{
205    /* No risk, no fun: run with interrupts on! */
206    if (new_mclk > cur_mclk) {
207        /* We're going FASTER, so update RTCOR
208         * after changing the frequency
209         */
210        jz_update_dram_rtcor(new_mclk);
211    } else {
212        /* We're going SLOWER: so update TRAS, RCD, TPC, TRWL
213         * and TRC of DMCR after changing the frequency.
214         */
215        jz_update_dram_dmcr(new_mclk);
216    }
217}
218
219static void jz_scale_divisors(struct dpm_regs *regs)
220{
221    unsigned int cpccr;
222    unsigned int cur_mclk, new_mclk;
223    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
224    unsigned int tmp = 0, wait = PLL_WAIT_500NS;
225
226    cpccr = REG_CPM_CPCCR;
227    cpccr &= ~((unsigned long)regs->cpccr_mask);
228    cpccr |= regs->cpccr;
229    cpccr |= CPM_CPCCR_CE; /* update immediately */
230
231    cur_mclk = __cpm_get_mclk();
232    new_mclk = __cpm_get_pllout() / div[(cpccr & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT];
233
234    /* Update some DRAM parameters before changing frequency */
235    jz_update_dram_prev(cur_mclk, new_mclk);
236
237    /* update register to change the clocks.
238     * align this code to a cache line.
239     */
240    __asm__ __volatile__(
241        ".set noreorder\n\t"
242        ".align 5\n"
243        "sw %1,0(%0)\n\t"
244        "li %3,0\n\t"
245        "1:\n\t"
246        "bne %3,%2,1b\n\t"
247        "addi %3, 1\n\t"
248        "nop\n\t"
249        "nop\n\t"
250        "nop\n\t"
251        "nop\n\t"
252        ".set reorder\n\t"
253        :
254        : "r" (CPM_CPCCR), "r" (cpccr), "r" (wait), "r" (tmp));
255
256    /* Update some other DRAM parameters after changing frequency */
257    jz_update_dram_post(cur_mclk, new_mclk);
258}
259
260#ifdef CHANGE_PLL
261/* Maintain the LCD clock and pixel clock */
262static void jz_scale_lcd_divisors(struct dpm_regs *regs)
263{
264    unsigned int new_pll, new_lcd_div, new_lcdpix_div;
265    unsigned int cpccr;
266    unsigned int tmp = 0, wait = PLL_WAIT_500NS;
267
268    if (!boot_config.lcd_clks_initialized) return;
269
270    new_pll = __cpm_get_pllout();
271    new_lcd_div = new_pll / boot_config.lcd_clk;
272    new_lcdpix_div = new_pll / boot_config.lcdpix_clk;
273
274    if (new_lcd_div < 1)
275        new_lcd_div = 1;
276    if (new_lcd_div > 16)
277        new_lcd_div = 16;
278
279    if (new_lcdpix_div < 1)
280        new_lcdpix_div = 1;
281    if (new_lcdpix_div > 512)
282        new_lcdpix_div = 512;
283
284// REG_CPM_CPCCR2 = new_lcdpix_div - 1;
285
286    cpccr = REG_CPM_CPCCR;
287    cpccr &= ~CPM_CPCCR_LDIV_MASK;
288    cpccr |= ((new_lcd_div - 1) << CPM_CPCCR_LDIV_BIT);
289    cpccr |= CPM_CPCCR_CE; /* update immediately */
290
291    /* update register to change the clocks.
292     * align this code to a cache line.
293     */
294    __asm__ __volatile__(
295        ".set noreorder\n\t"
296        ".align 5\n"
297        "sw %1,0(%0)\n\t"
298        "li %3,0\n\t"
299        "1:\n\t"
300        "bne %3,%2,1b\n\t"
301        "addi %3, 1\n\t"
302        "nop\n\t"
303        "nop\n\t"
304        "nop\n\t"
305        "nop\n\t"
306        ".set reorder\n\t"
307        :
308        : "r" (CPM_CPCCR), "r" (cpccr), "r" (wait), "r" (tmp));
309}
310
311static void jz_scale_pll(struct dpm_regs *regs)
312{
313    unsigned int cppcr;
314    unsigned int cur_mclk, new_mclk, new_pll;
315    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
316    int od[] = {1, 2, 2, 4};
317
318    cppcr = REG_CPM_CPPCR;
319    cppcr &= ~(regs->cppcr_mask | CPM_CPPCR_PLLS | CPM_CPPCR_PLLEN | CPM_CPPCR_PLLST_MASK);
320    regs->cppcr &= ~CPM_CPPCR_PLLEN;
321    cppcr |= (regs->cppcr | 0xff);
322
323    /* Update some DRAM parameters before changing frequency */
324    new_pll = JZ_EXTAL * ((cppcr>>23)+2) / ((((cppcr>>18)&0x1f)+2) * od[(cppcr>>16)&0x03]);
325    cur_mclk = __cpm_get_mclk();
326    new_mclk = new_pll / div[(REG_CPM_CPCCR>>CPM_CPCCR_MDIV_BIT) & 0xf];
327
328    /*
329     * Update some SDRAM parameters
330     */
331    jz_update_dram_prev(cur_mclk, new_mclk);
332
333    /*
334     * Update PLL, align code to cache line.
335     */
336    cppcr |= CPM_CPPCR_PLLEN;
337    __asm__ __volatile__(
338        ".set noreorder\n\t"
339        ".align 5\n"
340        "sw %1,0(%0)\n\t"
341        "nop\n\t"
342        "nop\n\t"
343        "nop\n\t"
344        "nop\n\t"
345        "nop\n\t"
346        "nop\n\t"
347        "nop\n\t"
348        ".set reorder\n\t"
349        :
350        : "r" (CPM_CPPCR), "r" (cppcr));
351
352    /* Update some other DRAM parameters after changing frequency */
353    jz_update_dram_post(cur_mclk, new_mclk);
354}
355#endif
356
357static void jz4740_transition(struct dpm_regs *regs)
358{
359    /*
360     * Get and save some boot-time conditions.
361     */
362    jz_init_boot_config();
363
364#ifdef CHANGE_PLL
365    /*
366     * Disable LCD before scaling pll.
367     * LCD and LCD pixel clocks should not be changed even if the PLL
368     * output frequency has been changed.
369     */
370    REG_LCD_CTRL &= ~LCD_CTRL_ENA;
371
372    /*
373     * Stop module clocks before scaling PLL
374     */
375    __cpm_stop_eth();
376    __cpm_stop_aic(1);
377    __cpm_stop_aic(2);
378#endif
379
380    /* ... add more as necessary */
381
382    if (regs->pll_up_flag == PLL_GOES_UP) {
383        /* the pll frequency is going up, so change dividors first */
384        jz_scale_divisors(regs);
385#ifdef CHANGE_PLL
386        jz_scale_pll(regs);
387#endif
388    }
389    else if (regs->pll_up_flag == PLL_GOES_DOWN) {
390        /* the pll frequency is going down, so change pll first */
391#ifdef CHANGE_PLL
392        jz_scale_pll(regs);
393#endif
394        jz_scale_divisors(regs);
395    }
396    else {
397        /* the pll frequency is unchanged, so change divisors only */
398        jz_scale_divisors(regs);
399    }
400
401#ifdef CHANGE_PLL
402    /*
403     * Restart module clocks before scaling PLL
404     */
405    __cpm_start_eth();
406    __cpm_start_aic(1);
407    __cpm_start_aic(2);
408
409    /* ... add more as necessary */
410
411    /* Scale the LCD divisors after scaling pll */
412    if (regs->pll_up_flag != PLL_UNCHANGED) {
413        jz_scale_lcd_divisors(regs);
414    }
415
416    /* Enable LCD controller */
417    REG_LCD_CTRL &= ~LCD_CTRL_DIS;
418    REG_LCD_CTRL |= LCD_CTRL_ENA;
419#endif
420}
421
422extern unsigned int idle_times;
423static unsigned int jz4740_freq_get(unsigned int cpu)
424{
425    return (__cpm_get_cclk() / 1000);
426}
427
428static unsigned int index_to_divisor(unsigned int index, struct dpm_regs *regs)
429{
430    int n2FR[33] = {
431        0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
432        7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
433        9
434    };
435    int div[4] = {1, 2, 2, 2}; /* divisors of I:S:P:M */
436    unsigned int div_of_cclk, new_freq, i;
437
438    regs->pll_up_flag = PLL_UNCHANGED;
439    regs->cpccr_mask = CPM_CPCCR_CDIV_MASK | CPM_CPCCR_HDIV_MASK | CPM_CPCCR_PDIV_MASK | CPM_CPCCR_MDIV_MASK;
440
441    new_freq = jz4740_freq_table.table[index].frequency;
442
443    do {
444        div_of_cclk = __cpm_get_pllout() / (1000 * new_freq);
445    } while (div_of_cclk==0);
446
447    if(div_of_cclk == 1 || div_of_cclk == 2 || div_of_cclk == 4) {
448        for(i = 1; i<4; i++) {
449            div[i] = 3;
450        }
451    } else {
452        for(i = 1; i<4; i++) {
453            div[i] = 2;
454        }
455    }
456
457    for(i = 0; i<4; i++) {
458        div[i] *= div_of_cclk;
459    }
460
461    dprintk("divisors of I:S:P:M = %d:%d:%d:%d\n", div[0], div[1], div[2], div[3]);
462
463    regs->cpccr =
464        (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
465        (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
466        (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
467        (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT);
468
469    return div_of_cclk;
470}
471
472static void jz4740_set_cpu_divider_index(unsigned int cpu, unsigned int index)
473{
474    unsigned long divisor, old_divisor;
475    struct cpufreq_freqs freqs;
476    struct dpm_regs regs;
477
478    old_divisor = __cpm_get_pllout() / __cpm_get_cclk();
479    divisor = index_to_divisor(index, &regs);
480
481    freqs.old = __cpm_get_cclk() / 1000;
482    freqs.new = __cpm_get_pllout() / (1000 * divisor);
483    freqs.cpu = cpu;
484
485    cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
486
487    if (old_divisor != divisor)
488        jz4740_transition(&regs);
489
490    cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
491}
492
493static int jz4740_freq_target(struct cpufreq_policy *policy,
494              unsigned int target_freq,
495              unsigned int relation)
496{
497    unsigned int new_index = 0;
498
499    if (cpufreq_frequency_table_target(policy,
500                       &jz4740_freq_table.table[0],
501                       target_freq, relation, &new_index))
502        return -EINVAL;
503
504    jz4740_set_cpu_divider_index(policy->cpu, new_index);
505
506    dprintk("new frequency is %d KHz (REG_CPM_CPCCR:0x%x)\n", __cpm_get_cclk() / 1000, REG_CPM_CPCCR);
507
508    return 0;
509}
510
511static int jz4740_freq_verify(struct cpufreq_policy *policy)
512{
513    return cpufreq_frequency_table_verify(policy,
514                          &jz4740_freq_table.table[0]);
515}
516
517static int __init jz4740_cpufreq_driver_init(struct cpufreq_policy *policy)
518{
519
520    struct cpufreq_frequency_table *table = &jz4740_freq_table.table[0];
521    unsigned int MAX_FREQ;
522
523    dprintk(KERN_INFO "Jz4740 cpufreq driver\n");
524
525    if (policy->cpu != 0)
526        return -EINVAL;
527
528    policy->cur = MAX_FREQ = __cpm_get_cclk() / 1000; /* in kHz. Current and max frequency is determined by u-boot */
529    policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
530
531    policy->cpuinfo.min_freq = MAX_FREQ/8;
532    policy->cpuinfo.max_freq = MAX_FREQ;
533    policy->cpuinfo.transition_latency = 100000; /* in 10^(-9) s = nanoseconds */
534
535    table[0].index = 0;
536    table[0].frequency = MAX_FREQ/8;
537    table[1].index = 1;
538    table[1].frequency = MAX_FREQ/6;
539    table[2].index = 2;
540    table[2].frequency = MAX_FREQ/4;
541    table[3].index = 3;
542    table[3].frequency = MAX_FREQ/3;
543    table[4].index = 4;
544    table[4].frequency = MAX_FREQ/2;
545    table[5].index = 5;
546    table[5].frequency = MAX_FREQ;
547    table[6].index = 6;
548    table[6].frequency = CPUFREQ_TABLE_END;
549
550#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
551    cpufreq_frequency_table_get_attr(table, policy->cpu); /* for showing /sys/devices/system/cpu/cpuX/cpufreq/stats/ */
552#endif
553
554    return cpufreq_frequency_table_cpuinfo(policy, table);
555}
556
557static struct cpufreq_driver cpufreq_jz4740_driver = {
558// .flags = CPUFREQ_STICKY,
559    .init = jz4740_cpufreq_driver_init,
560    .verify = jz4740_freq_verify,
561    .target = jz4740_freq_target,
562    .get = jz4740_freq_get,
563    .name = "jz4740",
564};
565
566static int __init jz4740_cpufreq_init(void)
567{
568    return cpufreq_register_driver(&cpufreq_jz4740_driver);
569}
570
571static void __exit jz4740_cpufreq_exit(void)
572{
573        cpufreq_unregister_driver(&cpufreq_jz4740_driver);
574}
575
576module_init(jz4740_cpufreq_init);
577module_exit(jz4740_cpufreq_exit);
578
579MODULE_AUTHOR("Regen <lhhuang@ingenic.cn>");
580MODULE_DESCRIPTION("cpufreq driver for Jz4740");
581MODULE_LICENSE("GPL");
582
arch/mips/jz4740/dma.c
1/*
2 * linux/arch/mips/jz4740/dma.c
3 *
4 * Support functions for the JZ4740 internal DMA channels.
5 * No-descriptor transfer only.
6 * Descriptor transfer should also call jz_request_dma() to get a free
7 * channel and call jz_free_dma() to free the channel. And driver should
8 * build the DMA descriptor and setup the DMA channel by itself.
9 *
10 * Copyright (C) 2006 Ingenic Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/sched.h>
23#include <linux/spinlock.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26
27#include <asm/system.h>
28#include <asm/addrspace.h>
29#include <asm/mach-jz4740/regs.h>
30#include <asm/mach-jz4740/ops.h>
31#include <asm/mach-jz4740/dma.h>
32
33#define JZ_REG_DMA_SRC_ADDR(x) ((x) * 0x20 + 0x00)
34#define JZ_REG_DMA_DEST_ADDR(x) ((x) * 0x20 + 0x04)
35#define JZ_REG_DMA_COUNT(x) ((x) * 0x20 + 0x08)
36#define JZ_REG_DMA_TYPE(x) ((x) * 0x20 + 0x0c)
37#define JZ_REG_DMA_STATUS(x) ((x) * 0x20 + 0x10)
38#define JZ_REG_DMA_CMD(x) ((x) * 0x20 + 0x14)
39#define JZ_REG_DMA_DESC_ADDR(x) ((x) * 0x20 + 0x18)
40#define JZ_REG_DMA_CTRL 0x300
41#define JZ_REG_DMA_IRQ 0x304
42#define JZ_REG_DMA_DOORBELL 0x308
43#define JZ_REG_DMA_DOORBELL_SET 0x30C
44
45#define JZ_DMA_STATUS_NO_DESC BIT(31)
46#define JZ_DMA_STATUS_CDOA_MASK (0xff << 16)
47#define JZ_DMA_STATUS_INV_DESC BIT(6)
48#define JZ_DMA_STATUS_ADDR_ERROR BIT(4)
49#define JZ_DMA_STATUS_TERMINATE_TRANSFER BIT(3)
50#define JZ_DMA_STATUS_HALT BIT(2)
51#define JZ_DMA_STATUS_CT BIT(1)
52#define JZ_DMA_STATUS_ENABLE BIT(0)
53
54#define JZ_DMA_CMD_SAI BIT(23)
55#define JZ_DMA_CMD_DAI BIT(22)
56#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
57#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
58#define JZ_DMA_CMD_DEST_WIDTH_MASK (0x3 << 12)
59#define JZ_DMA_CMD_TRANSFER_SIZE_MASK (0x7 << 8)
60#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
61#define JZ_DMA_CMD_VALID BIT(4)
62#define JZ_DMA_CMD_VALID_MODE BIT(3)
63#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
64#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
65#define JZ_DMA_CMD_LINK BIT(0)
66
67
68static void __iomem *jz_dma_base;
69static spinlock_t jz_dma_lock;
70
71static inline uint32_t jz_dma_read(size_t reg)
72{
73    return readl(jz_dma_base + reg);
74}
75
76static inline void jz_dma_write(size_t reg, uint32_t val)
77{
78    writel(val, jz_dma_base + reg);
79}
80
81
82
83/*
84 * A note on resource allocation:
85 *
86 * All drivers needing DMA channels, should allocate and release them
87 * through the public routines `jz_request_dma()' and `jz_free_dma()'.
88 *
89 * In order to avoid problems, all processes should allocate resources in
90 * the same sequence and release them in the reverse order.
91 *
92 * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
93 * When releasing them, first release the IRQ, then release the DMA. The
94 * main reason for this order is that, if you are requesting the DMA buffer
95 * done interrupt, you won't know the irq number until the DMA channel is
96 * returned from jz_request_dma().
97 */
98
99struct jz_dma_chan jz_dma_table[MAX_DMA_NUM] = {
100    {dev_id:-1,},
101    {dev_id:-1,},
102    {dev_id:-1,},
103    {dev_id:-1,},
104    {dev_id:-1,},
105    {dev_id:-1,},
106};
107
108// Device FIFO addresses and default DMA modes
109static const struct {
110    unsigned int fifo_addr;
111    unsigned int dma_mode;
112    unsigned int dma_source;
113} dma_dev_table[DMA_ID_MAX] = {
114    {CPHYSADDR(UART0_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART0OUT},
115    {CPHYSADDR(UART0_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART0IN},
116    {CPHYSADDR(SSI_DR), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSIOUT},
117    {CPHYSADDR(SSI_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSIIN},
118    {CPHYSADDR(AIC_DR), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
119    {CPHYSADDR(AIC_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_AICIN},
120    {CPHYSADDR(MSC_TXFIFO), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSCOUT},
121    {CPHYSADDR(MSC_RXFIFO), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSCIN},
122    {0, DMA_AUTOINIT, DMAC_DRSR_RS_TCU},
123    {0, DMA_AUTOINIT, DMAC_DRSR_RS_AUTO},
124    {},
125};
126
127
128int jz_dma_read_proc(char *buf, char **start, off_t fpos,
129             int length, int *eof, void *data)
130{
131    int i, len = 0;
132    struct jz_dma_chan *chan;
133
134    for (i = 0; i < MAX_DMA_NUM; i++) {
135        if ((chan = get_dma_chan(i)) != NULL) {
136            len += sprintf(buf + len, "%2d: %s\n",
137                       i, chan->dev_str);
138        }
139    }
140
141    if (fpos >= len) {
142        *start = buf;
143        *eof = 1;
144        return 0;
145    }
146    *start = buf + fpos;
147    if ((len -= fpos) > length)
148        return length;
149    *eof = 1;
150    return len;
151}
152
153
154void dump_jz_dma_channel(unsigned int dmanr)
155{
156    struct jz_dma_chan *chan;
157
158    if (dmanr > MAX_DMA_NUM)
159        return;
160    chan = &jz_dma_table[dmanr];
161
162    printk("DMA%d Registers:\n", dmanr);
163    printk(" DMACR = 0x%08x\n", REG_DMAC_DMACR);
164    printk(" DSAR = 0x%08x\n", REG_DMAC_DSAR(dmanr));
165    printk(" DTAR = 0x%08x\n", REG_DMAC_DTAR(dmanr));
166    printk(" DTCR = 0x%08x\n", REG_DMAC_DTCR(dmanr));
167    printk(" DRSR = 0x%08x\n", REG_DMAC_DRSR(dmanr));
168    printk(" DCCSR = 0x%08x\n", REG_DMAC_DCCSR(dmanr));
169    printk(" DCMD = 0x%08x\n", REG_DMAC_DCMD(dmanr));
170    printk(" DDA = 0x%08x\n", REG_DMAC_DDA(dmanr));
171    printk(" DMADBR = 0x%08x\n", REG_DMAC_DMADBR);
172}
173
174
175/**
176 * jz_request_dma - dynamically allcate an idle DMA channel to return
177 * @dev_id: the specified dma device id or DMA_ID_RAW_SET
178 * @dev_str: the specified dma device string name
179 * @irqhandler: the irq handler, or NULL
180 * @irqflags: the irq handler flags
181 * @irq_dev_id: the irq handler device id for shared irq
182 *
183 * Finds a free channel, and binds the requested device to it.
184 * Returns the allocated channel number, or negative on error.
185 * Requests the DMA done IRQ if irqhandler != NULL.
186 *
187*/
188/*int jz_request_dma(int dev_id, const char *dev_str,
189           void (*irqhandler)(int, void *, struct pt_regs *),
190           unsigned long irqflags,
191           void *irq_dev_id)
192*/
193
194int jz_request_dma(int dev_id, const char *dev_str,
195           irqreturn_t (*irqhandler)(int, void *),
196           unsigned long irqflags,
197           void *irq_dev_id)
198{
199    struct jz_dma_chan *chan;
200    int i, ret;
201
202    if (dev_id < 0 || dev_id >= DMA_ID_MAX)
203        return -EINVAL;
204
205    for (i = 0; i < MAX_DMA_NUM; i++) {
206        if (jz_dma_table[i].dev_id < 0)
207            break;
208    }
209    if (i == MAX_DMA_NUM) /* no free channel */
210        return -ENODEV;
211
212    /* we got a free channel */
213    chan = &jz_dma_table[i];
214
215    if (irqhandler) {
216        chan->irq = JZ_IRQ_DMA(i); // allocate irq number
217        chan->irq_dev = irq_dev_id;
218        if ((ret = request_irq(chan->irq, irqhandler, irqflags,
219                       dev_str, chan->irq_dev))) {
220            chan->irq = -1;
221            chan->irq_dev = NULL;
222            return ret;
223        }
224    } else {
225        chan->irq = -1;
226        chan->irq_dev = NULL;
227    }
228
229    // fill it in
230    chan->io = i;
231    chan->dev_id = dev_id;
232    chan->dev_str = dev_str;
233    chan->fifo_addr = dma_dev_table[dev_id].fifo_addr;
234    chan->mode = dma_dev_table[dev_id].dma_mode;
235    chan->source = dma_dev_table[dev_id].dma_source;
236
237    return i;
238}
239
240void jz_free_dma(unsigned int dmanr)
241{
242    struct jz_dma_chan *chan = get_dma_chan(dmanr);
243
244    if (!chan) {
245        printk("Trying to free DMA%d\n", dmanr);
246        return;
247    }
248
249    disable_dma(dmanr);
250    if (chan->irq)
251        free_irq(chan->irq, chan->irq_dev);
252
253    chan->irq = -1;
254    chan->irq_dev = NULL;
255    chan->dev_id = -1;
256}
257
258void jz_set_dma_dest_width(int dmanr, int nbit)
259{
260    struct jz_dma_chan *chan = get_dma_chan(dmanr);
261
262    if (!chan)
263               return;
264
265    chan->mode &= ~DMAC_DCMD_DWDH_MASK;
266    switch (nbit) {
267    case 8:
268        chan->mode |= DMAC_DCMD_DWDH_8;
269        break;
270    case 16:
271        chan->mode |= DMAC_DCMD_DWDH_16;
272        break;
273    case 32:
274        chan->mode |= DMAC_DCMD_DWDH_32;
275        break;
276    }
277}
278
279void jz_set_dma_src_width(int dmanr, int nbit)
280{
281    struct jz_dma_chan *chan = get_dma_chan(dmanr);
282
283    if (!chan)
284               return;
285
286    chan->mode &= ~DMAC_DCMD_SWDH_MASK;
287    switch (nbit) {
288    case 8:
289        chan->mode |= DMAC_DCMD_SWDH_8;
290        break;
291    case 16:
292        chan->mode |= DMAC_DCMD_SWDH_16;
293        break;
294    case 32:
295        chan->mode |= DMAC_DCMD_SWDH_32;
296        break;
297    }
298}
299
300void jz_set_dma_block_size(int dmanr, int nbyte)
301{
302    struct jz_dma_chan *chan = get_dma_chan(dmanr);
303
304    if (!chan)
305        return;
306
307    chan->mode &= ~DMAC_DCMD_DS_MASK;
308    switch (nbyte) {
309    case 1:
310        chan->mode |= DMAC_DCMD_DS_8BIT;
311        break;
312    case 2:
313        chan->mode |= DMAC_DCMD_DS_16BIT;
314        break;
315    case 4:
316        chan->mode |= DMAC_DCMD_DS_32BIT;
317        break;
318    case 16:
319        chan->mode |= DMAC_DCMD_DS_16BYTE;
320        break;
321    case 32:
322        chan->mode |= DMAC_DCMD_DS_32BYTE;
323        break;
324    }
325}
326
327unsigned int jz_get_dma_command(int dmanr)
328{
329    struct jz_dma_chan *chan = get_dma_chan(dmanr);
330    return chan->mode;
331}
332
333/**
334 * jz_set_dma_mode - do the raw settings for the specified DMA channel
335 * @dmanr: the specified DMA channel
336 * @mode: dma operate mode, DMA_MODE_READ or DMA_MODE_WRITE
337 * @dma_mode: dma raw mode
338 * @dma_source: dma raw request source
339 * @fifo_addr: dma raw device fifo address
340 *
341 * Ensure call jz_request_dma(DMA_ID_RAW_SET, ...) first, then call
342 * jz_set_dma_mode() rather than set_dma_mode() if you work with
343 * and external request dma device.
344 *
345 * NOTE: Don not dynamically allocate dma channel if one external request
346 * dma device will occupy this channel.
347*/
348int jz_set_dma_mode(unsigned int dmanr, unsigned int mode,
349            unsigned int dma_mode, unsigned int dma_source,
350            unsigned int fifo_addr)
351{
352    int dev_id, i;
353    struct jz_dma_chan *chan;
354
355    if (dmanr > MAX_DMA_NUM)
356        return -ENODEV;
357
358    for (i = 0; i < MAX_DMA_NUM; i++) {
359        if (jz_dma_table[i].dev_id < 0)
360            break;
361    }
362    if (i == MAX_DMA_NUM)
363        return -ENODEV;
364
365    chan = &jz_dma_table[dmanr];
366    dev_id = chan->dev_id;
367    if (dev_id > 0) {
368        printk(KERN_DEBUG "%s sets the allocated DMA channel %d!\n",
369               __FUNCTION__, dmanr);
370        return -ENODEV;
371    }
372
373    /* clone it from the dynamically allocated. */
374    if (i != dmanr) {
375        chan->irq = jz_dma_table[i].irq;
376        chan->irq_dev = jz_dma_table[i].irq_dev;
377        chan->dev_str = jz_dma_table[i].dev_str;
378        jz_dma_table[i].irq = 0;
379        jz_dma_table[i].irq_dev = NULL;
380        jz_dma_table[i].dev_id = -1;
381    }
382    chan->dev_id = DMA_ID_RAW_SET;
383    chan->io = dmanr;
384    chan->fifo_addr = fifo_addr;
385    chan->mode = dma_mode;
386    chan->source = dma_source;
387
388    set_dma_mode(dmanr, dma_mode);
389
390    return dmanr;
391}
392
393void enable_dma(unsigned int dmanr)
394{
395    struct jz_dma_chan *chan = get_dma_chan(dmanr);
396
397    if (!chan)
398        return;
399
400    REG_DMAC_DCCSR(dmanr) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
401    REG_DMAC_DCCSR(dmanr) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
402    __dmac_enable_channel(dmanr);
403    if (chan->irq)
404        __dmac_channel_enable_irq(dmanr);
405}
406
407#define DMA_DISABLE_POLL 0x10000
408
409void disable_dma(unsigned int dmanr)
410{
411    int i;
412    struct jz_dma_chan *chan = get_dma_chan(dmanr);
413
414    if (!chan)
415        return;
416
417    if (!__dmac_channel_enabled(dmanr))
418        return;
419
420    for (i = 0; i < DMA_DISABLE_POLL; i++)
421        if (__dmac_channel_transmit_end_detected(dmanr))
422            break;
423#if 0
424    if (i == DMA_DISABLE_POLL)
425        printk(KERN_INFO "disable_dma: poll expired!\n");
426#endif
427
428    __dmac_disable_channel(dmanr);
429    if (chan->irq)
430        __dmac_channel_disable_irq(dmanr);
431}
432
433/* Note: DMA_MODE_MASK is simulated by sw */
434void set_dma_mode(unsigned int dmanr, unsigned int mode)
435{
436    struct jz_dma_chan *chan = get_dma_chan(dmanr);
437
438    if (!chan)
439        return;
440
441    chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
442    mode &= DMA_MODE_MASK;
443    if (mode == DMA_MODE_READ) {
444        chan->mode |= DMAC_DCMD_DAI;
445        chan->mode &= ~DMAC_DCMD_SAI;
446    } else if (mode == DMA_MODE_WRITE) {
447        chan->mode |= DMAC_DCMD_SAI;
448        chan->mode &= ~DMAC_DCMD_DAI;
449    } else {
450        printk(KERN_DEBUG "set_dma_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
451    }
452    jz_dma_write(JZ_REG_DMA_CMD(chan->io), chan->mode & ~DMA_MODE_MASK);
453    jz_dma_write(JZ_REG_DMA_TYPE(chan->io), chan->source);
454}
455
456void set_dma_addr(unsigned int dmanr, unsigned int phyaddr)
457{
458    unsigned int mode;
459    struct jz_dma_chan *chan = get_dma_chan(dmanr);
460
461    if (!chan)
462        return;
463
464    mode = chan->mode & DMA_MODE_MASK;
465    if (mode == DMA_MODE_READ) {
466        jz_dma_write(JZ_REG_DMA_SRC_ADDR(chan->io), chan->fifo_addr);
467        jz_dma_write(JZ_REG_DMA_DEST_ADDR(chan->io), phyaddr);
468    } else if (mode == DMA_MODE_WRITE) {
469        jz_dma_write(JZ_REG_DMA_SRC_ADDR(chan->io), phyaddr);
470        jz_dma_write(JZ_REG_DMA_DEST_ADDR(chan->io), chan->fifo_addr);
471    } else
472        printk(KERN_DEBUG "Driver should call set_dma_mode() ahead set_dma_addr()!\n");
473}
474
475void set_dma_count(unsigned int dmanr, unsigned int bytecnt)
476{
477    struct jz_dma_chan *chan = get_dma_chan(dmanr);
478    int dma_ds[] = {4, 1, 2, 16, 32};
479    unsigned int ds;
480
481    if (!chan)
482               return;
483
484    ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
485
486    jz_dma_write(JZ_REG_DMA_COUNT(chan->io), bytecnt / dma_ds[ds]);
487}
488
489unsigned int get_dma_residue(unsigned int dmanr)
490{
491    unsigned int count, ds;
492    int dma_ds[] = {4, 1, 2, 16, 32};
493    struct jz_dma_chan *chan = get_dma_chan(dmanr);
494    if (!chan)
495        return 0;
496
497    ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
498    count = jz_dma_read(JZ_REG_DMA_COUNT(chan->io));
499    count = count * dma_ds[ds];
500
501    return count;
502}
503
504
505void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
506{
507    struct jz_dma_chan *chan = get_dma_chan(dmanr);
508
509    if (!chan)
510        return;
511
512    switch (audio_fmt) {
513    case 8:
514        /* SNDRV_PCM_FORMAT_S8 burst mode : 32BIT */
515        break;
516    case 16:
517        /* SNDRV_PCM_FORMAT_S16_LE burst mode : 16BYTE */
518        if (mode == DMA_MODE_READ) {
519            chan->mode = DMA_AIC_16BYTE_RX_CMD | DMA_MODE_READ;
520            chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
521            mode &= DMA_MODE_MASK;
522            chan->mode |= DMAC_DCMD_DAI;
523            chan->mode &= ~DMAC_DCMD_SAI;
524        } else if (mode == DMA_MODE_WRITE) {
525            chan->mode = DMA_AIC_16BYTE_TX_CMD | DMA_MODE_WRITE;
526            chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
527            mode &= DMA_MODE_MASK;
528            chan->mode |= DMAC_DCMD_SAI;
529            chan->mode &= ~DMAC_DCMD_DAI;
530        } else {
531            printk("alsa_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
532        }
533
534        jz_dma_write(JZ_REG_DMA_CMD(chan->io), chan->mode & ~DMA_MODE_MASK);
535        jz_dma_write(JZ_REG_DMA_TYPE(chan->io), chan->source);
536
537        break;
538    }
539}
540
541#undef JZ4740_DMAC_TEST_ENABLE
542
543#ifdef JZ4740_DMAC_TEST_ENABLE
544
545/*
546 * DMA test: external address <--> external address
547 */
548#define TEST_DMA_SIZE 16*1024
549
550static jz_dma_desc *dma_desc;
551
552static int dma_chan;
553static dma_addr_t dma_desc_phys_addr;
554static unsigned int dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr;
555
556static int dma_check_result(void *src, void *dst, int size)
557{
558    unsigned int addr1, addr2, i, err = 0;
559
560    addr1 = (unsigned int)src;
561    addr2 = (unsigned int)dst;
562
563    for (i = 0; i < size; i += 4) {
564        if (*(volatile unsigned int *)addr1 != *(volatile unsigned int *)addr2) {
565            err++;
566            printk("wrong data at 0x%08x: src 0x%08x dst 0x%08x\n", addr2, *(volatile unsigned int *)addr1, *(volatile unsigned int *)addr2);
567        }
568        addr1 += 4;
569        addr2 += 4;
570    }
571    printk("check DMA result err=%d\n", err);
572    return err;
573}
574
575static void jz4740_dma_irq(int irq, void *dev_id, struct pt_regs *regs)
576{
577    printk("jz4740_dma_irq %d\n", irq);
578
579    REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN; /* disable DMA */
580
581    if (__dmac_channel_transmit_halt_detected(dma_chan)) {
582        printk("DMA HALT\n");
583        __dmac_channel_clear_transmit_halt(dma_chan);
584    }
585
586    if (__dmac_channel_address_error_detected(dma_chan)) {
587        printk("DMA ADDR ERROR\n");
588        __dmac_channel_clear_address_error(dma_chan);
589    }
590
591    if (__dmac_channel_descriptor_invalid_detected(dma_chan)) {
592        printk("DMA DESC INVALID\n");
593        __dmac_channel_clear_descriptor_invalid(dma_chan);
594    }
595
596    if (__dmac_channel_count_terminated_detected(dma_chan)) {
597        printk("DMA CT\n");
598        __dmac_channel_clear_count_terminated(dma_chan);
599    }
600
601    if (__dmac_channel_transmit_end_detected(dma_chan)) {
602        printk("DMA TT\n");
603        __dmac_channel_clear_transmit_end(dma_chan);
604        dump_jz_dma_channel(dma_chan);
605        dma_check_result((void *)dma_src_addr, (void *)dma_dst_addr, TEST_DMA_SIZE);
606    }
607
608    /* free buffers */
609    printk("free DMA buffers\n");
610    free_pages(dma_src_addr, 2);
611    free_pages(dma_dst_addr, 2);
612
613    if (dma_desc)
614        free_pages((unsigned int)dma_desc, 0);
615
616    /* free dma */
617    jz_free_dma(dma_chan);
618}
619
620void dma_nodesc_test(void)
621{
622    unsigned int addr, i;
623
624    printk("dma_nodesc_test\n");
625
626    /* Request DMA channel and setup irq handler */
627    dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4740_dma_irq,
628                   SA_INTERRUPT, NULL);
629    if (dma_chan < 0) {
630        printk("Setup irq failed\n");
631        return;
632    }
633
634    printk("Requested DMA channel = %d\n", dma_chan);
635
636    /* Allocate DMA buffers */
637    dma_src_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
638    dma_dst_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
639
640    dma_src_phys_addr = CPHYSADDR(dma_src_addr);
641    dma_dst_phys_addr = CPHYSADDR(dma_dst_addr);
642
643    printk("Buffer addresses: 0x%08x 0x%08x 0x%08x 0x%08x\n",
644           dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr);
645
646    /* Prepare data for source buffer */
647    addr = (unsigned int)dma_src_addr;
648    for (i = 0; i < TEST_DMA_SIZE; i += 4) {
649        *(volatile unsigned int *)addr = addr;
650        addr += 4;
651    }
652    dma_cache_wback((unsigned long)dma_src_addr, TEST_DMA_SIZE);
653
654    /* Init target buffer */
655    memset((void *)dma_dst_addr, 0, TEST_DMA_SIZE);
656    dma_cache_wback((unsigned long)dma_dst_addr, TEST_DMA_SIZE);
657
658    /* Init DMA module */
659    printk("Starting DMA\n");
660    REG_DMAC_DMACR = 0;
661    REG_DMAC_DCCSR(dma_chan) = 0;
662    REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO;
663    REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr;
664    REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr;
665    REG_DMAC_DTCR(dma_chan) = 512;
666    REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TIE;
667    REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
668    REG_DMAC_DMACR = DMAC_DMACR_DMAE; /* global DMA enable bit */
669
670    printk("DMA started. IMR=%08x\n", REG_INTC_IMR);
671}
672
673void dma_desc_test(void)
674{
675    unsigned int next, addr, i;
676    static jz_dma_desc *desc;
677
678    printk("dma_desc_test\n");
679
680    /* Request DMA channel and setup irq handler */
681    dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4740_dma_irq,
682                  SA_INTERRUPT, NULL);
683    if (dma_chan < 0) {
684        printk("Setup irq failed\n");
685        return;
686    }
687
688    printk("Requested DMA channel = %d\n", dma_chan);
689
690    /* Allocate DMA buffers */
691    dma_src_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
692    dma_dst_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
693
694    dma_src_phys_addr = CPHYSADDR(dma_src_addr);
695    dma_dst_phys_addr = CPHYSADDR(dma_dst_addr);
696
697    printk("Buffer addresses: 0x%08x 0x%08x 0x%08x 0x%08x\n",
698           dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr);
699
700    /* Prepare data for source buffer */
701    addr = (unsigned int)dma_src_addr;
702    for (i = 0; i < TEST_DMA_SIZE; i += 4) {
703        *(volatile unsigned int *)addr = addr;
704        addr += 4;
705    }
706    dma_cache_wback((unsigned long)dma_src_addr, TEST_DMA_SIZE);
707
708    /* Init target buffer */
709    memset((void *)dma_dst_addr, 0, TEST_DMA_SIZE);
710    dma_cache_wback((unsigned long)dma_dst_addr, TEST_DMA_SIZE);
711
712    /* Allocate DMA descriptors */
713    dma_desc = (jz_dma_desc *)__get_free_pages(GFP_KERNEL, 0);
714    dma_desc_phys_addr = CPHYSADDR((unsigned long)dma_desc);
715
716    printk("DMA descriptor address: 0x%08x 0x%08x\n", (u32)dma_desc, dma_desc_phys_addr);
717
718    /* Setup DMA descriptors */
719    desc = dma_desc;
720    next = (dma_desc_phys_addr + (sizeof(jz_dma_desc))) >> 4;
721
722    desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TM | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
723    desc->dsadr = dma_src_phys_addr; /* DMA source address */
724    desc->dtadr = dma_dst_phys_addr; /* DMA target address */
725    desc->ddadr = (next << 24) + 128; /* size: 128*32 bytes = 4096 bytes */
726
727    desc++;
728    next = (dma_desc_phys_addr + 2*(sizeof(jz_dma_desc))) >> 4;
729
730    desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
731    desc->dsadr = dma_src_phys_addr + 4096; /* DMA source address */
732    desc->dtadr = dma_dst_phys_addr + 4096; /* DMA target address */
733    desc->ddadr = (next << 24) + 256; /* size: 256*16 bytes = 4096 bytes */
734
735    desc++;
736    next = (dma_desc_phys_addr + 3*(sizeof(jz_dma_desc))) >> 4;
737
738    desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
739    desc->dsadr = dma_src_phys_addr + 8192; /* DMA source address */
740    desc->dtadr = dma_dst_phys_addr + 8192; /* DMA target address */
741    desc->ddadr = (next << 24) + 256; /* size: 256*16 bytes = 4096 bytes */
742
743    desc++;
744    next = (dma_desc_phys_addr + 4*(sizeof(jz_dma_desc))) >> 4;
745
746    desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE;
747    desc->dsadr = dma_src_phys_addr + 12*1024; /* DMA source address */
748    desc->dtadr = dma_dst_phys_addr + 12*1024; /* DMA target address */
749    desc->ddadr = (next << 24) + 1024; /* size: 1024*4 bytes = 4096 bytes */
750
751    dma_cache_wback((unsigned long)dma_desc, 4*(sizeof(jz_dma_desc)));
752
753    /* Setup DMA descriptor address */
754    REG_DMAC_DDA(dma_chan) = dma_desc_phys_addr;
755
756    /* Setup request source */
757    REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO;
758
759    /* Setup DMA channel control/status register */
760    REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_EN; /* descriptor transfer, clear status, start channel */
761
762    /* Enable DMA */
763    REG_DMAC_DMACR = DMAC_DMACR_DMAE;
764
765    /* DMA doorbell set -- start DMA now ... */
766    REG_DMAC_DMADBSR = 1 << dma_chan;
767
768    printk("DMA started. IMR=%08x\n", REG_INTC_IMR);
769}
770
771#endif
772
773static void jz_dma_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
774{
775    int i;
776    uint32_t pending;
777
778    pending = jz_dma_read(JZ_REG_DMA_IRQ);
779
780    for (i = 0; i < 6; ++i) {
781        if (pending & BIT(i))
782            generic_handle_irq(JZ_IRQ_DMA(i));
783    }
784}
785
786#define IRQ_TO_DMA(irq) ((irq) - JZ_IRQ_DMA(0))
787
788static void dma_irq_unmask(unsigned int irq)
789{
790    unsigned long flags;
791    uint32_t mask;
792    unsigned int chan;
793
794    chan = IRQ_TO_DMA(irq);
795
796    spin_lock_irqsave(&jz_dma_lock, flags);
797
798    mask = jz_dma_read(JZ_REG_DMA_CMD(chan));
799    mask |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
800    jz_dma_write(JZ_REG_DMA_CMD(chan), mask);
801
802    spin_unlock_irqrestore(&jz_dma_lock, flags);
803}
804
805static void dma_irq_mask(unsigned int irq)
806{
807    unsigned long flags;
808    uint32_t mask;
809    unsigned int chan;
810
811    chan = IRQ_TO_DMA(irq);
812
813    spin_lock_irqsave(&jz_dma_lock, flags);
814
815    mask = jz_dma_read(JZ_REG_DMA_CMD(chan));
816    mask &= ~JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
817    jz_dma_write(JZ_REG_DMA_CMD(chan), mask);
818
819    spin_unlock_irqrestore(&jz_dma_lock, flags);
820}
821
822static void dma_irq_ack(unsigned int irq)
823{
824    unsigned long flags;
825    uint32_t pending;
826
827    spin_lock_irqsave(&jz_dma_lock, flags);
828
829    pending = jz_dma_read(JZ_REG_DMA_IRQ);
830    pending &= ~BIT(irq);
831    jz_dma_write(JZ_REG_DMA_IRQ, pending);
832
833    spin_unlock_irqrestore(&jz_dma_lock, flags);
834}
835
836static void dma_irq_end(unsigned int irq)
837{
838    if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
839        dma_irq_unmask(irq);
840    }
841}
842
843static struct irq_chip dma_irq_type = {
844    .name = "DMA",
845    .unmask = dma_irq_unmask,
846    .mask = dma_irq_mask,
847    .ack = dma_irq_ack,
848    .end = dma_irq_end,
849};
850
851static int jz_dma_init(void)
852{
853    int i;
854
855    jz_dma_base = ioremap(CPHYSADDR(DMAC_BASE), 0x400);
856
857    if (!jz_dma_base)
858        return -EBUSY;
859
860    spin_lock_init(&jz_dma_lock);
861
862    set_irq_chained_handler(JZ_IRQ_DMAC, jz_dma_irq_demux_handler);
863
864    for (i = 0; i < NUM_DMA; i++) {
865        dma_irq_mask(JZ_IRQ_DMA(i));
866        set_irq_chip_and_handler(JZ_IRQ_DMA(i), &dma_irq_type, handle_level_irq);
867    }
868
869    return 0;
870}
871arch_initcall(jz_dma_init);
872
873//EXPORT_SYMBOL_NOVERS(jz_dma_table);
874EXPORT_SYMBOL(jz_dma_table);
875EXPORT_SYMBOL(jz_request_dma);
876EXPORT_SYMBOL(jz_free_dma);
877EXPORT_SYMBOL(jz_set_dma_src_width);
878EXPORT_SYMBOL(jz_set_dma_dest_width);
879EXPORT_SYMBOL(jz_set_dma_block_size);
880EXPORT_SYMBOL(jz_set_dma_mode);
881EXPORT_SYMBOL(set_dma_mode);
882EXPORT_SYMBOL(jz_set_alsa_dma);
883EXPORT_SYMBOL(set_dma_addr);
884EXPORT_SYMBOL(set_dma_count);
885EXPORT_SYMBOL(get_dma_residue);
886EXPORT_SYMBOL(enable_dma);
887EXPORT_SYMBOL(disable_dma);
888EXPORT_SYMBOL(dump_jz_dma_channel);
arch/mips/jz4740/gpio.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ74xx platform GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/delay.h>
24#include <linux/irq.h>
25#include <linux/interrupt.h>
26#include <linux/bitops.h>
27
28#include <asm/mach-jz4740/regs.h>
29
30#define JZ_GPIO_BASE_A (32*0)
31#define JZ_GPIO_BASE_B (32*1)
32#define JZ_GPIO_BASE_C (32*2)
33#define JZ_GPIO_BASE_D (32*3)
34
35#define JZ_GPIO_NUM_A 32
36#define JZ_GPIO_NUM_B 32
37#define JZ_GPIO_NUM_C 31
38#define JZ_GPIO_NUM_D 32
39
40#define JZ_IRQ_GPIO_BASE_A JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_A
41#define JZ_IRQ_GPIO_BASE_B JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_B
42#define JZ_IRQ_GPIO_BASE_C JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_C
43#define JZ_IRQ_GPIO_BASE_D JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_D
44
45#define JZ_IRQ_GPIO_A(num) (num < JZ_GPIO_NUM_A ? JZ_IRQ_GPIO_BASE_A + num : -EINVAL)
46#define JZ_IRQ_GPIO_B(num) (num < JZ_GPIO_NUM_B ? JZ_IRQ_GPIO_BASE_B + num : -EINVAL)
47#define JZ_IRQ_GPIO_C(num) (num < JZ_GPIO_NUM_C ? JZ_IRQ_GPIO_BASE_C + num : -EINVAL)
48#define JZ_IRQ_GPIO_D(num) (num < JZ_GPIO_NUM_D ? JZ_IRQ_GPIO_BASE_D + num : -EINVAL)
49
50
51#define CHIP_TO_REG(chip, reg) (jz_gpio_base + (((chip)->base) << 3) + reg)
52#define CHIP_TO_PIN_REG(chip) CHIP_TO_REG(chip, 0x00)
53#define CHIP_TO_DATA_REG(chip) CHIP_TO_REG(chip, 0x10)
54#define CHIP_TO_DATA_SET_REG(chip) CHIP_TO_REG(chip, 0x14)
55#define CHIP_TO_DATA_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x18)
56#define CHIP_TO_PULL_REG(chip) CHIP_TO_REG(chip, 0x30)
57#define CHIP_TO_PULL_SET_REG(chip) CHIP_TO_REG(chip, 0x34)
58#define CHIP_TO_PULL_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x38)
59#define CHIP_TO_DATA_SELECT_REG(chip) CHIP_TO_REG(chip, 0x50)
60#define CHIP_TO_DATA_SELECT_SET_REG(chip) CHIP_TO_REG(chip, 0x54)
61#define CHIP_TO_DATA_SELECT_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x58)
62#define CHIP_TO_DIRECION_REG(chip) CHIP_TO_REG(chip, 0x60)
63#define CHIP_TO_DIRECTION_SET_REG(chip) CHIP_TO_REG(chip, 0x64)
64#define CHIP_TO_DIRECTION_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x68)
65
66#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
67
68#define GPIO_TO_REG(gpio, reg) (jz_gpio_base + ((gpio >> 5) << 8) + reg)
69#define GPIO_TO_MASK_REG(gpio) GPIO_TO_REG(gpio, 0x20)
70#define GPIO_TO_MASK_SET_REG(gpio) GPIO_TO_REG(gpio, 0x24)
71#define GPIO_TO_MASK_CLEAR_REG(gpio) GPIO_TO_REG(gpio, 0x28)
72#define GPIO_TO_PULL_REG(gpio) GPIO_TO_REG(gpio, 0x30)
73#define GPIO_TO_PULL_SET_REG(gpio) GPIO_TO_REG(gpio, 0x34)
74#define GPIO_TO_PULL_CLEAR_REG(gpio) GPIO_TO_REG(gpio, 0x38)
75#define GPIO_TO_FUNC_REG(gpio) GPIO_TO_REG(gpio, 0x40)
76#define GPIO_TO_FUNC_SET_REG(gpio) GPIO_TO_REG(gpio, 0x44)
77#define GPIO_TO_FUNC_CLEAR_REG(gpio) GPIO_TO_REG(gpio, 0x48)
78#define GPIO_TO_SEL_REG(gpio) GPIO_TO_REG(gpio, 0x50)
79#define GPIO_TO_SEL_SET_REG(gpio) GPIO_TO_REG(gpio, 0x54)
80#define GPIO_TO_SEL_CLEAR_REG(gpio) GPIO_TO_REG(gpio, 0x58)
81#define GPIO_TO_TRIGGER_REG(gpio) GPIO_TO_REG(gpio, 0x70)
82#define GPIO_TO_TRIGGER_SET_REG(gpio) GPIO_TO_REG(gpio, 0x74)
83#define GPIO_TO_TRIGGER_CLEAR_REG(gpio) GPIO_TO_REG(gpio, 0x78)
84
85
86
87static void __iomem *jz_gpio_base;
88static spinlock_t jz_gpio_lock;
89
90struct jz_gpio_chip {
91    unsigned int irq;
92    unsigned int irq_base;
93    uint32_t wakeup;
94    uint32_t saved[4];
95    struct gpio_chip gpio_chip;
96    struct irq_chip irq_chip;
97    uint32_t edge_trigger_both;
98};
99
100static struct jz_gpio_chip *jz_irq_to_chip(unsigned int irq)
101{
102    return get_irq_chip_data(irq);
103}
104
105int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
106{
107    if (function == JZ_GPIO_FUNC_NONE) {
108        writew(GPIO_TO_BIT(gpio), GPIO_TO_FUNC_CLEAR_REG(gpio));
109        writew(GPIO_TO_BIT(gpio), GPIO_TO_SEL_CLEAR_REG(gpio));
110        writew(GPIO_TO_BIT(gpio), GPIO_TO_TRIGGER_CLEAR_REG(gpio));
111    } else {
112        writew(GPIO_TO_BIT(gpio), GPIO_TO_FUNC_SET_REG(gpio));
113        switch (function) {
114        case JZ_GPIO_FUNC1:
115            writew(GPIO_TO_BIT(gpio), GPIO_TO_SEL_CLEAR_REG(gpio));
116            break;
117        case JZ_GPIO_FUNC3:
118            writew(GPIO_TO_BIT(gpio), GPIO_TO_TRIGGER_SET_REG(gpio));
119        case JZ_GPIO_FUNC2: /* Falltrough */
120            writew(GPIO_TO_BIT(gpio), GPIO_TO_SEL_SET_REG(gpio));
121            break;
122        default:
123            BUG();
124            break;
125        }
126    }
127
128    return 0;
129}
130EXPORT_SYMBOL_GPL(jz_gpio_set_function);
131
132int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
133{
134    size_t i;
135    int ret;
136
137    for (i = 0; i < num; ++i, ++request) {
138        ret = gpio_request(request->gpio, request->name);
139        if (ret)
140            goto err;
141        jz_gpio_set_function(request->gpio, request->function);
142    }
143
144    return 0;
145err:
146    for (--request; i > 0; --i, --request)
147        gpio_free(request->gpio);
148
149    return ret;
150}
151EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
152
153void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
154{
155    size_t i;
156
157    for (i = 0; i < num; ++i, ++request) {
158        gpio_free(request->gpio);
159        jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
160    }
161
162}
163EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
164
165void jz_gpio_enable_pullup(unsigned gpio)
166{
167    writel(GPIO_TO_BIT(gpio), GPIO_TO_PULL_CLEAR_REG(gpio));
168}
169EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
170
171void jz_gpio_disable_pullup(unsigned gpio)
172{
173    writel(GPIO_TO_BIT(gpio), GPIO_TO_PULL_SET_REG(gpio));
174}
175EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
176
177static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
178{
179    return !!(readl(CHIP_TO_PIN_REG(chip)) & BIT(gpio));
180}
181
182static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
183{
184    uint32_t __iomem *reg = CHIP_TO_DATA_SET_REG(chip) + ((!value) << 2);
185    writel(BIT(gpio), reg);
186}
187
188static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
189{
190    writel(BIT(gpio), CHIP_TO_DIRECTION_SET_REG(chip));
191    jz_gpio_set_value(chip, gpio, value);
192
193    return 0;
194}
195
196static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
197{
198    writel(BIT(gpio), CHIP_TO_DIRECTION_CLEAR_REG(chip));
199
200    return 0;
201}
202
203
204#define IRQ_TO_GPIO(irq) (irq - JZ_IRQ_GPIO(0))
205#define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
206
207
208#define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
209#define IRQ_TO_PIN_REG(irq) IRQ_TO_REG(irq, 0x00)
210#define IRQ_TO_MASK_REG(irq) IRQ_TO_REG(irq, 0x20)
211#define IRQ_TO_MASK_SET_REG(irq) IRQ_TO_REG(irq, 0x24)
212#define IRQ_TO_MASK_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x28)
213#define IRQ_TO_SELECT_REG(irq) IRQ_TO_REG(irq, 0x50)
214#define IRQ_TO_SELECT_SET_REG(irq) IRQ_TO_REG(irq, 0x54)
215#define IRQ_TO_SELECT_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x58)
216#define IRQ_TO_DIRECTION_REG(irq) IRQ_TO_REG(irq, 0x60)
217#define IRQ_TO_DIRECTION_SET_REG(irq) IRQ_TO_REG(irq, 0x64)
218#define IRQ_TO_DIRECTION_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x68)
219#define IRQ_TO_TRIGGER_REG(irq) IRQ_TO_REG(irq, 0x70)
220#define IRQ_TO_TRIGGER_SET_REG(irq) IRQ_TO_REG(irq, 0x74)
221#define IRQ_TO_TRIGGER_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x78)
222#define IRQ_TO_FLAG_REG(irq) IRQ_TO_REG(irq, 0x80)
223#define IRQ_TO_FLAG_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x14)
224
225
226static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
227{
228    uint32_t flag;
229    unsigned int gpio_irq;
230    unsigned int gpio_bank;
231    struct jz_gpio_chip *chip = get_irq_desc_data(desc);
232
233    gpio_bank = JZ_IRQ_GPIO0 - irq;
234
235    flag = readl(jz_gpio_base + (gpio_bank << 8) + 0x80);
236
237    gpio_irq = ffs(flag) - 1;
238
239    if (chip->edge_trigger_both & BIT(gpio_irq)) {
240        uint32_t value = readl(CHIP_TO_PIN_REG(&chip->gpio_chip));
241        if (value & BIT(gpio_irq)) {
242            writel(BIT(gpio_irq),
243                CHIP_TO_DIRECTION_CLEAR_REG(&chip->gpio_chip));
244        } else {
245            writel(BIT(gpio_irq),
246                CHIP_TO_DIRECTION_SET_REG(&chip->gpio_chip));
247        }
248    }
249
250
251    gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0);
252
253
254    generic_handle_irq(gpio_irq);
255};
256
257/* TODO: Check if function is gpio */
258static unsigned int jz_gpio_irq_startup(unsigned int irq)
259{
260    writel(IRQ_TO_BIT(irq), IRQ_TO_SELECT_SET_REG(irq));
261    spin_lock(&jz_gpio_lock);
262    writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_CLEAR_REG(irq));
263    spin_unlock(&jz_gpio_lock);
264    return 0;
265}
266
267static void jz_gpio_irq_shutdown(unsigned int irq)
268{
269    spin_lock(&jz_gpio_lock);
270    writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_SET_REG(irq));
271    spin_unlock(&jz_gpio_lock);
272    /* Set direction to input */
273    writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_CLEAR_REG(irq));
274    writel(IRQ_TO_BIT(irq), IRQ_TO_SELECT_CLEAR_REG(irq));
275}
276
277static void jz_gpio_irq_mask(unsigned int irq)
278{
279    writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_SET_REG(irq));
280};
281
282static void jz_gpio_irq_unmask(unsigned int irq)
283{
284    writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_CLEAR_REG(irq));
285};
286
287static void jz_gpio_irq_ack(unsigned int irq)
288{
289    writel(IRQ_TO_BIT(irq), IRQ_TO_FLAG_CLEAR_REG(irq));
290};
291
292static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
293{
294    uint32_t mask;
295    struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
296    spin_lock(&jz_gpio_lock);
297
298    mask = readl(IRQ_TO_MASK_REG(irq));
299
300    writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_CLEAR_REG(irq));
301    if (flow_type == IRQ_TYPE_EDGE_BOTH) {
302        uint32_t value = readl(IRQ_TO_PIN_REG(irq));
303        if (value & IRQ_TO_BIT(irq))
304            flow_type = IRQ_TYPE_EDGE_FALLING;
305        else
306            flow_type = IRQ_TYPE_EDGE_RISING;
307        chip->edge_trigger_both |= IRQ_TO_BIT(irq);
308    } else {
309        chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
310    }
311
312    switch(flow_type) {
313    case IRQ_TYPE_EDGE_RISING:
314        writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_SET_REG(irq));
315        writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_SET_REG(irq));
316        break;
317    case IRQ_TYPE_EDGE_FALLING:
318        writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_CLEAR_REG(irq));
319        writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_SET_REG(irq));
320        break;
321    case IRQ_TYPE_LEVEL_HIGH:
322        writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_SET_REG(irq));
323        writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_CLEAR_REG(irq));
324        break;
325    case IRQ_TYPE_LEVEL_LOW:
326        writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_CLEAR_REG(irq));
327        writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_CLEAR_REG(irq));
328        break;
329    default:
330        return -EINVAL;
331    }
332
333    writel(mask, IRQ_TO_MASK_SET_REG(irq));
334
335    spin_unlock(&jz_gpio_lock);
336
337    return 0;
338}
339
340static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
341{
342    struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
343    if (on) {
344        chip->wakeup |= IRQ_TO_BIT(irq);
345    } else {
346        chip->wakeup &= ~IRQ_TO_BIT(irq);
347    }
348    set_irq_wake(chip->irq, on);
349    return 0;
350}
351
352int gpio_to_irq(unsigned gpio)
353{
354    return JZ_IRQ_GPIO(0) + gpio;
355}
356EXPORT_SYMBOL_GPL(gpio_to_irq);
357
358int irq_to_gpio(unsigned gpio)
359{
360    return IRQ_TO_GPIO(gpio);
361}
362EXPORT_SYMBOL_GPL(irq_to_gpio);
363
364#define JZ_GPIO_CHIP(_bank) { \
365    .irq_base = JZ_IRQ_GPIO_BASE_ ## _bank, \
366    .gpio_chip = { \
367        .label = "Bank " # _bank, \
368        .owner = THIS_MODULE, \
369        .set = jz_gpio_set_value, \
370        .get = jz_gpio_get_value, \
371        .direction_output = jz_gpio_direction_output, \
372        .direction_input = jz_gpio_direction_input, \
373        .base = JZ_GPIO_BASE_ ## _bank, \
374        .ngpio = JZ_GPIO_NUM_ ## _bank, \
375    }, \
376    .irq_chip = { \
377        .name = "GPIO Bank " # _bank, \
378        .mask = jz_gpio_irq_mask, \
379        .unmask = jz_gpio_irq_unmask, \
380        .ack = jz_gpio_irq_ack, \
381        .startup = jz_gpio_irq_startup, \
382        .shutdown = jz_gpio_irq_shutdown, \
383        .set_type = jz_gpio_irq_set_type, \
384        .set_wake = jz_gpio_irq_set_wake, \
385    }, \
386}
387
388static struct jz_gpio_chip jz_gpio_chips[] = {
389    JZ_GPIO_CHIP(A),
390    JZ_GPIO_CHIP(B),
391    JZ_GPIO_CHIP(C),
392    JZ_GPIO_CHIP(D),
393};
394
395int __init jz_gpiolib_init(void)
396{
397    struct jz_gpio_chip *chip = jz_gpio_chips;
398    int i, irq;
399
400    jz_gpio_base = ioremap(0x10010000, 0x400);
401
402    for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
403        gpiochip_add(&chip->gpio_chip);
404        chip->irq = JZ_IRQ_INTC_GPIO(i);
405        set_irq_data(chip->irq, chip);
406        set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
407        for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio;
408        ++irq) {
409            set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
410            set_irq_chip_data(irq, chip);
411        }
412    }
413
414    printk("JZ GPIO initalized\n");
415
416    return 0;
417}
418
419void jz_gpiolib_suspend(void)
420{
421    struct jz_gpio_chip *chip = jz_gpio_chips;
422    int i, gpio;
423    for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
424        gpio = chip->gpio_chip.base;
425        chip->saved[0] = readl(GPIO_TO_MASK_REG(gpio));
426        writel(~(chip->wakeup), GPIO_TO_MASK_SET_REG(gpio));
427    }
428}
429
430/* TODO: Use sysdev */
431void jz_gpiolib_resume(void)
432{
433    struct jz_gpio_chip *chip = jz_gpio_chips;
434    int i, gpio;
435    for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
436        writel(~(chip->saved[0]), GPIO_TO_MASK_CLEAR_REG(chip->gpio_chip.base));
437    }
438}
arch/mips/jz4740/irq.c
1/*
2 * linux/arch/mips/jz4740/irq.c
3 *
4 * JZ4740 interrupt routines.
5 *
6 * Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
7 * Author: <lhhuang@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <asm/mach-jz4740/irq.h>
15#include <linux/irq.h>
16
17#include <linux/errno.h>
18#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/interrupt.h>
21#include <linux/ioport.h>
22#include <linux/timex.h>
23#include <linux/slab.h>
24#include <linux/delay.h>
25
26#include <asm/io.h>
27#include <asm/mipsregs.h>
28#include <asm/irq_cpu.h>
29
30static void __iomem *jz_intc_base;
31static uint32_t jz_intc_wakeup;
32static uint32_t jz_intc_saved;
33
34#define JZ_REG_BASE_INTC 0x10001000
35
36#define JZ_REG_INTC_STATUS 0x00
37#define JZ_REG_INTC_MASK 0x04
38#define JZ_REG_INTC_SET_MASK 0x08
39#define JZ_REG_INTC_CLEAR_MASK 0x0c
40#define JZ_REG_INTC_PENDING 0x10
41
42#define IRQ_BIT(x) BIT((x) - JZ_IRQ_BASE)
43
44static void intc_irq_unmask(unsigned int irq)
45{
46    writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
47}
48
49static void intc_irq_mask(unsigned int irq)
50{
51    writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
52}
53
54static void intc_irq_ack(unsigned int irq)
55{
56    writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING);
57}
58
59static void intc_irq_end(unsigned int irq)
60{
61    if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
62        intc_irq_unmask(irq);
63    }
64}
65
66static int intc_irq_set_wake(unsigned int irq, unsigned int on)
67{
68    if (on)
69        jz_intc_wakeup |= IRQ_BIT(irq);
70    else
71        jz_intc_wakeup &= ~IRQ_BIT(irq);
72
73    return 0;
74}
75
76static struct irq_chip intc_irq_type = {
77    .name = "INTC",
78    .mask = intc_irq_mask,
79    .unmask = intc_irq_unmask,
80    .ack = intc_irq_ack,
81    .end = intc_irq_end,
82    .set_wake = intc_irq_set_wake,
83};
84
85static irqreturn_t jz4740_cascade(int irq, void *data)
86{
87    uint32_t irq_reg;
88    irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
89
90    if (irq_reg) {
91        generic_handle_irq(ffs(irq_reg) - 1 + JZ_IRQ_BASE);
92        return IRQ_HANDLED;
93    }
94
95    return 0;
96}
97
98static struct irqaction jz4740_cascade_action = {
99    .handler = jz4740_cascade,
100    .name = "JZ4740 cascade interrupt"
101};
102
103void __init arch_init_irq(void)
104{
105    int i;
106    mips_cpu_irq_init();
107
108    jz_intc_base = ioremap(JZ_REG_BASE_INTC, 0x14);
109
110    for (i = JZ_IRQ_BASE; i < JZ_IRQ_BASE + 32; i++) {
111        intc_irq_mask(i);
112        set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
113    }
114
115    setup_irq(2, &jz4740_cascade_action);
116}
117
118asmlinkage void plat_irq_dispatch(void)
119{
120    unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
121    if (pending & STATUSF_IP2)
122        jz4740_cascade(2, NULL);
123    else if(pending & STATUSF_IP3)
124        do_IRQ(3);
125    else
126        spurious_interrupt();
127}
128
129/* TODO: Use sysdev */
130void jz4740_intc_suspend(void)
131{
132    jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
133    printk("intc wakeup: %d\n", jz_intc_wakeup);
134    writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
135}
136
137void jz4740_intc_resume(void)
138{
139    writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
140}
arch/mips/jz4740/platform.c
1/*
2 * Platform device support for Jz4740 SoC.
3 *
4 * Copyright 2007, <yliu@ingenic.cn>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/device.h>
12#include <linux/platform_device.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/resource.h>
16
17#include <asm/mach-jz4740/platform.h>
18#include <asm/mach-jz4740/regs.h>
19#include <asm/mach-jz4740/irq.h>
20
21/* OHCI (USB full speed host controller) */
22static struct resource jz4740_usb_ohci_resources[] = {
23    [0] = {
24        .start = CPHYSADDR(UHC_BASE),
25        .end = CPHYSADDR(UHC_BASE) + 0x10000 - 1,
26        .flags = IORESOURCE_MEM,
27    },
28    [1] = {
29        .start = JZ_IRQ_UHC,
30        .end = JZ_IRQ_UHC,
31        .flags = IORESOURCE_IRQ,
32    },
33};
34
35/* The dmamask must be set for OHCI to work */
36static u64 ohci_dmamask = ~(u32)0;
37
38struct platform_device jz4740_usb_ohci_device = {
39    .name = "jz-ohci",
40    .id = 0,
41    .dev = {
42        .dma_mask = &ohci_dmamask,
43        .coherent_dma_mask = 0xffffffff,
44    },
45    .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources),
46    .resource = jz4740_usb_ohci_resources,
47};
48
49/* UDC (USB gadget controller) */
50static struct resource jz4740_usb_gdt_resources[] = {
51    [0] = {
52        .start = CPHYSADDR(UDC_BASE),
53        .end = CPHYSADDR(UDC_BASE) + 0x10000 - 1,
54        .flags = IORESOURCE_MEM,
55    },
56    [1] = {
57        .start = JZ_IRQ_UDC,
58        .end = JZ_IRQ_UDC,
59        .flags = IORESOURCE_IRQ,
60    },
61};
62
63static u64 jz4740_udc_dmamask = ~(u32)0;
64
65struct platform_device jz4740_usb_gdt_device = {
66    .name = "jz-udc",
67    .id = -1,
68    .dev = {
69        .dma_mask = &jz4740_udc_dmamask,
70        .coherent_dma_mask = 0xffffffff,
71    },
72    .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources),
73    .resource = jz4740_usb_gdt_resources,
74};
75
76/** MMC/SD controller **/
77static struct resource jz4740_mmc_resources[] = {
78    [0] = {
79        .start = CPHYSADDR(MSC_BASE),
80        .end = CPHYSADDR(MSC_BASE) + 0x10000 - 1,
81        .flags = IORESOURCE_MEM,
82    },
83    [1] = {
84        .start = JZ_IRQ_MSC,
85        .end = JZ_IRQ_MSC,
86        .flags = IORESOURCE_IRQ,
87    }
88};
89
90static u64 jz4740_mmc_dmamask = ~(u32)0;
91
92struct platform_device jz4740_mmc_device = {
93    .name = "jz-mmc",
94    .id = 0,
95    .dev = {
96        .dma_mask = &jz4740_mmc_dmamask,
97        .coherent_dma_mask = 0xffffffff,
98    },
99    .num_resources = ARRAY_SIZE(jz4740_mmc_resources),
100    .resource = jz4740_mmc_resources,
101};
102
103static struct resource jz4740_rtc_resources[] = {
104    [0] = {
105        .start = CPHYSADDR(RTC_BASE),
106        .end = CPHYSADDR(RTC_BASE) + 0x10,
107        .flags = IORESOURCE_MEM,
108    },
109    [1] = {
110        .start = JZ_IRQ_RTC,
111        .end = JZ_IRQ_RTC,
112        .flags = IORESOURCE_IRQ,
113    },
114};
115
116struct platform_device jz4740_rtc_device = {
117    .name = "jz4740-rtc",
118    .id = -1,
119    .num_resources = ARRAY_SIZE(jz4740_rtc_resources),
120    .resource = jz4740_rtc_resources,
121};
122
123/** I2C controller **/
124static struct resource jz4740_i2c_resources[] = {
125    [0] = {
126        .start = CPHYSADDR(I2C_BASE),
127        .end = CPHYSADDR(I2C_BASE) + 0x10000 - 1,
128        .flags = IORESOURCE_MEM,
129    },
130    [1] = {
131        .start = JZ_IRQ_I2C,
132        .end = JZ_IRQ_I2C,
133        .flags = IORESOURCE_IRQ,
134    }
135};
136
137static u64 jz4740_i2c_dmamask = ~(u32)0;
138
139struct platform_device jz4740_i2c_device = {
140    .name = "jz_i2c",
141    .id = 0,
142    .dev = {
143        .dma_mask = &jz4740_i2c_dmamask,
144        .coherent_dma_mask = 0xffffffff,
145    },
146    .num_resources = ARRAY_SIZE(jz4740_i2c_resources),
147    .resource = jz4740_i2c_resources,
148};
149
150static struct resource jz4740_nand_resources[] = {
151    [0] = {
152        .start = CPHYSADDR(EMC_BASE),
153        .end = CPHYSADDR(EMC_BASE) + 0x10000 - 1,
154        .flags = IORESOURCE_MEM,
155    },
156};
157
158struct platform_device jz4740_nand_device = {
159    .name = "jz4740-nand",
160    .num_resources = ARRAY_SIZE(jz4740_nand_resources),
161    .resource = jz4740_nand_resources,
162};
163
164static struct resource jz4740_framebuffer_resources[] = {
165    [0] = {
166        .start = CPHYSADDR(LCD_BASE),
167        .end = CPHYSADDR(LCD_BASE) + 0x10000 - 1,
168        .flags = IORESOURCE_MEM,
169    },
170};
171
172static u64 jz4740_fb_dmamask = ~(u32)0;
173
174struct platform_device jz4740_framebuffer_device = {
175    .name = "jz4740-fb",
176    .id = -1,
177    .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
178    .resource = jz4740_framebuffer_resources,
179    .dev = {
180        .dma_mask = &jz4740_fb_dmamask,
181        .coherent_dma_mask = 0xffffffff,
182    },
183};
184
185static struct resource jz4740_i2s_resources[] = {
186    [0] = {
187        .start = CPHYSADDR(AIC_BASE),
188        .end = CPHYSADDR(AIC_BASE) + 0x38 - 1,
189        .flags = IORESOURCE_MEM,
190    },
191};
192
193struct platform_device jz4740_i2s_device = {
194    .name = "jz4740-i2s",
195    .id = -1,
196    .num_resources = ARRAY_SIZE(jz4740_i2s_resources),
197    .resource = jz4740_i2s_resources,
198};
199
200static struct resource jz4740_codec_resources[] = {
201    [0] = {
202        .start = CPHYSADDR(AIC_BASE) + 0x80,
203        .end = CPHYSADDR(AIC_BASE) + 0x88 - 1,
204        .flags = IORESOURCE_MEM,
205    },
206};
207
208struct platform_device jz4740_codec_device = {
209    .name = "jz4740-codec",
210    .id = -1,
211    .num_resources = ARRAY_SIZE(jz4740_codec_resources),
212    .resource = jz4740_codec_resources,
213};
214
215static struct resource jz4740_adc_resources[] = {
216    [0] = {
217        .start = CPHYSADDR(SADC_BASE),
218        .end = CPHYSADDR(SADC_BASE) + 0x30,
219        .flags = IORESOURCE_MEM,
220    },
221    [1] = {
222        .start = JZ_IRQ_SADC,
223        .end = JZ_IRQ_SADC,
224        .flags = IORESOURCE_IRQ,
225    },
226};
227
228struct platform_device jz4740_adc_device = {
229    .name = "jz4740-adc",
230    .id = -1,
231    .num_resources = ARRAY_SIZE(jz4740_adc_resources),
232    .resource = jz4740_adc_resources,
233};
234
235struct platform_device jz4740_battery_device = {
236    .name = "jz4740-battery",
237    .id = -1,
238    .dev = {
239        .parent = &jz4740_adc_device.dev
240    },
241};
arch/mips/jz4740/pm.c
1/*
2 * linux/arch/mips/jz4740/common/pm.c
3 *
4 * JZ4740 Power Management Routines
5 *
6 * Copyright (C) 2006 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 */
23
24#include <linux/init.h>
25#include <linux/pm.h>
26#include <linux/delay.h>
27#include <linux/suspend.h>
28#include <asm/mach-jz4740/regs.h>
29
30extern void jz4740_intc_suspend(void);
31extern void jz4740_intc_resume(void);
32extern void jz_gpiolib_suspend(void);
33extern void jz_gpiolib_resume(void);
34
35static int jz_pm_enter(suspend_state_t state)
36{
37    unsigned long delta;
38    unsigned long nfcsr = REG_EMC_NFCSR;
39    uint32_t scr = REG_CPM_SCR;
40
41    /* Preserve current time */
42    delta = xtime.tv_sec - REG_RTC_RSR;
43
44    /* Disable nand flash */
45    REG_EMC_NFCSR = ~0xff;
46
47     udelay(100);
48
49    /*stop udc and usb*/
50    REG_CPM_SCR &= ~( 1<<6 | 1<<7);
51    REG_CPM_SCR |= 0<<6 | 1<<7;
52
53    jz_gpiolib_suspend();
54    jz4740_intc_suspend();
55
56     /* Enter SLEEP mode */
57    REG_CPM_LCR &= ~CPM_LCR_LPM_MASK;
58    REG_CPM_LCR |= CPM_LCR_LPM_SLEEP;
59    __asm__(".set\tmips3\n\t"
60        "wait\n\t"
61        ".set\tmips0");
62
63    /* Restore to IDLE mode */
64    REG_CPM_LCR &= ~CPM_LCR_LPM_MASK;
65    REG_CPM_LCR |= CPM_LCR_LPM_IDLE;
66
67    /* Restore nand flash control register */
68    REG_EMC_NFCSR = nfcsr;
69
70    jz4740_intc_resume();
71    jz_gpiolib_resume();
72
73    /* Restore sleep control register */
74    REG_CPM_SCR = scr;
75
76    /* Restore current time */
77    xtime.tv_sec = REG_RTC_RSR + delta;
78
79    return 0;
80}
81
82static struct platform_suspend_ops jz_pm_ops = {
83    .valid = suspend_valid_only_mem,
84    .enter = jz_pm_enter,
85};
86
87/*
88 * Initialize power interface
89 */
90int __init jz_pm_init(void)
91{
92    suspend_set_ops(&jz_pm_ops);
93    return 0;
94
95}
96late_initcall(jz_pm_init);
arch/mips/jz4740/proc.c
1/*
2 * linux/arch/mips/jz4740/proc.c
3 *
4 * /proc/jz/ procfs for jz4740 on-chip modules.
5 *
6 * Copyright (C) 2006 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 */
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/sysctl.h>
28#include <linux/proc_fs.h>
29#include <linux/page-flags.h>
30#include <asm/uaccess.h>
31#include <asm/pgtable.h>
32#include <asm/mach-jz4740/regs.h>
33#include <asm/mach-jz4740/clock.h>
34#include <asm/mach-jz4740/ops.h>
35
36//#define DEBUG 1
37#undef DEBUG
38
39
40struct proc_dir_entry *proc_jz_root;
41
42
43/*
44 * EMC Modules
45 */
46static int emc_read_proc (char *page, char **start, off_t off,
47              int count, int *eof, void *data)
48{
49    int len = 0;
50
51    len += sprintf (page+len, "SMCR(0-5): 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", REG_EMC_SMCR0, REG_EMC_SMCR1, REG_EMC_SMCR2, REG_EMC_SMCR3, REG_EMC_SMCR4);
52    len += sprintf (page+len, "SACR(0-5): 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", REG_EMC_SACR0, REG_EMC_SACR1, REG_EMC_SACR2, REG_EMC_SACR3, REG_EMC_SACR4);
53    len += sprintf (page+len, "DMCR: 0x%08x\n", REG_EMC_DMCR);
54    len += sprintf (page+len, "RTCSR: 0x%04x\n", REG_EMC_RTCSR);
55    len += sprintf (page+len, "RTCOR: 0x%04x\n", REG_EMC_RTCOR);
56    return len;
57}
58
59/*
60 * Power Manager Module
61 */
62static int pmc_read_proc (char *page, char **start, off_t off,
63              int count, int *eof, void *data)
64{
65    int len = 0;
66    unsigned long lcr = REG_CPM_LCR;
67    unsigned long clkgr = REG_CPM_CLKGR;
68
69    len += sprintf (page+len, "Low Power Mode : %s\n",
70            ((lcr & CPM_LCR_LPM_MASK) == (CPM_LCR_LPM_IDLE)) ?
71            "IDLE" : (((lcr & CPM_LCR_LPM_MASK) == (CPM_LCR_LPM_SLEEP)) ?
72                  "SLEEP" : "HIBERNATE"));
73    len += sprintf (page+len, "Doze Mode : %s\n",
74            (lcr & CPM_LCR_DOZE_ON) ? "on" : "off");
75    if (lcr & CPM_LCR_DOZE_ON)
76        len += sprintf (page+len, " duty : %d\n", (int)((lcr & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT));
77    len += sprintf (page+len, "IPU : %s\n",
78            (clkgr & CPM_CLKGR_IPU) ? "stopped" : "running");
79    len += sprintf (page+len, "DMAC : %s\n",
80            (clkgr & CPM_CLKGR_DMAC) ? "stopped" : "running");
81    len += sprintf (page+len, "UHC : %s\n",
82            (clkgr & CPM_CLKGR_UHC) ? "stopped" : "running");
83    len += sprintf (page+len, "UDC : %s\n",
84            (clkgr & CPM_CLKGR_UDC) ? "stopped" : "running");
85    len += sprintf (page+len, "LCD : %s\n",
86            (clkgr & CPM_CLKGR_LCD) ? "stopped" : "running");
87    len += sprintf (page+len, "CIM : %s\n",
88            (clkgr & CPM_CLKGR_CIM) ? "stopped" : "running");
89    len += sprintf (page+len, "SADC : %s\n",
90            (clkgr & CPM_CLKGR_SADC) ? "stopped" : "running");
91    len += sprintf (page+len, "MSC : %s\n",
92            (clkgr & CPM_CLKGR_MSC) ? "stopped" : "running");
93    len += sprintf (page+len, "AIC1 : %s\n",
94            (clkgr & CPM_CLKGR_AIC1) ? "stopped" : "running");
95    len += sprintf (page+len, "AIC2 : %s\n",
96            (clkgr & CPM_CLKGR_AIC2) ? "stopped" : "running");
97    len += sprintf (page+len, "SSI : %s\n",
98            (clkgr & CPM_CLKGR_SSI) ? "stopped" : "running");
99    len += sprintf (page+len, "I2C : %s\n",
100            (clkgr & CPM_CLKGR_I2C) ? "stopped" : "running");
101    len += sprintf (page+len, "RTC : %s\n",
102            (clkgr & CPM_CLKGR_RTC) ? "stopped" : "running");
103    len += sprintf (page+len, "TCU : %s\n",
104            (clkgr & CPM_CLKGR_TCU) ? "stopped" : "running");
105    len += sprintf (page+len, "UART1 : %s\n",
106            (clkgr & CPM_CLKGR_UART1) ? "stopped" : "running");
107    len += sprintf (page+len, "UART0 : %s\n",
108            (clkgr & CPM_CLKGR_UART0) ? "stopped" : "running");
109    return len;
110}
111
112static int pmc_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
113{
114    REG_CPM_CLKGR = simple_strtoul(buffer, 0, 16);
115    return count;
116}
117
118/*
119 * Clock Generation Module
120 */
121#define TO_MHZ(x) (x/1000000),(x%1000000)/10000
122#define TO_KHZ(x) (x/1000),(x%1000)/10
123
124static int cgm_read_proc (char *page, char **start, off_t off,
125              int count, int *eof, void *data)
126{
127    int len = 0;
128    unsigned int cppcr = REG_CPM_CPPCR; /* PLL Control Register */
129    unsigned int cpccr = REG_CPM_CPCCR; /* Clock Control Register */
130    unsigned int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
131    unsigned int od[4] = {1, 2, 2, 4};
132
133    len += sprintf (page+len, "CPPCR : 0x%08x\n", cppcr);
134    len += sprintf (page+len, "CPCCR : 0x%08x\n", cpccr);
135    len += sprintf (page+len, "PLL : %s\n",
136            (cppcr & CPM_CPPCR_PLLEN) ? "ON" : "OFF");
137    len += sprintf (page+len, "m:n:o : %d:%d:%d\n",
138            __cpm_get_pllm() + 2,
139            __cpm_get_plln() + 2,
140            od[__cpm_get_pllod()]
141        );
142    len += sprintf (page+len, "C:H:M:P : %d:%d:%d:%d\n",
143            div[__cpm_get_cdiv()],
144            div[__cpm_get_hdiv()],
145            div[__cpm_get_mdiv()],
146            div[__cpm_get_pdiv()]
147        );
148    len += sprintf (page+len, "PLL Freq : %3d.%02d MHz\n", TO_MHZ(__cpm_get_pllout()));
149    len += sprintf (page+len, "CCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_cclk()));
150    len += sprintf (page+len, "HCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_hclk()));
151    len += sprintf (page+len, "MCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mclk()));
152    len += sprintf (page+len, "PCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_pclk()));
153    len += sprintf (page+len, "LCDCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_lcdclk()));
154    len += sprintf (page+len, "PIXCLK : %3d.%02d KHz\n", TO_KHZ(__cpm_get_pixclk()));
155    len += sprintf (page+len, "I2SCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_i2sclk()));
156    len += sprintf (page+len, "USBCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_usbclk()));
157    len += sprintf (page+len, "MSCCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mscclk()));
158    len += sprintf (page+len, "EXTALCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_extalclk()));
159    len += sprintf (page+len, "RTCCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_rtcclk()));
160
161    return len;
162}
163
164static int cgm_write_proc(struct file *file, const char *buffer, unsigned long count, void *data)
165{
166    REG_CPM_CPCCR = simple_strtoul(buffer, 0, 16);
167    return count;
168}
169
170
171extern void local_flush_tlb_all(void);
172
173/* CP0 hazard avoidance. */
174#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
175                     "nop; nop; nop; nop; nop; nop;\n\t" \
176                     ".set reorder\n\t")
177void show_tlb(void)
178{
179#define ASID_MASK 0xFF
180
181        unsigned long flags;
182        unsigned int old_ctx;
183    unsigned int entry;
184    unsigned int entrylo0, entrylo1, entryhi;
185    unsigned int pagemask;
186
187    local_irq_save(flags);
188
189    /* Save old context */
190    old_ctx = (read_c0_entryhi() & 0xff);
191
192    printk("TLB content:\n");
193    entry = 0;
194    while(entry < 32) {
195        write_c0_index(entry);
196        BARRIER;
197        tlb_read();
198        BARRIER;
199        entryhi = read_c0_entryhi();
200        entrylo0 = read_c0_entrylo0();
201        entrylo1 = read_c0_entrylo1();
202        pagemask = read_c0_pagemask();
203        printk("%02d: ASID=%02d%s VA=0x%08x ", entry, entryhi & ASID_MASK, (entrylo0 & entrylo1 & 1) ? "(G)" : " ", entryhi & ~ASID_MASK);
204        printk("PA0=0x%08x C0=%x %s%s%s\n", (entrylo0>>6)<<12, (entrylo0>>3) & 7, (entrylo0 & 4) ? "Dirty " : "", (entrylo0 & 2) ? "Valid " : "Invalid ", (entrylo0 & 1) ? "Global" : "");
205        printk("\t\t\t PA1=0x%08x C1=%x %s%s%s\n", (entrylo1>>6)<<12, (entrylo1>>3) & 7, (entrylo1 & 4) ? "Dirty " : "", (entrylo1 & 2) ? "Valid " : "Invalid ", (entrylo1 & 1) ? "Global" : "");
206
207        printk("\t\tpagemask=0x%08x", pagemask);
208        printk("\tentryhi=0x%08x\n", entryhi);
209        printk("\t\tentrylo0=0x%08x", entrylo0);
210        printk("\tentrylo1=0x%08x\n", entrylo1);
211
212        entry++;
213    }
214    BARRIER;
215    write_c0_entryhi(old_ctx);
216
217    local_irq_restore(flags);
218}
219
220/*
221 * UDC hotplug
222 */
223#ifdef CONFIG_JZ_UDC_HOTPLUG
224extern int jz_udc_active; /* defined in drivers/char/jzchar/jz_udc_hotplug.c */
225#endif
226
227#ifndef GPIO_UDC_HOTPLUG
228#define GPIO_UDC_HOTPLUG 86
229#endif
230
231static int udc_read_proc(char *page, char **start, off_t off,
232             int count, int *eof, void *data)
233{
234        int len = 0;
235
236    if (__gpio_get_pin(GPIO_UDC_HOTPLUG)) {
237
238#ifdef CONFIG_JZ_UDC_HOTPLUG
239
240        /* Cable has connected, wait for disconnection. */
241        __gpio_as_irq_fall_edge(GPIO_UDC_HOTPLUG);
242
243        if (jz_udc_active)
244            len += sprintf (page+len, "CONNECT_CABLE\n");
245        else
246            len += sprintf (page+len, "CONNECT_POWER\n");
247#else
248        len += sprintf (page+len, "CONNECT\n");
249#endif
250    }
251    else {
252
253#ifdef CONFIG_JZ_UDC_HOTPLUG
254        /* Cable has disconnected, wait for connection. */
255        __gpio_as_irq_rise_edge(GPIO_UDC_HOTPLUG);
256#endif
257
258        len += sprintf (page+len, "REMOVE\n");
259    }
260
261        return len;
262}
263
264/*
265 * /proc/jz/xxx entry
266 *
267 */
268static int __init jz_proc_init(void)
269{
270    struct proc_dir_entry *res;
271    unsigned int virt_addr, i;
272
273    proc_jz_root = proc_mkdir("jz", 0);
274
275    /* External Memory Controller */
276    res = create_proc_entry("emc", 0644, proc_jz_root);
277    if (res) {
278        res->read_proc = emc_read_proc;
279        res->write_proc = NULL;
280        res->data = NULL;
281    }
282
283    /* Power Management Controller */
284    res = create_proc_entry("pmc", 0644, proc_jz_root);
285    if (res) {
286        res->read_proc = pmc_read_proc;
287        res->write_proc = pmc_write_proc;
288        res->data = NULL;
289    }
290
291    /* Clock Generation Module */
292    res = create_proc_entry("cgm", 0644, proc_jz_root);
293    if (res) {
294        res->read_proc = cgm_read_proc;
295        res->write_proc = cgm_write_proc;
296        res->data = NULL;
297    }
298
299    /* udc hotplug */
300    res = create_proc_entry("udc", 0644, proc_jz_root);
301    if (res) {
302        res->read_proc = udc_read_proc;
303        res->write_proc = NULL;
304        res->data = NULL;
305    }
306
307    return 0;
308}
309
310__initcall(jz_proc_init);
arch/mips/jz4740/prom.c
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PROM library initialisation code, supports YAMON and U-Boot.
5 *
6 * Copyright 2000, 2001, 2006 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This file was derived from Carsten Langgaard's
11 * arch/mips/mips-boards/xx files.
12 *
13 * Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36
37#include <linux/module.h>
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/string.h>
41
42#include <asm/bootinfo.h>
43#include <asm/mach-jz4740/regs.h>
44
45/* #define DEBUG_CMDLINE */
46
47int prom_argc;
48char **prom_argv, **prom_envp;
49
50char * prom_getcmdline(void)
51{
52    return &(arcs_cmdline[0]);
53}
54
55void prom_init_cmdline(void)
56{
57    char *cp;
58    int actr;
59
60    actr = 1; /* Always ignore argv[0] */
61
62    cp = &(arcs_cmdline[0]);
63    while(actr < prom_argc) {
64            strcpy(cp, prom_argv[actr]);
65        cp += strlen(prom_argv[actr]);
66        *cp++ = ' ';
67        actr++;
68    }
69    if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
70        --cp;
71    if (prom_argc > 1)
72        *cp = '\0';
73
74}
75
76
77char *prom_getenv(char *envname)
78{
79#if 0
80    /*
81     * Return a pointer to the given environment variable.
82     * YAMON uses "name", "value" pairs, while U-Boot uses "name=value".
83     */
84
85    char **env = prom_envp;
86    int i = strlen(envname);
87    int yamon = (*env && strchr(*env, '=') == NULL);
88
89    while (*env) {
90        if (yamon) {
91            if (strcmp(envname, *env++) == 0)
92                return *env;
93        } else {
94            if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=')
95                return *env + i + 1;
96        }
97        env++;
98    }
99#endif
100    return NULL;
101}
102
103inline unsigned char str2hexnum(unsigned char c)
104{
105    if(c >= '0' && c <= '9')
106        return c - '0';
107    if(c >= 'a' && c <= 'f')
108        return c - 'a' + 10;
109    if(c >= 'A' && c <= 'F')
110        return c - 'A' + 10;
111    return 0; /* foo */
112}
113
114inline void str2eaddr(unsigned char *ea, unsigned char *str)
115{
116    int i;
117
118    for(i = 0; i < 6; i++) {
119        unsigned char num;
120
121        if((*str == '.') || (*str == ':'))
122            str++;
123        num = str2hexnum(*str++) << 4;
124        num |= (str2hexnum(*str++));
125        ea[i] = num;
126    }
127}
128
129int get_ethernet_addr(char *ethernet_addr)
130{
131        char *ethaddr_str;
132
133        ethaddr_str = prom_getenv("ethaddr");
134    if (!ethaddr_str) {
135            printk("ethaddr not set in boot prom\n");
136        return -1;
137    }
138    str2eaddr(ethernet_addr, ethaddr_str);
139
140#if 0
141    {
142        int i;
143
144    printk("get_ethernet_addr: ");
145    for (i=0; i<5; i++)
146        printk("%02x:", (unsigned char)*(ethernet_addr+i));
147    printk("%02x\n", *(ethernet_addr+i));
148    }
149#endif
150
151    return 0;
152}
153
154void __init prom_free_prom_memory(void)
155{
156}
157
158void __init prom_init(void)
159{
160    unsigned char *memsize_str;
161    unsigned long memsize;
162
163    prom_argc = (int) fw_arg0;
164    prom_argv = (char **) fw_arg1;
165    prom_envp = (char **) fw_arg2;
166
167    mips_machtype = MACH_INGENIC_JZ4740;
168
169    prom_init_cmdline();
170    memsize_str = prom_getenv("memsize");
171    if (!memsize_str) {
172        memsize = 0x04000000;
173    } else {
174        memsize = simple_strtol(memsize_str, NULL, 0);
175    }
176    add_memory_region(0, memsize, BOOT_MEM_RAM);
177}
178
179/* used by early printk */
180void prom_putchar(char c)
181{
182    volatile u8 *uart_lsr = (volatile u8 *)(UART0_BASE + OFF_LSR);
183    volatile u8 *uart_tdr = (volatile u8 *)(UART0_BASE + OFF_TDR);
184
185    /* Wait for fifo to shift out some bytes */
186    while ( !((*uart_lsr & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60) );
187
188    *uart_tdr = (u8)c;
189}
190
191const char *get_system_type(void)
192{
193    return "JZ4740";
194}
195
196EXPORT_SYMBOL(prom_getcmdline);
197EXPORT_SYMBOL(get_ethernet_addr);
198EXPORT_SYMBOL(str2eaddr);
arch/mips/jz4740/reset.c
1/*
2 * linux/arch/mips/jz4740/reset.c
3 *
4 * JZ4740 reset routines.
5 *
6 * Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
7 * Author: <yliu@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <asm/io.h>
16#include <asm/pgtable.h>
17#include <asm/processor.h>
18#include <asm/reboot.h>
19#include <asm/system.h>
20#include <asm/mach-jz4740/regs.h>
21#include <asm/mach-jz4740/jz4740.h>
22
23void jz_restart(char *command)
24{
25    printk(KERN_NOTICE "Restarting after 4 ms\n");
26    REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
27    REG_WDT_TCNT = 0;
28    REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */
29    REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */
30    REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */
31    while (1);
32}
33
34void jz_halt(void)
35{
36    /* Put CPU to power down mode */
37    while (!(REG_RTC_RCR & RTC_RCR_WRDY));
38    REG_RTC_HCR = RTC_HCR_PD;
39
40    while (1)
41        __asm__(".set\tmips3\n\t"
42                    "wait\n\t"
43            ".set\tmips0");
44}
45
46void jz_power_off(void)
47{
48    jz_halt();
49}
arch/mips/jz4740/setup.c
1/*
2 * linux/arch/mips/jz4740/common/setup.c
3 *
4 * JZ4740 common setup routines.
5 *
6 * Copyright (C) 2006 Ingenic Semiconductor Inc.
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 */
22#include <linux/init.h>
23#include <linux/string.h>
24#include <linux/kernel.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/ioport.h>
28#include <linux/tty.h>
29#include <linux/serial.h>
30#include <linux/serial_core.h>
31#include <linux/serial_8250.h>
32
33#include <asm/cpu.h>
34#include <asm/bootinfo.h>
35#include <asm/irq.h>
36#include <asm/mipsregs.h>
37#include <asm/reboot.h>
38#include <asm/pgtable.h>
39#include <asm/time.h>
40#include <asm/mach-jz4740/regs.h>
41#include <asm/mach-jz4740/ops.h>
42#include <asm/mach-jz4740/clock.h>
43#include <asm/mach-jz4740/serial.h>
44
45extern char * __init prom_getcmdline(void);
46extern void __init jz_board_setup(void);
47extern void jz_restart(char *);
48extern void jz_halt(void);
49extern void jz_power_off(void);
50extern void jz_time_init(void);
51
52static void __init sysclocks_setup(void)
53{
54#if 0
55    printk("CPU clock: %dMHz, System clock: %dMHz, Peripheral clock: %dMHz, Memory clock: %dMHz\n",
56           (jz_clocks.cclk + 500000) / 1000000,
57           (jz_clocks.hclk + 500000) / 1000000,
58           (jz_clocks.pclk + 500000) / 1000000,
59           (jz_clocks.mclk + 500000) / 1000000);
60#endif
61}
62
63static void __init soc_cpm_setup(void)
64{
65    /* Enable CKO to external memory */
66    __cpm_enable_cko();
67
68    /* CPU enters IDLE mode when executing 'wait' instruction */
69    __cpm_idle_mode();
70
71    /* Setup system clocks */
72    sysclocks_setup();
73}
74
75static void __init soc_harb_setup(void)
76{
77// __harb_set_priority(0x00); /* CIM>LCD>DMA>ETH>PCI>USB>CBB */
78// __harb_set_priority(0x03); /* LCD>CIM>DMA>ETH>PCI>USB>CBB */
79// __harb_set_priority(0x0a); /* ETH>LCD>CIM>DMA>PCI>USB>CBB */
80}
81
82static void __init soc_emc_setup(void)
83{
84}
85
86static void __init soc_dmac_setup(void)
87{
88    __dmac_enable_module();
89}
90
91static void __init jz_soc_setup(void)
92{
93    soc_cpm_setup();
94    soc_harb_setup();
95    soc_emc_setup();
96    soc_dmac_setup();
97}
98
99static void __init jz_serial_setup(void)
100{
101#ifdef CONFIG_SERIAL_8250
102    struct uart_port s;
103    REG8(UART0_FCR) |= UARTFCR_UUE; /* enable UART module */
104    memset(&s, 0, sizeof(s));
105    s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
106    s.iotype = SERIAL_IO_MEM;
107    s.regshift = 2;
108    s.uartclk = JZ_EXTAL;
109
110    s.line = 0;
111    s.membase = (u8 *)UART0_BASE;
112    s.irq = JZ_IRQ_UART0;
113    if (early_serial_setup(&s) != 0) {
114        printk(KERN_ERR "Serial ttyS0 setup failed!\n");
115    }
116
117    s.line = 1;
118    s.membase = (u8 *)UART1_BASE;
119    s.irq = JZ_IRQ_UART1;
120    if (early_serial_setup(&s) != 0) {
121        printk(KERN_ERR "Serial ttyS1 setup failed!\n");
122    }
123#endif
124}
125
126void __init plat_mem_setup(void)
127{
128    char *argptr;
129
130    argptr = prom_getcmdline();
131
132    /* IO/MEM resources. Which will be the addtion value in `inX' and
133     * `outX' macros defined in asm/io.h */
134    set_io_port_base(0);
135    ioport_resource.start = 0x00000000;
136    ioport_resource.end = 0xffffffff;
137    iomem_resource.start = 0x00000000;
138    iomem_resource.end = 0xffffffff;
139
140    _machine_restart = jz_restart;
141    _machine_halt = jz_halt;
142    pm_power_off = jz_power_off;
143    jz_soc_setup();
144    jz_serial_setup();
145}
146
arch/mips/jz4740/time.c
1/*
2 * linux/arch/mips/jz4740/time.c
3 *
4 * Setting up the clock on the JZ4740 boards.
5 *
6 * Copyright (C) 2008 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 */
23#include <linux/types.h>
24#include <linux/interrupt.h>
25#include <linux/time.h>
26#include <linux/clockchips.h>
27
28#include <asm/time.h>
29#include <asm/mach-jz4740/regs.h>
30#include <asm/mach-jz4740/jz4740.h>
31
32/* This is for machines which generate the exact clock. */
33
34#define JZ_TIMER_CHAN 0
35#define JZ_TIMER_IRQ JZ_IRQ_TCU0
36
37#define JZ_TIMER_CLOCK (JZ_EXTAL>>4) /* Jz timer clock frequency */
38
39static struct clocksource clocksource_jz; /* Jz clock source */
40static struct clock_event_device jz_clockevent_device; /* Jz clock event */
41
42void (*jz_timer_callback)(void);
43
44static irqreturn_t jz_timer_interrupt(int irq, void *dev_id)
45{
46    struct clock_event_device *cd = dev_id;
47
48    REG_TCU_TFCR = 1 << JZ_TIMER_CHAN; /* ACK timer */
49
50    if (jz_timer_callback)
51        jz_timer_callback();
52
53    cd->event_handler(cd);
54
55    return IRQ_HANDLED;
56}
57
58static struct irqaction jz_irqaction = {
59    .handler = jz_timer_interrupt,
60    .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
61    .name = "jz-timerirq",
62};
63
64
65cycle_t jz_get_cycles(void)
66{
67    /* convert jiffes to jz timer cycles */
68    return (cycle_t)( jiffies*((JZ_TIMER_CLOCK)/HZ) + REG_TCU_TCNT(JZ_TIMER_CHAN));
69}
70
71static struct clocksource clocksource_jz = {
72    .name = "jz_clocksource",
73    .rating = 300,
74    .read = jz_get_cycles,
75    .mask = 0xFFFF,
76    .shift = 10,
77    .flags = CLOCK_SOURCE_WATCHDOG,
78};
79
80static int __init jz_clocksource_init(void)
81{
82    clocksource_jz.mult = clocksource_hz2mult(JZ_TIMER_CLOCK, clocksource_jz.shift);
83    clocksource_register(&clocksource_jz);
84    return 0;
85}
86
87static int jz_set_next_event(unsigned long evt,
88                  struct clock_event_device *unused)
89{
90    return 0;
91}
92
93static void jz_set_mode(enum clock_event_mode mode,
94            struct clock_event_device *evt)
95{
96    switch (mode) {
97    case CLOCK_EVT_MODE_PERIODIC:
98                break;
99        case CLOCK_EVT_MODE_ONESHOT:
100        case CLOCK_EVT_MODE_UNUSED:
101        case CLOCK_EVT_MODE_SHUTDOWN:
102                break;
103        case CLOCK_EVT_MODE_RESUME:
104                break;
105        }
106}
107
108static struct clock_event_device jz_clockevent_device = {
109    .name = "jz-clockenvent",
110    .features = CLOCK_EVT_FEAT_PERIODIC,
111// .features = CLOCK_EVT_FEAT_ONESHOT, /* Jz4740 not support dynamic clock now */
112
113    /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
114    .mult = 1,
115    .rating = 300,
116    .irq = JZ_TIMER_IRQ,
117    .set_mode = jz_set_mode,
118    .set_next_event = jz_set_next_event,
119};
120
121static void __init jz_clockevent_init(void)
122{
123    struct clock_event_device *cd = &jz_clockevent_device;
124    unsigned int cpu = smp_processor_id();
125
126    cd->cpumask = cpumask_of(cpu);
127    clockevents_register_device(cd);
128}
129
130static void __init jz_timer_setup(void)
131{
132    jz_clocksource_init(); /* init jz clock source */
133    jz_clockevent_init(); /* init jz clock event */
134
135    /*
136     * Make irqs happen for the system timer
137     */
138    jz_irqaction.dev_id = &jz_clockevent_device;
139    setup_irq(JZ_TIMER_IRQ, &jz_irqaction);
140}
141
142
143void __init plat_time_init(void)
144{
145    unsigned int latch;
146    /* Init timer */
147    latch = ( JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
148
149    REG_TCU_TCSR(JZ_TIMER_CHAN) = TCU_TCSR_PRESCALE16 | TCU_TCSR_EXT_EN;
150    REG_TCU_TCNT(JZ_TIMER_CHAN) = 0;
151    REG_TCU_TDHR(JZ_TIMER_CHAN) = 0;
152    REG_TCU_TDFR(JZ_TIMER_CHAN) = latch;
153
154    REG_TCU_TMSR = (1 << (JZ_TIMER_CHAN + 16)); /* mask half irq */
155    REG_TCU_TMCR = (1 << JZ_TIMER_CHAN); /* unmask full irq */
156    REG_TCU_TSCR = (1 << JZ_TIMER_CHAN); /* enable timer clock */
157    REG_TCU_TESR = (1 << JZ_TIMER_CHAN); /* start counting up */
158
159    jz_timer_setup();
160}
drivers/misc/jz4740-adc.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC ADC driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 * This driver is meant to synchronize access to the adc core for the battery
15 * and touchscreen driver. Thus these drivers should use the adc driver as a
16 * parent.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/jz4740-adc.h>
25
26#define JZ_REG_ADC_ENABLE 0x00
27#define JZ_REG_ADC_CFG 0x04
28#define JZ_REG_ADC_CTRL 0x08
29#define JZ_REG_ADC_STATUS 0x0C
30#define JZ_REG_ADC_SAME 0x10
31#define JZ_REG_ADC_WAIT 0x14
32#define JZ_REG_ADC_TOUCH 0x18
33#define JZ_REG_ADC_BATTERY 0x1C
34#define JZ_REG_ADC_ADCIN 0x20
35
36#define JZ_ADC_ENABLE_TOUCH BIT(2)
37#define JZ_ADC_ENABLE_BATTERY BIT(1)
38#define JZ_ADC_ENABLE_ADCIN BIT(0)
39
40#define JZ_ADC_CFG_SPZZ BIT(31)
41#define JZ_ADC_CFG_EX_IN BIT(30)
42#define JZ_ADC_CFG_DNUM_MASK (0x7 << 16)
43#define JZ_ADC_CFG_DMA_ENABLE BIT(15)
44#define JZ_ADC_CFG_XYZ_MASK (0x2 << 13)
45#define JZ_ADC_CFG_SAMPLE_NUM_MASK (0x7 << 10)
46#define JZ_ADC_CFG_CLKDIV (0xf << 5)
47#define JZ_ADC_CFG_BAT_MB BIT(4)
48
49#define JZ_ADC_CFG_DNUM_OFFSET 16
50#define JZ_ADC_CFG_XYZ_OFFSET 13
51#define JZ_ADC_CFG_SAMPLE_NUM_OFFSET 10
52#define JZ_ADC_CFG_CLKDIV_OFFSET 5
53
54#define JZ_ADC_IRQ_PENDOWN BIT(4)
55#define JZ_ADC_IRQ_PENUP BIT(3)
56#define JZ_ADC_IRQ_TOUCH BIT(2)
57#define JZ_ADC_IRQ_BATTERY BIT(1)
58#define JZ_ADC_IRQ_ADCIN BIT(0)
59
60#define JZ_ADC_TOUCH_TYPE1 BIT(31)
61#define JZ_ADC_TOUCH_DATA1_MASK 0xfff
62#define JZ_ADC_TOUCH_TYPE0 BIT(15)
63#define JZ_ADC_TOUCH_DATA0_MASK 0xfff
64
65#define JZ_ADC_BATTERY_MASK 0xfff
66
67#define JZ_ADC_ADCIN_MASK 0xfff
68
69struct jz4740_adc {
70    struct resource *mem;
71    void __iomem *base;
72
73    int irq;
74
75    struct completion bat_completion;
76    struct completion adc_completion;
77
78    spinlock_t lock;
79};
80
81static irqreturn_t jz4740_adc_irq(int irq, void *data)
82{
83    struct jz4740_adc *adc = data;
84    uint8_t status;
85
86    status = readb(adc->base + JZ_REG_ADC_STATUS);
87
88    if (status & JZ_ADC_IRQ_BATTERY)
89        complete(&adc->bat_completion);
90    if (status & JZ_ADC_IRQ_ADCIN)
91        complete(&adc->adc_completion);
92
93    writeb(0xff, adc->base + JZ_REG_ADC_STATUS);
94
95    return IRQ_HANDLED;
96}
97
98static void jz4740_adc_enable_irq(struct jz4740_adc *adc, int irq)
99{
100    unsigned long flags;
101    uint8_t val;
102
103    spin_lock_irqsave(&adc->lock, flags);
104
105    val = readb(adc->base + JZ_REG_ADC_CTRL);
106    val &= ~irq;
107    writeb(val, adc->base + JZ_REG_ADC_CTRL);
108
109    spin_unlock_irqrestore(&adc->lock, flags);
110}
111
112static void jz4740_adc_disable_irq(struct jz4740_adc *adc, int irq)
113{
114    unsigned long flags;
115    uint8_t val;
116
117    spin_lock_irqsave(&adc->lock, flags);
118
119    val = readb(adc->base + JZ_REG_ADC_CTRL);
120    val |= irq;
121    writeb(val, adc->base + JZ_REG_ADC_CTRL);
122
123    spin_unlock_irqrestore(&adc->lock, flags);
124}
125
126static void jz4740_adc_enable_adc(struct jz4740_adc *adc, int engine)
127{
128    unsigned long flags;
129    uint8_t val;
130
131    spin_lock_irqsave(&adc->lock, flags);
132
133    val = readb(adc->base + JZ_REG_ADC_ENABLE);
134    val |= engine;
135    writeb(val, adc->base + JZ_REG_ADC_ENABLE);
136
137    spin_unlock_irqrestore(&adc->lock, flags);
138}
139
140static void jz4740_adc_disable_adc(struct jz4740_adc *adc, int engine)
141{
142    unsigned long flags;
143    uint8_t val;
144
145    spin_lock_irqsave(&adc->lock, flags);
146
147    val = readb(adc->base + JZ_REG_ADC_ENABLE);
148    val &= ~engine;
149    writeb(val, adc->base + JZ_REG_ADC_ENABLE);
150
151    spin_unlock_irqrestore(&adc->lock, flags);
152}
153
154static inline void jz4740_adc_set_cfg(struct jz4740_adc *adc, uint32_t mask,
155uint32_t val)
156{
157    unsigned long flags;
158    uint32_t cfg;
159
160    spin_lock_irqsave(&adc->lock, flags);
161
162    cfg = readl(adc->base + JZ_REG_ADC_CFG);
163
164    cfg &= ~mask;
165    cfg |= val;
166
167    writel(cfg, adc->base + JZ_REG_ADC_CFG);
168
169    spin_unlock_irqrestore(&adc->lock, flags);
170}
171
172long jz4740_adc_read_battery_voltage(struct device *dev,
173                        enum jz_adc_battery_scale scale)
174{
175    struct jz4740_adc *adc = dev_get_drvdata(dev);
176    unsigned long t;
177    long long voltage;
178    uint16_t val;
179
180    if (!adc)
181        return -ENODEV;
182
183    if (scale == JZ_ADC_BATTERY_SCALE_2V5)
184        jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, JZ_ADC_CFG_BAT_MB);
185    else
186        jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, 0);
187
188    jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_BATTERY);
189    jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_BATTERY);
190
191    t = wait_for_completion_interruptible_timeout(&adc->bat_completion,
192                            HZ);
193
194    jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_BATTERY);
195
196    if (t <= 0) {
197        jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_BATTERY);
198        return t ? t : -ETIMEDOUT;
199    }
200
201    val = readw(adc->base + JZ_REG_ADC_BATTERY);
202
203    if (scale == JZ_ADC_BATTERY_SCALE_2V5)
204        voltage = (((long long)val) * 2500000LL) >> 12LL;
205    else
206        voltage = ((((long long)val) * 7395000LL) >> 12LL) + 33000LL;
207
208    return voltage;
209}
210EXPORT_SYMBOL_GPL(jz4740_adc_read_battery_voltage);
211
212static ssize_t jz4740_adc_read_adcin(struct device *dev,
213                    struct device_attribute *dev_attr,
214                    char *buf)
215{
216    struct jz4740_adc *adc = dev_get_drvdata(dev);
217    unsigned long t;
218    uint16_t val;
219
220    jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_ADCIN);
221    jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_ADCIN);
222
223    t = wait_for_completion_interruptible_timeout(&adc->adc_completion,
224                            HZ);
225
226    jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_ADCIN);
227
228    if (t <= 0) {
229        jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_ADCIN);
230        return t ? t : -ETIMEDOUT;
231    }
232
233    val = readw(adc->base + JZ_REG_ADC_ADCIN);
234
235    return sprintf(buf, "%d\n", val);
236}
237
238static DEVICE_ATTR(adcin, S_IRUGO, jz4740_adc_read_adcin, NULL);
239
240static int __devinit jz4740_adc_probe(struct platform_device *pdev)
241{
242    int ret;
243    struct jz4740_adc *adc;
244
245    adc = kmalloc(sizeof(*adc), GFP_KERNEL);
246
247    adc->irq = platform_get_irq(pdev, 0);
248
249    if (adc->irq < 0) {
250        ret = adc->irq;
251        dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
252        goto err_free;
253    }
254
255    adc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
256
257    if (!adc->mem) {
258        ret = -ENOENT;
259        dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
260        goto err_free;
261    }
262
263    adc->mem = request_mem_region(adc->mem->start, resource_size(adc->mem),
264                    pdev->name);
265
266    if (!adc->mem) {
267        ret = -EBUSY;
268        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
269        goto err_free;
270    }
271
272    adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
273
274    if (!adc->base) {
275        ret = -EBUSY;
276        dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
277        goto err_release_mem_region;
278    }
279
280
281    init_completion(&adc->bat_completion);
282    init_completion(&adc->adc_completion);
283
284    spin_lock_init(&adc->lock);
285
286    platform_set_drvdata(pdev, adc);
287
288    ret = request_irq(adc->irq, jz4740_adc_irq, 0, pdev->name, adc);
289
290    if (ret) {
291        dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
292        goto err_iounmap;
293    }
294
295    ret = device_create_file(&pdev->dev, &dev_attr_adcin);
296    if (ret) {
297        dev_err(&pdev->dev, "Failed to create sysfs file: %d\n", ret);
298        goto err_free_irq;
299    }
300
301    writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
302    writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
303
304    return 0;
305
306err_free_irq:
307    free_irq(adc->irq, adc);
308err_iounmap:
309    platform_set_drvdata(pdev, NULL);
310    iounmap(adc->base);
311err_release_mem_region:
312    release_mem_region(adc->mem->start, resource_size(adc->mem));
313err_free:
314    kfree(adc);
315
316    return ret;
317}
318
319static int __devexit jz4740_adc_remove(struct platform_device *pdev)
320{
321    struct jz4740_adc *adc = platform_get_drvdata(pdev);
322
323    device_remove_file(&pdev->dev, &dev_attr_adcin);
324
325    free_irq(adc->irq, adc);
326
327    iounmap(adc->base);
328    release_mem_region(adc->mem->start, resource_size(adc->mem));
329
330    platform_set_drvdata(pdev, NULL);
331
332    kfree(adc);
333
334    return 0;
335}
336
337struct platform_driver jz4740_adc_driver = {
338    .probe = jz4740_adc_probe,
339    .remove = jz4740_adc_remove,
340    .driver = {
341        .name = "jz4740-adc",
342        .owner = THIS_MODULE,
343    },
344};
345
346static int __init jz4740_adc_init(void)
347{
348    return platform_driver_register(&jz4740_adc_driver);
349}
350module_init(jz4740_adc_init);
351
352static void __exit jz4740_adc_exit(void)
353{
354    platform_driver_unregister(&jz4740_adc_driver);
355}
356module_exit(jz4740_adc_exit);
357
358MODULE_DESCRIPTION("JZ4720/JZ4740 SoC ADC driver");
359MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
360MODULE_LICENSE("GPL");
361MODULE_ALIAS("platform:jz4740-adc");
362MODULE_ALIAS("platform:jz4720-adc");
drivers/mmc/host/jz_mmc.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 GPIO SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/mmc/host.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/scatterlist.h>
24#include <linux/clk.h>
25#include <linux/mmc/jz4740_mmc.h>
26
27#include <linux/gpio.h>
28#include <asm/mach-jz4740/gpio.h>
29#include <asm/cacheflush.h>
30
31#define JZ_REG_MMC_STRPCL 0x00
32#define JZ_REG_MMC_STATUS 0x04
33#define JZ_REG_MMC_CLKRT 0x08
34#define JZ_REG_MMC_CMDAT 0x0C
35#define JZ_REG_MMC_RESTO 0x10
36#define JZ_REG_MMC_RDTO 0x14
37#define JZ_REG_MMC_BLKLEN 0x18
38#define JZ_REG_MMC_NOB 0x1C
39#define JZ_REG_MMC_SNOB 0x20
40#define JZ_REG_MMC_IMASK 0x24
41#define JZ_REG_MMC_IREG 0x28
42#define JZ_REG_MMC_CMD 0x2C
43#define JZ_REG_MMC_ARG 0x30
44#define JZ_REG_MMC_RESP_FIFO 0x34
45#define JZ_REG_MMC_RXFIFO 0x38
46#define JZ_REG_MMC_TXFIFO 0x3C
47
48
49#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
50#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
51#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
52#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
53#define JZ_MMC_STRPCL_RESET BIT(3)
54#define JZ_MMC_STRPCL_START_OP BIT(2)
55#define JZ_MMC_STRPCL_CLOCK_CONTROL BIT(1) | BIT(0)
56#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
57#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
58
59
60#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
61#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
62#define JZ_MMC_STATUS_PRG_DONE BIT(13)
63#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
64#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
65#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
66#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
67#define JZ_MMC_STATUS_CLK_EN BIT(8)
68#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
69#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
70#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
71#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
72#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
73#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
74#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
75#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
76
77#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
78#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
79
80
81#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
82#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
83#define JZ_MMC_CMDAT_DMA_EN BIT(8)
84#define JZ_MMC_CMDAT_INIT BIT(7)
85#define JZ_MMC_CMDAT_BUSY BIT(6)
86#define JZ_MMC_CMDAT_STREAM BIT(5)
87#define JZ_MMC_CMDAT_WRITE BIT(4)
88#define JZ_MMC_CMDAT_DATA_EN BIT(3)
89#define JZ_MMC_CMDAT_RESPONSE_FORMAT BIT(2) | BIT(1) | BIT(0)
90#define JZ_MMC_CMDAT_RSP_R1 1
91#define JZ_MMC_CMDAT_RSP_R2 2
92#define JZ_MMC_CMDAT_RSP_R3 3
93
94#define JZ_MMC_IRQ_SDIO BIT(7)
95#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
96#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
97#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
98#define JZ_MMC_IRQ_PRG_DONE BIT(1)
99#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
100
101
102#define JZ_MMC_CLK_RATE 24000000
103
104
105struct jz4740_mmc_host {
106    struct mmc_host *mmc;
107    struct platform_device *pdev;
108    struct jz4740_mmc_platform_data *pdata;
109    struct clk *clk;
110
111    int irq;
112    int card_detect_irq;
113
114    struct resource *mem;
115    void __iomem *base;
116    struct mmc_request *req;
117    struct mmc_command *cmd;
118
119    int max_clock;
120    uint32_t cmdat;
121
122    spinlock_t lock;
123    struct timer_list clock_timer;
124    struct timer_list timeout_timer;
125    unsigned waiting:1;
126};
127
128static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
129
130static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
131{
132    uint16_t mask;
133    mask = readw(host->base + JZ_REG_MMC_IMASK);
134    mask &= ~irq;
135    writew(mask, host->base + JZ_REG_MMC_IMASK);
136}
137
138static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
139{
140    uint16_t mask;
141    mask = readw(host->base + JZ_REG_MMC_IMASK);
142    mask |= irq;
143    writew(mask, host->base + JZ_REG_MMC_IMASK);
144}
145
146static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
147{
148    uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
149
150    if (start_transfer)
151        val |= JZ_MMC_STRPCL_START_OP;
152
153    writew(val, host->base + JZ_REG_MMC_STRPCL);
154}
155
156static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
157{
158    uint16_t status;
159    writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
160    do {
161        status = readl(host->base + JZ_REG_MMC_STATUS);
162    } while (status & JZ_MMC_STATUS_CLK_EN);
163
164}
165
166static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
167{
168    writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
169    udelay(10);
170    while(readw(host->base + JZ_REG_MMC_STATUS) & JZ_MMC_STATUS_IS_RESETTING);
171}
172
173static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
174{
175    struct mmc_request *req;
176    unsigned long flags;
177
178    spin_lock_irqsave(&host->lock, flags);
179    req = host->req;
180    host->req = NULL;
181    spin_unlock_irqrestore(&host->lock, flags);
182
183    if (!unlikely(req))
184        return;
185
186    if (req->cmd->error != 0)
187        jz4740_mmc_reset(host);
188    mmc_request_done(host->mmc, req);
189}
190
191static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
192    struct scatterlist *sg;
193    uint32_t *sg_pointer;
194    int i, status;
195
196    for (sg = data->sg; sg; sg = sg_next(sg)) {
197        sg_pointer = page_address(sg_page(sg)) + sg->offset;
198        i = 0;
199        while (i < sg->length) {
200            do {
201                status = readl(host->base + JZ_REG_MMC_STATUS);
202                if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
203                    goto err;
204            } while (status & JZ_MMC_STATUS_DATA_FIFO_FULL);
205            writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
206            ++sg_pointer;
207            i += 4;
208        }
209        data->bytes_xfered += sg->length;
210    }
211    do {
212        status = readl(host->base + JZ_REG_MMC_STATUS);
213    } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0);
214
215    return;
216
217err:
218    if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
219        host->cmd->error = -ETIMEDOUT;
220        data->error = -ETIMEDOUT;
221    } else {
222        host->cmd->error = -EILSEQ;
223        data->error = -EILSEQ;
224    }
225}
226
227static void jz4740_mmc_timeout(unsigned long data)
228{
229    struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)host;
230    unsigned long flags;
231
232    spin_lock_irqsave(&host->lock, flags);
233    if (!host->waiting) {
234        spin_unlock_irqrestore(&host->lock, flags);
235        return;
236    }
237
238    host->waiting = 0;
239
240    spin_unlock_irqrestore(&host->lock, flags);
241
242    host->cmd->error = -ETIMEDOUT;
243    jz4740_mmc_request_done(host);
244}
245
246static void jz4740_mmc_read_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
247    struct scatterlist *sg;
248    void *sg_pointer;
249    uint32_t d;
250    int status = 0;
251    size_t i = 0;
252
253    for (sg = data->sg; sg; sg = sg_next(sg)) {
254        sg_pointer = sg_virt(sg);
255        i = sg->length;
256        while (i >= 4) {
257            do {
258                status = readl(host->base + JZ_REG_MMC_STATUS);
259                if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
260                    goto err;
261            } while (status & JZ_MMC_STATUS_DATA_FIFO_EMPTY);
262            d = readl(host->base + JZ_REG_MMC_RXFIFO);
263            memcpy(sg_pointer, &d, 4);
264
265            sg_pointer += 4;
266            i -= 4;
267        }
268        if (i > 0) {
269            d = readl(host->base + JZ_REG_MMC_RXFIFO);
270            memcpy(sg_pointer, &d, i);
271        }
272        data->bytes_xfered += sg->length;
273
274        flush_dcache_page(sg_page(sg));
275    }
276
277    /* For whatever reason there is sometime one word more in the fifo then
278     * requested */
279    while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0) {
280        d = readl(host->base + JZ_REG_MMC_RXFIFO);
281        status = readl(host->base + JZ_REG_MMC_STATUS);
282    }
283    return;
284
285err:
286    if(status & JZ_MMC_STATUS_TIMEOUT_READ) {
287        host->cmd->error = -ETIMEDOUT;
288        data->error = -ETIMEDOUT;
289    } else {
290        host->cmd->error = -EILSEQ;
291        data->error = -EILSEQ;
292    }
293}
294
295static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
296{
297    struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)devid;
298
299    if (host->cmd->error)
300        jz4740_mmc_request_done(host);
301    else
302        jz4740_mmc_cmd_done(host);
303
304    return IRQ_HANDLED;
305}
306
307static irqreturn_t jz_mmc_irq(int irq, void *devid)
308{
309    struct jz4740_mmc_host *host = devid;
310    uint16_t irq_reg, status;
311    unsigned long flags;
312    irqreturn_t ret = IRQ_HANDLED;
313
314    if (!host->req || !host->cmd) {
315        return IRQ_HANDLED;
316    }
317
318    spin_lock_irqsave(&host->lock, flags);
319    if (!host->waiting) {
320        spin_unlock_irqrestore(&host->lock, flags);
321        return IRQ_HANDLED;
322    }
323    host->waiting = 0;
324    spin_unlock_irqrestore(&host->lock, flags);
325
326    del_timer(&host->timeout_timer);
327
328    irq_reg = readw(host->base + JZ_REG_MMC_IREG);
329    status = readl(host->base + JZ_REG_MMC_STATUS);
330
331    if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
332        host->cmd->error = -ETIMEDOUT;
333    } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
334        host->cmd->error = -EIO;
335    } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
336                        JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
337        host->cmd->data->error = -EIO;
338    } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
339                        JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
340        host->cmd->data->error = -ETIMEDOUT;
341    }
342
343    if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
344        jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
345        writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
346        ret = IRQ_WAKE_THREAD;
347    }
348
349    if (irq_reg & JZ_MMC_IRQ_SDIO) {
350        writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
351        mmc_signal_sdio_irq(host->mmc);
352    }
353    writew(0xff, host->base + JZ_REG_MMC_IREG);
354
355    return ret;
356}
357
358static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
359    int div = 0;
360    int real_rate = host->max_clock;
361    jz4740_mmc_clock_disable(host);
362
363    while ((real_rate >> 1) >= rate && div < 7) {
364        ++div;
365        real_rate >>= 1;
366    }
367    clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
368
369    writew(div, host->base + JZ_REG_MMC_CLKRT);
370    return real_rate;
371}
372
373
374static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
375{
376    int i;
377    uint16_t tmp;
378    if (cmd->flags & MMC_RSP_136) {
379        tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
380        for (i = 0; i < 4; ++i) {
381            cmd->resp[i] = tmp << 24;
382            cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
383            tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
384            cmd->resp[i] |= tmp >> 8;
385        }
386    } else {
387        cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
388        cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
389        cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
390    }
391}
392
393static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
394{
395    uint32_t cmdat = host->cmdat;
396
397    host->cmdat &= ~JZ_MMC_CMDAT_INIT;
398    jz4740_mmc_clock_disable(host);
399
400    host->cmd = cmd;
401
402    if (cmd->flags & MMC_RSP_BUSY)
403        cmdat |= JZ_MMC_CMDAT_BUSY;
404
405    switch (mmc_resp_type(cmd)) {
406    case MMC_RSP_R1B:
407    case MMC_RSP_R1:
408        cmdat |= JZ_MMC_CMDAT_RSP_R1;
409        break;
410    case MMC_RSP_R2:
411        cmdat |= JZ_MMC_CMDAT_RSP_R2;
412        break;
413    case MMC_RSP_R3:
414        cmdat |= JZ_MMC_CMDAT_RSP_R3;
415        break;
416    default:
417        break;
418    }
419
420    if (cmd->data) {
421        cmdat |= JZ_MMC_CMDAT_DATA_EN;
422        if (cmd->data->flags & MMC_DATA_WRITE)
423            cmdat |= JZ_MMC_CMDAT_WRITE;
424        if (cmd->data->flags & MMC_DATA_STREAM)
425            cmdat |= JZ_MMC_CMDAT_STREAM;
426
427        writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
428        writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
429    }
430
431    writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
432    writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
433    writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
434
435    host->waiting = 1;
436    jz4740_mmc_clock_enable(host, 1);
437    mod_timer(&host->timeout_timer, HZ);
438}
439
440static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
441{
442    uint32_t status;
443    struct mmc_command *cmd = host->req->cmd;
444    struct mmc_request *req = host->req;
445    status = readl(host->base + JZ_REG_MMC_STATUS);
446
447    if (cmd->flags & MMC_RSP_PRESENT)
448        jz4740_mmc_read_response(host, cmd);
449
450    if (cmd->data) {
451        if (cmd->data->flags & MMC_DATA_READ)
452            jz4740_mmc_read_data(host, cmd->data);
453        else
454            jz4740_mmc_write_data(host, cmd->data);
455    }
456
457    if (req->stop) {
458        jz4740_mmc_send_command(host, req->stop);
459        do {
460            status = readl(host->base + JZ_REG_MMC_STATUS);
461        } while ((status & JZ_MMC_STATUS_PRG_DONE) == 0);
462    }
463
464    jz4740_mmc_request_done(host);
465}
466
467static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
468{
469    struct jz4740_mmc_host *host = mmc_priv(mmc);
470
471    host->req = req;
472
473    writel(0xffffffff, host->base + JZ_REG_MMC_IREG);
474
475    writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
476    jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
477    jz4740_mmc_send_command(host, req->cmd);
478}
479
480
481static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
482{
483    struct jz4740_mmc_host *host = mmc_priv(mmc);
484    if (ios->clock)
485        jz4740_mmc_set_clock_rate(host, ios->clock);
486
487    switch(ios->power_mode) {
488    case MMC_POWER_UP:
489        if (gpio_is_valid(host->pdata->gpio_power))
490            gpio_set_value(host->pdata->gpio_power, 0);
491        host->cmdat |= JZ_MMC_CMDAT_INIT;
492        clk_enable(host->clk);
493        break;
494    case MMC_POWER_ON:
495        break;
496    default:
497        if (gpio_is_valid(host->pdata->gpio_power))
498            gpio_set_value(host->pdata->gpio_power, 1);
499        clk_disable(host->clk);
500        break;
501    }
502
503    switch(ios->bus_width) {
504    case MMC_BUS_WIDTH_1:
505        host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
506        break;
507    case MMC_BUS_WIDTH_4:
508        host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
509        break;
510    default:
511        dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
512    }
513}
514
515static int jz4740_mmc_get_ro(struct mmc_host *mmc)
516{
517    struct jz4740_mmc_host *host = mmc_priv(mmc);
518    if (!gpio_is_valid(host->pdata->gpio_read_only))
519        return -ENOSYS;
520
521    return gpio_get_value(host->pdata->gpio_read_only) ^
522        host->pdata->read_only_active_low;
523}
524
525static int jz4740_mmc_get_cd(struct mmc_host *mmc)
526{
527    struct jz4740_mmc_host *host = mmc_priv(mmc);
528    if (!gpio_is_valid(host->pdata->gpio_card_detect))
529        return -ENOSYS;
530
531    return gpio_get_value(host->pdata->gpio_card_detect) ^
532            host->pdata->card_detect_active_low;
533}
534
535static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
536{
537    struct jz4740_mmc_host *host = devid;
538
539    mmc_detect_change(host->mmc, HZ / 3);
540
541    return IRQ_HANDLED;
542}
543
544static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
545{
546    struct jz4740_mmc_host *host = mmc_priv(mmc);
547    if (enable)
548        jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
549    else
550        jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
551}
552
553static const struct mmc_host_ops jz4740_mmc_ops = {
554    .request = jz4740_mmc_request,
555    .set_ios = jz4740_mmc_set_ios,
556    .get_ro = jz4740_mmc_get_ro,
557    .get_cd = jz4740_mmc_get_cd,
558    .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
559};
560
561static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
562    JZ_GPIO_BULK_PIN(MSC_CMD),
563    JZ_GPIO_BULK_PIN(MSC_CLK),
564    JZ_GPIO_BULK_PIN(MSC_DATA0),
565    JZ_GPIO_BULK_PIN(MSC_DATA1),
566    JZ_GPIO_BULK_PIN(MSC_DATA2),
567    JZ_GPIO_BULK_PIN(MSC_DATA3),
568};
569
570static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
571{
572    int ret;
573    struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
574
575    if (!pdata)
576        return 0;
577
578    if (gpio_is_valid(pdata->gpio_card_detect)) {
579        ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
580        if (ret) {
581            dev_err(&pdev->dev, "Failed to request detect change gpio\n");
582            goto err;
583        }
584        gpio_direction_input(pdata->gpio_card_detect);
585    }
586
587    if (gpio_is_valid(pdata->gpio_read_only)) {
588        ret = gpio_request(pdata->gpio_read_only, "MMC read only");
589        if (ret) {
590            dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
591            goto err_free_gpio_card_detect;
592        }
593        gpio_direction_input(pdata->gpio_read_only);
594    }
595
596    if (gpio_is_valid(pdata->gpio_power)) {
597        ret = gpio_request(pdata->gpio_power, "MMC power");
598        if (ret) {
599            dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
600            goto err_free_gpio_read_only;
601        }
602        gpio_direction_output(pdata->gpio_card_detect, 1);
603    }
604
605    return 0;
606
607err_free_gpio_read_only:
608    if (gpio_is_valid(pdata->gpio_read_only))
609        gpio_free(pdata->gpio_read_only);
610err_free_gpio_card_detect:
611    if (gpio_is_valid(pdata->gpio_card_detect))
612        gpio_free(pdata->gpio_card_detect);
613err:
614    return ret;
615}
616
617static void jz4740_mmc_free_gpios(struct platform_device *pdev)
618{
619    struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
620
621    if (!pdata)
622        return;
623
624    if (gpio_is_valid(pdata->gpio_power))
625        gpio_free(pdata->gpio_power);
626    if (gpio_is_valid(pdata->gpio_read_only))
627        gpio_free(pdata->gpio_read_only);
628    if (gpio_is_valid(pdata->gpio_card_detect))
629        gpio_free(pdata->gpio_card_detect);
630}
631
632static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
633{
634    int ret;
635    struct mmc_host *mmc;
636    struct jz4740_mmc_host *host;
637    struct jz4740_mmc_platform_data *pdata;
638
639    pdata = pdev->dev.platform_data;
640
641    mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
642
643    if (!mmc) {
644        dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
645        return -ENOMEM;
646    }
647
648    host = mmc_priv(mmc);
649
650    host->irq = platform_get_irq(pdev, 0);
651
652    if (host->irq < 0) {
653        ret = host->irq;
654        dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
655        goto err_free_host;
656    }
657
658    host->clk = clk_get(&pdev->dev, "mmc");
659    if (!host->clk) {
660        ret = -ENOENT;
661        dev_err(&pdev->dev, "Failed to get mmc clock\n");
662        goto err_free_host;
663    }
664
665    host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
666
667    if (!host->mem) {
668        ret = -ENOENT;
669        dev_err(&pdev->dev, "Failed to get base platform memory\n");
670        goto err_clk_put;
671    }
672
673    host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
674                    pdev->name);
675
676    if (!host->mem) {
677        ret = -EBUSY;
678        dev_err(&pdev->dev, "Failed to request base memory region\n");
679        goto err_clk_put;
680    }
681
682    host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
683
684    if (!host->base) {
685        ret = -EBUSY;
686        dev_err(&pdev->dev, "Failed to ioremap base memory\n");
687        goto err_release_mem_region;
688    }
689
690    if (pdata && pdata->data_1bit)
691        ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
692    else
693        ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
694
695    if (ret) {
696        dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
697        goto err_iounmap;
698    }
699
700    ret = jz4740_mmc_request_gpios(pdev);
701    if (ret)
702        goto err_gpio_bulk_free;
703
704    mmc->ops = &jz4740_mmc_ops;
705    mmc->f_min = JZ_MMC_CLK_RATE / 128;
706    mmc->f_max = JZ_MMC_CLK_RATE;
707    mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
708    mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
709    mmc->max_seg_size = 4096;
710    mmc->max_phys_segs = 10;
711
712    mmc->max_blk_size = (1 << 10) - 1;
713    mmc->max_blk_count = (1 << 15) - 1;
714    mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
715
716    host->mmc = mmc;
717    host->pdev = pdev;
718    host->pdata = pdata;
719    host->max_clock = JZ_MMC_CLK_RATE;
720
721    host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
722
723    if (host->card_detect_irq < 0) {
724        dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
725    } else {
726        ret = request_irq(host->card_detect_irq,
727                jz4740_mmc_card_detect_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC/SD detect changed", host);
728
729        if (ret) {
730            dev_err(&pdev->dev, "Failed to request card detect irq");
731            goto err_free_gpios;
732        }
733    }
734
735    ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, "MMC/SD", host);
736    if (ret) {
737        dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
738        goto err_free_card_detect_irq;
739    }
740
741    jz4740_mmc_reset(host);
742    jz4740_mmc_clock_disable(host);
743    setup_timer(&host->timeout_timer, jz4740_mmc_timeout, (unsigned long)host);
744
745    platform_set_drvdata(pdev, host);
746    ret = mmc_add_host(mmc);
747
748    if (ret) {
749        dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
750        goto err_free_irq;
751    }
752    printk("JZ SD/MMC card driver registered\n");
753
754    return 0;
755
756err_free_irq:
757    free_irq(host->irq, host);
758err_free_card_detect_irq:
759    if (host->card_detect_irq >= 0)
760        free_irq(host->card_detect_irq, host);
761err_free_gpios:
762    jz4740_mmc_free_gpios(pdev);
763err_gpio_bulk_free:
764    if (pdata && pdata->data_1bit)
765        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
766    else
767        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
768err_iounmap:
769    iounmap(host->base);
770err_release_mem_region:
771    release_mem_region(host->mem->start, resource_size(host->mem));
772err_clk_put:
773    clk_put(host->clk);
774err_free_host:
775    platform_set_drvdata(pdev, NULL);
776    mmc_free_host(mmc);
777
778    return ret;
779}
780
781static int jz4740_mmc_remove(struct platform_device *pdev)
782{
783    struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
784    struct jz4740_mmc_platform_data *pdata = host->pdata;
785
786    del_timer_sync(&host->timeout_timer);
787    jz4740_mmc_disable_irq(host, 0xff);
788    jz4740_mmc_reset(host);
789
790    mmc_remove_host(host->mmc);
791
792    free_irq(host->irq, host);
793    if (host->card_detect_irq >= 0)
794        free_irq(host->card_detect_irq, host);
795
796    jz4740_mmc_free_gpios(pdev);
797    if (pdata && pdata->data_1bit)
798        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
799    else
800        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
801
802    iounmap(host->base);
803    release_mem_region(host->mem->start, resource_size(host->mem));
804
805    clk_put(host->clk);
806
807    platform_set_drvdata(pdev, NULL);
808    mmc_free_host(host->mmc);
809
810    return 0;
811}
812
813#ifdef CONFIG_PM
814static int jz4740_mmc_suspend(struct device *dev)
815{
816    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
817
818    /* TODO: Set gpio pins to high Z */
819
820    mmc_suspend_host(host->mmc, PMSG_SUSPEND);
821
822    return 0;
823}
824
825static int jz4740_mmc_resume(struct device *dev)
826{
827    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
828
829    mmc_resume_host(host->mmc);
830
831    return 0;
832}
833
834struct dev_pm_ops jz4740_mmc_pm_ops = {
835    .suspend = jz4740_mmc_suspend,
836    .resume = jz4740_mmc_resume,
837    .poweroff = jz4740_mmc_suspend,
838    .restore = jz4740_mmc_resume,
839};
840
841#define jz4740_mmc_PM_OPS (&jz4740_mmc_pm_ops)
842#else
843#define jz4740_mmc_PM_OPS NULL
844#endif
845
846static struct platform_driver jz4740_mmc_driver = {
847    .probe = jz4740_mmc_probe,
848    .remove = jz4740_mmc_remove,
849    .driver = {
850        .name = "jz4740-mmc",
851        .owner = THIS_MODULE,
852        .pm = jz4740_mmc_PM_OPS,
853    },
854};
855
856static int __init jz4740_mmc_init(void) {
857    return platform_driver_register(&jz4740_mmc_driver);
858}
859module_init(jz4740_mmc_init);
860
861static void __exit jz4740_mmc_exit(void) {
862    platform_driver_unregister(&jz4740_mmc_driver);
863}
864module_exit(jz4740_mmc_exit);
865
866MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
867MODULE_LICENSE("GPLv2");
868MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
drivers/mtd/nand/jz4740_nand.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC NAND controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
22
23#include <linux/mtd/jz4740_nand.h>
24#include <linux/gpio.h>
25
26#define JZ_REG_NAND_CTRL 0x50
27#define JZ_REG_NAND_ECC_CTRL 0x100
28#define JZ_REG_NAND_DATA 0x104
29#define JZ_REG_NAND_PAR0 0x108
30#define JZ_REG_NAND_PAR1 0x10C
31#define JZ_REG_NAND_PAR2 0x110
32#define JZ_REG_NAND_IRQ_STAT 0x114
33#define JZ_REG_NAND_IRQ_CTRL 0x118
34#define JZ_REG_NAND_ERR(x) (0x11C + (x << 2))
35
36#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
37#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
38#define JZ_NAND_ECC_CTRL_RS BIT(2)
39#define JZ_NAND_ECC_CTRL_RESET BIT(1)
40#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
41
42#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
43#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
44#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
45#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
46#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
47#define JZ_NAND_STATUS_ERROR BIT(0)
48
49#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT(x << 1)
50#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT((x << 1) + 1)
51
52#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
53#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
54#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
55
56struct jz_nand {
57    struct mtd_info mtd;
58    struct nand_chip chip;
59    void __iomem *base;
60    struct resource *mem;
61
62    struct jz_nand_platform_data *pdata;
63};
64
65static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
66{
67    return container_of(mtd, struct jz_nand, mtd);
68}
69
70static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
71{
72    struct jz_nand *nand = mtd_to_jz_nand(mtd);
73    struct nand_chip *chip = mtd->priv;
74    uint32_t reg;
75
76    if (ctrl & NAND_CTRL_CHANGE) {
77        BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
78        if (ctrl & NAND_ALE)
79            chip->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
80        else if (ctrl & NAND_CLE)
81            chip->IO_ADDR_W = JZ_NAND_CMD_ADDR;
82        else
83            chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
84
85        reg = readl(nand->base + JZ_REG_NAND_CTRL);
86        if ( ctrl & NAND_NCE )
87            reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
88        else
89            reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
90        writel(reg, nand->base + JZ_REG_NAND_CTRL);
91    }
92    if (dat != NAND_CMD_NONE)
93        writeb(dat, chip->IO_ADDR_W);
94}
95
96static int jz_nand_dev_ready(struct mtd_info *mtd)
97{
98    struct jz_nand *nand = mtd_to_jz_nand(mtd);
99    return gpio_get_value_cansleep(nand->pdata->busy_gpio);
100}
101
102static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
103{
104    struct jz_nand *nand = mtd_to_jz_nand(mtd);
105    uint32_t reg;
106
107
108    writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
109    reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
110
111    reg |= JZ_NAND_ECC_CTRL_RESET;
112    reg |= JZ_NAND_ECC_CTRL_ENABLE;
113    reg |= JZ_NAND_ECC_CTRL_RS;
114
115    switch(mode) {
116    case NAND_ECC_READ:
117        reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
118        break;
119    case NAND_ECC_WRITE:
120        reg |= JZ_NAND_ECC_CTRL_ENCODING;
121        break;
122    default:
123        break;
124    }
125
126    writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
127}
128
129static int jz_nand_calculate_ecc_rs(struct mtd_info* mtd, const uint8_t* dat,
130                    uint8_t *ecc_code)
131{
132    struct jz_nand *nand = mtd_to_jz_nand(mtd);
133    uint32_t reg, status;
134    int i;
135
136    do {
137        status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
138    } while(!(status & JZ_NAND_STATUS_ENC_FINISH));
139
140    reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
141    reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
142    writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
143
144    for (i = 0; i < 9; ++i) {
145        ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
146    }
147
148    return 0;
149}
150
151static void correct_data(uint8_t *dat, int index, int mask)
152{
153    int offset = index & 0x7;
154    uint16_t data;
155    printk("correct: ");
156
157    index += (index >> 3);
158
159    data = dat[index];
160    data |= dat[index+1] << 8;
161
162    printk("0x%x -> ", data);
163
164    mask ^= (data >> offset) & 0x1ff;
165    data &= ~(0x1ff << offset);
166    data |= (mask << offset);
167
168    printk("0x%x\n", data);
169
170    dat[index] = data & 0xff;
171    dat[index+1] = (data >> 8) & 0xff;
172}
173
174static int jz_nand_correct_ecc_rs(struct mtd_info* mtd, uint8_t *dat,
175                  uint8_t *read_ecc, uint8_t *calc_ecc)
176{
177    struct jz_nand *nand = mtd_to_jz_nand(mtd);
178    int i, error_count, index;
179    uint32_t reg, status, error;
180
181    for(i = 0; i < 9; ++i) {
182        if (read_ecc[i] != 0xff)
183            break;
184    }
185    if (i == 9) {
186        for (i = 0; i < nand->chip.ecc.size; ++i) {
187            if (dat[i] != 0xff)
188                break;
189        }
190        if (i == nand->chip.ecc.size)
191            return 0;
192    }
193
194    for(i = 0; i < 9; ++i)
195        writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
196
197    reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
198    reg |= JZ_NAND_ECC_CTRL_PAR_READY;
199    writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
200
201    do {
202        status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
203    } while (!(status & JZ_NAND_STATUS_DEC_FINISH));
204
205    reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
206    reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
207    writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
208
209    if (status & JZ_NAND_STATUS_ERROR) {
210        if (status & JZ_NAND_STATUS_UNCOR_ERROR) {
211            printk("uncorrectable ecc:");
212            for(i = 0; i < 9; ++i)
213                printk(" 0x%x", read_ecc[i]);
214            printk("\n");
215            printk("uncorrectable data:");
216            for(i = 0; i < 32; ++i)
217                printk(" 0x%x", dat[i]);
218            printk("\n");
219            return -1;
220        }
221
222        error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
223
224        printk("error_count: %d %x\n", error_count, status);
225
226        for(i = 0; i < error_count; ++i) {
227            error = readl(nand->base + JZ_REG_NAND_ERR(i));
228            index = ((error >> 16) & 0x1ff) - 1;
229            if (index >= 0 && index < 512) {
230                correct_data(dat, index, error & 0x1ff);
231            }
232        }
233
234        return error_count;
235    }
236
237    return 0;
238}
239
240
241
242#ifdef CONFIG_MTD_CMDLINE_PARTS
243static const char *part_probes[] = {"cmdline", NULL};
244#endif
245
246static int __devinit jz_nand_probe(struct platform_device *pdev)
247{
248    int ret;
249    struct jz_nand *nand;
250    struct nand_chip *chip;
251    struct mtd_info *mtd;
252    struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
253#ifdef CONFIG_MTD_PARTITIONS
254    struct mtd_partition *partition_info;
255    int num_partitions = 0;
256#endif
257
258    nand = kzalloc(sizeof(*nand), GFP_KERNEL);
259    if (!nand) {
260        dev_err(&pdev->dev, "Failed to allocate device structure.\n");
261        return -ENOMEM;
262    }
263
264    nand->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265    if (!nand->mem) {
266        dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
267        ret = -ENOENT;
268        goto err_free;
269    }
270
271    nand->mem = request_mem_region(nand->mem->start, resource_size(nand->mem),
272                    pdev->name);
273
274    if (!nand->mem) {
275        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
276        ret = -EBUSY;
277        goto err_free;
278    }
279
280    nand->base = ioremap(nand->mem->start, resource_size(nand->mem));
281
282    if (!nand->base) {
283        dev_err(&pdev->dev, "Faild to ioremap mmio memory region\n");
284        ret = -EBUSY;
285        goto err_release_mem;
286    }
287
288    if (pdata && gpio_is_valid(pdata->busy_gpio)) {
289        ret = gpio_request(pdata->busy_gpio, "jz nand busy line");
290        if (ret) {
291            dev_err(&pdev->dev, "Failed to request busy gpio %d: %d\n",
292                    pdata->busy_gpio, ret);
293            goto err_iounmap;
294        }
295    }
296
297    mtd = &nand->mtd;
298    chip = &nand->chip;
299    mtd->priv = chip;
300    mtd->owner = THIS_MODULE;
301    mtd->name = "jz4740-nand";
302
303    chip->ecc.hwctl = jz_nand_hwctl;
304
305    chip->ecc.calculate = jz_nand_calculate_ecc_rs;
306    chip->ecc.correct = jz_nand_correct_ecc_rs;
307    chip->ecc.mode = NAND_ECC_HW;
308    chip->ecc.size = 512;
309    chip->ecc.bytes = 9;
310    if (pdata)
311        chip->ecc.layout = pdata->ecc_layout;
312
313    chip->chip_delay = 50;
314    chip->cmd_ctrl = jz_nand_cmd_ctrl;
315
316    if (pdata && gpio_is_valid(pdata->busy_gpio))
317        chip->dev_ready = jz_nand_dev_ready;
318
319    chip->IO_ADDR_R = JZ_NAND_DATA_ADDR;
320    chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
321
322    nand->pdata = pdata;
323    platform_set_drvdata(pdev, nand);
324
325    ret = nand_scan_ident(mtd, 1);
326    if (ret) {
327        dev_err(&pdev->dev, "Failed to scan nand\n");
328        goto err_gpio_free;
329    }
330
331    if (pdata && pdata->ident_callback) {
332        pdata->ident_callback(pdev, chip, &pdata->partitions, &pdata->num_partitions);
333    }
334
335    ret = nand_scan_tail(mtd);
336    if (ret) {
337        dev_err(&pdev->dev, "Failed to scan nand\n");
338        goto err_gpio_free;
339    }
340
341#ifdef CONFIG_MTD_PARTITIONS
342#ifdef CONFIG_MTD_CMDLINE_PARTS
343    num_partitions = parse_mtd_partitions(mtd, part_probes,
344                        &partition_info, 0);
345#endif
346    if (num_partitions <= 0 && pdata) {
347        num_partitions = pdata->num_partitions;
348        partition_info = pdata->partitions;
349    }
350
351    if (num_partitions > 0)
352        ret = add_mtd_partitions(mtd, partition_info, num_partitions);
353    else
354#endif
355    ret = add_mtd_device(mtd);
356
357    if (ret) {
358        dev_err(&pdev->dev, "Failed to add mtd device\n");
359        goto err_nand_release;
360    }
361
362    dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
363
364    return 0;
365err_nand_release:
366    nand_release(&nand->mtd);
367err_gpio_free:
368    platform_set_drvdata(pdev, NULL);
369    gpio_free(pdata->busy_gpio);
370err_iounmap:
371    iounmap(nand->base);
372err_release_mem:
373    release_mem_region(nand->mem->start, resource_size(nand->mem));
374err_free:
375    kfree(nand);
376    return ret;
377}
378
379static void __devexit jz_nand_remove(struct platform_device *pdev)
380{
381    struct jz_nand *nand = platform_get_drvdata(pdev);
382
383    nand_release(&nand->mtd);
384
385    iounmap(nand->base);
386
387    release_mem_region(nand->mem->start, resource_size(nand->mem));
388
389    platform_set_drvdata(pdev, NULL);
390    kfree(nand);
391}
392
393struct platform_driver jz_nand_driver = {
394    .probe = jz_nand_probe,
395    .remove = __devexit_p(jz_nand_probe),
396    .driver = {
397        .name = "jz4740-nand",
398        .owner = THIS_MODULE,
399    },
400};
401
402static int __init jz_nand_init(void)
403{
404    return platform_driver_register(&jz_nand_driver);
405}
406module_init(jz_nand_init);
407
408static void __exit jz_nand_exit(void)
409{
410    platform_driver_unregister(&jz_nand_driver);
411}
412module_exit(jz_nand_exit);
413
414MODULE_LICENSE("GPL");
415MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
416MODULE_DESCRIPTION("NAND controller driver for JZ4720/JZ4740 SoC");
417MODULE_ALIAS("platform:jz4740-nand");
418MODULE_ALIAS("platform:jz4720-nand");
drivers/power/jz4740-battery.c
1/*
2 * Battery measurement code for Ingenic JZ SOC.
3 *
4 * based on tosa_battery.c
5 *
6 * Copyright (C) 2008 Marek Vasut <marek.vasut@gmail.com>
7 * Copyright (C) 2009 Jiejing Zhang <kzjeef@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/power_supply.h>
17#include <linux/delay.h>
18#include <linux/spinlock.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22
23#include <linux/power/jz4740-battery.h>
24#include <linux/jz4740-adc.h>
25
26struct jz_battery_info {
27    struct power_supply usb;
28    struct power_supply bat;
29    struct power_supply ac;
30    int bat_status;
31    struct jz_batt_info *pdata;
32    struct mutex work_lock;
33    struct workqueue_struct *monitor_wqueue;
34    struct delayed_work bat_work;
35};
36
37#define ps_to_jz_battery(x) container_of((x), struct jz_battery_info, bat);
38
39/*********************************************************************
40 * Power
41 *********************************************************************/
42
43
44static int jz_get_power_prop(struct jz_battery_info *bat_info,
45                 struct power_supply *psy,
46                 enum power_supply_property psp,
47                 union power_supply_propval *val)
48{
49    int gpio;
50
51    if (bat_info == 0 || bat_info->pdata == 0)
52        return -EINVAL;
53    gpio = (psy->type == POWER_SUPPLY_TYPE_MAINS) ?
54        bat_info->pdata->dc_dect_gpio :
55        bat_info->pdata->usb_dect_gpio;
56    if (!gpio_is_valid(gpio))
57        return -EINVAL;
58    switch (psp) {
59    case POWER_SUPPLY_PROP_ONLINE:
60        val->intval = !gpio_get_value(gpio);
61        break;
62    default:
63        return -EINVAL;
64    }
65
66    return 0;
67}
68
69static int jz_usb_get_power_prop(struct power_supply *psy,
70                 enum power_supply_property psp,
71                 union power_supply_propval *val)
72{
73    struct jz_battery_info *bat_info = container_of(psy, struct jz_battery_info, usb);
74    return jz_get_power_prop(bat_info, psy, psp, val);
75}
76
77static int jz_ac_get_power_prop(struct power_supply *psy,
78                 enum power_supply_property psp,
79                 union power_supply_propval *val)
80{
81    struct jz_battery_info *bat_info = container_of(psy, struct jz_battery_info, ac);
82    return jz_get_power_prop(bat_info, psy, psp, val);
83}
84
85
86static enum power_supply_property jz_power_props[] = {
87    POWER_SUPPLY_PROP_ONLINE,
88};
89
90static struct power_supply jz_ac = {
91    .name = "ac",
92    .type = POWER_SUPPLY_TYPE_MAINS,
93    .properties = jz_power_props,
94    .num_properties = ARRAY_SIZE(jz_power_props),
95    .get_property = jz_ac_get_power_prop,
96};
97
98static struct power_supply jz_usb = {
99    .name = "usb",
100    .type = POWER_SUPPLY_TYPE_USB,
101    .properties = jz_power_props,
102    .num_properties = ARRAY_SIZE(jz_power_props),
103    .get_property = jz_usb_get_power_prop,
104};
105
106
107/*********************************************************************
108 * Battery properties
109 *********************************************************************/
110
111static long jz_read_bat(struct power_supply *psy)
112{
113    struct jz_battery_info *bat_info = ps_to_jz_battery(psy);
114    enum jz_adc_battery_scale scale;
115
116    if (bat_info->pdata->max_voltag > 2500000)
117        scale = JZ_ADC_BATTERY_SCALE_7V5;
118    else
119        scale = JZ_ADC_BATTERY_SCALE_2V5;
120
121    return jz4740_adc_read_battery_voltage(psy->dev->parent->parent, scale);
122}
123
124static int jz_bat_get_capacity(struct power_supply *psy)
125{
126    int ret;
127    struct jz_battery_info *bat_info = ps_to_jz_battery(psy);
128
129    ret = jz_read_bat(psy);
130
131    if (ret < 0)
132        return ret;
133
134    ret = (ret - bat_info->pdata->min_voltag) * 100
135        / (bat_info->pdata->max_voltag - bat_info->pdata->min_voltag);
136
137    if (ret > 100)
138        ret = 100;
139    else if (ret < 0)
140        ret = 0;
141
142    return ret;
143}
144
145static int jz_bat_get_property(struct power_supply *psy,
146                enum power_supply_property psp,
147                union power_supply_propval *val)
148{
149    struct jz_battery_info *bat_info = ps_to_jz_battery(psy)
150
151    switch (psp) {
152    case POWER_SUPPLY_PROP_STATUS:
153        val->intval = bat_info->bat_status;
154        break;
155    case POWER_SUPPLY_PROP_TECHNOLOGY:
156        val->intval = bat_info->pdata->batt_tech;
157        break;
158    case POWER_SUPPLY_PROP_HEALTH:
159        if(jz_read_bat(psy) < bat_info->pdata->min_voltag) {
160            dev_dbg(psy->dev, "%s: battery is dead,"
161                "voltage too low!\n", __func__);
162            val->intval = POWER_SUPPLY_HEALTH_DEAD;
163        } else {
164            dev_dbg(psy->dev, "%s: battery is good,"
165                "voltage normal.\n", __func__);
166            val->intval = POWER_SUPPLY_HEALTH_GOOD;
167        }
168        break;
169    case POWER_SUPPLY_PROP_CAPACITY:
170        val->intval = jz_bat_get_capacity(psy);
171        dev_dbg(psy->dev, "%s: battery_capacity = %d\n",
172            __func__, val->intval);
173        break;
174    case POWER_SUPPLY_PROP_VOLTAGE_NOW:
175        val->intval = jz_read_bat(psy);
176        if (val->intval < 0)
177            return val->intval;
178        break;
179    case POWER_SUPPLY_PROP_VOLTAGE_MAX:
180    case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
181        val->intval = bat_info->pdata->max_voltag;
182        break;
183    case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
184        val->intval = bat_info->pdata->min_voltag;
185        break;
186    case POWER_SUPPLY_PROP_PRESENT:
187        val->intval = 1;
188        break;
189    default:
190        return -EINVAL;
191    }
192    return 0;
193}
194
195static void jz_bat_external_power_changed(struct power_supply *psy)
196{
197    struct jz_battery_info *bat_info = ps_to_jz_battery(psy);
198
199    cancel_delayed_work(&bat_info->bat_work);
200    queue_delayed_work(bat_info->monitor_wqueue, &bat_info->bat_work, HZ / 8);
201}
202
203static char *status_text[] = {
204    [POWER_SUPPLY_STATUS_UNKNOWN] = "Unknown",
205    [POWER_SUPPLY_STATUS_CHARGING] = "Charging",
206    [POWER_SUPPLY_STATUS_DISCHARGING] = "Discharging",
207    [POWER_SUPPLY_STATUS_NOT_CHARGING] = "Not charging",
208};
209
210static void jz_bat_update(struct power_supply *psy)
211{
212    struct jz_battery_info *bat_info = ps_to_jz_battery(psy);
213
214    int old_status = bat_info->bat_status;
215    static unsigned long old_batt_vol = 0;
216    unsigned long batt_vol = jz_read_bat(psy);
217
218    mutex_lock(&bat_info->work_lock);
219
220    if (gpio_is_valid(bat_info->pdata->charg_stat_gpio)) {
221        if(!gpio_get_value(bat_info->pdata->charg_stat_gpio))
222            bat_info->bat_status = POWER_SUPPLY_STATUS_CHARGING;
223        else
224            bat_info->bat_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
225        dev_dbg(psy->dev, "%s: battery status=%s\n",
226            __func__, status_text[bat_info->bat_status]);
227
228        if (old_status != bat_info->bat_status) {
229            dev_dbg(psy->dev, "%s %s -> %s\n",
230                psy->name,
231                status_text[old_status],
232                status_text[bat_info->bat_status]);
233
234            power_supply_changed(psy);
235        }
236    }
237
238    if (old_batt_vol - batt_vol > 50000) {
239        dev_dbg(psy->dev, "voltage change : %ld -> %ld\n",
240            old_batt_vol, batt_vol);
241        power_supply_changed(psy);
242        old_batt_vol = batt_vol;
243    }
244
245    mutex_unlock(&bat_info->work_lock);
246}
247
248static enum power_supply_property jz_bat_main_props[] = {
249    POWER_SUPPLY_PROP_STATUS,
250    POWER_SUPPLY_PROP_TECHNOLOGY,
251    POWER_SUPPLY_PROP_HEALTH,
252    POWER_SUPPLY_PROP_CAPACITY, /* in percents! */
253    POWER_SUPPLY_PROP_VOLTAGE_NOW,
254    POWER_SUPPLY_PROP_VOLTAGE_MAX,
255    POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
256    POWER_SUPPLY_PROP_PRESENT,
257};
258
259struct power_supply bat_ps = {
260    .name = "battery",
261    .type = POWER_SUPPLY_TYPE_BATTERY,
262    .properties = jz_bat_main_props,
263    .num_properties = ARRAY_SIZE(jz_bat_main_props),
264    .get_property = jz_bat_get_property,
265    .external_power_changed = jz_bat_external_power_changed,
266    .use_for_apm = 1,
267};
268
269static void jz_bat_work(struct work_struct *work)
270{
271    /* query interval too small will increase system workload*/
272    const int interval = HZ * 30;
273    struct jz_battery_info *bat_info = container_of(work,struct jz_battery_info, bat_work.work);
274
275    jz_bat_update(&bat_info->bat);
276    queue_delayed_work(bat_info->monitor_wqueue,
277               &bat_info->bat_work, interval);
278}
279
280#ifdef CONFIG_PM
281static int jz_bat_suspend(struct platform_device *pdev, pm_message_t state)
282{
283    struct jz_battery_info *bat_info = platform_get_drvdata(pdev);
284
285    bat_info->bat_status = POWER_SUPPLY_STATUS_UNKNOWN;
286
287    return 0;
288}
289
290static int jz_bat_resume(struct platform_device *pdev)
291{
292    struct jz_battery_info *bat_info = platform_get_drvdata(pdev);
293
294    bat_info->bat_status = POWER_SUPPLY_STATUS_UNKNOWN;
295
296    cancel_delayed_work(&bat_info->bat_work);
297    queue_delayed_work(bat_info->monitor_wqueue, &bat_info->bat_work, HZ/10);
298
299    return 0;
300}
301#else
302#define jz_bat_suspend NULL
303#define jz_bat_resume NULL
304#endif
305
306static int jz_bat_probe(struct platform_device *pdev)
307{
308    int ret = 0;
309    struct jz_battery_info *bat_info;
310
311    bat_info = kzalloc(sizeof(struct jz_battery_info), GFP_KERNEL);
312
313    if (!bat_info) {
314        return -ENOMEM;
315    }
316
317    if (!pdev->dev.platform_data) {
318        dev_err(&pdev->dev, "Please set battery info\n");
319        ret = -EINVAL;
320        goto err_platform_data;
321    }
322    platform_set_drvdata(pdev, bat_info);
323    bat_info->pdata = pdev->dev.platform_data;
324    bat_info->bat = bat_ps;
325    bat_info->usb = jz_usb;
326    bat_info->ac = jz_ac;
327    mutex_init(&bat_info->work_lock);
328    INIT_DELAYED_WORK(&bat_info->bat_work, jz_bat_work);
329
330    if (gpio_is_valid(bat_info->pdata->dc_dect_gpio)) {
331        ret = gpio_request(bat_info->pdata->dc_dect_gpio, "AC/DC DECT");
332        if (ret) {
333            dev_err(&pdev->dev, "ac/dc dect gpio request failed.\n");
334
335            goto err_dc_gpio_request;
336        }
337        ret = gpio_direction_input(bat_info->pdata->dc_dect_gpio);
338        if (ret) {
339            dev_err(&pdev->dev, "ac/dc dect gpio direction failed.\n");
340
341            goto err_dc_gpio_direction;
342        }
343    }
344
345    if (gpio_is_valid(bat_info->pdata->usb_dect_gpio)) {
346        ret = gpio_request(bat_info->pdata->usb_dect_gpio, "USB DECT");
347        if (ret) {
348            dev_err(&pdev->dev, "usb dect gpio request failed.\n");
349
350            goto err_usb_gpio_request;
351        }
352        ret = gpio_direction_input(bat_info->pdata->usb_dect_gpio);
353        if (ret) {
354            dev_err(&pdev->dev, "usb dect gpio set direction failed.\n");
355            goto err_usb_gpio_direction;
356        }
357
358        jz_gpio_disable_pullup(bat_info->pdata->usb_dect_gpio);
359        /* TODO: Use generic gpio is better */
360    }
361
362    if (gpio_is_valid(bat_info->pdata->charg_stat_gpio)) {
363        ret = gpio_request(bat_info->pdata->charg_stat_gpio, "CHARG STAT");
364        if (ret) {
365            dev_err(&pdev->dev, "charger state gpio request failed.\n");
366            goto err_charg_gpio_request;
367        }
368        ret = gpio_direction_input(bat_info->pdata->charg_stat_gpio);
369        if (ret) {
370            dev_err(&pdev->dev, "charger state gpio set direction failed.\n");
371            goto err_charg_gpio_direction;
372        }
373    }
374
375    if (gpio_is_valid(bat_info->pdata->dc_dect_gpio)) {
376        ret = power_supply_register(&pdev->dev, &bat_info->ac);
377        if (ret) {
378            dev_err(&pdev->dev, "power supply ac/dc register failed.\n");
379            goto err_power_register_ac;
380        }
381    }
382
383    if (gpio_is_valid(bat_info->pdata->usb_dect_gpio)) {
384        ret = power_supply_register(&pdev->dev, &bat_info->usb);
385        if (ret) {
386            dev_err(&pdev->dev, "power supply usb register failed.\n");
387            goto err_power_register_usb;
388        }
389    }
390
391    if (gpio_is_valid(bat_info->pdata->charg_stat_gpio)) {
392        ret = power_supply_register(&pdev->dev, &bat_info->bat);
393        if (ret) {
394            dev_err(&pdev->dev, "power supply battery register failed.\n");
395            goto err_power_register_bat;
396        } else {
397            bat_info->monitor_wqueue = create_singlethread_workqueue("jz_battery");
398            if (!bat_info->monitor_wqueue) {
399                return -ESRCH;
400            }
401            queue_delayed_work(bat_info->monitor_wqueue, &bat_info->bat_work, HZ * 1);
402        }
403    }
404    printk(KERN_INFO "jz_bat init success.\n");
405    return ret;
406
407err_power_register_bat:
408    power_supply_unregister(&bat_info->usb);
409err_power_register_usb:
410    power_supply_unregister(&bat_info->ac);
411err_power_register_ac:
412err_charg_gpio_direction:
413    gpio_free(bat_info->pdata->charg_stat_gpio);
414err_charg_gpio_request:
415err_usb_gpio_direction:
416    gpio_free(bat_info->pdata->usb_dect_gpio);
417err_usb_gpio_request:
418err_dc_gpio_direction:
419    gpio_free(bat_info->pdata->dc_dect_gpio);
420err_dc_gpio_request:
421err_platform_data:
422    kfree(bat_info);
423    return ret;
424}
425
426static int jz_bat_remove(struct platform_device *pdev)
427{
428    struct jz_battery_info *bat_info = platform_get_drvdata(pdev);
429
430    if (bat_info->pdata) {
431        if (gpio_is_valid(bat_info->pdata->dc_dect_gpio))
432            gpio_free(bat_info->pdata->dc_dect_gpio);
433        if (gpio_is_valid(bat_info->pdata->usb_dect_gpio))
434            gpio_free(bat_info->pdata->usb_dect_gpio);
435        if (gpio_is_valid(bat_info->pdata->charg_stat_gpio))
436            gpio_free(bat_info->pdata->charg_stat_gpio);
437    }
438
439    power_supply_unregister(&bat_ps);
440    power_supply_unregister(&jz_ac);
441    power_supply_unregister(&jz_usb);
442
443    return 0;
444}
445
446static struct platform_driver jz_bat_driver = {
447    .probe = jz_bat_probe,
448    .remove = __devexit_p(jz_bat_remove),
449    .suspend = jz_bat_suspend,
450    .resume = jz_bat_resume,
451    .driver = {
452        .name = "jz4740-battery",
453        .owner = THIS_MODULE,
454    },
455};
456
457static int __init jz_bat_init(void)
458{
459    return platform_driver_register(&jz_bat_driver);
460}
461module_init(jz_bat_init);
462
463static void __exit jz_bat_exit(void)
464{
465    platform_driver_unregister(&jz_bat_driver);
466}
467module_exit(jz_bat_exit);
468
469MODULE_LICENSE("GPL");
470MODULE_AUTHOR("Jiejing Zhang <kzjeef@gmail.com>");
471MODULE_DESCRIPTION("JZ4720/JZ4740 SoC battery driver");
drivers/rtc/rtc-jz4740.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC RTC driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/spinlock.h>
20#include <linux/rtc.h>
21
22#define JZ_REG_RTC_CTRL 0x00
23#define JZ_REG_RTC_SEC 0x04
24#define JZ_REG_RTC_SEC_ALARM 0x08
25#define JZ_REG_REGULATOR 0x0C
26
27#define JZ_RTC_CTRL_WRDY BIT(7)
28#define JZ_RTC_CTRL_1HZ BIT(6)
29#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
30#define JZ_RTC_CTRL_AF BIT(4)
31#define JZ_RTC_CTRL_AF_IRQ BIT(3)
32#define JZ_RTC_CTRL_AE BIT(2)
33#define JZ_RTC_CTRL_ENABLE BIT(0)
34
35struct jz4740_rtc {
36    struct resource *mem;
37    void __iomem *base;
38
39    struct rtc_device *rtc;
40
41    unsigned int irq;
42
43    spinlock_t lock;
44};
45
46static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
47{
48    return readl(rtc->base + reg);
49}
50
51static inline void jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
52{
53    uint32_t ctrl;
54    do {
55        ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
56    } while (!(ctrl & JZ_RTC_CTRL_WRDY));
57}
58
59
60static inline void jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
61                    uint32_t val)
62{
63    jz4740_rtc_wait_write_ready(rtc);
64    writel(val, rtc->base + reg);
65}
66
67static void jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
68                    uint32_t val)
69{
70    unsigned long flags;
71    uint32_t ctrl;
72
73    spin_lock_irqsave(&rtc->lock, flags);
74
75    ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
76
77    /* Don't clear interrupt flags by accident */
78    ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
79
80    ctrl &= ~mask;
81    ctrl |= val;
82
83    jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
84
85    spin_unlock_irqrestore(&rtc->lock, flags);
86}
87
88static inline struct jz4740_rtc *dev_to_rtc(struct device *dev)
89{
90    return dev_get_drvdata(dev);
91}
92
93static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
94{
95    struct jz4740_rtc *rtc = dev_to_rtc(dev);
96    uint32_t secs, secs2;
97
98    secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
99    secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
100
101    while (secs != secs2) {
102        secs = secs2;
103        secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
104    }
105
106    rtc_time_to_tm(secs, time);
107
108    return rtc_valid_tm(time);
109}
110
111static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
112{
113    struct jz4740_rtc *rtc = dev_to_rtc(dev);
114
115    if ((uint32_t)secs != secs)
116        return -EINVAL;
117
118    jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
119
120    return 0;
121}
122
123static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
124{
125    struct jz4740_rtc *rtc = dev_to_rtc(dev);
126    uint32_t secs, secs2;
127    uint32_t ctrl;
128
129    secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
130    secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
131
132    while (secs != secs2){
133        secs = secs2;
134        secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
135    }
136
137    ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
138
139    alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
140    alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
141
142    rtc_time_to_tm(secs, &alrm->time);
143
144    return rtc_valid_tm(&alrm->time);
145}
146
147static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
148{
149    struct jz4740_rtc *rtc = dev_to_rtc(dev);
150    unsigned long secs;
151
152    rtc_tm_to_time(&alrm->time, &secs);
153
154    if ((uint32_t)secs != secs)
155        return -EINVAL;
156
157    jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, (uint32_t)secs);
158    jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AE,
159                    alrm->enabled ? JZ_RTC_CTRL_AE : 0);
160
161    return 0;
162}
163
164static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enabled)
165{
166    struct jz4740_rtc *rtc = dev_to_rtc(dev);
167    jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ,
168                    enabled ? JZ_RTC_CTRL_1HZ_IRQ : 0);
169    return 0;
170}
171
172
173static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
174{
175    struct jz4740_rtc *rtc = dev_to_rtc(dev);
176    jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ,
177                    enabled ? JZ_RTC_CTRL_AF_IRQ : 0);
178    return 0;
179}
180
181static struct rtc_class_ops jz4740_rtc_ops = {
182    .read_time = jz4740_rtc_read_time,
183    .set_mmss = jz4740_rtc_set_mmss,
184    .read_alarm = jz4740_rtc_read_alarm,
185    .set_alarm = jz4740_rtc_set_alarm,
186    .update_irq_enable = jz4740_rtc_update_irq_enable,
187    .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
188};
189
190static irqreturn_t jz4740_rtc_irq(int irq, void *data)
191{
192    struct jz4740_rtc *rtc = data;
193    uint32_t ctrl;
194    unsigned long events = 0;
195    ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
196
197    if (ctrl & JZ_RTC_CTRL_1HZ)
198        events |= (RTC_UF | RTC_IRQF);
199
200    if (ctrl & JZ_RTC_CTRL_AF)
201        events |= (RTC_AF | RTC_IRQF);
202
203    rtc_update_irq(rtc->rtc, 1, events);
204
205    jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, 0);
206
207    return IRQ_HANDLED;
208}
209
210static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
211{
212    int ret;
213    struct jz4740_rtc *rtc;
214
215    rtc = kmalloc(sizeof(*rtc), GFP_KERNEL);
216
217    rtc->irq = platform_get_irq(pdev, 0);
218
219    if (rtc->irq < 0) {
220        ret = -ENOENT;
221        dev_err(&pdev->dev, "Failed to get platform irq\n");
222        goto err_free;
223    }
224
225    rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226    if (!rtc->mem) {
227        ret = -ENOENT;
228        dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
229        goto err_free;
230    }
231
232    rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
233                    pdev->name);
234
235    if (!rtc->mem) {
236        ret = -EBUSY;
237        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
238        goto err_free;
239    }
240
241    rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
242
243    if (!rtc->base) {
244        ret = -EBUSY;
245        dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
246        goto err_release_mem_region;
247    }
248
249    platform_set_drvdata(pdev, rtc);
250
251    rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
252                    THIS_MODULE);
253
254    if (IS_ERR(rtc->rtc)) {
255        ret = PTR_ERR(rtc->rtc);
256        dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
257        goto err_iounmap;
258    }
259
260    ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
261                pdev->name, rtc);
262
263    if (ret) {
264        dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
265        goto err_unregister_rtc;
266    }
267    printk("rtc-ctrl: %d\n", jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL));
268
269    return 0;
270
271err_unregister_rtc:
272    rtc_device_unregister(rtc->rtc);
273err_iounmap:
274    platform_set_drvdata(pdev, NULL);
275    iounmap(rtc->base);
276err_release_mem_region:
277    release_mem_region(rtc->mem->start, resource_size(rtc->mem));
278err_free:
279    kfree(rtc);
280
281    return ret;
282}
283
284static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
285{
286    struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
287
288    rtc_device_unregister(rtc->rtc);
289
290    iounmap(rtc->base);
291    release_mem_region(rtc->mem->start, resource_size(rtc->mem));
292
293    kfree(rtc);
294
295    platform_set_drvdata(pdev, NULL);
296
297    return 0;
298}
299
300struct platform_driver jz4740_rtc_driver = {
301    .probe = jz4740_rtc_probe,
302    .remove = __devexit_p(jz4740_rtc_remove),
303    .driver = {
304        .name = "jz4740-rtc",
305        .owner = THIS_MODULE,
306    },
307};
308
309static int __init jz4740_rtc_init(void)
310{
311    return platform_driver_register(&jz4740_rtc_driver);
312}
313module_init(jz4740_rtc_init);
314
315static void __exit jz4740_rtc_exit(void)
316{
317    platform_driver_unregister(&jz4740_rtc_driver);
318}
319module_exit(jz4740_rtc_exit);
320
321MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
322MODULE_LICENSE("GPL");
323MODULE_DESCRIPTION("RTC driver for the JZ4720/JZ4740 SoC\n");
324MODULE_ALIAS("platform:jz4740-rtc");
325MODULE_ALIAS("platform:jz4720-rtc");
drivers/usb/gadget/jz4740_udc.c
1/*
2 * linux/drivers/usb/gadget/jz4740_udc.c
3 *
4 * Ingenic JZ4740 on-chip high speed USB device controller
5 *
6 * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15/*
16 * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
17 *
18 * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
19 * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/list.h>
31#include <linux/interrupt.h>
32#include <linux/proc_fs.h>
33#include <linux/usb.h>
34#include <linux/usb/gadget.h>
35
36#include <asm/byteorder.h>
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/system.h>
40#include <asm/mach-jz4740/regs.h>
41#include <asm/mach-jz4740/clock.h>
42
43#include "jz4740_udc.h"
44
45#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
46#define JZ_REG_UDC_POWER 0x01 /* Power Managemetn 8-bit */
47#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
48#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
49#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
50#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
51#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
52#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
53#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
54#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
55#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
56
57#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
58#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
59#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
60#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
61#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
62#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
63#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
64#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
65
66#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
67
68#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
69#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
70
71#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
72#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
73#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
74#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
75#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
76#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
77#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
78
79#ifndef DEBUG
80# define DEBUG(fmt,args...) do {} while(0)
81#endif
82#ifndef DEBUG_EP0
83# define NO_STATES
84# define DEBUG_EP0(fmt,args...) do {} while(0)
85#endif
86#ifndef DEBUG_SETUP
87# define DEBUG_SETUP(fmt,args...) do {} while(0)
88#endif
89
90static unsigned int udc_debug = 0; /* 0: normal mode, 1: test udc cable type mode */
91
92module_param(udc_debug, int, 0);
93MODULE_PARM_DESC(udc_debug, "test udc cable or power type");
94
95static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */
96
97module_param(use_dma, int, 0);
98MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
99
100struct jz4740_udc *the_controller;
101
102/*
103 * Local declarations.
104 */
105static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
106static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
107
108static void done(struct jz4740_ep *ep, struct jz4740_request *req,
109         int status);
110static void pio_irq_enable(struct jz4740_ep *ep);
111static void pio_irq_disable(struct jz4740_ep *ep);
112static void stop_activity(struct jz4740_udc *dev,
113              struct usb_gadget_driver *driver);
114static void nuke(struct jz4740_ep *ep, int status);
115static void flush(struct jz4740_ep *ep);
116static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
117
118/*-------------------------------------------------------------------------*/
119
120/* inline functions of register read/write/set/clear */
121
122static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
123{
124    return readb(udc->base + reg);
125}
126
127static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
128{
129    return readw(udc->base + reg);
130}
131
132static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
133{
134    return readl(udc->base + reg);
135}
136
137static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
138{
139    writeb(val, udc->base + reg);
140}
141
142static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
143{
144    writew(val, udc->base + reg);
145}
146
147static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
148{
149    writel(val, udc->base + reg);
150}
151
152static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
153{
154    usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
155}
156
157static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask)
158{
159    usb_writew(udc, reg, usb_readw(udc, reg) | mask);
160}
161
162static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
163{
164    usb_writel(udc, reg, usb_readl(udc, reg) | mask);
165}
166
167static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
168{
169    usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
170}
171
172static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
173{
174    usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
175}
176
177static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
178{
179    usb_writel(udc, reg, usb_readl(udc, reg) & ~mask);
180}
181
182/*-------------------------------------------------------------------------*/
183
184static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
185{
186    usb_writeb(udc, JZ_REG_UDC_INDEX, index);
187}
188
189static inline void jz_udc_select_ep(struct jz4740_ep *ep)
190{
191    jz_udc_set_index(ep->dev, ep_index(ep));
192}
193
194static inline int write_packet(struct jz4740_ep *ep,
195                   struct jz4740_request *req, int max)
196{
197    uint8_t *buf;
198    int length, nlong, nbyte;
199    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
200
201    buf = req->req.buf + req->req.actual;
202    prefetch(buf);
203
204    length = req->req.length - req->req.actual;
205    length = min(length, max);
206    req->req.actual += length;
207
208    DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo);
209
210    nlong = length >> 2;
211    nbyte = length & 0x3;
212    while (nlong--) {
213        usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf));
214        buf += 4;
215    }
216    while (nbyte--) {
217        usb_writeb(ep->dev, ep->fifo, *buf++);
218    }
219
220    return length;
221}
222
223static inline int read_packet(struct jz4740_ep *ep,
224                  struct jz4740_request *req, int count)
225{
226    uint8_t *buf;
227    int length, nlong, nbyte;
228    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
229
230    buf = req->req.buf + req->req.actual;
231    prefetchw(buf);
232
233    length = req->req.length - req->req.actual;
234    length = min(length, count);
235    req->req.actual += length;
236
237    DEBUG("Read %d, fifo %x\n", length, ep->fifo);
238
239    nlong = length >> 2;
240    nbyte = length & 0x3;
241    while (nlong--) {
242        *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo);
243        buf += 4;
244    }
245    while (nbyte--) {
246        *buf++ = usb_readb(ep->dev, ep->fifo);
247    }
248
249    return length;
250}
251
252/*-------------------------------------------------------------------------*/
253
254/*
255 * udc_disable - disable USB device controller
256 */
257static void udc_disable(struct jz4740_udc *dev)
258{
259    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
260
261    udc_set_address(dev, 0);
262
263    /* Disable interrupts */
264    usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
265    usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
266    usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
267
268    /* Disable DMA */
269    usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
270    usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
271
272    /* Disconnect from usb */
273    usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
274
275    /* Disable the USB PHY */
276#ifdef CONFIG_SOC_JZ4740
277    REG_CPM_SCR &= ~CPM_SCR_USBPHY_ENABLE;
278#elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
279    REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE;
280#endif
281
282    dev->ep0state = WAIT_FOR_SETUP;
283    dev->gadget.speed = USB_SPEED_UNKNOWN;
284
285    return;
286}
287
288/*
289 * udc_reinit - initialize software state
290 */
291static void udc_reinit(struct jz4740_udc *dev)
292{
293    int i;
294    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
295
296    /* device/ep0 records init */
297    INIT_LIST_HEAD(&dev->gadget.ep_list);
298    INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
299    dev->ep0state = WAIT_FOR_SETUP;
300
301    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
302        struct jz4740_ep *ep = &dev->ep[i];
303
304        if (i != 0)
305            list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
306
307        INIT_LIST_HEAD(&ep->queue);
308        ep->desc = 0;
309        ep->stopped = 0;
310        ep->pio_irqs = 0;
311    }
312}
313
314/* until it's enabled, this UDC should be completely invisible
315 * to any USB host.
316 */
317static void udc_enable(struct jz4740_udc *dev)
318{
319    int i;
320    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
321
322    /* UDC state is incorrect - Added by River */
323    if (dev->state != UDC_STATE_ENABLE) {
324        return;
325    }
326
327    dev->gadget.speed = USB_SPEED_UNKNOWN;
328
329    /* Flush FIFO for each */
330    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
331        struct jz4740_ep *ep = &dev->ep[i];
332
333        jz_udc_set_index(dev, ep_index(ep));
334        flush(ep);
335    }
336
337    /* Set this bit to allow the UDC entering low-power mode when
338     * there are no actions on the USB bus.
339     * UDC still works during this bit was set.
340     */
341    __cpm_stop_udc();
342
343    /* Enable the USB PHY */
344#ifdef CONFIG_SOC_JZ4740
345    REG_CPM_SCR |= CPM_SCR_USBPHY_ENABLE;
346#elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
347    REG_CPM_OPCR |= CPM_OPCR_UDCPHY_ENABLE;
348#endif
349
350    /* Disable interrupts */
351/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
352    usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
353    usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
354
355    /* Enable interrupts */
356    usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
357    usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
358    /* Don't enable rest of the interrupts */
359    /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
360       usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
361
362    /* Enable SUSPEND */
363    /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
364
365    /* Enable HS Mode */
366    usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
367
368    /* Let host detect UDC:
369     * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
370     * transistor on and pull the USBDP pin HIGH.
371     */
372    usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
373
374    return;
375}
376
377/*-------------------------------------------------------------------------*/
378
379/* keeping it simple:
380 * - one bus driver, initted first;
381 * - one function driver, initted second
382 */
383
384/*
385 * Register entry point for the peripheral controller driver.
386 */
387
388int usb_gadget_register_driver(struct usb_gadget_driver *driver)
389{
390    struct jz4740_udc *dev = the_controller;
391    int retval;
392
393    if (!driver || !driver->bind) {
394        return -EINVAL;
395    }
396
397    if (!dev) {
398        return -ENODEV;
399    }
400
401    if (dev->driver) {
402        return -EBUSY;
403    }
404
405    /* hook up the driver */
406    dev->driver = driver;
407    dev->gadget.dev.driver = &driver->driver;
408
409    retval = driver->bind(&dev->gadget);
410    if (retval) {
411        DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
412                    driver->driver.name, retval);
413        dev->driver = 0;
414        return retval;
415    }
416
417    /* then enable host detection and ep0; and we're ready
418     * for set_configuration as well as eventual disconnect.
419     */
420    udc_enable(dev);
421
422    DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
423          driver->driver.name);
424
425    return 0;
426}
427
428EXPORT_SYMBOL(usb_gadget_register_driver);
429
430static void stop_activity(struct jz4740_udc *dev,
431              struct usb_gadget_driver *driver)
432{
433    int i;
434
435    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
436
437    /* don't disconnect drivers more than once */
438    if (dev->gadget.speed == USB_SPEED_UNKNOWN)
439        driver = 0;
440    dev->gadget.speed = USB_SPEED_UNKNOWN;
441
442    /* prevent new request submissions, kill any outstanding requests */
443    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
444        struct jz4740_ep *ep = &dev->ep[i];
445
446        ep->stopped = 1;
447
448        jz_udc_set_index(dev, ep_index(ep));
449        nuke(ep, -ESHUTDOWN);
450    }
451
452    /* report disconnect; the driver is already quiesced */
453    if (driver) {
454        spin_unlock(&dev->lock);
455        driver->disconnect(&dev->gadget);
456        spin_lock(&dev->lock);
457    }
458
459    /* re-init driver-visible data structures */
460    udc_reinit(dev);
461}
462
463
464/*
465 * Unregister entry point for the peripheral controller driver.
466 */
467int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
468{
469    struct jz4740_udc *dev = the_controller;
470    unsigned long flags;
471    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
472
473    if (!dev)
474        return -ENODEV;
475    if (!driver || driver != dev->driver)
476        return -EINVAL;
477    if (!driver->unbind)
478        return -EBUSY;
479
480    spin_lock_irqsave(&dev->lock, flags);
481    dev->driver = 0;
482    stop_activity(dev, driver);
483    spin_unlock_irqrestore(&dev->lock, flags);
484
485    driver->unbind(&dev->gadget);
486
487    udc_disable(dev);
488
489    DEBUG("unregistered driver '%s'\n", driver->driver.name);
490
491    return 0;
492}
493
494EXPORT_SYMBOL(usb_gadget_unregister_driver);
495
496/*-------------------------------------------------------------------------*/
497
498/*
499 * Starting DMA using mode 1
500 */
501static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req)
502{
503    struct jz4740_udc *dev = ep->dev;
504    uint32_t count = req->req.length;
505    uint32_t physaddr = virt_to_phys((void *)req->req.buf);
506
507    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
508
509    jz_udc_select_ep(ep);
510
511    if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */
512        ep->reg_addr = JZ_REG_UDC_ADDR1;
513
514        dma_cache_wback_inv((unsigned long)req->req.buf, count);
515
516        pio_irq_enable(ep);
517
518        usb_writeb(dev, JZ_REG_UDC_INCSRH,
519               USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
520
521        usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr);
522        usb_writel(dev, JZ_REG_UDC_COUNT1, count);
523        usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 |
524               USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
525    }
526    else { /* Bulk-OUT transfer using DMA channel 2 */
527        ep->reg_addr = JZ_REG_UDC_ADDR2;
528
529        dma_cache_wback_inv((unsigned long)req->req.buf, count);
530
531        pio_irq_enable(ep);
532
533        usb_setb(dev, JZ_REG_UDC_OUTCSRH,
534             USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
535
536        usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr);
537        usb_writel(dev, JZ_REG_UDC_COUNT2, count);
538        usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 |
539               USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
540    }
541}
542
543/*-------------------------------------------------------------------------*/
544
545/** Write request to FIFO (max write == maxp size)
546 * Return: 0 = still running, 1 = completed, negative = errno
547 * NOTE: INDEX register must be set for EP
548 */
549static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
550{
551    struct jz4740_udc *dev = ep->dev;
552    uint32_t max, csr;
553    uint32_t physaddr = virt_to_phys((void *)req->req.buf);
554
555    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
556    max = le16_to_cpu(ep->desc->wMaxPacketSize);
557
558    if (use_dma) {
559        uint32_t dma_count;
560
561        /* DMA interrupt generated due to the last packet loaded into the FIFO */
562
563        dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
564        req->req.actual += dma_count;
565
566        if (dma_count % max) {
567            /* If the last packet is less than MAXP, set INPKTRDY manually */
568            usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
569        }
570
571        done(ep, req, 0);
572        if (list_empty(&ep->queue)) {
573            pio_irq_disable(ep);
574            return 1;
575        }
576        else {
577            /* advance the request queue */
578            req = list_entry(ep->queue.next, struct jz4740_request, queue);
579            kick_dma(ep, req);
580            return 0;
581        }
582    }
583
584    /*
585     * PIO mode handling starts here ...
586     */
587
588    csr = usb_readb(dev, ep->csr);
589
590    if (!(csr & USB_INCSR_FFNOTEMPT)) {
591        unsigned count;
592        int is_last, is_short;
593
594        count = write_packet(ep, req, max);
595        usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
596
597        /* last packet is usually short (or a zlp) */
598        if (unlikely(count != max))
599            is_last = is_short = 1;
600        else {
601            if (likely(req->req.length != req->req.actual)
602                || req->req.zero)
603                is_last = 0;
604            else
605                is_last = 1;
606            /* interrupt/iso maxpacket may not fill the fifo */
607            is_short = unlikely(max < ep_maxpacket(ep));
608        }
609
610        DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
611              ep->ep.name, count,
612              is_last ? "/L" : "", is_short ? "/S" : "",
613              req->req.length - req->req.actual, req);
614
615        /* requests complete when all IN data is in the FIFO */
616        if (is_last) {
617            done(ep, req, 0);
618            if (list_empty(&ep->queue)) {
619                pio_irq_disable(ep);
620            }
621            return 1;
622        }
623    } else {
624        DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
625    }
626
627    return 0;
628}
629
630/** Read to request from FIFO (max read == bytes in fifo)
631 * Return: 0 = still running, 1 = completed, negative = errno
632 * NOTE: INDEX register must be set for EP
633 */
634static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
635{
636    struct jz4740_udc *dev = ep->dev;
637    uint32_t csr;
638    unsigned count, is_short;
639    uint32_t physaddr = virt_to_phys((void *)req->req.buf);
640
641    if (use_dma) {
642        uint32_t dma_count;
643
644        /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
645
646        dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
647        req->req.actual += dma_count;
648
649        /* Disable interrupt and DMA */
650        pio_irq_disable(ep);
651        usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
652
653        /* Read all bytes from this packet */
654        count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
655        count = read_packet(ep, req, count);
656
657        if (count) {
658            /* If the last packet is greater than zero, clear OUTPKTRDY manually */
659            usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
660        }
661        done(ep, req, 0);
662
663        if (!list_empty(&ep->queue)) {
664            /* advance the request queue */
665            req = list_entry(ep->queue.next, struct jz4740_request, queue);
666            kick_dma(ep, req);
667        }
668
669        return 1;
670    }
671
672    /*
673     * PIO mode handling starts here ...
674     */
675
676    /* make sure there's a packet in the FIFO. */
677    csr = usb_readb(dev, ep->csr);
678    if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
679        DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
680        return -EINVAL;
681    }
682
683    /* read all bytes from this packet */
684    count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
685
686    is_short = (count < ep->ep.maxpacket);
687
688    count = read_packet(ep, req, count);
689
690    DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
691          ep->ep.name, csr, count,
692          is_short ? "/S" : "", req, req->req.actual, req->req.length);
693
694    /* Clear OutPktRdy */
695    usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
696
697    /* completion */
698    if (is_short || req->req.actual == req->req.length) {
699        done(ep, req, 0);
700
701        if (list_empty(&ep->queue))
702            pio_irq_disable(ep);
703        return 1;
704    }
705
706    /* finished that packet. the next one may be waiting... */
707    return 0;
708}
709
710/*
711 * done - retire a request; caller blocked irqs
712 * INDEX register is preserved to keep same
713 */
714static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
715{
716    unsigned int stopped = ep->stopped;
717    unsigned long flags;
718    uint32_t index;
719
720    DEBUG("%s, %p\n", __FUNCTION__, ep);
721    list_del_init(&req->queue);
722
723    if (likely(req->req.status == -EINPROGRESS))
724        req->req.status = status;
725    else
726        status = req->req.status;
727
728    if (status && status != -ESHUTDOWN)
729        DEBUG("complete %s req %p stat %d len %u/%u\n",
730              ep->ep.name, &req->req, status,
731              req->req.actual, req->req.length);
732
733    /* don't modify queue heads during completion callback */
734    ep->stopped = 1;
735    /* Read current index (completion may modify it) */
736    spin_lock_irqsave(&ep->dev->lock, flags);
737    index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
738
739    req->req.complete(&ep->ep, &req->req);
740
741    /* Restore index */
742    jz_udc_set_index(ep->dev, index);
743    spin_unlock_irqrestore(&ep->dev->lock, flags);
744    ep->stopped = stopped;
745}
746
747/** Enable EP interrupt */
748static void pio_irq_enable(struct jz4740_ep *ep)
749{
750    uint8_t index = ep_index(ep);
751    struct jz4740_udc *dev = ep->dev;
752    DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
753
754    if (ep_is_in(ep)) {
755        switch (index) {
756        case 1:
757        case 2:
758            usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index));
759            dev->in_mask |= BIT(index);
760            break;
761        default:
762            DEBUG("Unknown endpoint: %d\n", index);
763            break;
764        }
765    }
766    else {
767        switch (index) {
768        case 1:
769            usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index));
770            dev->out_mask |= BIT(index);
771            break;
772        default:
773            DEBUG("Unknown endpoint: %d\n", index);
774            break;
775        }
776    }
777}
778
779/** Disable EP interrupt */
780static void pio_irq_disable(struct jz4740_ep *ep)
781{
782    uint8_t index = ep_index(ep);
783    struct jz4740_udc *dev = ep->dev;
784
785    DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
786
787    if (ep_is_in(ep)) {
788        switch (ep_index(ep)) {
789        case 1:
790        case 2:
791            usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index));
792            dev->in_mask &= ~BIT(index);
793            break;
794        default:
795            DEBUG("Unknown endpoint: %d\n", index);
796            break;
797        }
798    }
799    else {
800        switch (ep_index(ep)) {
801        case 1:
802            usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index));
803            dev->out_mask &= ~BIT(index);
804            break;
805        default:
806            DEBUG("Unknown endpoint: %d\n", index);
807            break;
808        }
809    }
810}
811
812/*
813 * nuke - dequeue ALL requests
814 */
815static void nuke(struct jz4740_ep *ep, int status)
816{
817    struct jz4740_request *req;
818
819    DEBUG("%s, %p\n", __FUNCTION__, ep);
820
821    /* Flush FIFO */
822    flush(ep);
823
824    /* called with irqs blocked */
825    while (!list_empty(&ep->queue)) {
826        req = list_entry(ep->queue.next, struct jz4740_request, queue);
827        done(ep, req, status);
828    }
829
830    /* Disable IRQ if EP is enabled (has descriptor) */
831    if (ep->desc)
832        pio_irq_disable(ep);
833}
834
835/** Flush EP FIFO
836 * NOTE: INDEX register must be set before this call
837 */
838static void flush(struct jz4740_ep *ep)
839{
840    DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
841
842    switch (ep->type) {
843    case ep_bulk_in:
844    case ep_interrupt:
845        usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
846        break;
847    case ep_bulk_out:
848        usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
849        break;
850    case ep_control:
851        break;
852    }
853}
854
855/**
856 * jz4740_in_epn - handle IN interrupt
857 */
858static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
859{
860    uint32_t csr;
861    struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
862    struct jz4740_request *req;
863    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
864
865    jz_udc_set_index(dev, ep_index(ep));
866
867    csr = usb_readb(dev, ep->csr);
868    DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
869
870    if (csr & USB_INCSR_SENTSTALL) {
871        DEBUG("USB_INCSR_SENTSTALL\n");
872        usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
873        return;
874    }
875
876    if (!ep->desc) {
877        DEBUG("%s: NO EP DESC\n", __FUNCTION__);
878        return;
879    }
880
881    if (list_empty(&ep->queue))
882        req = 0;
883    else
884        req = list_entry(ep->queue.next, struct jz4740_request, queue);
885
886    DEBUG("req: %p\n", req);
887
888    if (!req)
889        return;
890
891    write_fifo(ep, req);
892}
893
894/*
895 * Bulk OUT (recv)
896 */
897static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
898{
899    struct jz4740_ep *ep = &dev->ep[ep_idx];
900    struct jz4740_request *req;
901
902    DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
903
904    jz_udc_set_index(dev, ep_index(ep));
905    if (ep->desc) {
906        uint32_t csr;
907
908        if (use_dma) {
909            /* DMA starts here ... */
910            if (list_empty(&ep->queue))
911                req = 0;
912            else
913                req = list_entry(ep->queue.next, struct jz4740_request, queue);
914
915            if (req)
916                read_fifo(ep, req);
917            return;
918        }
919
920        /*
921         * PIO mode starts here ...
922         */
923
924        while ((csr = usb_readb(dev, ep->csr)) &
925               (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
926            DEBUG("%s: %x\n", __FUNCTION__, csr);
927
928            if (csr & USB_OUTCSR_SENTSTALL) {
929                DEBUG("%s: stall sent, flush fifo\n",
930                      __FUNCTION__);
931                /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
932                flush(ep);
933            } else if (csr & USB_OUTCSR_OUTPKTRDY) {
934                if (list_empty(&ep->queue))
935                    req = 0;
936                else
937                    req =
938                        list_entry(ep->queue.next,
939                               struct jz4740_request,
940                               queue);
941
942                if (!req) {
943                    DEBUG("%s: NULL REQ %d\n",
944                          __FUNCTION__, ep_idx);
945                    break;
946                } else {
947                    read_fifo(ep, req);
948                }
949            }
950        }
951    } else {
952        /* Throw packet away.. */
953        DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
954        flush(ep);
955    }
956}
957
958/** Halt specific EP
959 * Return 0 if success
960 * NOTE: Sets INDEX register to EP !
961 */
962static int jz4740_set_halt(struct usb_ep *_ep, int value)
963{
964    struct jz4740_udc *dev;
965    struct jz4740_ep *ep;
966    unsigned long flags;
967
968    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
969
970    ep = container_of(_ep, struct jz4740_ep, ep);
971    if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
972        DEBUG("%s, bad ep\n", __FUNCTION__);
973        return -EINVAL;
974    }
975
976    dev = ep->dev;
977
978    spin_lock_irqsave(&dev->lock, flags);
979
980    jz_udc_select_ep(ep);
981
982    DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
983
984    if (ep_index(ep) == 0) {
985        /* EP0 */
986        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
987    } else if (ep_is_in(ep)) {
988        uint32_t csr = usb_readb(dev, ep->csr);
989        if (value && ((csr & USB_INCSR_FFNOTEMPT)
990                  || !list_empty(&ep->queue))) {
991            /*
992             * Attempts to halt IN endpoints will fail (returning -EAGAIN)
993             * if any transfer requests are still queued, or if the controller
994             * FIFO still holds bytes that the host hasnÂ’t collected.
995             */
996            spin_unlock_irqrestore(&dev->lock, flags);
997            DEBUG
998                ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
999                 (csr & USB_INCSR_FFNOTEMPT),
1000                 !list_empty(&ep->queue));
1001            return -EAGAIN;
1002        }
1003        flush(ep);
1004        if (value) {
1005            usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
1006        }
1007        else {
1008            usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
1009            usb_setb(dev, ep->csr, USB_INCSR_CDT);
1010        }
1011    } else {
1012
1013        flush(ep);
1014        if (value) {
1015            usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1016        }
1017        else {
1018            usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1019            usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
1020        }
1021    }
1022
1023    if (value) {
1024        ep->stopped = 1;
1025    } else {
1026        ep->stopped = 0;
1027    }
1028
1029    spin_unlock_irqrestore(&dev->lock, flags);
1030
1031    DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
1032
1033    return 0;
1034}
1035
1036
1037static int jz4740_ep_enable(struct usb_ep *_ep,
1038                const struct usb_endpoint_descriptor *desc)
1039{
1040    struct jz4740_ep *ep;
1041    struct jz4740_udc *dev;
1042    unsigned long flags;
1043    uint32_t max, csrh = 0;
1044
1045    DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
1046
1047    if (!_ep || !desc)
1048        return -EINVAL;
1049
1050    ep = container_of(_ep, struct jz4740_ep, ep);
1051    if (ep->desc || ep->type == ep_control
1052        || desc->bDescriptorType != USB_DT_ENDPOINT
1053        || ep->bEndpointAddress != desc->bEndpointAddress) {
1054        DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
1055        return -EINVAL;
1056    }
1057
1058    /* xfer types must match, except that interrupt ~= bulk */
1059    if (ep->bmAttributes != desc->bmAttributes
1060        && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
1061        && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
1062        DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
1063        return -EINVAL;
1064    }
1065
1066    dev = ep->dev;
1067    if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1068        DEBUG("%s, bogus device state\n", __FUNCTION__);
1069        return -ESHUTDOWN;
1070    }
1071
1072    max = le16_to_cpu(desc->wMaxPacketSize);
1073
1074    spin_lock_irqsave(&ep->dev->lock, flags);
1075
1076    /* Configure the endpoint */
1077    jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F);
1078    if (ep_is_in(ep)) {
1079        usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1080        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1081        case USB_ENDPOINT_XFER_BULK:
1082        case USB_ENDPOINT_XFER_INT:
1083            csrh &= ~USB_INCSRH_ISO;
1084            break;
1085        case USB_ENDPOINT_XFER_ISOC:
1086            csrh |= USB_INCSRH_ISO;
1087            break;
1088        }
1089        usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1090    }
1091    else {
1092        usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1093        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1094        case USB_ENDPOINT_XFER_BULK:
1095             csrh &= ~USB_OUTCSRH_ISO;
1096            break;
1097        case USB_ENDPOINT_XFER_INT:
1098            csrh &= ~USB_OUTCSRH_ISO;
1099            csrh |= USB_OUTCSRH_DNYT;
1100            break;
1101        case USB_ENDPOINT_XFER_ISOC:
1102            csrh |= USB_OUTCSRH_ISO;
1103            break;
1104        }
1105        usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1106    }
1107
1108
1109    ep->stopped = 0;
1110    ep->desc = desc;
1111    ep->pio_irqs = 0;
1112    ep->ep.maxpacket = max;
1113
1114    spin_unlock_irqrestore(&ep->dev->lock, flags);
1115
1116    /* Reset halt state (does flush) */
1117    jz4740_set_halt(_ep, 0);
1118
1119    DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1120
1121    return 0;
1122}
1123
1124/** Disable EP
1125 * NOTE: Sets INDEX register
1126 */
1127static int jz4740_ep_disable(struct usb_ep *_ep)
1128{
1129    struct jz4740_ep *ep;
1130    unsigned long flags;
1131
1132    DEBUG("%s, %p\n", __FUNCTION__, _ep);
1133
1134    ep = container_of(_ep, struct jz4740_ep, ep);
1135    if (!_ep || !ep->desc) {
1136        DEBUG("%s, %s not enabled\n", __FUNCTION__,
1137              _ep ? ep->ep.name : NULL);
1138        return -EINVAL;
1139    }
1140
1141    spin_lock_irqsave(&ep->dev->lock, flags);
1142
1143    jz_udc_select_ep(ep);
1144
1145    /* Nuke all pending requests (does flush) */
1146    nuke(ep, -ESHUTDOWN);
1147
1148    /* Disable ep IRQ */
1149    pio_irq_disable(ep);
1150
1151    ep->desc = 0;
1152    ep->stopped = 1;
1153
1154    spin_unlock_irqrestore(&ep->dev->lock, flags);
1155
1156    DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1157    return 0;
1158}
1159
1160static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1161{
1162    struct jz4740_request *req;
1163
1164    DEBUG("%s, %p\n", __FUNCTION__, ep);
1165
1166    req = kzalloc(sizeof(*req), gfp_flags);
1167    if (!req)
1168        return 0;
1169
1170    INIT_LIST_HEAD(&req->queue);
1171
1172    return &req->req;
1173}
1174
1175static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1176{
1177    struct jz4740_request *req;
1178
1179    DEBUG("%s, %p\n", __FUNCTION__, ep);
1180
1181    req = container_of(_req, struct jz4740_request, req);
1182    WARN_ON(!list_empty(&req->queue));
1183    kfree(req);
1184}
1185
1186/*--------------------------------------------------------------------*/
1187
1188/** Queue one request
1189 * Kickstart transfer if needed
1190 * NOTE: Sets INDEX register
1191 */
1192static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1193            gfp_t gfp_flags)
1194{
1195    struct jz4740_request *req;
1196    struct jz4740_ep *ep;
1197    struct jz4740_udc *dev;
1198    unsigned long flags;
1199
1200    DEBUG("%s, %p\n", __FUNCTION__, _ep);
1201
1202    req = container_of(_req, struct jz4740_request, req);
1203    if (unlikely
1204        (!_req || !_req->complete || !_req->buf
1205         || !list_empty(&req->queue))) {
1206        DEBUG("%s, bad params\n", __FUNCTION__);
1207        return -EINVAL;
1208    }
1209
1210    ep = container_of(_ep, struct jz4740_ep, ep);
1211    if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1212        DEBUG("%s, bad ep\n", __FUNCTION__);
1213        return -EINVAL;
1214    }
1215
1216    dev = ep->dev;
1217    if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1218        DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1219        return -ESHUTDOWN;
1220    }
1221
1222    DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1223          _req->buf);
1224
1225    spin_lock_irqsave(&dev->lock, flags);
1226
1227    _req->status = -EINPROGRESS;
1228    _req->actual = 0;
1229
1230    /* kickstart this i/o queue? */
1231    DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1232          ep->stopped);
1233    if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1234        uint32_t csr;
1235
1236        if (unlikely(ep_index(ep) == 0)) {
1237            /* EP0 */
1238            list_add_tail(&req->queue, &ep->queue);
1239            jz4740_ep0_kick(dev, ep);
1240            req = 0;
1241        } else if (use_dma) {
1242            /* DMA */
1243            kick_dma(ep, req);
1244        }
1245        /* PIO */
1246        else if (ep_is_in(ep)) {
1247            /* EP1 & EP2 */
1248            jz_udc_set_index(dev, ep_index(ep));
1249            csr = usb_readb(dev, ep->csr);
1250            pio_irq_enable(ep);
1251            if (!(csr & USB_INCSR_FFNOTEMPT)) {
1252                if (write_fifo(ep, req) == 1)
1253                    req = 0;
1254            }
1255        } else {
1256            /* EP1 */
1257            jz_udc_set_index(dev, ep_index(ep));
1258            csr = usb_readb(dev, ep->csr);
1259            pio_irq_enable(ep);
1260            if (csr & USB_OUTCSR_OUTPKTRDY) {
1261                if (read_fifo(ep, req) == 1)
1262                    req = 0;
1263            }
1264        }
1265    }
1266
1267    /* pio or dma irq handler advances the queue. */
1268    if (likely(req != 0))
1269        list_add_tail(&req->queue, &ep->queue);
1270
1271    spin_unlock_irqrestore(&dev->lock, flags);
1272
1273    return 0;
1274}
1275
1276/* dequeue JUST ONE request */
1277static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1278{
1279    struct jz4740_ep *ep;
1280    struct jz4740_request *req;
1281    unsigned long flags;
1282
1283    DEBUG("%s, %p\n", __FUNCTION__, _ep);
1284
1285    ep = container_of(_ep, struct jz4740_ep, ep);
1286    if (!_ep || ep->type == ep_control)
1287        return -EINVAL;
1288
1289    spin_lock_irqsave(&ep->dev->lock, flags);
1290
1291    /* make sure it's actually queued on this endpoint */
1292    list_for_each_entry(req, &ep->queue, queue) {
1293        if (&req->req == _req)
1294            break;
1295    }
1296    if (&req->req != _req) {
1297        spin_unlock_irqrestore(&ep->dev->lock, flags);
1298        return -EINVAL;
1299    }
1300    done(ep, req, -ECONNRESET);
1301
1302    spin_unlock_irqrestore(&ep->dev->lock, flags);
1303    return 0;
1304}
1305
1306/** Return bytes in EP FIFO
1307 * NOTE: Sets INDEX register to EP
1308 */
1309static int jz4740_fifo_status(struct usb_ep *_ep)
1310{
1311    uint32_t csr;
1312    int count = 0;
1313    struct jz4740_ep *ep;
1314    unsigned long flags;
1315
1316    ep = container_of(_ep, struct jz4740_ep, ep);
1317    if (!_ep) {
1318        DEBUG("%s, bad ep\n", __FUNCTION__);
1319        return -ENODEV;
1320    }
1321
1322    DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1323
1324    /* LPD can't report unclaimed bytes from IN fifos */
1325    if (ep_is_in(ep))
1326        return -EOPNOTSUPP;
1327
1328    spin_lock_irqsave(&ep->dev->lock, flags);
1329    jz_udc_set_index(ep->dev, ep_index(ep));
1330
1331    csr = usb_readb(ep->dev, ep->csr);
1332    if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1333        csr & 0x1) {
1334        count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1335    }
1336
1337    spin_unlock_irqrestore(&ep->dev->lock, flags);
1338
1339    return count;
1340}
1341
1342/** Flush EP FIFO
1343 * NOTE: Sets INDEX register to EP
1344 */
1345static void jz4740_fifo_flush(struct usb_ep *_ep)
1346{
1347    struct jz4740_ep *ep;
1348    unsigned long flags;
1349
1350    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1351
1352    ep = container_of(_ep, struct jz4740_ep, ep);
1353    if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1354        DEBUG("%s, bad ep\n", __FUNCTION__);
1355        return;
1356    }
1357
1358    spin_lock_irqsave(&ep->dev->lock, flags);
1359
1360    jz_udc_set_index(ep->dev, ep_index(ep));
1361    flush(ep);
1362
1363    spin_unlock_irqrestore(&ep->dev->lock, flags);
1364}
1365
1366/****************************************************************/
1367/* End Point 0 related functions */
1368/****************************************************************/
1369
1370/* return: 0 = still running, 1 = completed, negative = errno */
1371static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1372{
1373    uint32_t max;
1374    unsigned count;
1375    int is_last;
1376
1377    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1378    max = ep_maxpacket(ep);
1379
1380    count = write_packet(ep, req, max);
1381
1382    /* last packet is usually short (or a zlp) */
1383    if (unlikely(count != max))
1384        is_last = 1;
1385    else {
1386        if (likely(req->req.length != req->req.actual) || req->req.zero)
1387            is_last = 0;
1388        else
1389            is_last = 1;
1390    }
1391
1392    DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1393          ep->ep.name, count,
1394          is_last ? "/L" : "", req->req.length - req->req.actual, req);
1395
1396    /* requests complete when all IN data is in the FIFO */
1397    if (is_last) {
1398        done(ep, req, 0);
1399        return 1;
1400    }
1401
1402    return 0;
1403}
1404
1405static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1406                       unsigned char *cp, int max)
1407{
1408    int bytes;
1409    int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1410
1411    if (count > max)
1412        count = max;
1413    bytes = count;
1414    while (count--)
1415        *cp++ = usb_readb(ep->dev, ep->fifo);
1416
1417    return bytes;
1418}
1419
1420static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1421                     unsigned char *cp, int count)
1422{
1423    DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1424    while (count--)
1425        usb_writeb(ep->dev, ep->fifo, *cp++);
1426}
1427
1428static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1429{
1430    struct jz4740_udc *dev = ep->dev;
1431    uint32_t csr;
1432    uint8_t *buf;
1433    unsigned bufferspace, count, is_short;
1434
1435    DEBUG_EP0("%s\n", __FUNCTION__);
1436
1437    csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1438    if (!(csr & USB_CSR0_OUTPKTRDY))
1439        return 0;
1440
1441    buf = req->req.buf + req->req.actual;
1442    prefetchw(buf);
1443    bufferspace = req->req.length - req->req.actual;
1444
1445    /* read all bytes from this packet */
1446    if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1447        count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1448        req->req.actual += min(count, bufferspace);
1449    } else /* zlp */
1450        count = 0;
1451
1452    is_short = (count < ep->ep.maxpacket);
1453    DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1454          ep->ep.name, csr, count,
1455          is_short ? "/S" : "", req, req->req.actual, req->req.length);
1456
1457    while (likely(count-- != 0)) {
1458        uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1459
1460        if (unlikely(bufferspace == 0)) {
1461            /* this happens when the driver's buffer
1462             * is smaller than what the host sent.
1463             * discard the extra data.
1464             */
1465            if (req->req.status != -EOVERFLOW)
1466                DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1467                      count);
1468            req->req.status = -EOVERFLOW;
1469        } else {
1470            *buf++ = byte;
1471            bufferspace--;
1472        }
1473    }
1474
1475    /* completion */
1476    if (is_short || req->req.actual == req->req.length) {
1477        done(ep, req, 0);
1478        return 1;
1479    }
1480
1481    /* finished that packet. the next one may be waiting... */
1482    return 0;
1483}
1484
1485/**
1486 * udc_set_address - set the USB address for this device
1487 * @address:
1488 *
1489 * Called from control endpoint function after it decodes a set address setup packet.
1490 */
1491static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1492{
1493    DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1494
1495    dev->usb_address = address;
1496    usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1497}
1498
1499/*
1500 * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1501 * - if error
1502 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1503 * - else
1504 * set USB_CSR0_SVDOUTPKTRDY bit
1505                 if last set USB_CSR0_DATAEND bit
1506 */
1507static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1508{
1509    struct jz4740_request *req;
1510    struct jz4740_ep *ep = &dev->ep[0];
1511    int ret;
1512
1513    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1514
1515    if (list_empty(&ep->queue))
1516        req = 0;
1517    else
1518        req = list_entry(ep->queue.next, struct jz4740_request, queue);
1519
1520    if (req) {
1521        if (req->req.length == 0) {
1522            DEBUG_EP0("ZERO LENGTH OUT!\n");
1523            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1524            dev->ep0state = WAIT_FOR_SETUP;
1525            return;
1526        } else if (kickstart) {
1527            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1528            return;
1529        }
1530        ret = read_fifo_ep0(ep, req);
1531        if (ret) {
1532            /* Done! */
1533            DEBUG_EP0("%s: finished, waiting for status\n",
1534                  __FUNCTION__);
1535            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1536            dev->ep0state = WAIT_FOR_SETUP;
1537        } else {
1538            /* Not done yet.. */
1539            DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1540            usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1541        }
1542    } else {
1543        DEBUG_EP0("NO REQ??!\n");
1544    }
1545}
1546
1547/*
1548 * DATA_STATE_XMIT
1549 */
1550static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1551{
1552    struct jz4740_request *req;
1553    struct jz4740_ep *ep = &dev->ep[0];
1554    int ret, need_zlp = 0;
1555
1556    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1557
1558    if (list_empty(&ep->queue))
1559        req = 0;
1560    else
1561        req = list_entry(ep->queue.next, struct jz4740_request, queue);
1562
1563    if (!req) {
1564        DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1565        return 0;
1566    }
1567
1568    if (req->req.length == 0) {
1569        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1570        dev->ep0state = WAIT_FOR_SETUP;
1571        return 1;
1572    }
1573
1574    if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1575        /* Next write will end with the packet size, */
1576        /* so we need zero-length-packet */
1577        need_zlp = 1;
1578    }
1579
1580    ret = write_fifo_ep0(ep, req);
1581
1582    if (ret == 1 && !need_zlp) {
1583        /* Last packet */
1584        DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1585
1586        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1587        dev->ep0state = WAIT_FOR_SETUP;
1588    } else {
1589        DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1590        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1591    }
1592
1593    if (need_zlp) {
1594        DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1595        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1596        dev->ep0state = DATA_STATE_NEED_ZLP;
1597    }
1598
1599    return 1;
1600}
1601
1602static int jz4740_handle_get_status(struct jz4740_udc *dev,
1603                    struct usb_ctrlrequest *ctrl)
1604{
1605    struct jz4740_ep *ep0 = &dev->ep[0];
1606    struct jz4740_ep *qep;
1607    int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1608    uint16_t val = 0;
1609
1610    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1611
1612    if (reqtype == USB_RECIP_INTERFACE) {
1613        /* This is not supported.
1614         * And according to the USB spec, this one does nothing..
1615         * Just return 0
1616         */
1617        DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1618    } else if (reqtype == USB_RECIP_DEVICE) {
1619        DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1620        val |= (1 << 0); /* Self powered */
1621        /*val |= (1<<1); *//* Remote wakeup */
1622    } else if (reqtype == USB_RECIP_ENDPOINT) {
1623        int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1624
1625        DEBUG_SETUP
1626            ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1627             ep_num, ctrl->wLength);
1628
1629        if (ctrl->wLength > 2 || ep_num > 3)
1630            return -EOPNOTSUPP;
1631
1632        qep = &dev->ep[ep_num];
1633        if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1634            && ep_index(qep) != 0) {
1635            return -EOPNOTSUPP;
1636        }
1637
1638        jz_udc_set_index(dev, ep_index(qep));
1639
1640        /* Return status on next IN token */
1641        switch (qep->type) {
1642        case ep_control:
1643            val =
1644                (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1645                USB_CSR0_SENDSTALL;
1646            break;
1647        case ep_bulk_in:
1648        case ep_interrupt:
1649            val =
1650                (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1651                USB_INCSR_SENDSTALL;
1652            break;
1653        case ep_bulk_out:
1654            val =
1655                (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1656                USB_OUTCSR_SENDSTALL;
1657            break;
1658        }
1659
1660        /* Back to EP0 index */
1661        jz_udc_set_index(dev, 0);
1662
1663        DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1664                ctrl->wIndex, val);
1665    } else {
1666        DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1667        return -EOPNOTSUPP;
1668    }
1669
1670    /* Clear "out packet ready" */
1671    usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1672    /* Put status to FIFO */
1673    jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1674    /* Issue "In packet ready" */
1675    usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1676
1677    return 0;
1678}
1679
1680/*
1681 * WAIT_FOR_SETUP (OUTPKTRDY)
1682 * - read data packet from EP0 FIFO
1683 * - decode command
1684 * - if error
1685 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1686 * - else
1687 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1688 */
1689static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1690{
1691    struct jz4740_ep *ep = &dev->ep[0];
1692    struct usb_ctrlrequest ctrl;
1693    int i;
1694
1695    DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1696
1697    /* Nuke all previous transfers */
1698    nuke(ep, -EPROTO);
1699
1700    /* read control req from fifo (8 bytes) */
1701    jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1702
1703    DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1704            ctrl.bRequestType, ctrl.bRequest,
1705            ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1706
1707    /* Set direction of EP0 */
1708    if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1709        ep->bEndpointAddress |= USB_DIR_IN;
1710    } else {
1711        ep->bEndpointAddress &= ~USB_DIR_IN;
1712    }
1713
1714    /* Handle some SETUP packets ourselves */
1715    switch (ctrl.bRequest) {
1716    case USB_REQ_SET_ADDRESS:
1717        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1718            break;
1719
1720        DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1721        udc_set_address(dev, ctrl.wValue);
1722        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1723        return;
1724
1725    case USB_REQ_SET_CONFIGURATION:
1726        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1727            break;
1728
1729        DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1730/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1731
1732        /* Enable RESUME and SUSPEND interrupts */
1733        usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1734        break;
1735
1736    case USB_REQ_SET_INTERFACE:
1737        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1738            break;
1739
1740        DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1741/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1742        break;
1743
1744    case USB_REQ_GET_STATUS:
1745        if (jz4740_handle_get_status(dev, &ctrl) == 0)
1746            return;
1747
1748    case USB_REQ_CLEAR_FEATURE:
1749    case USB_REQ_SET_FEATURE:
1750        if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1751            struct jz4740_ep *qep;
1752            int ep_num = (ctrl.wIndex & 0x0f);
1753
1754            /* Support only HALT feature */
1755            if (ctrl.wValue != 0 || ctrl.wLength != 0
1756                || ep_num > 3 || ep_num < 1)
1757                break;
1758
1759            qep = &dev->ep[ep_num];
1760            spin_unlock(&dev->lock);
1761            if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1762                DEBUG_SETUP("SET_FEATURE (%d)\n",
1763                        ep_num);
1764                jz4740_set_halt(&qep->ep, 1);
1765            } else {
1766                DEBUG_SETUP("CLR_FEATURE (%d)\n",
1767                        ep_num);
1768                jz4740_set_halt(&qep->ep, 0);
1769            }
1770            spin_lock(&dev->lock);
1771
1772            jz_udc_set_index(dev, 0);
1773
1774            /* Reply with a ZLP on next IN token */
1775            usb_setb(dev, JZ_REG_UDC_CSR0,
1776                 (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1777            return;
1778        }
1779        break;
1780
1781    default:
1782        break;
1783    }
1784
1785    /* gadget drivers see class/vendor specific requests,
1786     * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1787     * and more.
1788     */
1789    if (dev->driver) {
1790        /* device-2-host (IN) or no data setup command, process immediately */
1791        spin_unlock(&dev->lock);
1792
1793        i = dev->driver->setup(&dev->gadget, &ctrl);
1794        spin_lock(&dev->lock);
1795
1796        if (unlikely(i < 0)) {
1797            /* setup processing failed, force stall */
1798            DEBUG_SETUP
1799                (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1800                 i);
1801            jz_udc_set_index(dev, 0);
1802            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1803
1804            /* ep->stopped = 1; */
1805            dev->ep0state = WAIT_FOR_SETUP;
1806        }
1807        else {
1808            DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1809/* if (!ctrl.wLength) {
1810                usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1811            }*/
1812        }
1813    }
1814}
1815
1816/*
1817 * DATA_STATE_NEED_ZLP
1818 */
1819static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1820{
1821    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1822
1823    usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1824    dev->ep0state = WAIT_FOR_SETUP;
1825}
1826
1827/*
1828 * handle ep0 interrupt
1829 */
1830static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1831{
1832    struct jz4740_ep *ep = &dev->ep[0];
1833    uint32_t csr;
1834
1835    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1836    /* Set index 0 */
1837    jz_udc_set_index(dev, 0);
1838    csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1839
1840    DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1841
1842    /*
1843     * if SENT_STALL is set
1844     * - clear the SENT_STALL bit
1845     */
1846    if (csr & USB_CSR0_SENTSTALL) {
1847        DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1848        usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1849        nuke(ep, -ECONNABORTED);
1850        dev->ep0state = WAIT_FOR_SETUP;
1851        return;
1852    }
1853
1854    /*
1855     * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1856     * - fill EP0 FIFO
1857     * - if last packet
1858     * - set IN_PKT_RDY | DATA_END
1859     * - else
1860     * set IN_PKT_RDY
1861     */
1862    if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1863        DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1864              __FUNCTION__);
1865
1866        switch (dev->ep0state) {
1867        case DATA_STATE_XMIT:
1868            DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1869            jz4740_ep0_in(dev, csr);
1870            return;
1871        case DATA_STATE_NEED_ZLP:
1872            DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1873            jz4740_ep0_in_zlp(dev, csr);
1874            return;
1875        default:
1876            /* Stall? */
1877// DEBUG_EP0("Odd state!! state = %s\n",
1878// state_names[dev->ep0state]);
1879            dev->ep0state = WAIT_FOR_SETUP;
1880            /* nuke(ep, 0); */
1881            /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1882// break;
1883            return;
1884        }
1885    }
1886
1887    /*
1888     * if SETUPEND is set
1889     * - abort the last transfer
1890     * - set SERVICED_SETUP_END_BIT
1891     */
1892    if (csr & USB_CSR0_SETUPEND) {
1893        DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1894
1895        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1896        nuke(ep, 0);
1897        dev->ep0state = WAIT_FOR_SETUP;
1898    }
1899
1900    /*
1901     * if USB_CSR0_OUTPKTRDY is set
1902     * - read data packet from EP0 FIFO
1903     * - decode command
1904     * - if error
1905     * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1906     * - else
1907     * set SVDOUTPKTRDY | DATAEND bits
1908     */
1909    if (csr & USB_CSR0_OUTPKTRDY) {
1910
1911        DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1912              csr);
1913
1914        switch (dev->ep0state) {
1915        case WAIT_FOR_SETUP:
1916            DEBUG_EP0("WAIT_FOR_SETUP\n");
1917            jz4740_ep0_setup(dev, csr);
1918            break;
1919
1920        case DATA_STATE_RECV:
1921            DEBUG_EP0("DATA_STATE_RECV\n");
1922            jz4740_ep0_out(dev, csr, 0);
1923            break;
1924
1925        default:
1926            /* send stall? */
1927            DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1928                  dev->ep0state);
1929            break;
1930        }
1931    }
1932}
1933
1934static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1935{
1936    uint32_t csr;
1937
1938    jz_udc_set_index(dev, 0);
1939
1940    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1941
1942    /* Clear "out packet ready" */
1943
1944    if (ep_is_in(ep)) {
1945        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1946        csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1947        dev->ep0state = DATA_STATE_XMIT;
1948        jz4740_ep0_in(dev, csr);
1949    } else {
1950        csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1951        dev->ep0state = DATA_STATE_RECV;
1952        jz4740_ep0_out(dev, csr, 1);
1953    }
1954}
1955
1956/** Handle USB RESET interrupt
1957 */
1958static void jz4740_reset_irq(struct jz4740_udc *dev)
1959{
1960    dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1961        USB_SPEED_HIGH : USB_SPEED_FULL;
1962
1963    DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address,
1964            (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1965}
1966
1967/*
1968 * jz4740 usb device interrupt handler.
1969 */
1970static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
1971{
1972    struct jz4740_udc *dev = _dev;
1973    uint8_t index;
1974
1975    uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1976    uint32_t intr_in = usb_readw(dev, JZ_REG_UDC_INTRIN);
1977    uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT);
1978    uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR);
1979
1980    if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1981        return IRQ_HANDLED;
1982
1983
1984    DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1985          intr_out, intr_in, intr_usb);
1986
1987    spin_lock(&dev->lock);
1988    index = usb_readb(dev, JZ_REG_UDC_INDEX);
1989
1990    /* Check for resume from suspend mode */
1991    if ((intr_usb & USB_INTR_RESUME) &&
1992        (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1993        DEBUG("USB resume\n");
1994        dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */
1995    }
1996
1997    /* Check for system interrupts */
1998    if (intr_usb & USB_INTR_RESET) {
1999        DEBUG("USB reset\n");
2000        jz4740_reset_irq(dev);
2001    }
2002
2003    /* Check for endpoint 0 interrupt */
2004    if (intr_in & USB_INTR_EP0) {
2005        DEBUG("USB_INTR_EP0 (control)\n");
2006        jz4740_handle_ep0(dev, intr_in);
2007    }
2008
2009    /* Check for Bulk-IN DMA interrupt */
2010    if (intr_dma & 0x1) {
2011        int ep_num;
2012        struct jz4740_ep *ep;
2013        ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
2014        ep = &dev->ep[ep_num + 1];
2015        jz_udc_set_index(dev, ep_num);
2016        usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
2017/* jz4740_in_epn(dev, ep_num, intr_in);*/
2018    }
2019
2020    /* Check for Bulk-OUT DMA interrupt */
2021    if (intr_dma & 0x2) {
2022        int ep_num;
2023        ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
2024        jz4740_out_epn(dev, ep_num, intr_out);
2025    }
2026
2027    /* Check for each configured endpoint interrupt */
2028    if (intr_in & USB_INTR_INEP1) {
2029        DEBUG("USB_INTR_INEP1\n");
2030        jz4740_in_epn(dev, 1, intr_in);
2031    }
2032
2033    if (intr_in & USB_INTR_INEP2) {
2034        DEBUG("USB_INTR_INEP2\n");
2035        jz4740_in_epn(dev, 2, intr_in);
2036    }
2037
2038    if (intr_out & USB_INTR_OUTEP1) {
2039        DEBUG("USB_INTR_OUTEP1\n");
2040        jz4740_out_epn(dev, 1, intr_out);
2041    }
2042
2043    /* Check for suspend mode */
2044    if ((intr_usb & USB_INTR_SUSPEND) &&
2045        (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
2046        DEBUG("USB suspend\n");
2047        dev->driver->suspend(&dev->gadget);
2048        /* Host unloaded from us, can do something, such as flushing
2049         the NAND block cache etc. */
2050    }
2051
2052    jz_udc_set_index(dev, index);
2053
2054    spin_unlock(&dev->lock);
2055
2056    return IRQ_HANDLED;
2057}
2058
2059
2060
2061/*-------------------------------------------------------------------------*/
2062
2063/* Common functions - Added by River */
2064static struct jz4740_udc udc_dev;
2065
2066static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
2067{
2068    return container_of(gadget, struct jz4740_udc, gadget);
2069}
2070/* End added */
2071
2072static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
2073{
2074    DEBUG("%s, %p\n", __FUNCTION__, _gadget);
2075    return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
2076}
2077
2078static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
2079{
2080    /* host may not have enabled remote wakeup */
2081    /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2082       return -EHOSTUNREACH;
2083       udc_set_mask_UDCCR(UDCCR_RSM); */
2084    return -ENOTSUPP;
2085}
2086
2087static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
2088{
2089    struct jz4740_udc *udc = gadget_to_udc(_gadget);
2090
2091    unsigned long flags;
2092
2093    local_irq_save(flags);
2094
2095    if (on) {
2096        udc->state = UDC_STATE_ENABLE;
2097        udc_enable(udc);
2098    } else {
2099        udc->state = UDC_STATE_DISABLE;
2100        udc_disable(udc);
2101    }
2102
2103    local_irq_restore(flags);
2104
2105    return 0;
2106}
2107
2108static const struct usb_gadget_ops jz4740_udc_ops = {
2109    .get_frame = jz4740_udc_get_frame,
2110    .wakeup = jz4740_udc_wakeup,
2111    .pullup = jz4740_udc_pullup,
2112    /* current versions must always be self-powered */
2113};
2114
2115static struct usb_ep_ops jz4740_ep_ops = {
2116    .enable = jz4740_ep_enable,
2117    .disable = jz4740_ep_disable,
2118
2119    .alloc_request = jz4740_alloc_request,
2120    .free_request = jz4740_free_request,
2121
2122    .queue = jz4740_queue,
2123    .dequeue = jz4740_dequeue,
2124
2125    .set_halt = jz4740_set_halt,
2126    .fifo_status = jz4740_fifo_status,
2127    .fifo_flush = jz4740_fifo_flush,
2128};
2129
2130
2131/*-------------------------------------------------------------------------*/
2132
2133static struct jz4740_udc udc_dev = {
2134    .usb_address = 0,
2135    .gadget = {
2136        .ops = &jz4740_udc_ops,
2137        .ep0 = &udc_dev.ep[0].ep,
2138        .name = "jz-udc",
2139        .dev = {
2140            .init_name = "gadget",
2141        },
2142    },
2143
2144    /* control endpoint */
2145    .ep[0] = {
2146        .ep = {
2147            .name = "ep0",
2148            .ops = &jz4740_ep_ops,
2149            .maxpacket = EP0_MAXPACKETSIZE,
2150        },
2151        .dev = &udc_dev,
2152
2153        .bEndpointAddress = 0,
2154        .bmAttributes = 0,
2155
2156        .type = ep_control,
2157        .fifo = JZ_REG_UDC_EP_FIFO(0),
2158        .csr = JZ_REG_UDC_CSR0,
2159    },
2160
2161    /* bulk out endpoint */
2162    .ep[1] = {
2163        .ep = {
2164            .name = "ep1out-bulk",
2165            .ops = &jz4740_ep_ops,
2166            .maxpacket = EPBULK_MAXPACKETSIZE,
2167        },
2168        .dev = &udc_dev,
2169
2170        .bEndpointAddress = 1,
2171        .bmAttributes = USB_ENDPOINT_XFER_BULK,
2172
2173        .type = ep_bulk_out,
2174        .fifo = JZ_REG_UDC_EP_FIFO(1),
2175        .csr = JZ_REG_UDC_OUTCSR,
2176    },
2177
2178    /* bulk in endpoint */
2179    .ep[2] = {
2180        .ep = {
2181            .name = "ep1in-bulk",
2182            .ops = &jz4740_ep_ops,
2183            .maxpacket = EPBULK_MAXPACKETSIZE,
2184        },
2185        .dev = &udc_dev,
2186
2187        .bEndpointAddress = 1 | USB_DIR_IN,
2188        .bmAttributes = USB_ENDPOINT_XFER_BULK,
2189
2190        .type = ep_bulk_in,
2191        .fifo = JZ_REG_UDC_EP_FIFO(1),
2192        .csr = JZ_REG_UDC_INCSR,
2193    },
2194
2195    /* interrupt in endpoint */
2196    .ep[3] = {
2197        .ep = {
2198            .name = "ep2in-int",
2199            .ops = &jz4740_ep_ops,
2200            .maxpacket = EPINTR_MAXPACKETSIZE,
2201        },
2202        .dev = &udc_dev,
2203
2204        .bEndpointAddress = 2 | USB_DIR_IN,
2205        .bmAttributes = USB_ENDPOINT_XFER_INT,
2206
2207        .type = ep_interrupt,
2208        .fifo = JZ_REG_UDC_EP_FIFO(2),
2209        .csr = JZ_REG_UDC_INCSR,
2210    },
2211};
2212
2213static void gadget_release(struct device *_dev)
2214{
2215}
2216
2217
2218static int jz4740_udc_probe(struct platform_device *pdev)
2219{
2220    struct jz4740_udc *dev = &udc_dev;
2221    int ret;
2222
2223    spin_lock_init(&dev->lock);
2224    the_controller = dev;
2225
2226    dev->dev = &pdev->dev;
2227    dev_set_name(&dev->gadget.dev, "gadget");
2228    dev->gadget.dev.parent = &pdev->dev;
2229    dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2230    dev->gadget.dev.release = gadget_release;
2231
2232    ret = device_register(&dev->gadget.dev);
2233        if (ret)
2234        return ret;
2235
2236    platform_set_drvdata(pdev, dev);
2237
2238    dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2239
2240    if (!dev->mem) {
2241        ret = -ENOENT;
2242        dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2243        goto err_device_unregister;
2244    }
2245
2246    dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name);
2247
2248    if (!dev->mem) {
2249        ret = -EBUSY;
2250        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2251        goto err_device_unregister;
2252    }
2253
2254    dev->base = ioremap(dev->mem->start, resource_size(dev->mem));
2255
2256    if (!dev->base) {
2257        ret = -EBUSY;
2258        dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2259        goto err_release_mem_region;
2260    }
2261
2262    dev->irq = platform_get_irq(pdev, 0);
2263
2264    ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED,
2265                            pdev->name, dev);
2266        if (ret) {
2267                dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2268                goto err_iounmap;
2269    }
2270
2271    udc_disable(dev);
2272    udc_reinit(dev);
2273
2274    return 0;
2275
2276err_iounmap:
2277    iounmap(dev->base);
2278err_release_mem_region:
2279    release_mem_region(dev->mem->start, resource_size(dev->mem));
2280err_device_unregister:
2281    device_unregister(&dev->gadget.dev);
2282    platform_set_drvdata(pdev, NULL);
2283
2284    the_controller = 0;
2285
2286        return ret;
2287}
2288
2289static int jz4740_udc_remove(struct platform_device *pdev)
2290{
2291    struct jz4740_udc *dev = platform_get_drvdata(pdev);
2292
2293    if (dev->driver)
2294        return -EBUSY;
2295
2296    udc_disable(dev);
2297#ifdef UDC_PROC_FILE
2298    remove_proc_entry(proc_node_name, NULL);
2299#endif
2300
2301    free_irq(dev->irq, dev);
2302    iounmap(dev->base);
2303    release_mem_region(dev->mem->start, resource_size(dev->mem));
2304
2305    platform_set_drvdata(pdev, NULL);
2306    device_unregister(&dev->gadget.dev);
2307    the_controller = NULL;
2308
2309    return 0;
2310}
2311
2312static struct platform_driver udc_driver = {
2313    .probe = jz4740_udc_probe,
2314    .remove = jz4740_udc_remove,
2315    .driver = {
2316        .name = "jz-udc",
2317        .owner = THIS_MODULE,
2318    },
2319};
2320
2321/*-------------------------------------------------------------------------*/
2322
2323static int __init udc_init (void)
2324{
2325    return platform_driver_register(&udc_driver);
2326}
2327
2328static void __exit udc_exit (void)
2329{
2330    platform_driver_unregister(&udc_driver);
2331}
2332
2333module_init(udc_init);
2334module_exit(udc_exit);
2335
2336MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2337MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2338MODULE_LICENSE("GPL");
drivers/usb/gadget/jz4740_udc.h
1/*
2 * linux/drivers/usb/gadget/jz4740_udc.h
3 *
4 * Ingenic JZ4740 on-chip high speed USB device controller
5 *
6 * Copyright (C) 2006 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef __USB_GADGET_JZ4740_H__
16#define __USB_GADGET_JZ4740_H__
17
18/*-------------------------------------------------------------------------*/
19
20// Max packet size
21#define EP0_MAXPACKETSIZE 64
22#define EPBULK_MAXPACKETSIZE 512
23#define EPINTR_MAXPACKETSIZE 64
24
25#define UDC_MAX_ENDPOINTS 4
26
27/*-------------------------------------------------------------------------*/
28
29typedef enum ep_type {
30    ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
31} ep_type_t;
32
33struct jz4740_ep {
34    struct usb_ep ep;
35    struct jz4740_udc *dev;
36
37    const struct usb_endpoint_descriptor *desc;
38    unsigned long pio_irqs;
39
40    uint8_t stopped;
41    uint8_t bEndpointAddress;
42    uint8_t bmAttributes;
43
44    ep_type_t type;
45    size_t fifo;
46    u32 csr;
47
48    uint32_t reg_addr;
49    struct list_head queue;
50};
51
52struct jz4740_request {
53    struct usb_request req;
54    struct list_head queue;
55};
56
57enum ep0state {
58    WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
59    DATA_STATE_XMIT, /* data tx stage */
60    DATA_STATE_NEED_ZLP, /* data tx zlp stage */
61    WAIT_FOR_OUT_STATUS, /* status stages */
62    DATA_STATE_RECV, /* data rx stage */
63};
64
65/* For function binding with UDC Disable - Added by River */
66typedef enum {
67    UDC_STATE_ENABLE = 0,
68    UDC_STATE_DISABLE,
69}udc_state_t;
70
71struct jz4740_udc {
72    struct usb_gadget gadget;
73    struct usb_gadget_driver *driver;
74    struct device *dev;
75    spinlock_t lock;
76
77    enum ep0state ep0state;
78    struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
79
80    unsigned char usb_address;
81
82    udc_state_t state;
83
84    struct resource *mem;
85    void __iomem *base;
86    int irq;
87    uint32_t in_mask;
88    uint32_t out_mask;
89};
90
91extern struct jz4740_udc *the_controller;
92
93#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
94#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
95#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
96
97#endif /* __USB_GADGET_JZ4740_H__ */
drivers/usb/gadget/udc_hotplug.h
1/*
2 * Ingenic USB Device Contoller Hotplug External Interfaces
3 */
4
5#ifndef __UDC_HOTPLUG_H__
6#define __UDC_HOTPLUG_H__
7
8#include <linux/notifier.h>
9
10typedef enum {
11    BROADCAST_TYPE_STATE = 0,
12    BROADCAST_TYPE_EVENT,
13}udc_hotplug_broadcast_type_t;
14
15typedef enum {
16    EVENT_STATE_OFFLINE = 0,
17    EVENT_STATE_ONLINE,
18}udc_hotplug_event_state_t;
19
20typedef enum {
21    EVENT_TYPE_USB = 0,
22    EVENT_TYPE_CABLE,
23}udc_hotplug_event_type_t;
24
25enum {
26    EVENT_FLAG_UDC_PHY_TOUCHED = 0,
27};
28
29typedef struct {
30    udc_hotplug_event_type_t type;
31    udc_hotplug_event_state_t state;
32    unsigned long flags;
33}udc_hotplug_event_t;
34
35/* Register notifier */
36int udc_hotplug_register_notifier(struct notifier_block *n, int request_state);
37
38/* Unregister notifier */
39int udc_hotplug_unregister_notifier(struct notifier_block *n);
40
41/* Start keep alive */
42int udc_hotplug_start_keep_alive(unsigned long timer_interval_in_jiffies, unsigned long counter_limit);
43
44/* Do keep alive */
45void udc_hotplug_do_keep_alive(void);
46
47/* Stop keep alive */
48void udc_hotplug_stop_keep_alive(void);
49
50#endif /* Define __UDC_HOTPLUG_H__ */
drivers/usb/gadget/udc_hotplug_core.c
1/*
2 * Ingenic USB Device Controller Hotplug Core Function
3 * Detection mechanism and code are based on the old version of udc_hotplug.c
4 */
5
6#include <linux/sched.h>
7#include <linux/module.h>
8#include <linux/notifier.h>
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/slab.h>
12#include <linux/err.h>
13#include <linux/wait.h>
14#include <linux/kthread.h>
15#include <linux/timer.h>
16
17#include <asm/jzsoc.h>
18
19#include "udc_hotplug.h"
20
21#define PFX "jz_hotplug_udc"
22
23#define D(msg, fmt...) \
24// printk(KERN_ERR PFX": %s(): "msg, __func__, ##fmt);
25
26/* HAVE_DETECT_SYNC
27   Provide a lock like seqlock keep the synchronization between the start and the end of a detection,
28   If the lock seems not synchronous(new interrupt comes, when doing our detection) in the end of a detection,
29   the result of the detection is discarded. No event will be broadcast, and the detection will be restarted.
30
31   Use to filter out more significant events when the interrupt is too noisy.
32*/
33
34//#define HAVE_DETECT_SYNC 1
35
36#if defined (HAVE_DETECT_SYNC)
37#define NR_RESTART_TIMES 3
38#define NR_JIFFIES_SLEEP_BEFORE_RESTART 7
39#endif
40
41#define NR_GPIO_STABLE_TIMES 50
42#define NR_JIFFIES_USB_DETECT_WAIT 11
43
44#define DEFAULT_KEEP_ALIVE_TIMER_INTERVAL (2 * HZ)
45#define DEFAULT_KEEP_ALIVE_COUNTER_LIMIT 2
46
47#define UDC_HOTPLUG_PIN GPIO_UDC_HOTPLUG
48#define UDC_HOTPLUG_IRQ (IRQ_GPIO_0 + UDC_HOTPLUG_PIN)
49
50/* UDC State bits */
51enum {
52    /* Online state. */
53    BIT_CABLE_ONLINE = 0,
54    BIT_USB_ONLINE,
55
56    /* State changed ?*/
57    BIT_CABLE_CHANGE,
58    BIT_USB_CHANGE,
59
60    /* What detection will be done ? */
61    BIT_DO_CABLE_DETECT,
62    BIT_DO_USB_DETECT,
63
64    /* What detection is requested ? */
65    BIT_REQUEST_CABLE_DETECT,
66    BIT_REQUEST_USB_DETECT,
67
68    /* Indicate whether a detection is finisned. */
69    BIT_USB_DETECT_DONE,
70    BIT_CABLE_DETECT_DONE,
71
72    BIT_UDC_PHY_TOUCHED,
73
74    /* Keep alive */
75    BIT_KEEP_ALIVE,
76    BIT_KEEP_ALIVE_TIMEOUT,
77};
78
79struct uh_data {
80    /* Notifier */
81    struct blocking_notifier_head notifier_head;
82
83    /* Thread */
84    struct task_struct *kthread;
85
86    /* Wait queue */
87    wait_queue_head_t kthread_wq; /* Kernel thread sleep here. */
88    wait_queue_head_t wq; /* Others sleep here. */
89
90    /* UDC State */
91    unsigned long state;
92
93    /* Current Event */
94    udc_hotplug_event_t cur_uh_event;
95
96#if defined (HAVE_DETECT_SYNC)
97    /* Sync seq */
98    unsigned long irq_sync_seq;
99    unsigned long our_sync_seq;
100#endif
101
102    /* Keep alive */
103    struct timer_list keep_alive_timer;
104
105    unsigned long keep_alive_counter_limit;
106    unsigned long keep_alive_timer_interval;
107    unsigned long keep_alive_counter;
108};
109
110static struct uh_data *g_puh_data = NULL;
111
112#if defined (HAVE_DETECT_SYNC)
113/* Seq sync function */
114
115static inline int is_seq_sync(struct uh_data *uh)
116{
117    return (uh->our_sync_seq == uh->irq_sync_seq);
118}
119
120static inline void reset_seq(struct uh_data *uh)
121{
122    uh->our_sync_seq = uh->irq_sync_seq = 0;
123
124    return;
125}
126
127static inline void sync_seq(struct uh_data *uh)
128{
129    uh->our_sync_seq = uh->irq_sync_seq;
130
131    return;
132}
133#endif
134
135/* Call kernel thread to detect. */
136static inline void start_detect(struct uh_data *uh)
137{
138    D("called.\n");
139
140#if defined (HAVE_DETECT_SYNC)
141    uh->irq_sync_seq ++;
142#endif
143
144    wake_up_process(uh->kthread);
145
146    return;
147}
148
149static void wait_gpio_pin_stable(struct uh_data *uh)
150{
151    unsigned long pin = 0;
152    int i = 1;
153
154    pin = __gpio_get_pin(UDC_HOTPLUG_PIN);
155
156    while (i < NR_GPIO_STABLE_TIMES) {
157        if (__gpio_get_pin(UDC_HOTPLUG_PIN) != pin) {
158            pin = __gpio_get_pin(UDC_HOTPLUG_PIN);
159            i = 1;
160        }else
161            i++;
162
163        sleep_on_timeout(&uh->wq, 1);
164    }
165
166    return;
167}
168
169/* Do cable detection */
170static void cable_detect(struct uh_data *uh)
171{
172    D("Wait pin stable.\n");
173
174    /* Wait GPIO pin stable first. */
175    wait_gpio_pin_stable(uh);
176
177    if (__gpio_get_pin(UDC_HOTPLUG_PIN)) {
178        D("Cable online.\n");
179
180        if (!test_and_set_bit(BIT_CABLE_ONLINE, &uh->state)) {
181            D("Cable state change to online.\n");
182
183            set_bit(BIT_CABLE_CHANGE, &uh->state);
184        }
185    }else {
186        D("Cable offline.\n");
187
188        /* Clear keep alive bit. */
189        clear_bit(BIT_KEEP_ALIVE, &uh->state);
190
191        if (test_and_clear_bit(BIT_CABLE_ONLINE, &uh->state)) {
192            D("Cable state change to offline.\n");
193
194            set_bit(BIT_CABLE_CHANGE, &uh->state);
195        }
196    }
197
198    set_bit(BIT_CABLE_DETECT_DONE, &uh->state);
199
200    return;
201}
202
203/* Really do USB detection */
204static int do_usb_detect(struct uh_data *uh)
205{
206    u32 intr_usb;
207    int rv;
208
209    D("called.\n");
210
211    __intc_mask_irq(IRQ_UDC);
212
213    /* Now enable PHY to start detect */
214#ifdef CONFIG_SOC_JZ4740
215    REG_CPM_SCR |= CPM_SCR_USBPHY_ENABLE;
216#elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
217    REG_CPM_OPCR |= CPM_OPCR_UDCPHY_ENABLE;
218#endif
219    /* Clear IRQs */
220    REG16(USB_REG_INTRINE) = 0;
221    REG16(USB_REG_INTROUTE) = 0;
222    REG8(USB_REG_INTRUSBE) = 0;
223
224    /* disable UDC IRQs first */
225    REG16(USB_REG_INTRINE) = 0;
226    REG16(USB_REG_INTROUTE) = 0;
227    REG8(USB_REG_INTRUSBE) = 0;
228
229    /* Disable DMA */
230    REG32(USB_REG_CNTL1) = 0;
231    REG32(USB_REG_CNTL2) = 0;
232
233    /* Enable HS Mode */
234    REG8(USB_REG_POWER) |= USB_POWER_HSENAB;
235    /* Enable soft connect */
236    REG8(USB_REG_POWER) |= USB_POWER_SOFTCONN;
237
238    D("enable phy! %x %x %x %x %x\n",
239           REG8(USB_REG_POWER),
240           REG_CPM_OPCR,
241           REG16(USB_REG_INTRINE),
242           REG16(USB_REG_INTROUTE),
243           REG8(USB_REG_INTRUSBE));
244
245    /* Wait a moment. */
246    sleep_on_timeout(&uh->wq, NR_JIFFIES_USB_DETECT_WAIT);
247
248    intr_usb = REG8(USB_REG_INTRUSB);
249    if ((intr_usb & USB_INTR_RESET) ||
250        (intr_usb & USB_INTR_RESUME) ||
251        (intr_usb & USB_INTR_SUSPEND))
252    {
253        rv = 1;
254    }
255    else
256    {
257        rv = 0;
258    }
259
260    /* Detect finish ,clean every thing */
261    /* Disconnect from usb */
262    REG8(USB_REG_POWER) &= ~USB_POWER_SOFTCONN;
263    /* Disable the USB PHY */
264#ifdef CONFIG_SOC_JZ4740
265    REG_CPM_SCR &= ~CPM_SCR_USBPHY_ENABLE;
266#elif defined(CONFIG_SOC_JZ4750) || defined(CONFIG_SOC_JZ4750D)
267    REG_CPM_OPCR &= ~CPM_OPCR_UDCPHY_ENABLE;
268#endif
269    /* Clear IRQs */
270    REG16(USB_REG_INTRINE) = 0;
271    REG16(USB_REG_INTROUTE) = 0;
272    REG8(USB_REG_INTRUSBE) = 0;
273    __intc_ack_irq(IRQ_UDC);
274    __intc_unmask_irq(IRQ_UDC);
275
276    mdelay(1);
277
278    return rv;
279}
280
281/* Do USB bus protocol detection */
282static void usb_detect(struct uh_data *uh)
283{
284    int rv = 0;
285
286    D("Called.\n");
287
288    /* If the cable has already been offline, we just pass the real USB detection. */
289    if (test_bit(BIT_CABLE_ONLINE, &uh->state)) {
290
291        D("Do real detection.\n");
292
293        rv = do_usb_detect(uh);
294        set_bit(BIT_UDC_PHY_TOUCHED, &uh->state);
295    }else{
296        clear_bit(BIT_UDC_PHY_TOUCHED, &uh->state);
297        D("No need to do real detection.\n");
298    }
299
300    if (rv) {
301        if (!test_and_set_bit(BIT_USB_ONLINE, &uh->state))
302            set_bit(BIT_USB_CHANGE, &uh->state);
303    }else{
304        /* Clear keep alive bit. */
305        clear_bit(BIT_KEEP_ALIVE, &uh->state);
306
307        if (test_and_clear_bit(BIT_USB_ONLINE, &uh->state))
308            set_bit(BIT_USB_CHANGE, &uh->state);
309    }
310
311    set_bit(BIT_USB_DETECT_DONE, &uh->state);
312    return;
313}
314
315/* USB is active ? */
316static int usb_is_active(void)
317{
318    unsigned long tmp;
319
320    tmp = REG16(USB_REG_FRAME);
321
322    mdelay(2); /* USB 1.1 Frame length is 1ms, USB 2.0 HS Frame length is 125us */
323
324    rmb();
325
326    return tmp == REG16(USB_REG_FRAME) ? 0 : 1;
327}
328
329/* Broadcast event to notifier */
330static void do_broadcast_event(struct uh_data *uh)
331{
332    udc_hotplug_event_t *e = &uh->cur_uh_event;
333
334    /* Collect Information */
335    if (test_and_clear_bit(BIT_CABLE_CHANGE, &uh->state)) {
336        e->type = EVENT_TYPE_CABLE;
337        e->state = (test_bit(BIT_CABLE_ONLINE, &uh->state)) ? EVENT_STATE_ONLINE: EVENT_STATE_OFFLINE;
338        e->flags = 0;
339
340        D("Broadcast cable event -> State: %s.\n", (e->state == EVENT_STATE_ONLINE ? "Online" : "Offline"));
341
342        /* Kick chain. */
343        blocking_notifier_call_chain(&uh->notifier_head, BROADCAST_TYPE_EVENT, e);
344    }
345
346    if (test_and_clear_bit(BIT_USB_CHANGE, &uh->state)) {
347        e->type = EVENT_TYPE_USB;
348        e->state = (test_bit(BIT_USB_ONLINE, &uh->state)) ? EVENT_STATE_ONLINE : EVENT_STATE_OFFLINE;
349        e->flags = 0;
350
351        if (test_bit(BIT_UDC_PHY_TOUCHED, &uh->state)) {
352            set_bit(EVENT_FLAG_UDC_PHY_TOUCHED, &e->flags);
353        }
354
355        D("Broadcast USB event -> State: %s.\n", (e->state == EVENT_STATE_ONLINE ? "Online" : "Offline"));
356
357               /* Kick chain. */
358        blocking_notifier_call_chain(&uh->notifier_head, BROADCAST_TYPE_EVENT, e);
359    }
360
361    return;
362}
363
364/* Handle pending request */
365static inline void handle_request(struct uh_data *uh)
366{
367    if (test_and_clear_bit(BIT_REQUEST_CABLE_DETECT, &uh->state))
368        set_bit(BIT_DO_CABLE_DETECT, &uh->state);
369
370    if (test_and_clear_bit(BIT_REQUEST_USB_DETECT, &uh->state))
371        set_bit(BIT_DO_USB_DETECT, &uh->state);
372
373    return;
374}
375
376/* Have pending request ? */
377static inline int pending_request(struct uh_data *uh)
378{
379    if (test_bit(BIT_REQUEST_CABLE_DETECT, &uh->state) || test_bit(BIT_REQUEST_USB_DETECT, &uh->state))
380        return 1;
381    else
382        return 0;
383}
384
385#if defined (HAVE_DETECT_SYNC)
386static void prepare_restart(struct uh_data *uh, wait_queue_head_t *wq)
387{
388
389    D("Called.\n");
390
391    if (test_bit(BIT_CABLE_DETECT_DONE, &uh->state))
392        set_bit(BIT_DO_CABLE_DETECT, &uh->state);
393
394    if (test_bit(BIT_USB_DETECT_DONE, &uh->state))
395        set_bit(BIT_DO_USB_DETECT, &uh->state);
396
397    sleep_on_timeout(wq, NR_JIFFIES_SLEEP_BEFORE_RESTART);
398
399    sync_seq(uh);
400
401    return;
402}
403
404/* Called from kernel thread */
405static void udc_pnp_detect(struct uh_data *uh)
406{
407    int nr_restart = 0;
408
409    D("Do UDC detection.\n");
410
411    while (nr_restart != NR_RESTART_TIMES) {
412        /* Do cable detection ? */
413        if (test_bit(BIT_DO_CABLE_DETECT, &uh->state)) {
414            D("Do cable detection.\n");
415
416            cable_detect(uh);
417        }
418
419        /* Need restart ? */
420        if (!is_seq_sync(uh)) {
421            nr_restart ++;
422
423            prepare_restart(uh, &uh->wq);
424            continue;
425        }
426
427        /* Do USB detection ? */
428        if (test_bit(BIT_DO_USB_DETECT, &uh->state)) {
429            D("Do USB detection.\n");
430
431            usb_detect(uh);
432        }
433
434        /* Need restart ? */
435        if (!is_seq_sync(uh)) {
436            nr_restart ++;
437
438            prepare_restart(uh, &uh->wq);
439            continue;
440        }
441
442        /* Done */
443        D("Done.\n");
444
445        clear_bit(BIT_DO_CABLE_DETECT, &uh->state);
446        clear_bit(BIT_DO_USB_DETECT, &uh->state);
447
448        break;
449    }
450
451    return;
452}
453
454static inline void broadcast_event(struct uh_data *uh)
455{
456        /* Sync ? */
457        if (is_seq_sync(uh)) {
458        D("Sync -> Broadcast event.\n");
459
460        do_broadcast_event(uh);
461    }else{
462        D("Not sync -> Prepare restarting.\n");
463
464        prepare_restart(uh, &uh->kthread_wq);
465    }
466}
467
468static inline void udc_pnp_thread_sleep(struct uh_data *uh)
469{
470    /* Sync ? -> Sleep. */
471    if ( !pending_request(uh) || is_seq_sync(uh)) {
472        D("Sleep.\n");
473
474        sleep_on(&uh->kthread_wq);
475    }
476
477    return;
478}
479
480#else /* !HAVE_DETECT_SYNC */
481
482/* Called from kernel thread */
483static void udc_pnp_detect(struct uh_data *uh)
484{
485    D("Do UDC detection.\n");
486
487    /* Do cable detection ? */
488    if (test_bit(BIT_DO_CABLE_DETECT, &uh->state)) {
489        D("Do cable detection.\n");
490
491        cable_detect(uh);
492    }
493
494    /* Do USB detection ? */
495    if (test_bit(BIT_DO_USB_DETECT, &uh->state)) {
496        D("Do USB detection.\n");
497
498        usb_detect(uh);
499    }
500
501    /* Done */
502    D("Done.\n");
503
504    clear_bit(BIT_DO_CABLE_DETECT, &uh->state);
505    clear_bit(BIT_DO_USB_DETECT, &uh->state);
506
507    return;
508}
509
510static inline void broadcast_event(struct uh_data *uh)
511{
512    D("Broadcast event.\n");
513
514    do_broadcast_event(uh);
515
516    return;
517}
518
519static inline void udc_pnp_thread_sleep(struct uh_data *uh)
520{
521    if (!pending_request(uh)) {
522        D("Sleep.\n");
523
524        sleep_on(&uh->kthread_wq);
525    }
526
527    return;
528}
529#endif /* HAVE_DETECT_SYNC */
530
531/* Kernel thread */
532static int udc_pnp_thread(void *data)
533{
534    struct uh_data *uh = (struct uh_data *)data;
535
536    while (!kthread_should_stop()) {
537        /* Sleep. */
538        udc_pnp_thread_sleep(uh);
539
540        D("Running.\n");
541
542        if (kthread_should_stop())
543            break;
544
545#if defined (HAVE_DETECT_SYNC)
546        /* Sync */
547        sync_seq(uh);
548#endif
549
550        D("Will do UDC detection.\n");
551
552        handle_request(uh);
553
554        /* Do detect */
555        udc_pnp_detect(uh);
556
557        D("Done.\n");
558
559        /* Broadcast event. */
560        broadcast_event(uh);
561    }
562
563    D("Exit.\n");
564
565    return 0;
566}
567
568static irqreturn_t udc_pnp_irq(int irq, void *dev_id)
569{
570    struct uh_data *uh = (struct uh_data *)dev_id;
571
572    D("called.\n");
573
574        /* clear interrupt pending status */
575        __gpio_ack_irq(UDC_HOTPLUG_PIN);
576
577        set_bit(BIT_REQUEST_CABLE_DETECT, &uh->state);
578    set_bit(BIT_REQUEST_USB_DETECT, &uh->state);
579
580    start_detect(uh);
581
582    return IRQ_HANDLED;
583}
584
585static void __init init_gpio(struct uh_data *uh)
586{
587        /* get current pin level */
588    __gpio_disable_pull(UDC_HOTPLUG_PIN);
589        __gpio_as_input(UDC_HOTPLUG_PIN);
590    udelay(1);
591
592    cable_detect(uh);
593
594    /* Because of every plug IN/OUT action will casue more than one interrupt,
595       So whether rising trigger or falling trigger method can both start the detection.
596         */
597
598    __gpio_as_irq_rise_edge(UDC_HOTPLUG_PIN);
599
600        if (test_bit(BIT_CABLE_ONLINE, &uh->state)) {
601        D("Cable Online -> Do start detection.\n");
602
603        set_bit(BIT_REQUEST_CABLE_DETECT, &uh->state);
604        set_bit(BIT_REQUEST_USB_DETECT, &uh->state);
605
606        start_detect(uh);
607        }else{
608        D("Cable Offline.\n");
609        }
610
611    return;
612}
613
614/* ---------------------------------------------------------------------------------- */
615/* Export routines */
616static void udc_hotplug_keep_alive_timer_func(unsigned long data)
617{
618    struct uh_data *uh = (struct uh_data *)data;
619
620    D("Timer running.\n");
621
622    /* Decrease the counter. */
623    if (test_bit(BIT_KEEP_ALIVE, &uh->state) && !(--uh->keep_alive_counter)) {
624
625        if (!usb_is_active()) {
626            D("Timeout.\n");
627
628            set_bit(BIT_KEEP_ALIVE_TIMEOUT, &uh->state);
629
630            clear_bit(BIT_USB_ONLINE, &uh->state);
631            set_bit(BIT_USB_CHANGE, &uh->state);
632
633            /* No detection needed. We just want to broadcast our event. */
634            start_detect(uh);
635        }
636    }
637
638    /* Set next active time. */
639    if (test_bit(BIT_KEEP_ALIVE, &uh->state) && !test_bit(BIT_KEEP_ALIVE_TIMEOUT, &uh->state))
640        mod_timer(&uh->keep_alive_timer, uh->keep_alive_timer_interval + jiffies);
641    else
642        D("Timer will stop.\n");
643
644    return;
645}
646
647int udc_hotplug_register_notifier(struct notifier_block *n, int request_state)
648{
649    struct uh_data *uh = g_puh_data;
650
651    udc_hotplug_event_t e;
652
653    D("Register notifier: 0x%p.\n", (void *)n);
654
655    /* Notifer will be registered is requesting current state. */
656    if (request_state) {
657
658        BUG_ON(!n->notifier_call);
659
660        /* Cable State */
661        e.type = EVENT_TYPE_CABLE;
662        e.state = (test_bit(BIT_CABLE_ONLINE, &uh->state)) ? EVENT_STATE_ONLINE: EVENT_STATE_OFFLINE;
663
664        n->notifier_call(n, BROADCAST_TYPE_STATE, &e);
665
666        /* USB State */
667        e.type = EVENT_TYPE_USB;
668        e.state = (test_bit(BIT_CABLE_ONLINE, &uh->state)) ? EVENT_STATE_ONLINE: EVENT_STATE_OFFLINE;
669
670        n->notifier_call(n, BROADCAST_TYPE_STATE, &e);
671    }
672
673    return blocking_notifier_chain_register(&uh->notifier_head, n);
674
675}EXPORT_SYMBOL(udc_hotplug_register_notifier);
676
677int udc_hotplug_unregister_notifier(struct notifier_block *n)
678{
679    struct uh_data *uh = g_puh_data;
680
681    D("Unregister notifier: 0x%p.\n", (void *)n);
682
683    return blocking_notifier_chain_unregister(&uh->notifier_head, n);
684
685}EXPORT_SYMBOL(udc_hotplug_unregister_notifier);
686
687/* Start keep alive, 0 - Use default value */
688int udc_hotplug_start_keep_alive(unsigned long timer_interval_in_jiffies, unsigned long counter_limit)
689{
690    struct uh_data *uh = g_puh_data;
691
692    /* Already started. */
693    if (test_and_set_bit(BIT_KEEP_ALIVE, &uh->state))
694        return 0;
695
696    if (timer_interval_in_jiffies)
697        uh->keep_alive_timer_interval = timer_interval_in_jiffies;
698    else
699        uh->keep_alive_timer_interval = DEFAULT_KEEP_ALIVE_TIMER_INTERVAL;
700
701    if (counter_limit)
702        uh->keep_alive_counter_limit = counter_limit;
703    else
704        uh->keep_alive_counter_limit = DEFAULT_KEEP_ALIVE_COUNTER_LIMIT;
705
706    uh->keep_alive_counter = uh->keep_alive_counter_limit;
707
708    /* Active our timer. */
709    return mod_timer(&uh->keep_alive_timer, 3 + jiffies);
710
711}EXPORT_SYMBOL(udc_hotplug_start_keep_alive);
712
713void udc_hotplug_do_keep_alive(void)
714{
715    struct uh_data *uh = g_puh_data;
716
717    D("Keep alive.\n");
718
719        /* Reset counter */
720    uh->keep_alive_counter = uh->keep_alive_counter_limit;
721
722    /* We are alive again. */
723    if (test_and_clear_bit(BIT_KEEP_ALIVE_TIMEOUT, &uh->state)) {
724        D("Reactive timer.\n");
725
726        /* Active timer. */
727        set_bit(BIT_KEEP_ALIVE, &uh->state);
728        mod_timer(&uh->keep_alive_timer, 3 + jiffies);
729    }
730
731    return;
732}EXPORT_SYMBOL(udc_hotplug_do_keep_alive);
733
734void udc_hotplug_stop_keep_alive(void)
735{
736    struct uh_data *uh = g_puh_data;
737
738    clear_bit(BIT_KEEP_ALIVE, &uh->state);
739
740    return;
741
742}EXPORT_SYMBOL(udc_hotplug_stop_keep_alive);
743
744/* ----------------------------------------------------------------------------- */
745
746/*
747 * Module init and exit
748 */
749static int __init udc_hotplug_init(void)
750{
751    struct uh_data *uh;
752
753    unsigned long status = 0;
754
755        int rv;
756
757    g_puh_data = (struct uh_data *)kzalloc(sizeof(struct uh_data), GFP_KERNEL);
758    if (!g_puh_data) {
759        printk(KERN_ERR PFX": Failed to allocate memory.\n");
760        return -ENOMEM;
761    }
762
763    uh = g_puh_data;
764
765    set_bit(1, &status);
766
767    BLOCKING_INIT_NOTIFIER_HEAD(&uh->notifier_head);
768
769    init_waitqueue_head(&uh->kthread_wq);
770    init_waitqueue_head(&uh->wq);
771
772    init_timer(&uh->keep_alive_timer);
773
774    uh->keep_alive_timer.function = udc_hotplug_keep_alive_timer_func;
775    uh->keep_alive_timer.expires = jiffies - 1; /* Add a stopped timer */
776    uh->keep_alive_timer.data = (unsigned long)uh;
777
778    add_timer(&uh->keep_alive_timer);
779
780#if defined (HAVE_DETECT_SYNC)
781    reset_seq(uh);
782#endif
783
784    /* Create pnp thread and register IRQ */
785    uh->kthread = kthread_run(udc_pnp_thread, uh, "kudcd");
786    if (IS_ERR(uh->kthread)) {
787        printk(KERN_ERR PFX": Failed to create system monitor thread.\n");
788        rv = PTR_ERR(uh->kthread);
789        goto err;
790    }
791
792    set_bit(2, &status);
793
794        rv = request_irq(UDC_HOTPLUG_IRQ, udc_pnp_irq, IRQF_DISABLED, "udc_pnp", uh);
795        if (rv) {
796                printk(KERN_ERR PFX": Could not get udc hotplug irq %d\n", UDC_HOTPLUG_IRQ);
797        goto err;
798        }
799
800    init_gpio(uh);
801
802#if defined (HAVE_DETECT_SYNC)
803    printk(KERN_ERR PFX": Registered(HAVE_DETECT_SYNC).\n");
804#else
805    printk(KERN_ERR PFX": Registered.\n");
806#endif
807    return 0;
808
809err:
810    if (test_bit(2, &status)) {
811        kthread_stop(uh->kthread);
812    }
813
814    if (test_bit(1, &status)) {
815        kfree(g_puh_data);
816    }
817
818    return rv;
819}
820
821static void __exit udc_hotplug_exit(void)
822{
823    free_irq(UDC_HOTPLUG_IRQ, g_puh_data);
824
825    kthread_stop(g_puh_data->kthread);
826
827    kfree(g_puh_data);
828
829    return;
830}
831
832module_init(udc_hotplug_init);
833module_exit(udc_hotplug_exit);
834
835MODULE_AUTHOR("River Wang <zwang@ingenic.cn>");
836MODULE_LICENSE("GPL");
drivers/video/backlight/gpm940b0.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC LCD framebuffer driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/module.h>
17#include <linux/spi/spi.h>
18#include <linux/lcd.h>
19#include <linux/backlight.h>
20#include <linux/delay.h>
21
22struct gpm940b0 {
23    struct spi_device *spi;
24    struct lcd_device *lcd;
25    struct backlight_device *bl;
26    unsigned enabled:1;
27};
28
29static int gpm940b0_write_reg(struct spi_device *spi, uint8_t reg,
30                uint8_t data)
31{
32    uint8_t buf[2];
33    buf[0] = ((reg & 0x40) << 1) | (reg & 0x3f);
34    buf[1] = data;
35
36    return spi_write(spi, buf, sizeof(buf));
37}
38
39static void gpm940b0_power_disable(struct gpm940b0 *gpm940b0)
40{
41    int ret = gpm940b0_write_reg(gpm940b0->spi, 0x5, 0xc6) ;
42    if (ret < 0)
43        printk("Failed to disable power: %d\n", ret);
44}
45
46static void gpm940b0_power_enable(struct gpm940b0 *gpm940b0)
47{
48    gpm940b0_write_reg(gpm940b0->spi, 0x5, 0xc7);
49}
50
51
52static int gpm940b0_set_power(struct lcd_device *lcd, int power)
53{
54    struct gpm940b0 *gpm940b0 = lcd_get_data(lcd);
55
56    switch (power) {
57    case FB_BLANK_UNBLANK:
58        gpm940b0->enabled = 1;
59        gpm940b0_power_enable(gpm940b0);
60        break;
61    default:
62        gpm940b0->enabled = 0;
63        gpm940b0_power_disable(gpm940b0);
64        break;
65    }
66    return 0;
67}
68
69static int gpm940b0_set_contrast(struct lcd_device *lcd, int contrast)
70{
71    struct gpm940b0 *gpm940b0 = lcd_get_data(lcd);
72    gpm940b0_write_reg(gpm940b0->spi, 0x0d, contrast);
73    return 0;
74}
75
76static int gpm940b0_set_mode(struct lcd_device *lcd, struct fb_videomode *mode)
77{
78    if (mode->xres != 320 && mode->yres != 240)
79        return -EINVAL;
80
81    return 0;
82}
83
84/*
85int gpm940b0_bl_update_status(struct backlight_device *bl)
86{
87    struct gpm940b0 *gpm940b0 = bl_get_data(bl);
88
89    gpm940b0->reg5 &= ~0x38;
90    gpm940b0->reg5 |= ((bl->props.brightness << 3) & 0x38);
91
92    gpm940b0_write_reg(gpm940b0->spi, 0x5, gpm940b0->reg5);
93
94    return 0;
95}*/
96
97static ssize_t reg_write(struct device *dev, struct device_attribute *attr,
98                        const char *buf, size_t count)
99{
100    char *buf2;
101    uint32_t reg = simple_strtoul(buf, &buf2, 10);
102    uint32_t val = simple_strtoul(buf2 + 1, NULL, 10);
103    struct gpm940b0 *gpm940b0 = dev_get_drvdata(dev);
104
105    if (reg < 0 || val < 0)
106        return -EINVAL;
107
108    gpm940b0_write_reg(gpm940b0->spi, reg, val);
109    return count;
110}
111
112static DEVICE_ATTR(reg, 0644, NULL, reg_write);
113
114static struct lcd_ops gpm940b0_lcd_ops = {
115    .set_power = gpm940b0_set_power,
116    .set_contrast = gpm940b0_set_contrast,
117    .set_mode = gpm940b0_set_mode,
118};
119
120#if 0
121static struct backlight_ops gpm940b0_bl_ops = {
122/* .get_brightness = gpm940b0_bl_get_brightness,*/
123    .update_status = gpm940b0_bl_update_status,
124};
125#endif
126
127static int __devinit gpm940b0_probe(struct spi_device *spi)
128{
129    int ret;
130    struct gpm940b0 *gpm940b0;
131
132    gpm940b0 = kmalloc(sizeof(*gpm940b0), GFP_KERNEL);
133
134    spi->bits_per_word = 8;
135
136    ret = spi_setup(spi);
137    if (ret) {
138        dev_err(&spi->dev, "Failed to setup spi\n");
139        goto err_free_gpm940b0;
140    }
141
142    gpm940b0->spi = spi;
143
144    gpm940b0->lcd = lcd_device_register("gpm940b0-lcd", &spi->dev, gpm940b0,
145                        &gpm940b0_lcd_ops);
146
147    if (IS_ERR(gpm940b0->lcd)) {
148        ret = PTR_ERR(gpm940b0->lcd);
149        dev_err(&spi->dev, "Failed to register lcd device: %d\n", ret);
150        goto err_free_gpm940b0;
151    }
152
153    gpm940b0->lcd->props.max_contrast = 255;
154
155#if 0
156    gpm940b0->bl = backlight_device_register("gpm940b0-bl", &spi->dev, gpm940b0,
157                         &gpm940b0_bl_ops);
158
159    if (IS_ERR(gpm940b0->bl)) {
160        ret = PTR_ERR(gpm940b0->bl);
161        dev_err(&spi->dev, "Failed to register backlight device: %d\n", ret);
162        gpm940b0->bl = NULL;
163    } else {
164        gpm940b0->bl->props.max_brightness = 8;
165        gpm940b0->bl->props.brightness = 0;
166        gpm940b0->bl->props.power = FB_BLANK_UNBLANK;
167    }
168#endif
169
170    ret = device_create_file(&spi->dev, &dev_attr_reg);
171    if (ret)
172        goto err_unregister_lcd;
173
174    gpm940b0->enabled = 1;
175    dev_set_drvdata(&spi->dev, gpm940b0);
176
177    gpm940b0_write_reg(spi, 0x13, 0x01);
178    gpm940b0_write_reg(spi, 0x5, 0xc7);
179    return 0;
180err_unregister_lcd:
181    lcd_device_unregister(gpm940b0->lcd);
182err_free_gpm940b0:
183    kfree(gpm940b0);
184    return ret;
185}
186
187static int __devexit gpm940b0_remove(struct spi_device *spi)
188{
189    struct gpm940b0 *gpm940b0 = spi_get_drvdata(spi);
190#if 0
191    if (gpm940b0->bl)
192        backlight_device_unregister(gpm940b0->bl);
193#endif
194
195    lcd_device_unregister(gpm940b0->lcd);
196
197    spi_set_drvdata(spi, NULL);
198    kfree(gpm940b0);
199    return 0;
200}
201
202#ifdef CONFIG_PM
203
204static int gpm940b0_suspend(struct spi_device *spi, pm_message_t state)
205{
206    struct gpm940b0 *gpm940b0 = spi_get_drvdata(spi);
207    if (gpm940b0->enabled) {
208        gpm940b0_power_disable(gpm940b0);
209        mdelay(10);
210    }
211    return 0;
212}
213
214static int gpm940b0_resume(struct spi_device *spi)
215{
216    struct gpm940b0 *gpm940b0 = spi_get_drvdata(spi);
217    if (gpm940b0->enabled)
218        gpm940b0_power_enable(gpm940b0);
219    return 0;
220}
221
222#else
223#define gpm940b0_suspend NULL
224#define gpm940b0_resume NULL
225#endif
226
227static struct spi_driver gpm940b0_driver = {
228    .driver = {
229        .name = "gpm940b0",
230        .owner = THIS_MODULE,
231    },
232    .probe = gpm940b0_probe,
233    .remove = __devexit_p(gpm940b0_remove),
234    .suspend = gpm940b0_suspend,
235    .resume = gpm940b0_resume,
236};
237
238static int __init gpm940b0_init(void)
239{
240    return spi_register_driver(&gpm940b0_driver);
241}
242module_init(gpm940b0_init);
243
244static void __exit gpm940b0_exit(void)
245{
246    return spi_unregister_driver(&gpm940b0_driver);
247}
248module_exit(gpm940b0_exit)
249
250MODULE_AUTHOR("Lars-Peter Clausen");
251MODULE_LICENSE("GPL v2");
252MODULE_DESCRIPTION("LCD and backlight controll for Giantplus GPM940B0");
253MODULE_ALIAS("spi:gpm940b0");
drivers/video/jz4740_fb.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC LCD framebuffer driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/types.h>
17#include <linux/platform_device.h>
18#include <linux/fb.h>
19#include <linux/module.h>
20#include <linux/dma-mapping.h>
21#include <linux/jz4740_fb.h>
22
23#include <linux/delay.h>
24
25#define JZ_REG_LCD_CFG 0x00
26#define JZ_REG_LCD_VSYNC 0x04
27#define JZ_REG_LCD_HSYNC 0x08
28#define JZ_REG_LCD_VAT 0x0C
29#define JZ_REG_LCD_DAH 0x10
30#define JZ_REG_LCD_DAV 0x14
31#define JZ_REG_LCD_PS 0x18
32#define JZ_REG_LCD_CLS 0x1C
33#define JZ_REG_LCD_SPL 0x20
34#define JZ_REG_LCD_REV 0x24
35#define JZ_REG_LCD_CTRL 0x30
36#define JZ_REG_LCD_STATE 0x34
37#define JZ_REG_LCD_IID 0x38
38#define JZ_REG_LCD_DA0 0x40
39#define JZ_REG_LCD_SA0 0x44
40#define JZ_REG_LCD_FID0 0x48
41#define JZ_REG_LCD_CMD0 0x4C
42#define JZ_REG_LCD_DA1 0x50
43#define JZ_REG_LCD_SA1 0x54
44#define JZ_REG_LCD_FID1 0x58
45#define JZ_REG_LCD_CMD1 0x5C
46
47#define JZ_LCD_CFG_SLCD BIT(31)
48#define JZ_LCD_CFG_PSM BIT(23)
49#define JZ_LCD_CFG_CLSM BIT(22)
50#define JZ_LCD_CFG_SPLM BIT(21)
51#define JZ_LCD_CFG_REVM BIT(20)
52#define JZ_LCD_CFG_HSYNCM BIT(19)
53#define JZ_LCD_CFG_PCLKM BIT(18)
54#define JZ_LCD_CFG_INV BIT(17)
55#define JZ_LCD_CFG_SYNC_DIR BIT(16)
56#define JZ_LCD_CFG_PSP BIT(15)
57#define JZ_LCD_CFG_CLSP BIT(14)
58#define JZ_LCD_CFG_SPLP BIT(13)
59#define JZ_LCD_CFG_REVP BIT(12)
60#define JZ_LCD_CFG_HSYNCP BIT(11)
61#define JZ_LCD_CFG_PCLKP BIT(10)
62#define JZ_LCD_CFG_DEP BIT(9)
63#define JZ_LCD_CFG_VSYNCP BIT(8)
64#define JZ_LCD_CFG_18_BIT BIT(7)
65#define JZ_LCD_CFG_PDW BIT(5) | BIT(4)
66#define JZ_LCD_CFG_MODE_MASK 0xf
67
68#define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
69#define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
70#define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
71#define JZ_LCD_CTRL_RGB555 BIT(27)
72#define JZ_LCD_CTRL_OFUP BIT(26)
73#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
74#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
75#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
76#define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
77#define JZ_LCD_CTRL_EOF_IRQ BIT(13)
78#define JZ_LCD_CTRL_SOF_IRQ BIT(12)
79#define JZ_LCD_CTRL_OFU_IRQ BIT(11)
80#define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
81#define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
82#define JZ_LCD_CTRL_DD_IRQ BIT(8)
83#define JZ_LCD_CTRL_QDD_IRQ BIT(7)
84#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
85#define JZ_LCD_CTRL_LSB_FISRT BIT(5)
86#define JZ_LCD_CTRL_DISABLE BIT(4)
87#define JZ_LCD_CTRL_ENABLE BIT(3)
88#define JZ_LCD_CTRL_BPP_1 0x0
89#define JZ_LCD_CTRL_BPP_2 0x1
90#define JZ_LCD_CTRL_BPP_4 0x2
91#define JZ_LCD_CTRL_BPP_8 0x3
92#define JZ_LCD_CTRL_BPP_15_16 0x4
93#define JZ_LCD_CTRL_BPP_18_24 0x5
94
95#define JZ_LCD_CMD_SOF_IRQ BIT(15)
96#define JZ_LCD_CMD_EOF_IRQ BIT(16)
97#define JZ_LCD_CMD_ENABLE_PAL BIT(12)
98
99#define JZ_LCD_SYNC_MASK 0x3ff
100
101struct jzfb_framedesc {
102    uint32_t next;
103    uint32_t addr;
104    uint32_t id;
105    uint32_t cmd;
106} __attribute__((packed));
107
108struct jzfb {
109    struct fb_info *fb;
110    struct platform_device *pdev;
111    void __iomem *base;
112    struct resource *mem;
113    struct jz4740_fb_platform_data *pdata;
114
115    void *devmem;
116    size_t devmem_size;
117    dma_addr_t devmem_phys;
118    void *vidmem;
119    size_t vidmem_size;
120    dma_addr_t vidmem_phys;
121    struct jzfb_framedesc *framedesc;
122
123    uint32_t pseudo_palette[16];
124};
125
126static struct fb_fix_screeninfo jzfb_fix __devinitdata = {
127    .id = "JZ4740 FB",
128    .type = FB_TYPE_PACKED_PIXELS,
129    .visual = FB_VISUAL_TRUECOLOR,
130    .xpanstep = 0,
131    .ypanstep = 0,
132    .ywrapstep = 0,
133    .accel = FB_ACCEL_NONE,
134};
135
136int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
137            unsigned transp, struct fb_info *fb)
138{
139    ((uint32_t*)fb->pseudo_palette)[regno] = red << 16 | green << 8 | blue;
140    return 0;
141}
142
143static int jzfb_get_controller_bpp(struct jzfb *jzfb)
144{
145    switch(jzfb->pdata->bpp) {
146        case 18:
147        case 24:
148            return 32;
149            break;
150        default:
151            return jzfb->pdata->bpp;
152    }
153}
154
155static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb)
156{
157    struct jzfb* jzfb = fb->par;
158    struct fb_videomode *mode = jzfb->pdata->modes;
159    int i;
160
161    if (fb->var.bits_per_pixel != jzfb_get_controller_bpp(jzfb) &&
162        fb->var.bits_per_pixel != jzfb->pdata->bpp)
163        return -EINVAL;
164
165    for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) {
166        if (mode->xres == fb->var.xres && mode->yres == fb->var.yres)
167            break;
168    }
169
170    if (i == jzfb->pdata->num_modes)
171        return -EINVAL;
172
173    fb_videomode_to_var(&fb->var, fb->mode);
174
175    switch (jzfb->pdata->bpp) {
176    case 8:
177        break;
178    case 15:
179        var->red.offset = 10;
180        var->red.length = 5;
181        var->green.offset = 6;
182        var->green.length = 5;
183        var->blue.offset = 0;
184        var->blue.length = 5;
185        break;
186    case 16:
187        var->red.offset = 11;
188        var->red.length = 5;
189        var->green.offset = 6;
190        var->green.length = 6;
191        var->blue.offset = 0;
192        var->blue.length = 5;
193        break;
194    case 18:
195        var->red.offset = 16;
196        var->red.length = 6;
197        var->green.offset = 8;
198        var->green.length = 6;
199        var->blue.offset = 0;
200        var->blue.length = 6;
201        fb->var.bits_per_pixel = 32;
202        break;
203    case 32:
204    case 24:
205        var->transp.offset = 24;
206        var->transp.length = 8;
207        var->red.offset = 16;
208        var->red.length = 8;
209        var->green.offset = 8;
210        var->green.length = 8;
211        var->blue.offset = 0;
212        var->blue.length = 8;
213        fb->var.bits_per_pixel = 32;
214        break;
215    default:
216        break;
217    }
218
219    return 0;
220}
221
222static int jzfb_set_par(struct fb_info *info)
223{
224    struct jzfb* jzfb = info->par;
225    struct fb_var_screeninfo *var = &info->var;
226    uint16_t hds, vds;
227    uint16_t hde, vde;
228    uint16_t ht, vt;
229    uint32_t ctrl;
230
231    hds = var->hsync_len + var->left_margin;
232    hde = hds + var->xres;
233    ht = hde + var->right_margin;
234
235    vds = var->vsync_len + var->upper_margin;
236    vde = vds + var->yres;
237    vt = vde + var->lower_margin;
238
239    writel(var->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC);
240    writel(var->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC);
241
242    writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT);
243
244    writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH);
245    writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV);
246
247    ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
248    ctrl |= JZ_LCD_CTRL_ENABLE;
249
250    switch (jzfb->pdata->bpp) {
251    case 1:
252        ctrl |= JZ_LCD_CTRL_BPP_1;
253        break;
254    case 2:
255        ctrl |= JZ_LCD_CTRL_BPP_2;
256        break;
257    case 4:
258        ctrl |= JZ_LCD_CTRL_BPP_4;
259        break;
260    case 8:
261        ctrl |= JZ_LCD_CTRL_BPP_8;
262    break;
263    case 15:
264        ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */
265    case 16:
266        ctrl |= JZ_LCD_CTRL_BPP_15_16;
267        break;
268    case 18:
269    case 24:
270    case 32:
271        ctrl |= JZ_LCD_CTRL_BPP_18_24;
272        break;
273    default:
274        break;
275    }
276    writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
277
278    return 0;
279}
280
281
282static int jzfb_alloc_vidmem(struct jzfb *jzfb)
283{
284    size_t devmem_size;
285    int max_videosize = 0;
286    struct fb_videomode *mode = jzfb->pdata->modes;
287    struct jzfb_framedesc *framedesc;
288    void *page;
289    int i;
290
291    for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) {
292        if (max_videosize < mode->xres * mode->yres)
293            max_videosize = mode->xres * mode->yres;
294    }
295
296    max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3;
297
298    devmem_size = max_videosize + sizeof(struct jzfb_framedesc);
299
300    jzfb->devmem_size = devmem_size;
301    jzfb->devmem = dma_alloc_coherent(&jzfb->pdev->dev,
302                        PAGE_ALIGN(devmem_size),
303                        &jzfb->devmem_phys, GFP_KERNEL);
304
305    if (!jzfb->devmem) {
306        return -ENOMEM;
307    }
308
309    for (page = jzfb->vidmem;
310         page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size);
311         page += PAGE_SIZE) {
312        SetPageReserved(virt_to_page(page));
313    }
314
315
316    framedesc = jzfb->devmem + max_videosize;
317    jzfb->vidmem = jzfb->devmem;
318    jzfb->vidmem_phys = jzfb->devmem_phys;
319
320    framedesc->next = jzfb->devmem_phys + max_videosize;
321    framedesc->addr = jzfb->devmem_phys;
322    framedesc->id = 0;
323    framedesc->cmd = 0;
324    framedesc->cmd |= max_videosize / 4;
325
326    jzfb->framedesc = framedesc;
327
328
329    return 0;
330}
331
332static void jzfb_free_devmem(struct jzfb *jzfb)
333{
334    dma_free_coherent(&jzfb->pdev->dev, jzfb->devmem_size, jzfb->devmem,
335              jzfb->devmem_phys);
336}
337
338static struct fb_ops jzfb_ops = {
339    .owner = THIS_MODULE,
340    .fb_check_var = jzfb_check_var,
341    .fb_set_par = jzfb_set_par,
342/* .fb_blank = jzfb_blank,*/
343    .fb_fillrect = sys_fillrect,
344    .fb_copyarea = sys_copyarea,
345    .fb_imageblit = sys_imageblit,
346    .fb_setcolreg = jzfb_setcolreg,
347};
348
349static int __devinit jzfb_probe(struct platform_device *pdev)
350{
351    int ret;
352    struct jzfb *jzfb;
353    struct fb_info *fb;
354    struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data;
355    struct resource *mem;
356
357    if (!pdata) {
358        dev_err(&pdev->dev, "Missing platform data\n");
359        return -ENOENT;
360    }
361
362    mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
363
364    if (!mem) {
365        dev_err(&pdev->dev, "Failed to get register memory resource\n");
366        return -ENOENT;
367    }
368
369    mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
370
371    if (!mem) {
372        dev_err(&pdev->dev, "Failed to request register memory region\n");
373        return -EBUSY;
374    }
375
376
377    fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev);
378
379    if (!fb) {
380        dev_err(&pdev->dev, "Failed to allocate framebuffer device\n");
381        ret = -ENOMEM;
382        goto err_release_mem_region;
383    }
384
385    fb->fbops = &jzfb_ops;
386    fb->flags = FBINFO_DEFAULT;
387
388    jzfb = fb->par;
389    jzfb->pdev = pdev;
390    jzfb->pdata = pdata;
391    jzfb->mem = mem;
392
393    jzfb->base = ioremap(mem->start, resource_size(mem));
394
395    if (!jzfb->base) {
396        dev_err(&pdev->dev, "Failed to ioremap register memory region\n");
397        ret = -EBUSY;
398        goto err_framebuffer_release;
399    }
400
401    platform_set_drvdata(pdev, jzfb);
402
403    fb_videomode_to_modelist(pdata->modes, pdata->num_modes,
404                 &fb->modelist);
405    fb->mode = pdata->modes;
406
407    fb_videomode_to_var(&fb->var, fb->mode);
408    fb->var.bits_per_pixel = pdata->bpp;
409    jzfb_check_var(&fb->var, fb);
410
411    ret = jzfb_alloc_vidmem(jzfb);
412    if (ret) {
413        dev_err(&pdev->dev, "Failed to allocate video memory\n");
414        goto err_iounmap;
415    }
416
417    fb->fix = jzfb_fix;
418    fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8;
419    fb->fix.mmio_start = mem->start;
420    fb->fix.mmio_len = resource_size(mem);
421    fb->fix.smem_start = jzfb->vidmem_phys;
422    fb->fix.smem_len = fb->fix.line_length * fb->var.yres;
423    fb->screen_base = jzfb->vidmem;
424    fb->pseudo_palette = jzfb->pseudo_palette;
425
426    fb_alloc_cmap(&fb->cmap, 256, 0);
427
428    jzfb_set_par(fb);
429    writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
430
431    ret = register_framebuffer(fb);
432    if (ret) {
433        dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret);
434        goto err_free_devmem;
435    }
436
437    return 0;
438err_free_devmem:
439    jzfb_free_devmem(jzfb);
440err_iounmap:
441    iounmap(jzfb->base);
442err_framebuffer_release:
443    framebuffer_release(fb);
444err_release_mem_region:
445    release_mem_region(mem->start, resource_size(mem));
446    return ret;
447}
448
449static int __devexit jzfb_remove(struct platform_device *pdev)
450{
451    struct jzfb *jzfb = platform_get_drvdata(pdev);
452
453    iounmap(jzfb->base);
454    release_mem_region(jzfb->mem->start, resource_size(jzfb->mem));
455    jzfb_free_devmem(jzfb);
456    platform_set_drvdata(pdev, NULL);
457    framebuffer_release(jzfb->fb);
458    return 0;
459}
460
461static struct platform_driver jzfb_driver = {
462    .probe = jzfb_probe,
463    .remove = __devexit_p(jzfb_remove),
464
465    .driver = {
466        .name = "jz4740-fb",
467    },
468};
469
470int __init jzfb_init(void)
471{
472    return platform_driver_register(&jzfb_driver);
473}
474module_init(jzfb_init);
475
476void __exit jzfb_exit(void)
477{
478    platform_driver_unregister(&jzfb_driver);
479}
480module_exit(jzfb_exit);
481
482MODULE_LICENSE("GPL");
483MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
484MODULE_DESCRIPTION("JZ4720/JZ4740 SoC LCD framebuffer driver");
485MODULE_ALIAS("platform:jz4740-fb");
486MODULE_ALIAS("platform:jz4720-fb");
include/linux/jz4740-adc.h
1
2#ifndef __LINUX_JZ4740_ADC
3#define __LINUX_JZ4740_ADC
4
5#include <linux/device.h>
6
7enum jz_adc_battery_scale {
8    JZ_ADC_BATTERY_SCALE_2V5, /* Mesures voltages up to 2.5V */
9    JZ_ADC_BATTERY_SCALE_7V5, /* Mesures voltages up to 7.5V */
10};
11
12/*
13 * jz4740_adc_read_battery_voltage - Read battery voltage from the ADC PBAT pin
14 * @dev: Pointer to a jz4740-adc device
15 * @scale: Whether to use 2.5V or 7.5V scale
16 *
17 * Returns: Battery voltage in mircovolts
18 *
19 * Context: Process
20*/
21long jz4740_adc_read_battery_voltage(struct device *dev,
22                    enum jz_adc_battery_scale scale);
23
24
25#endif
include/linux/jz4740_fb.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __LINUX_JZ4740_FB_H
16#define __LINUX_JZ4740_FB_H
17
18#include <linux/fb.h>
19
20enum jz4740_fb_lcd_type {
21    JZ_LCD_TYPE_GENERIC_16_18_BIT = 0,
22    JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
23    JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
24    JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
25    JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
26    JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
27    JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
28    JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
29    JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
30    JZ_LCD_TYPE_8BIT_SERIAL = 11,
31};
32
33/*
34* width: width of the lcd display in mm
35* height: height of the lcd display in mm
36* num_modes: size of modes
37* modes: list of valid video modes
38* bpp: bits per pixel for the lcd
39* lcd_type: lcd type
40*/
41
42struct jz4740_fb_platform_data {
43    unsigned int width;
44    unsigned int height;
45
46    size_t num_modes;
47    struct fb_videomode *modes;
48    int bpp;
49    enum jz4740_fb_lcd_type lcd_type;
50};
51
52#endif
include/linux/mmc/jz4740_mmc.h
1#ifndef __LINUX_MMC_JZ4740_MMC
2#define __LINUX_MMC_JZ4740_MMC
3
4struct jz4740_mmc_platform_data {
5    int gpio_power;
6    int gpio_card_detect;
7    int gpio_read_only;
8    unsigned card_detect_active_low:1;
9    unsigned read_only_active_low:1;
10
11    unsigned data_1bit:1;
12};
13
14#endif
include/linux/mtd/jz4740_nand.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC NAND controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __JZ_NAND_H__
17#define __JZ_NAND_H__
18
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21
22struct jz_nand_platform_data {
23    int num_partitions;
24    struct mtd_partition *partitions;
25
26    struct nand_ecclayout *ecc_layout;
27
28    unsigned int busy_gpio;
29
30    void (*ident_callback)(struct platform_device *, struct nand_chip *,
31                struct mtd_partition **, int *num_partitions);
32};
33
34#endif
include/linux/power/jz4740-battery.h
1/*
2 * Copyright (C) 2009, Jiejing Zhang <kzjeef@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __JZ4740_BATTERY_H
16#define __JZ4740_BATTERY_H
17
18struct jz_batt_info {
19    int dc_dect_gpio; /* GPIO port of DC charger detection */
20    int usb_dect_gpio; /* GPIO port of USB charger detection */
21    int charg_stat_gpio; /* GPIO port of Charger state */
22
23    int min_voltag; /* Mininal battery voltage in uV */
24    int max_voltag; /* Maximum battery voltage in uV */
25    int batt_tech; /* Battery technology */
26};
27
28#endif
sound/soc/codecs/jzcodec.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * You should have received a copy of the GNU General Public License along
9 * with this program; if not, write to the Free Software Foundation, Inc.,
10 * 675 Mass Ave, Cambridge, MA 02139, USA.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/initval.h>
23#include <sound/soc-dapm.h>
24#include <sound/soc.h>
25
26#define JZ_REG_CODEC_1 0x0
27#define JZ_REG_CODEC_2 0x1
28
29#define JZ_CODEC_1_LINE_ENABLE BIT(29)
30#define JZ_CODEC_1_MIC_ENABLE BIT(28)
31#define JZ_CODEC_1_SW1_ENABLE BIT(27)
32#define JZ_CODEC_1_ADC_ENABLE BIT(26)
33#define JZ_CODEC_1_SW2_ENABLE BIT(25)
34#define JZ_CODEC_1_DAC_ENABLE BIT(24)
35#define JZ_CODEC_1_VREF_DISABLE BIT(20)
36#define JZ_CODEC_1_VREF_AMP_DISABLE BIT(19)
37#define JZ_CODEC_1_VREF_PULL_DOWN BIT(18)
38#define JZ_CODEC_1_VREF_LOW_CURRENT BIT(17)
39#define JZ_CODEC_1_VREF_HIGH_CURRENT BIT(16)
40#define JZ_CODEC_1_HEADPHONE_DISABLE BIT(14)
41#define JZ_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
42#define JZ_CODEC_1_HEADPHONE_CHANGE BIT(12)
43#define JZ_CODEC_1_HEADPHONE_PULL_DOWN_M BIT(11)
44#define JZ_CODEC_1_HEADPHONE_PULL_DOWN_R BIT(10)
45#define JZ_CODEC_1_HEADPHONE_POWER_DOWN_M BIT(9)
46#define JZ_CODEC_1_HEADPHONE_POWER_DOWN BIT(8)
47#define JZ_CODEC_1_SUSPEND BIT(1)
48#define JZ_CODEC_1_RESET BIT(0)
49
50#define JZ_CODEC_1_LINE_ENABLE_OFFSET 29
51#define JZ_CODEC_1_MIC_ENABLE_OFFSET 28
52#define JZ_CODEC_1_SW1_ENABLE_OFFSET 27
53#define JZ_CODEC_1_ADC_ENABLE_OFFSET 26
54#define JZ_CODEC_1_SW2_ENABLE_OFFSET 25
55#define JZ_CODEC_1_DAC_ENABLE_OFFSET 24
56#define JZ_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
57#define JZ_CODEC_1_HEADPHONE_POWER_DOWN_OFFSET 8
58
59#define JZ_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
60#define JZ_CODEC_2_SAMPLE_RATE_MASK 0x000f00
61#define JZ_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
62#define JZ_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
63
64#define JZ_CODEC_2_INPUT_VOLUME_OFFSET 16
65#define JZ_CODEC_2_SAMPLE_RATE_OFFSET 8
66#define JZ_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
67#define JZ_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
68
69struct jz_codec {
70    void __iomem *base;
71    struct resource *mem;
72
73    uint32_t reg_cache[2];
74    struct snd_soc_codec codec;
75};
76
77inline static struct jz_codec *codec_to_jz(struct snd_soc_codec *codec)
78{
79    return container_of(codec, struct jz_codec, codec);
80}
81
82static unsigned int jz_codec_read(struct snd_soc_codec *codec, unsigned int reg)
83{
84    struct jz_codec *jz_codec = codec_to_jz(codec);
85    return readl(jz_codec->base + (reg << 2));
86}
87
88static int jz_codec_write(struct snd_soc_codec *codec, unsigned int reg,
89unsigned int val)
90{
91    struct jz_codec *jz_codec = codec_to_jz(codec);
92    jz_codec->reg_cache[reg] = val;
93
94    writel(val, jz_codec->base + (reg << 2));
95    return 0;
96}
97
98static const struct snd_kcontrol_new jz_codec_controls[] = {
99    SOC_SINGLE("Master Playback Volume", JZ_REG_CODEC_2,
100            JZ_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0),
101    SOC_SINGLE("Capture Volume", JZ_REG_CODEC_2,
102            JZ_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0),
103    SOC_SINGLE("Master Playback Switch", JZ_REG_CODEC_1,
104            JZ_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
105    SOC_SINGLE("Mic Capture Volume", JZ_REG_CODEC_2,
106            JZ_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0),
107};
108
109static const struct snd_kcontrol_new jz_codec_output_controls[] = {
110    SOC_DAPM_SINGLE("Bypass Switch", JZ_REG_CODEC_1,
111            JZ_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
112    SOC_DAPM_SINGLE("DAC Switch", JZ_REG_CODEC_1,
113            JZ_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
114};
115
116static const struct snd_kcontrol_new jz_codec_input_controls[] =
117{
118    SOC_DAPM_SINGLE("Line Capture Switch", JZ_REG_CODEC_1,
119            JZ_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
120    SOC_DAPM_SINGLE("Mic Capture Switch", JZ_REG_CODEC_1,
121            JZ_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
122};
123
124static const struct snd_soc_dapm_widget jz_codec_dapm_widgets[] = {
125    SND_SOC_DAPM_ADC("ADC", "Capture", JZ_REG_CODEC_1,
126            JZ_CODEC_1_ADC_ENABLE_OFFSET, 0),
127    SND_SOC_DAPM_DAC("DAC", "Playback", JZ_REG_CODEC_1,
128            JZ_CODEC_1_DAC_ENABLE_OFFSET, 0),
129
130    SND_SOC_DAPM_MIXER("Output Mixer", JZ_REG_CODEC_1,
131            JZ_CODEC_1_HEADPHONE_POWER_DOWN_OFFSET, 1,
132            jz_codec_output_controls,
133            ARRAY_SIZE(jz_codec_output_controls)),
134
135    SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
136            jz_codec_input_controls,
137            ARRAY_SIZE(jz_codec_input_controls)),
138    SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
139
140    SND_SOC_DAPM_OUTPUT("LOUT"),
141    SND_SOC_DAPM_OUTPUT("ROUT"),
142
143    SND_SOC_DAPM_INPUT("MIC"),
144    SND_SOC_DAPM_INPUT("LIN"),
145    SND_SOC_DAPM_INPUT("RIN"),
146};
147
148static const struct snd_soc_dapm_route jz_codec_dapm_routes[] = {
149
150    {"Line Input", NULL, "LIN"},
151    {"Line Input", NULL, "RIN"},
152
153    {"Input Mixer", "Line Capture Switch", "Line Input"},
154    {"Input Mixer", "Mic Capture Switch", "MIC"},
155
156    {"ADC", NULL, "Input Mixer"},
157
158    {"Output Mixer", "Bypass Switch", "Input Mixer"},
159    {"Output Mixer", "DAC Switch", "DAC"},
160
161    {"LOUT", NULL, "Output Mixer"},
162    {"ROUT", NULL, "Output Mixer"},
163};
164
165static int jz_codec_hw_params(struct snd_pcm_substream *substream, struct
166snd_pcm_hw_params *params, struct snd_soc_dai *dai)
167{
168    uint32_t val;
169    struct snd_soc_pcm_runtime *rtd = substream->private_data;
170    struct snd_soc_device *socdev = rtd->socdev;
171    struct snd_soc_codec *codec = socdev->card->codec;
172
173    switch (params_format(params)) {
174    case SNDRV_PCM_FORMAT_S8:
175    case SNDRV_PCM_FORMAT_S16_LE:
176    case SNDRV_PCM_FORMAT_S18_3LE:
177        break;
178    default:
179        return -EINVAL;
180        break;
181    }
182
183    switch (params_rate(params)) {
184    case 8000:
185        val = 0;
186        break;
187    case 11025:
188        val = 1;
189        break;
190    case 12000:
191        val = 2;
192        break;
193    case 16000:
194        val = 3;
195        break;
196    case 22050:
197        val = 4;
198        break;
199    case 24000:
200        val = 5;
201        break;
202    case 32000:
203        val = 6;
204        break;
205    case 44100:
206        val = 7;
207        break;
208    case 48000:
209        val = 8;
210        break;
211    default:
212        return -EINVAL;
213    }
214
215    val <<= JZ_CODEC_2_SAMPLE_RATE_OFFSET;
216
217    snd_soc_update_bits(codec, JZ_REG_CODEC_2,
218                JZ_CODEC_2_SAMPLE_RATE_MASK, val);
219
220    return 0;
221}
222
223static int jz_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
224{
225    switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
226    case SND_SOC_DAIFMT_CBM_CFM:
227        break;
228    default:
229        return -EINVAL;
230    }
231
232    switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
233    case SND_SOC_DAIFMT_I2S:
234        break;
235    default:
236        return -EINVAL;
237    }
238
239    switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
240    case SND_SOC_DAIFMT_NB_NF:
241        break;
242    default:
243        return -EINVAL;
244    }
245
246    return 0;
247}
248
249static int jz_codec_set_sysclk(struct snd_soc_dai *codec_dai,
250        int clk_id, unsigned int freq, int dir)
251{
252    return 0;
253}
254
255
256static struct snd_soc_dai_ops jz_codec_dai_ops = {
257    .hw_params = jz_codec_hw_params,
258    .set_fmt = jz_codec_set_fmt,
259/* .set_clkdiv = jz_codec_set_clkdiv,*/
260    .set_sysclk = jz_codec_set_sysclk,
261};
262
263struct snd_soc_dai jz_codec_dai = {
264    .name = "jz-codec",
265    .playback = {
266        .stream_name = "Playback",
267        .channels_min = 2,
268        .channels_max = 2,
269        .rates = SNDRV_PCM_RATE_8000_44100,
270        .formats = SNDRV_PCM_FORMAT_S18_3LE,
271    },
272    .capture = {
273        .stream_name = "Capture",
274        .channels_min = 2,
275        .channels_max = 2,
276        .rates = SNDRV_PCM_RATE_8000_44100,
277        .formats = SNDRV_PCM_FORMAT_S16_LE,
278    },
279    .ops = &jz_codec_dai_ops,
280    .symmetric_rates = 1,
281};
282EXPORT_SYMBOL_GPL(jz_codec_dai);
283
284static int jz_codec_set_bias_level(struct snd_soc_codec *codec,
285                enum snd_soc_bias_level level)
286{
287
288    if (codec->bias_level == SND_SOC_BIAS_OFF && level != SND_SOC_BIAS_OFF) {
289        snd_soc_update_bits(codec, JZ_REG_CODEC_1,
290                JZ_CODEC_1_RESET, JZ_CODEC_1_RESET);
291        udelay(2);
292
293        snd_soc_update_bits(codec, JZ_REG_CODEC_1,
294                    JZ_CODEC_1_SUSPEND | JZ_CODEC_1_RESET, 0);
295    }
296    switch (level) {
297    case SND_SOC_BIAS_ON:
298        snd_soc_update_bits(codec, JZ_REG_CODEC_1,
299                    JZ_CODEC_1_VREF_DISABLE | JZ_CODEC_1_VREF_AMP_DISABLE |
300                    JZ_CODEC_1_HEADPHONE_POWER_DOWN_M |
301                    JZ_CODEC_1_VREF_LOW_CURRENT | JZ_CODEC_1_VREF_HIGH_CURRENT,
302                0);
303        break;
304    case SND_SOC_BIAS_PREPARE:
305        snd_soc_update_bits(codec, JZ_REG_CODEC_1,
306                    JZ_CODEC_1_VREF_LOW_CURRENT | JZ_CODEC_1_VREF_HIGH_CURRENT,
307                    JZ_CODEC_1_VREF_LOW_CURRENT | JZ_CODEC_1_VREF_HIGH_CURRENT);
308        break;
309    case SND_SOC_BIAS_STANDBY:
310        snd_soc_update_bits(codec, JZ_REG_CODEC_1,
311                    JZ_CODEC_1_VREF_DISABLE | JZ_CODEC_1_VREF_AMP_DISABLE,
312                    JZ_CODEC_1_VREF_DISABLE | JZ_CODEC_1_VREF_AMP_DISABLE);
313        break;
314    case SND_SOC_BIAS_OFF:
315        snd_soc_update_bits(codec, JZ_REG_CODEC_1,
316                    JZ_CODEC_1_SUSPEND, JZ_CODEC_1_SUSPEND);
317        break;
318    }
319    codec->bias_level = level;
320
321    return 0;
322}
323
324
325static struct snd_soc_codec *jz_codec_codec;
326
327static int jz_codec_dev_probe(struct platform_device *pdev)
328{
329    int ret;
330    struct snd_soc_device *socdev = platform_get_drvdata(pdev);
331    struct snd_soc_codec *codec = jz_codec_codec;
332
333    BUG_ON(!codec);
334
335    socdev->card->codec = codec;
336
337    ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
338    if (ret) {
339        dev_err(&pdev->dev, "Failed to create pcms: %d\n", ret);
340        goto err;
341    }
342    snd_soc_add_controls(codec, jz_codec_controls,
343    ARRAY_SIZE(jz_codec_controls));
344
345    snd_soc_dapm_new_controls(codec, jz_codec_dapm_widgets,
346    ARRAY_SIZE(jz_codec_dapm_widgets));
347
348    snd_soc_dapm_add_routes(codec, jz_codec_dapm_routes,
349    ARRAY_SIZE(jz_codec_dapm_routes));
350
351    snd_soc_dapm_new_widgets(codec);
352
353    ret = snd_soc_init_card(socdev);
354
355    if (ret) {
356        dev_err(&pdev->dev, "Failed to register card\n");
357        goto err;
358    }
359
360    return 0;
361
362err:
363    snd_soc_free_pcms(socdev);
364    snd_soc_dapm_free(socdev);
365
366    return ret;
367}
368
369static int jz_codec_dev_remove(struct platform_device *pdev)
370{
371    struct snd_soc_device *socdev = platform_get_drvdata(pdev);
372    snd_soc_free_pcms(socdev);
373    snd_soc_dapm_free(socdev);
374
375    return 0;
376}
377
378struct snd_soc_codec_device soc_codec_dev_jzcodec = {
379    .probe = jz_codec_dev_probe,
380    .remove = jz_codec_dev_remove,
381};
382EXPORT_SYMBOL_GPL(soc_codec_dev_jzcodec);
383
384static int __devinit jz_codec_probe(struct platform_device *pdev)
385{
386    int ret;
387    struct jz_codec *jz_codec;
388    struct snd_soc_codec *codec;
389
390    jz_codec = kzalloc(sizeof(*jz_codec), GFP_KERNEL);
391
392    if (!jz_codec)
393        return -ENOMEM;
394
395    jz_codec->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
396
397    if (!jz_codec->mem) {
398        dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
399        ret = -ENOENT;
400        goto err_free_jz_codec;
401    }
402
403    jz_codec->mem = request_mem_region(jz_codec->mem->start,
404                resource_size(jz_codec->mem), pdev->name);
405
406    if (!jz_codec->mem) {
407        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
408        ret = -EBUSY;
409        goto err_free_jz_codec;
410    }
411
412    jz_codec->base = ioremap(jz_codec->mem->start, resource_size(jz_codec->mem));
413
414    if (!jz_codec->base) {
415        dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
416        ret = -EBUSY;
417        goto err_release_mem_region;
418    }
419
420    jz_codec_dai.dev = &pdev->dev;
421
422    codec = &jz_codec->codec;
423
424    codec->dev = &pdev->dev;
425    codec->name = "jz-codec";
426    codec->owner = THIS_MODULE;
427
428    codec->read = jz_codec_read;
429    codec->write = jz_codec_write;
430    codec->set_bias_level = jz_codec_set_bias_level;
431    codec->bias_level = SND_SOC_BIAS_OFF;
432
433    codec->dai = &jz_codec_dai;
434    codec->num_dai = 1;
435
436    codec->reg_cache = jz_codec->reg_cache;
437    codec->reg_cache_size = 2;
438
439    codec->private_data = jz_codec;
440
441    mutex_init(&codec->mutex);
442    INIT_LIST_HEAD(&codec->dapm_widgets);
443    INIT_LIST_HEAD(&codec->dapm_paths);
444
445    jz_codec_codec = codec;
446
447    platform_set_drvdata(pdev, jz_codec);
448    ret = snd_soc_register_codec(codec);
449
450    if (ret) {
451        dev_err(&pdev->dev, "Failed to register codec\n");
452        goto err_iounmap;
453    }
454
455    ret = snd_soc_register_dai(&jz_codec_dai);
456    if (ret) {
457        dev_err(&pdev->dev, "Failed to register codec dai\n");
458        goto err_unregister_codec;
459    }
460
461    jz_codec_set_bias_level (codec, SND_SOC_BIAS_STANDBY);
462
463    return 0;
464err_unregister_codec:
465    snd_soc_unregister_codec(codec);
466err_iounmap:
467    iounmap(jz_codec->base);
468err_release_mem_region:
469    release_mem_region(jz_codec->mem->start, resource_size(jz_codec->mem));
470err_free_jz_codec:
471    kfree(jz_codec);
472
473    return ret;
474}
475
476static int __devexit jz_codec_remove(struct platform_device *pdev)
477{
478    struct jz_codec *jz_codec = platform_get_drvdata(pdev);
479
480    snd_soc_unregister_dai(&jz_codec_dai);
481    snd_soc_unregister_codec(&jz_codec->codec);
482
483    iounmap(jz_codec->base);
484    release_mem_region(jz_codec->mem->start, resource_size(jz_codec->mem));
485
486    platform_set_drvdata(pdev, NULL);
487    kfree(jz_codec);
488
489    return 0;
490}
491
492static struct platform_driver jz_codec_driver = {
493    .probe = jz_codec_probe,
494    .remove = __devexit_p(jz_codec_remove),
495    .driver = {
496        .name = "jz4740-codec",
497        .owner = THIS_MODULE,
498    },
499};
500
501static int __init jz_codec_init(void)
502{
503    return platform_driver_register(&jz_codec_driver);
504}
505module_init(jz_codec_init);
506
507static void __exit jz_codec_exit(void)
508{
509    platform_driver_unregister(&jz_codec_driver);
510}
511module_exit(jz_codec_exit);
512
513MODULE_DESCRIPTION("JZ4720/JZ4740 SoC internal codec driver");
514MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
515MODULE_LICENSE("GPL v2");
516MODULE_ALIAS("platform:jz-codec");
sound/soc/codecs/jzcodec.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * You should have received a copy of the GNU General Public License along
9 * with this program; if not, write to the Free Software Foundation, Inc.,
10 * 675 Mass Ave, Cambridge, MA 02139, USA.
11 *
12 */
13
14#ifndef _ICODEC_H
15#define _ICODEC_H
16
17#define JZCODEC_SYSCLK 0
18
19extern struct snd_soc_dai jz_codec_dai;
20extern struct snd_soc_codec_device soc_codec_dev_jzcodec;
21
22#endif
sound/soc/jz4740/Kconfig
1config SND_JZ4740_SOC
2    tristate "SoC Audio for Ingenic JZ4740 SoC"
3    depends on SOC_JZ4740 && SND_SOC
4    help
5      Say Y or M if you want to add support for codecs attached to
6      the Jz4740 AC97, I2S or SSP interface. You will also need
7      to select the audio interfaces to support below.
8
9config SND_JZ4740_SOC_QI_LB60
10    tristate "SoC Audio support for Qi Hardware Ben Nanonote"
11    depends on SND_JZ4740_SOC && JZ4740_QI_LB60
12    select SND_JZ4740_SOC_I2S
13    select SND_SOC_JZCODEC
14    help
15      Say Y if you want to add support for SoC audio of internal codec on Ingenic Jz4740 QI_LB60 board.
16
17config SND_JZ4740_SOC_I2S
18    depends on SND_JZ4740_SOC
19    tristate "SoC Audio (I2S protocol) for Ingenic jz4740 chip"
20    help
21      Say Y if you want to use I2S protocol and I2S codec on Ingenic Jz4740 QI_LB60 board.
sound/soc/jz4740/Makefile
1#
2# Jz4740 Platform Support
3#
4snd-soc-jz4740-objs := jz4740-pcm.o
5snd-soc-jz4740-i2s-objs := jz4740-i2s.o
6
7obj-$(CONFIG_SND_JZ4740_SOC) += snd-soc-jz4740.o
8obj-$(CONFIG_SND_JZ4740_SOC_I2S) += snd-soc-jz4740-i2s.o
9
10# Jz4740 Machine Support
11snd-soc-qi-lb60-objs := qi_lb60.o
12
13obj-$(CONFIG_SND_JZ4740_SOC_QI_LB60) += snd-soc-qi-lb60.o
sound/soc/jz4740/jz4740-i2s.c
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Jiejing Zhang(kzjeef(at)gmail.com) 2009: Make jz soc sound card
8 * loaded by soc-core.
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/device.h>
14#include <linux/delay.h>
15#include <sound/core.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <sound/initval.h>
19#include <sound/soc.h>
20
21#include <asm/mach-jz4740/regs.h>
22#include <asm/mach-jz4740/ops.h>
23
24#include "jz4740-pcm.h"
25#include "jz4740-i2s.h"
26
27static struct jz4740_dma_client jz4740_dma_client_out = {
28    .name = "I2S PCM Stereo out"
29};
30
31static struct jz4740_dma_client jz4740_dma_client_in = {
32    .name = "I2S PCM Stereo in"
33};
34
35static struct jz4740_pcm_dma_params jz4740_i2s_pcm_stereo_out = {
36    .client = &jz4740_dma_client_out,
37    .channel = DMA_ID_AIC_TX,
38    .dma_addr = AIC_DR,
39    .dma_size = 2,
40};
41
42static struct jz4740_pcm_dma_params jz4740_i2s_pcm_stereo_in = {
43    .client = &jz4740_dma_client_in,
44    .channel = DMA_ID_AIC_RX,
45    .dma_addr = AIC_DR,
46    .dma_size = 2,
47};
48
49static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
50{
51    /*struct snd_soc_pcm_runtime *rtd = substream->private_data;
52      struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;*/
53
54    return 0;
55}
56
57static int jz4740_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
58        unsigned int fmt)
59{
60    /* interface format */
61    switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
62    case SND_SOC_DAIFMT_I2S:
63        /* 1 : ac97 , 0 : i2s */
64        break;
65    case SND_SOC_DAIFMT_LEFT_J:
66        break;
67    default:
68        return -EINVAL;
69    }
70
71    switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
72    case SND_SOC_DAIFMT_CBS_CFS:
73            /* 0 : slave */
74        break;
75    case SND_SOC_DAIFMT_CBM_CFS:
76        /* 1 : master */
77        break;
78    default:
79        break;
80    }
81
82    return 0;
83}
84
85/*
86* Set Jz4740 Clock source
87*/
88static int jz4740_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
89        int clk_id, unsigned int freq, int dir)
90{
91    return 0;
92}
93
94static void jz4740_snd_tx_ctrl(int on)
95{
96    if (on) {
97                /* enable replay */
98            __i2s_enable_transmit_dma();
99        __i2s_enable_replay();
100        __i2s_enable();
101
102    } else {
103        /* disable replay & capture */
104        __i2s_disable_replay();
105        __i2s_disable_record();
106        __i2s_disable_receive_dma();
107        __i2s_disable_transmit_dma();
108        __i2s_disable();
109    }
110}
111
112static void jz4740_snd_rx_ctrl(int on)
113{
114    if (on) {
115                /* enable capture */
116        __i2s_enable_receive_dma();
117        __i2s_enable_record();
118        __i2s_enable();
119
120    } else {
121                /* disable replay & capture */
122        __i2s_disable_replay();
123        __i2s_disable_record();
124        __i2s_disable_receive_dma();
125        __i2s_disable_transmit_dma();
126        __i2s_disable();
127    }
128}
129
130static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
131                struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
132{
133    struct snd_soc_pcm_runtime *rtd = substream->private_data;
134    struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
135    /* int channels = params_channels(params); */
136
137    jz4740_snd_rx_ctrl(0);
138    jz4740_snd_rx_ctrl(0);
139    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
140        cpu_dai->dma_data = &jz4740_i2s_pcm_stereo_out;
141        /*if (channels == 1)
142            __aic_enable_mono2stereo();
143        else
144        __aic_disable_mono2stereo();*/
145    } else
146        cpu_dai->dma_data = &jz4740_i2s_pcm_stereo_in;
147
148    switch (params_format(params)) {
149    case SNDRV_PCM_FORMAT_S8:
150        __i2s_set_transmit_trigger(4);
151        __i2s_set_receive_trigger(3);
152        __i2s_set_oss_sample_size(8);
153        __i2s_set_iss_sample_size(8);
154        break;
155    case SNDRV_PCM_FORMAT_S16_LE:
156        /* playback sample:16 bits, burst:16 bytes */
157        __i2s_set_transmit_trigger(4);
158        /* capture sample:16 bits, burst:16 bytes */
159        __i2s_set_receive_trigger(3);
160        __i2s_set_oss_sample_size(16);
161        __i2s_set_iss_sample_size(16);
162        break;
163    }
164
165    return 0;
166}
167
168static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
169{
170    int ret = 0;
171    switch (cmd) {
172    case SNDRV_PCM_TRIGGER_START:
173    case SNDRV_PCM_TRIGGER_RESUME:
174    case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
175        if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
176            jz4740_snd_rx_ctrl(1);
177        else
178            jz4740_snd_tx_ctrl(1);
179        break;
180    case SNDRV_PCM_TRIGGER_STOP:
181    case SNDRV_PCM_TRIGGER_SUSPEND:
182    case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
183        if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
184            jz4740_snd_rx_ctrl(0);
185        else
186            jz4740_snd_tx_ctrl(0);
187        break;
188    default:
189        ret = -EINVAL;
190    }
191
192    return ret;
193}
194
195static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
196{
197    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
198    } else {
199    }
200
201    return;
202}
203
204static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
205{
206    __i2s_internal_codec();
207    __i2s_as_slave();
208    __i2s_select_i2s();
209    __aic_select_i2s();
210    mdelay(2);
211
212    __i2s_disable();
213    __i2s_reset();
214    mdelay(2);
215
216       __i2s_disable();
217    __i2s_internal_codec();
218    __i2s_as_slave();
219    __i2s_select_i2s();
220    __aic_select_i2s();
221    __i2s_set_oss_sample_size(16);
222    __i2s_set_iss_sample_size(16);
223        __aic_play_lastsample();
224
225    __i2s_disable_record();
226    __i2s_disable_replay();
227    __i2s_disable_loopback();
228    __i2s_set_transmit_trigger(7);
229    __i2s_set_receive_trigger(7);
230
231    jz4740_snd_tx_ctrl(0);
232    jz4740_snd_rx_ctrl(0);
233
234    return 0;
235}
236
237#ifdef CONFIG_PM
238static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
239{
240    if (!dai->active)
241        return 0;
242
243    return 0;
244}
245
246static int jz4740_i2s_resume(struct snd_soc_dai *dai)
247{
248    if (!dai->active)
249        return 0;
250
251    return 0;
252}
253
254#else
255#define jz4740_i2s_suspend NULL
256#define jz4740_i2s_resume NULL
257#endif
258
259#define JZ4740_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
260        SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
261        SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
262        SNDRV_PCM_RATE_48000)
263
264struct snd_soc_dai_ops snd_jz4740_i2s_dai_ops = {
265    .startup = jz4740_i2s_startup,
266    .shutdown = jz4740_i2s_shutdown,
267    .trigger = jz4740_i2s_trigger,
268    .hw_params = jz4740_i2s_hw_params,
269    .set_fmt = jz4740_i2s_set_dai_fmt,
270    .set_sysclk = jz4740_i2s_set_dai_sysclk,
271};
272
273struct snd_soc_dai jz4740_i2s_dai = {
274    .name = "jz4740-i2s",
275    .id = 0,
276    .probe = jz4740_i2s_probe,
277    .suspend = jz4740_i2s_suspend,
278    .resume = jz4740_i2s_resume,
279    .playback = {
280        .channels_min = 1,
281        .channels_max = 2,
282        .rates = JZ4740_I2S_RATES,
283        .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
284    },
285    .capture = {
286        .channels_min = 1,
287        .channels_max = 2,
288        .rates = JZ4740_I2S_RATES,
289        .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
290    },
291    .ops = &snd_jz4740_i2s_dai_ops,
292};
293
294EXPORT_SYMBOL_GPL(jz4740_i2s_dai);
295
296static int __init jz4740_i2s_init(void)
297{
298    return snd_soc_register_dai(&jz4740_i2s_dai);
299}
300
301static void __exit jz4740_i2s_exit(void)
302{
303    snd_soc_unregister_dai(&jz4740_i2s_dai);
304}
305
306module_init(jz4740_i2s_init);
307module_exit(jz4740_i2s_exit);
308
309/* Module information */
310MODULE_AUTHOR("Richard, cjfeng@ingenic.cn, www.ingenic.cn");
311MODULE_DESCRIPTION("jz4740 I2S SoC Interface");
312MODULE_LICENSE("GPL");
sound/soc/jz4740/jz4740-i2s.h
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6
7#ifndef _JZ4740_I2S_H
8#define _JZ4740_I2S_H
9
10/* jz4740 DAI ID's */
11#define JZ4740_DAI_I2S 0
12
13/* I2S clock */
14#define JZ4740_I2S_SYSCLK 0
15
16extern struct snd_soc_dai jz4740_i2s_dai;
17
18#endif
sound/soc/jz4740/jz4740-pcm.c
1/*
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 as
5 * published by the Free Software Foundation.
6 */
7
8#include <linux/module.h>
9#include <linux/interrupt.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/dma-mapping.h>
14
15#include <sound/core.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <sound/soc.h>
19
20#include <asm/io.h>
21#include "jz4740-pcm.h"
22
23static long sum_bytes = 0;
24static int first_transfer = 0;
25static int printk_flag = 0;
26static int tran_bit = 0;
27#ifdef CONFIG_SND_OSSEMUL
28static int hw_params_cnt = 0;
29#endif
30
31static struct jz4740_dma_client jz4740_dma_client_out = {
32    .name = "I2S PCM Stereo out"
33};
34
35static struct jz4740_dma_client jz4740_dma_client_in = {
36    .name = "I2S PCM Stereo in"
37};
38
39static struct jz4740_pcm_dma_params jz4740_i2s_pcm_stereo_out = {
40    .client = &jz4740_dma_client_out,
41    .channel = DMA_ID_AIC_TX,
42    .dma_addr = AIC_DR,
43    .dma_size = 2,
44};
45
46static struct jz4740_pcm_dma_params jz4740_i2s_pcm_stereo_in = {
47    .client = &jz4740_dma_client_in,
48    .channel = DMA_ID_AIC_RX,
49    .dma_addr = AIC_DR,
50    .dma_size = 2,
51};
52
53
54struct jz4740_dma_buf_aic {
55    struct jz4740_dma_buf_aic *next;
56    int size; /* buffer size in bytes */
57    dma_addr_t data; /* start of DMA data */
58    dma_addr_t ptr; /* where the DMA got to [1] */
59    void *id; /* client's id */
60};
61
62struct jz4740_runtime_data {
63    spinlock_t lock;
64    int state;
65    int aic_dma_flag; /* start dma transfer or not */
66    unsigned int dma_loaded;
67    unsigned int dma_limit;
68    unsigned int dma_period;
69    dma_addr_t dma_start;
70    dma_addr_t dma_pos;
71    dma_addr_t dma_end;
72    struct jz4740_pcm_dma_params *params;
73
74    dma_addr_t user_cur_addr; /* user current write buffer start address */
75    unsigned int user_cur_len; /* user current write buffer length */
76
77    /* buffer list and information */
78    struct jz4740_dma_buf_aic *curr; /* current dma buffer */
79    struct jz4740_dma_buf_aic *next; /* next buffer to load */
80    struct jz4740_dma_buf_aic *end; /* end of queue */
81
82};
83
84/* identify hardware playback capabilities */
85static const struct snd_pcm_hardware jz4740_pcm_hardware = {
86    .info = SNDRV_PCM_INFO_MMAP |
87                                SNDRV_PCM_INFO_MMAP_VALID |
88                    SNDRV_PCM_INFO_INTERLEAVED |
89                                SNDRV_PCM_INFO_BLOCK_TRANSFER,
90    .formats = SNDRV_PCM_FMTBIT_S16_LE |
91                    SNDRV_PCM_FMTBIT_S8,
92    .rates = SNDRV_PCM_RATE_8000_48000/*0x3fe*/,
93    .rate_min = 8000,
94    .rate_min = 48000,
95    .channels_min = 2,
96    .channels_max = 2,
97    .buffer_bytes_max = 128 * 1024,//16 * 1024
98    .period_bytes_min = PAGE_SIZE,
99    .period_bytes_max = PAGE_SIZE * 2,
100    .periods_min = 2,
101    .periods_max = 128,//16,
102    .fifo_size = 32,
103};
104
105/* jz4740__dma_buf_enqueue
106 *
107 * queue an given buffer for dma transfer.
108 *
109 * data the physical address of the buffer data
110 * size the size of the buffer in bytes
111 *
112*/
113static int jz4740_dma_buf_enqueue(struct jz4740_runtime_data *prtd, dma_addr_t data, int size)
114{
115    struct jz4740_dma_buf_aic *aic_buf;
116
117    aic_buf = kzalloc(sizeof(struct jz4740_dma_buf_aic), GFP_KERNEL);
118    if (aic_buf == NULL) {
119        printk("aic buffer allocate failed,no memory!\n");
120        return -ENOMEM;
121    }
122    aic_buf->next = NULL;
123    aic_buf->data = aic_buf->ptr = data;
124    aic_buf->size = size;
125    if( prtd->curr == NULL) {
126        prtd->curr = aic_buf;
127        prtd->end = aic_buf;
128        prtd->next = NULL;
129    } else {
130        if (prtd->end == NULL)
131            printk("prtd->end is NULL\n");
132            prtd->end->next = aic_buf;
133            prtd->end = aic_buf;
134    }
135
136    /* if necessary, update the next buffer field */
137    if (prtd->next == NULL)
138        prtd->next = aic_buf;
139
140    return 0;
141}
142
143
144void audio_start_dma(struct jz4740_runtime_data *prtd, int mode)
145{
146    unsigned long flags;
147    struct jz4740_dma_buf_aic *aic_buf;
148    int channel;
149
150    switch (mode) {
151    case DMA_MODE_WRITE:
152        /* free cur aic_buf */
153        if (first_transfer == 1) {
154            first_transfer = 0;
155        } else {
156            aic_buf = prtd->curr;
157            if (aic_buf != NULL) {
158                prtd->curr = aic_buf->next;
159                prtd->next = aic_buf->next;
160                aic_buf->next = NULL;
161                kfree(aic_buf);
162                aic_buf = NULL;
163            }
164        }
165
166        aic_buf = prtd->next;
167        channel = prtd->params->channel;
168        if (aic_buf) {
169            disable_dma(channel);
170            jz_set_alsa_dma(channel, mode, tran_bit);
171            set_dma_addr(channel, aic_buf->data);
172            set_dma_count(channel, aic_buf->size);
173            enable_dma(channel);
174            prtd->aic_dma_flag |= AIC_START_DMA;
175        } else {
176            printk("next buffer is NULL for playback\n");
177            prtd->aic_dma_flag &= ~AIC_START_DMA;
178            return;
179        }
180        break;
181    case DMA_MODE_READ:
182                /* free cur aic_buf */
183        if (first_transfer == 1) {
184            first_transfer = 0;
185        } else {
186            aic_buf = prtd->curr;
187            if (aic_buf != NULL) {
188                prtd->curr = aic_buf->next;
189                prtd->next = aic_buf->next;
190                aic_buf->next = NULL;
191                kfree(aic_buf);
192                aic_buf = NULL;
193            }
194        }
195
196        aic_buf = prtd->next;
197        channel = prtd->params->channel;
198
199        if (aic_buf) {
200            disable_dma(channel);
201                        jz_set_alsa_dma(channel, mode, tran_bit);
202            set_dma_addr(channel, aic_buf->data);
203            set_dma_count(channel, aic_buf->size);
204            enable_dma(channel);
205            prtd->aic_dma_flag |= AIC_START_DMA;
206        } else {
207            printk("next buffer is NULL for capture\n");
208            prtd->aic_dma_flag &= ~AIC_START_DMA;
209            return;
210        }
211        break;
212    }
213    /* dump_jz_dma_channel(channel); */
214}
215
216/*
217 * place a dma buffer onto the queue for the dma system to handle.
218*/
219static void jz4740_pcm_enqueue(struct snd_pcm_substream *substream)
220{
221    struct snd_pcm_runtime *runtime = substream->runtime;
222    struct jz4740_runtime_data *prtd = runtime->private_data;
223    /*struct snd_dma_buffer *buf = &substream->dma_buffer;*/
224    dma_addr_t pos = prtd->dma_pos;
225    int ret;
226
227    while (prtd->dma_loaded < prtd->dma_limit) {
228        unsigned long len = prtd->dma_period;
229
230        if ((pos + len) > prtd->dma_end) {
231            len = prtd->dma_end - pos;
232        }
233        ret = jz4740_dma_buf_enqueue(prtd, pos, len);
234        if (ret == 0) {
235            prtd->dma_loaded++;
236            pos += prtd->dma_period;
237            if (pos >= prtd->dma_end)
238                pos = prtd->dma_start;
239        } else
240            break;
241    }
242
243    prtd->dma_pos = pos;
244}
245
246/*
247 * call the function:jz4740_pcm_dma_irq() after DMA has transfered the current buffer
248 */
249static irqreturn_t jz4740_pcm_dma_irq(int dma_ch, void *dev_id)
250{
251    struct snd_pcm_substream *substream = dev_id;
252    struct snd_pcm_runtime *runtime = substream->runtime;
253    struct jz4740_runtime_data *prtd = runtime->private_data;
254    /*struct jz4740_dma_buf_aic *aic_buf = prtd->curr;*/
255    int channel = prtd->params->channel;
256    unsigned long flags;
257
258    disable_dma(channel);
259    prtd->aic_dma_flag &= ~AIC_START_DMA;
260    /* must clear TT bit in DCCSR to avoid interrupt again */
261    if (__dmac_channel_transmit_end_detected(channel)) {
262        __dmac_channel_clear_transmit_end(channel);
263    }
264    if (__dmac_channel_transmit_halt_detected(channel)) {
265        __dmac_channel_clear_transmit_halt(channel);
266    }
267
268    if (__dmac_channel_address_error_detected(channel)) {
269        __dmac_channel_clear_address_error(channel);
270    }
271
272    if (substream)
273        snd_pcm_period_elapsed(substream);
274
275    spin_lock(&prtd->lock);
276    prtd->dma_loaded--;
277    if (prtd->state & ST_RUNNING) {
278        jz4740_pcm_enqueue(substream);
279    }
280    spin_unlock(&prtd->lock);
281
282    local_irq_save(flags);
283    if (prtd->state & ST_RUNNING) {
284        if (prtd->dma_loaded) {
285            if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
286                audio_start_dma(prtd, DMA_MODE_WRITE);
287            else
288                audio_start_dma(prtd, DMA_MODE_READ);
289        }
290    }
291    local_irq_restore(flags);
292    return IRQ_HANDLED;
293}
294
295/* some parameter about DMA operation */
296static int jz4740_pcm_hw_params(struct snd_pcm_substream *substream,
297    struct snd_pcm_hw_params *params)
298{
299    struct snd_pcm_runtime *runtime = substream->runtime;
300    struct jz4740_runtime_data *prtd = runtime->private_data;
301    struct snd_soc_pcm_runtime *rtd = substream->private_data;
302    struct jz4740_pcm_dma_params *dma = &jz4740_i2s_pcm_stereo_out;
303    size_t totbytes = params_buffer_bytes(params);
304    int ret;
305
306    if (!dma)
307         return 0;
308
309    switch (params_format(params)) {
310    case SNDRV_PCM_FORMAT_S8:
311        tran_bit = 8;
312        break;
313    case SNDRV_PCM_FORMAT_S16_LE:
314        tran_bit = 16;
315        break;
316    }
317
318    /* prepare DMA */
319    prtd->params = dma;
320    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
321        ret = jz_request_dma(DMA_ID_AIC_TX, prtd->params->client->name,
322                     jz4740_pcm_dma_irq, IRQF_DISABLED, substream);
323        if (ret < 0)
324            return ret;
325        prtd->params->channel = ret;
326    } else {
327        ret = jz_request_dma(DMA_ID_AIC_RX, prtd->params->client->name,
328                     jz4740_pcm_dma_irq, IRQF_DISABLED, substream);
329        if (ret < 0)
330            return ret;
331        prtd->params->channel = ret;
332    }
333
334    snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
335    runtime->dma_bytes = totbytes;
336
337    spin_lock_irq(&prtd->lock);
338    prtd->dma_loaded = 0;
339    prtd->aic_dma_flag = 0;
340    prtd->dma_limit = runtime->hw.periods_min;
341    prtd->dma_period = params_period_bytes(params);
342    prtd->dma_start = runtime->dma_addr;
343    prtd->dma_pos = prtd->dma_start;
344    prtd->dma_end = prtd->dma_start + totbytes;
345    prtd->curr = NULL;
346    prtd->next = NULL;
347    prtd->end = NULL;
348    sum_bytes = 0;
349    first_transfer = 1;
350    printk_flag = 0;
351
352    __dmac_disable_descriptor(prtd->params->channel);
353    __dmac_channel_disable_irq(prtd->params->channel);
354    spin_unlock_irq(&prtd->lock);
355    return ret;
356}
357
358static int jz4740_pcm_hw_free(struct snd_pcm_substream *substream)
359{
360    struct jz4740_runtime_data *prtd = substream->runtime->private_data;
361
362    snd_pcm_set_runtime_buffer(substream, NULL);
363    if (prtd->params) {
364        jz_free_dma(prtd->params->channel);
365        prtd->params = NULL;
366    }
367
368    return 0;
369}
370
371/* set some dma para for playback/capture */
372static int jz4740_dma_ctrl(int channel)
373{
374
375    disable_dma(channel);
376
377    /* must clear TT bit in DCCSR to avoid interrupt again */
378    if (__dmac_channel_transmit_end_detected(channel)) {
379        __dmac_channel_clear_transmit_end(channel);
380    }
381    if (__dmac_channel_transmit_halt_detected(channel)) {
382        __dmac_channel_clear_transmit_halt(channel);
383    }
384
385    if (__dmac_channel_address_error_detected(channel)) {
386        __dmac_channel_clear_address_error(channel);
387    }
388
389    return 0;
390
391}
392
393static int jz4740_pcm_prepare(struct snd_pcm_substream *substream)
394{
395    struct jz4740_runtime_data *prtd = substream->runtime->private_data;
396    int ret = 0;
397
398    /* return if this is a bufferless transfer e.g */
399    if (!prtd->params)
400         return 0;
401
402    /* flush the DMA channel and DMA channel bit check */
403    jz4740_dma_ctrl(prtd->params->channel);
404    prtd->dma_loaded = 0;
405    prtd->dma_pos = prtd->dma_start;
406
407    /* enqueue dma buffers */
408    jz4740_pcm_enqueue(substream);
409
410    return ret;
411
412}
413
414static int jz4740_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
415{
416    struct snd_pcm_runtime *runtime = substream->runtime;
417    struct jz4740_runtime_data *prtd = runtime->private_data;
418
419    int ret = 0;
420
421    switch (cmd) {
422    case SNDRV_PCM_TRIGGER_START:
423        prtd->state |= ST_RUNNING;
424        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
425            audio_start_dma(prtd, DMA_MODE_WRITE);
426        } else {
427            audio_start_dma(prtd, DMA_MODE_READ);
428        }
429
430        break;
431
432    case SNDRV_PCM_TRIGGER_STOP:
433    case SNDRV_PCM_TRIGGER_SUSPEND:
434    case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
435        prtd->state &= ~ST_RUNNING;
436        break;
437
438    case SNDRV_PCM_TRIGGER_RESUME:
439        printk(" RESUME \n");
440        break;
441    case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
442        printk(" RESTART \n");
443        break;
444
445    default:
446        ret = -EINVAL;
447    }
448
449    return ret;
450}
451
452static snd_pcm_uframes_t
453jz4740_pcm_pointer(struct snd_pcm_substream *substream)
454{
455    struct snd_pcm_runtime *runtime = substream->runtime;
456    struct jz4740_runtime_data *prtd = runtime->private_data;
457    struct jz4740_dma_buf_aic *aic_buf = prtd->curr;
458    long count,res;
459
460    dma_addr_t ptr;
461    snd_pcm_uframes_t x;
462    int channel = prtd->params->channel;
463
464    spin_lock(&prtd->lock);
465#if 1
466
467    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
468        count = get_dma_residue(channel);
469        count = aic_buf->size - count;
470        ptr = aic_buf->data + count;
471        res = ptr - prtd->dma_start;
472    } else {
473        count = get_dma_residue(channel);
474        count = aic_buf->size - count;
475        ptr = aic_buf->data + count;
476        res = ptr - prtd->dma_start;
477    }
478
479# else
480
481    if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
482        if ((prtd->aic_dma_flag & AIC_START_DMA) == 0) {
483            count = get_dma_residue(channel);
484            count = aic_buf->size - count;
485            ptr = aic_buf->data + count;
486            REG_DMAC_DSAR(channel) = ptr;
487            res = ptr - prtd->dma_start;
488        } else {
489            ptr = REG_DMAC_DSAR(channel);
490            if (ptr == 0x0)
491                printk("\ndma address is 00000000 in running!\n");
492            res = ptr - prtd->dma_start;
493        }
494    } else {
495        if ((prtd->aic_dma_flag & AIC_START_DMA) == 0) {
496            count = get_dma_residue(channel);
497            count = aic_buf->size - count;
498            ptr = aic_buf->data + count;
499            REG_DMAC_DTAR(channel) = ptr;
500            res = ptr - prtd->dma_start;
501        } else {
502            ptr = REG_DMAC_DTAR(channel);
503            if (ptr == 0x0)
504                printk("\ndma address is 00000000 in running!\n");
505            res = ptr - prtd->dma_start;
506        }
507    }
508#endif
509    spin_unlock(&prtd->lock);
510    x = bytes_to_frames(runtime, res);
511    if (x == runtime->buffer_size)
512        x = 0;
513
514    return x;
515}
516
517static int jz4740_pcm_open(struct snd_pcm_substream *substream)
518{
519    struct snd_pcm_runtime *runtime = substream->runtime;
520    struct jz4740_runtime_data *prtd;
521
522#ifdef CONFIG_SND_OSSEMUL
523    hw_params_cnt = 0;
524#endif
525    snd_soc_set_runtime_hwparams(substream, &jz4740_pcm_hardware);
526    prtd = kzalloc(sizeof(struct jz4740_runtime_data), GFP_KERNEL);
527    if (prtd == NULL)
528        return -ENOMEM;
529
530    spin_lock_init(&prtd->lock);
531
532    runtime->private_data = prtd;
533    REG_AIC_I2SCR = 0x10;
534    return 0;
535}
536
537static int jz4740_pcm_close(struct snd_pcm_substream *substream)
538{
539    struct snd_pcm_runtime *runtime = substream->runtime;
540    struct jz4740_runtime_data *prtd = runtime->private_data;
541    struct jz4740_dma_buf_aic *aic_buf = NULL;
542
543#ifdef CONFIG_SND_OSSEMUL
544    hw_params_cnt = 0;
545#endif
546
547    if (prtd)
548        aic_buf = prtd->curr;
549
550    while (aic_buf != NULL) {
551        prtd->curr = aic_buf->next;
552        prtd->next = aic_buf->next;
553        aic_buf->next = NULL;
554        kfree(aic_buf);
555        aic_buf = NULL;
556        aic_buf = prtd->curr;
557    }
558
559    if (prtd) {
560        prtd->curr = NULL;
561        prtd->next = NULL;
562        prtd->end = NULL;
563        kfree(prtd);
564    }
565
566    return 0;
567}
568
569static int jz4740_pcm_mmap(struct snd_pcm_substream *substream,
570               struct vm_area_struct *vma)
571{
572    struct snd_pcm_runtime *runtime = substream->runtime;
573
574    return remap_pfn_range(vma, vma->vm_start,
575               substream->dma_buffer.addr >> PAGE_SHIFT,
576               vma->vm_end - vma->vm_start, vma->vm_page_prot);
577}
578
579struct snd_pcm_ops jz4740_pcm_ops = {
580    .open = jz4740_pcm_open,
581    .close = jz4740_pcm_close,
582    .ioctl = snd_pcm_lib_ioctl,
583    .hw_params = jz4740_pcm_hw_params,
584    .hw_free = jz4740_pcm_hw_free,
585    .prepare = jz4740_pcm_prepare,
586    .trigger = jz4740_pcm_trigger,
587    .pointer = jz4740_pcm_pointer,
588    .mmap = jz4740_pcm_mmap,
589};
590
591static int jz4740_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
592{
593    struct snd_pcm_substream *substream = pcm->streams[stream].substream;
594    struct snd_dma_buffer *buf = &substream->dma_buffer;
595    size_t size = jz4740_pcm_hardware.buffer_bytes_max;
596    buf->dev.type = SNDRV_DMA_TYPE_DEV;
597    buf->dev.dev = pcm->card->dev;
598    buf->private_data = NULL;
599
600    /*buf->area = dma_alloc_coherent(pcm->card->dev, size,
601      &buf->addr, GFP_KERNEL);*/
602    buf->area = dma_alloc_noncoherent(pcm->card->dev, size,
603                      &buf->addr, GFP_KERNEL);
604    if (!buf->area)
605        return -ENOMEM;
606    buf->bytes = size;
607    return 0;
608}
609
610static void jz4740_pcm_free_dma_buffers(struct snd_pcm *pcm)
611{
612    struct snd_pcm_substream *substream;
613    struct snd_dma_buffer *buf;
614    int stream;
615
616    for (stream = 0; stream < 2; stream++) {
617        substream = pcm->streams[stream].substream;
618        if (!substream)
619            continue;
620
621        buf = &substream->dma_buffer;
622        if (!buf->area)
623            continue;
624
625        dma_free_noncoherent(pcm->card->dev, buf->bytes,
626          buf->area, buf->addr);
627        buf->area = NULL;
628    }
629}
630
631static u64 jz4740_pcm_dmamask = DMA_BIT_MASK(32);
632
633int jz4740_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
634    struct snd_pcm *pcm)
635{
636    int ret = 0;
637
638    printk("pcm new\n");
639
640    if (!card->dev->dma_mask)
641        card->dev->dma_mask = &jz4740_pcm_dmamask;
642    if (!card->dev->coherent_dma_mask)
643        card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
644
645    if (dai->playback.channels_min) {
646        ret = jz4740_pcm_preallocate_dma_buffer(pcm,
647            SNDRV_PCM_STREAM_PLAYBACK);
648        if (ret)
649            goto out;
650    }
651
652    if (dai->capture.channels_min) {
653        ret = jz4740_pcm_preallocate_dma_buffer(pcm,
654            SNDRV_PCM_STREAM_CAPTURE);
655        if (ret)
656            goto out;
657    }
658 out:
659
660    return ret;
661}
662
663struct snd_soc_platform jz4740_soc_platform = {
664    .name = "jz4740-audio",
665    .pcm_ops = &jz4740_pcm_ops,
666    .pcm_new = jz4740_pcm_new,
667    .pcm_free = jz4740_pcm_free_dma_buffers,
668};
669
670EXPORT_SYMBOL_GPL(jz4740_soc_platform);
671
672static int __init jz4740_soc_platform_init(void)
673{
674    return snd_soc_register_platform(&jz4740_soc_platform);
675}
676module_init(jz4740_soc_platform_init);
677
678static void __exit jz4740_soc_platform_exit(void)
679{
680    snd_soc_unregister_platform(&jz4740_soc_platform);
681}
682module_exit(jz4740_soc_platform_exit);
683
684MODULE_AUTHOR("Richard");
685MODULE_DESCRIPTION("Ingenic Jz4740 PCM DMA module");
686MODULE_LICENSE("GPL");
sound/soc/jz4740/jz4740-pcm.h
1/*
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 as
5 * published by the Free Software Foundation.
6 */
7
8#ifndef _JZ4740_PCM_H
9#define _JZ4740_PCM_H
10
11#include <asm/mach-jz4740/dma.h>
12
13#define ST_RUNNING (1<<0)
14#define ST_OPENED (1<<1)
15
16#define AIC_START_DMA (1<<0)
17#define AIC_END_DMA (1<<1)
18
19struct jz4740_dma_client {
20    char *name;
21};
22
23struct jz4740_pcm_dma_params {
24    struct jz4740_dma_client *client; /* stream identifier */
25    int channel; /* Channel ID */
26    dma_addr_t dma_addr;
27    int dma_size; /* Size of the DMA transfer */
28};
29
30/* platform data */
31extern struct snd_soc_platform jz4740_soc_platform;
32
33#endif
sound/soc/jz4740/qi_lb60.c
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * You should have received a copy of the GNU General Public License along
9 * with this program; if not, write to the Free Software Foundation, Inc.,
10 * 675 Mass Ave, Cambridge, MA 02139, USA.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/soc.h>
22#include <sound/soc-dapm.h>
23#include <linux/gpio.h>
24
25#include "../codecs/jzcodec.h"
26#include "jz4740-pcm.h"
27#include "jz4740-i2s.h"
28
29
30#define QI_LB60_SND_GPIO JZ_GPIO_PORTB(29)
31#define QI_LB60_AMP_GPIO JZ_GPIO_PORTD(4)
32
33static int qi_lb60_spk_event(struct snd_soc_dapm_widget *widget,
34                 struct snd_kcontrol *ctrl, int event)
35{
36    int on = 0;
37    if (event & SND_SOC_DAPM_POST_PMU)
38        on = 1;
39    else if (event & SND_SOC_DAPM_PRE_PMD)
40        on = 0;
41
42    gpio_set_value(QI_LB60_SND_GPIO, on);
43    gpio_set_value(QI_LB60_AMP_GPIO, on);
44
45    return 0;
46}
47
48static const struct snd_soc_dapm_widget qi_lb60_widgets[] = {
49    SND_SOC_DAPM_SPK("Speaker", qi_lb60_spk_event),
50    SND_SOC_DAPM_MIC("Mic", NULL),
51};
52
53static const struct snd_soc_dapm_route qi_lb60_routes[] = {
54    {"Mic", NULL, "MIC"},
55    {"Speaker", NULL, "LOUT"},
56    {"Speaker", NULL, "ROUT"},
57};
58
59#define QI_LB60_DAIFMT (SND_SOC_DAIFMT_I2S | \
60            SND_SOC_DAIFMT_NB_NF | \
61            SND_SOC_DAIFMT_CBM_CFM)
62
63static int qi_lb60_codec_init(struct snd_soc_codec *codec)
64{
65    int ret;
66    struct snd_soc_dai *cpu_dai = codec->socdev->card->dai_link->cpu_dai;
67    struct snd_soc_dai *codec_dai = codec->socdev->card->dai_link->codec_dai;
68
69    snd_soc_dapm_nc_pin(codec, "LIN");
70    snd_soc_dapm_nc_pin(codec, "RIN");
71
72    ret = snd_soc_dai_set_fmt(codec_dai, QI_LB60_DAIFMT);
73    if (ret < 0) {
74        dev_err(codec->dev, "Failed to set codec dai format: %d\n", ret);
75        return ret;
76    }
77
78    ret = snd_soc_dai_set_fmt(cpu_dai, QI_LB60_DAIFMT);
79    if (ret < 0) {
80        dev_err(codec->dev, "Failed to set cpu dai format: %d\n", ret);
81        return ret;
82    }
83
84    ret = snd_soc_dai_set_sysclk(codec_dai, JZCODEC_SYSCLK, 111,
85        SND_SOC_CLOCK_IN);
86    if (ret < 0) {
87        dev_err(codec->dev, "Failed to set codec dai sysclk: %d\n", ret);
88        return ret;
89    }
90
91    snd_soc_dapm_new_controls(codec, qi_lb60_widgets, ARRAY_SIZE(qi_lb60_widgets));
92
93    snd_soc_dapm_add_routes(codec, qi_lb60_routes, ARRAY_SIZE(qi_lb60_routes));
94
95    snd_soc_dapm_sync(codec);
96
97    return 0;
98}
99
100static struct snd_soc_dai_link qi_lb60_dai = {
101    .name = "jz-codec",
102    .stream_name = "JZCODEC",
103    .cpu_dai = &jz4740_i2s_dai,
104    .codec_dai = &jz_codec_dai,
105    .init = qi_lb60_codec_init,
106};
107
108static struct snd_soc_card qi_lb60 = {
109    .name = "QI LB60",
110    .dai_link = &qi_lb60_dai,
111    .num_links = 1,
112    .platform = &jz4740_soc_platform,
113};
114
115static struct snd_soc_device qi_lb60_snd_devdata = {
116    .card = &qi_lb60,
117    .codec_dev = &soc_codec_dev_jzcodec,
118};
119
120static struct platform_device *qi_lb60_snd_device;
121
122static int __init qi_lb60_init(void)
123{
124    int ret;
125
126    qi_lb60_snd_device = platform_device_alloc("soc-audio", -1);
127
128    if (!qi_lb60_snd_device)
129        return -ENOMEM;
130
131
132    ret = gpio_request(QI_LB60_SND_GPIO, "SND");
133    if (ret) {
134        pr_err("qi_lb60 snd: Failed to request SND GPIO(%d): %d\n",
135                QI_LB60_SND_GPIO, ret);
136        goto err_device_put;
137    }
138
139    ret = gpio_request(QI_LB60_AMP_GPIO, "AMP");
140    if (ret) {
141        pr_err("qi_lb60 snd: Failed to request AMP GPIO(%d): %d\n",
142                QI_LB60_AMP_GPIO, ret);
143        goto err_gpio_free_snd;
144    }
145
146    gpio_direction_output(JZ_GPIO_PORTB(29), 0);
147    gpio_direction_output(JZ_GPIO_PORTD(4), 0);
148
149    platform_set_drvdata(qi_lb60_snd_device, &qi_lb60_snd_devdata);
150    qi_lb60_snd_devdata.dev = &qi_lb60_snd_device->dev;
151    ret = platform_device_add(qi_lb60_snd_device);
152    if (ret) {
153        pr_err("qi_lb60 snd: Failed to add snd soc device: %d\n", ret);
154        goto err_unset_pdata;
155    }
156
157     return 0;
158
159err_unset_pdata:
160    platform_set_drvdata(qi_lb60_snd_device, NULL);
161/*err_gpio_free_amp:*/
162    gpio_free(QI_LB60_AMP_GPIO);
163err_gpio_free_snd:
164    gpio_free(QI_LB60_SND_GPIO);
165err_device_put:
166    platform_device_put(qi_lb60_snd_device);
167
168    return ret;
169}
170module_init(qi_lb60_init);
171
172static void __exit qi_lb60_exit(void)
173{
174    gpio_free(QI_LB60_AMP_GPIO);
175    gpio_free(QI_LB60_SND_GPIO);
176    platform_device_unregister(qi_lb60_snd_device);
177}
178module_exit(qi_lb60_exit);
179
180MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
181MODULE_DESCRIPTION("ALSA SoC QI LB60 Audio support");
182MODULE_LICENSE("GPL v2");

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