Date:2009-12-01 07:54:55 (11 years 1 month ago)
Author:xiangfu
Commit:ef60fc3200a68f7ebd2a5a9fff585073f233bb5e
Message:file
Files: arch/mips/boot/compressed/Makefile (1 diff)
arch/mips/boot/compressed/dummy.c (1 diff)
arch/mips/boot/compressed/head.S (1 diff)
arch/mips/boot/compressed/ld.script (1 diff)
arch/mips/boot/compressed/misc.c (1 diff)
arch/mips/boot/tools/entry (1 diff)
arch/mips/boot/tools/filesize (1 diff)
arch/mips/include/asm/mach-jz4740/board-qi_lb60.h (1 diff)
arch/mips/include/asm/mach-jz4740/clock.h (1 diff)
arch/mips/include/asm/mach-jz4740/dma.h (1 diff)
arch/mips/include/asm/mach-jz4740/gpio.h (1 diff)
arch/mips/include/asm/mach-jz4740/irq.h (1 diff)
arch/mips/include/asm/mach-jz4740/jz4740.h (1 diff)
arch/mips/include/asm/mach-jz4740/ops.h (1 diff)
arch/mips/include/asm/mach-jz4740/platform.h (1 diff)
arch/mips/include/asm/mach-jz4740/regs.h (1 diff)
arch/mips/include/asm/mach-jz4740/serial.h (1 diff)
arch/mips/include/asm/mach-jz4740/war.h (1 diff)
arch/mips/jz4740/Kconfig (1 diff)
arch/mips/jz4740/Makefile (1 diff)
arch/mips/jz4740/board-qi_lb60.c (1 diff)
arch/mips/jz4740/clock.c (1 diff)
arch/mips/jz4740/cpufreq.c (1 diff)
arch/mips/jz4740/dma.c (1 diff)
arch/mips/jz4740/gpio.c (1 diff)
arch/mips/jz4740/irq.c (1 diff)
arch/mips/jz4740/platform.c (1 diff)
arch/mips/jz4740/pm.c (1 diff)
arch/mips/jz4740/proc.c (1 diff)
arch/mips/jz4740/prom.c (1 diff)
arch/mips/jz4740/reset.c (1 diff)
arch/mips/jz4740/setup.c (1 diff)
arch/mips/jz4740/time.c (1 diff)
drivers/misc/jz4740-adc.c (1 diff)
drivers/mmc/host/jz_mmc.c (1 diff)
drivers/mtd/nand/jz4740_nand.c (1 diff)
drivers/power/jz4740-battery.c (1 diff)
drivers/rtc/rtc-jz4740.c (1 diff)
drivers/usb/gadget/jz4740_udc.c (1 diff)
drivers/usb/gadget/jz4740_udc.h (1 diff)
drivers/usb/gadget/udc_hotplug.h (1 diff)
drivers/usb/gadget/udc_hotplug_core.c (1 diff)
drivers/video/backlight/gpm940b0.c (1 diff)
drivers/video/jz4740_fb.c (1 diff)
include/linux/jz4740-adc.h (1 diff)
include/linux/jz4740_fb.h (1 diff)
include/linux/mmc/jz4740_mmc.h (1 diff)
include/linux/mtd/jz4740_nand.h (1 diff)
include/linux/power/jz4740-battery.h (1 diff)
sound/soc/codecs/jzcodec.c (1 diff)
sound/soc/codecs/jzcodec.h (1 diff)
sound/soc/jz4740/Kconfig (1 diff)
sound/soc/jz4740/Makefile (1 diff)
sound/soc/jz4740/jz4740-i2s.c (1 diff)
sound/soc/jz4740/jz4740-i2s.h (1 diff)
sound/soc/jz4740/jz4740-pcm.c (1 diff)
sound/soc/jz4740/jz4740-pcm.h (1 diff)
sound/soc/jz4740/qi_lb60.c (1 diff)

Change Details

arch/mips/boot/compressed/Makefile
1#
2# linux/arch/mips/boot/compressed/Makefile
3#
4# create a compressed zImage from the original vmlinux
5#
6
7targets := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o
8
9OBJS := $(obj)/head.o $(obj)/misc.o
10
11LD_ARGS := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic
12OBJCOPY_ARGS := -O elf32-tradlittlemips
13
14ENTRY := $(obj)/../tools/entry
15FILESIZE := $(obj)/../tools/filesize
16
17drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
18strip-flags = $(addprefix --remove-section=,$(drop-sections))
19
20
21$(obj)/vmlinux.bin.gz: vmlinux
22    rm -f $(obj)/vmlinux.bin.gz
23    $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin
24    gzip -v9f $(obj)/vmlinux.bin
25
26$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux
27    $(CC) $(KBUILD_AFLAGS) \
28    -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \
29    -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \
30    -DLOADADDR=$(loadaddr) \
31    -c -o $(obj)/head.o $<
32
33$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o
34    $(OBJCOPY) \
35        --add-section=.image=$(obj)/vmlinux.bin.gz \
36        --set-section-flags=.image=contents,alloc,load,readonly,data \
37        $(obj)/dummy.o $(obj)/piggy.o
38    $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o
39    $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap
40
41zImage: $(obj)/vmlinuz
42    $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage
arch/mips/boot/compressed/dummy.c
1int main(void)
2{
3    return 0;
4}
arch/mips/boot/compressed/head.S
1/*
2 * linux/arch/mips/boot/compressed/head.S
3 *
4 * Copyright (C) 2005-2008 Ingenic Semiconductor Inc.
5 */
6
7#include <asm/asm.h>
8#include <asm/cacheops.h>
9#include <asm/cachectl.h>
10#include <asm/regdef.h>
11
12#define IndexInvalidate_I 0x00
13#define IndexWriteBack_D 0x01
14
15    .set noreorder
16    LEAF(startup)
17startup:
18    move s0, a0 /* Save the boot loader transfered args */
19    move s1, a1
20    move s2, a2
21    move s3, a3
22
23    la a0, _edata
24    la a1, _end
251: sw zero, 0(a0) /* Clear BSS section */
26    bne a1, a0, 1b
27    addu a0, 4
28
29    la sp, (.stack + 8192)
30
31    la a0, __image_begin
32    la a1, IMAGESIZE
33    la a2, LOADADDR
34    la ra, 1f
35    la k0, decompress_kernel
36    jr k0
37    nop
381:
39
40    move a0, s0
41    move a1, s1
42    move a2, s2
43    move a3, s3
44    li k0, KERNEL_ENTRY
45    jr k0
46    nop
472:
48    b 32
49    END(startup)
50
51
52    LEAF(flushcaches)
53    la t0, 1f
54    la t1, 0xa0000000
55    or t0, t0, t1
56    jr t0
57    nop
581:
59    li k0, 0x80000000 # start address
60    li k1, 0x80004000 # end address (16KB I-Cache)
61    subu k1, 128
62
632:
64    .set mips3
65    cache IndexWriteBack_D, 0(k0)
66    cache IndexWriteBack_D, 32(k0)
67    cache IndexWriteBack_D, 64(k0)
68    cache IndexWriteBack_D, 96(k0)
69    cache IndexInvalidate_I, 0(k0)
70    cache IndexInvalidate_I, 32(k0)
71    cache IndexInvalidate_I, 64(k0)
72    cache IndexInvalidate_I, 96(k0)
73    .set mips0
74
75    bne k0, k1, 2b
76    addu k0, k0, 128
77    la t0, 3f
78    jr t0
79    nop
803:
81    jr ra
82    nop
83    END(flushcaches)
84
85    .comm .stack,4096*2,4
arch/mips/boot/compressed/ld.script
1OUTPUT_ARCH(mips)
2ENTRY(startup)
3SECTIONS
4{
5  /* Read-only sections, merged into text segment: */
6
7  .init : { *(.init) } =0
8  .text :
9  {
10    _ftext = . ;
11    *(.text)
12    *(.rodata)
13    *(.rodata1)
14    /* .gnu.warning sections are handled specially by elf32.em. */
15    *(.gnu.warning)
16  } =0
17  .kstrtab : { *(.kstrtab) }
18
19  . = ALIGN(16); /* Exception table */
20  __start___ex_table = .;
21  __ex_table : { *(__ex_table) }
22  __stop___ex_table = .;
23
24  __start___dbe_table = .; /* Exception table for data bus errors */
25  __dbe_table : { *(__dbe_table) }
26  __stop___dbe_table = .;
27
28  __start___ksymtab = .; /* Kernel symbol table */
29  __ksymtab : { *(__ksymtab) }
30  __stop___ksymtab = .;
31
32  _etext = .;
33
34  . = ALIGN(8192);
35  .data.init_task : { *(.data.init_task) }
36
37  /* Startup code */
38  . = ALIGN(4096);
39  __init_begin = .;
40  .text.init : { *(.text.init) }
41  .data.init : { *(.data.init) }
42  . = ALIGN(16);
43  __setup_start = .;
44  .setup.init : { *(.setup.init) }
45  __setup_end = .;
46  __initcall_start = .;
47  .initcall.init : { *(.initcall.init) }
48  __initcall_end = .;
49  . = ALIGN(4096); /* Align double page for init_task_union */
50  __init_end = .;
51
52  . = ALIGN(4096);
53  .data.page_aligned : { *(.data.idt) }
54
55  . = ALIGN(32);
56  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
57
58  .fini : { *(.fini) } =0
59  .reginfo : { *(.reginfo) }
60  /* Adjust the address for the data segment. We want to adjust up to
61     the same address within the page on the next page up. It would
62     be more correct to do this:
63       . = .;
64     The current expression does not correctly handle the case of a
65     text segment ending precisely at the end of a page; it causes the
66     data segment to skip a page. The above expression does not have
67     this problem, but it will currently (2/95) cause BFD to allocate
68     a single segment, combining both text and data, for this case.
69     This will prevent the text segment from being shared among
70     multiple executions of the program; I think that is more
71     important than losing a page of the virtual address space (note
72     that no actual memory is lost; the page which is skipped can not
73     be referenced). */
74  . = .;
75  .data :
76  {
77    _fdata = . ;
78    *(.data)
79
80   /* Put the compressed image here, so bss is on the end. */
81   __image_begin = .;
82   *(.image)
83   __image_end = .;
84   /* Align the initial ramdisk image (INITRD) on page boundaries. */
85   . = ALIGN(4096);
86   __ramdisk_begin = .;
87   *(.initrd)
88   __ramdisk_end = .;
89   . = ALIGN(4096);
90
91    CONSTRUCTORS
92  }
93  .data1 : { *(.data1) }
94  _gp = . + 0x8000;
95  .lit8 : { *(.lit8) }
96  .lit4 : { *(.lit4) }
97  .ctors : { *(.ctors) }
98  .dtors : { *(.dtors) }
99  .got : { *(.got.plt) *(.got) }
100  .dynamic : { *(.dynamic) }
101  /* We want the small data sections together, so single-instruction offsets
102     can access them all, and initialized data all before uninitialized, so
103     we can shorten the on-disk segment size. */
104  .sdata : { *(.sdata) }
105  . = ALIGN(4);
106  _edata = .;
107  PROVIDE (edata = .);
108
109  __bss_start = .;
110  _fbss = .;
111  .sbss : { *(.sbss) *(.scommon) }
112  .bss :
113  {
114   *(.dynbss)
115   *(.bss)
116   *(COMMON)
117   . = ALIGN(4);
118  _end = . ;
119  PROVIDE (end = .);
120  }
121
122  /* Sections to be discarded */
123  /DISCARD/ :
124  {
125        *(.text.exit)
126        *(.data.exit)
127        *(.exitcall.exit)
128  }
129
130  /* This is the MIPS specific mdebug section. */
131  .mdebug : { *(.mdebug) }
132  /* These are needed for ELF backends which have not yet been
133     converted to the new style linker. */
134  .stab 0 : { *(.stab) }
135  .stabstr 0 : { *(.stabstr) }
136  /* DWARF debug sections.
137     Symbols in the .debug DWARF section are relative to the beginning of the
138     section so we begin .debug at 0. It's not clear yet what needs to happen
139     for the others. */
140  .debug 0 : { *(.debug) }
141  .debug_srcinfo 0 : { *(.debug_srcinfo) }
142  .debug_aranges 0 : { *(.debug_aranges) }
143  .debug_pubnames 0 : { *(.debug_pubnames) }
144  .debug_sfnames 0 : { *(.debug_sfnames) }
145  .line 0 : { *(.line) }
146  /* These must appear regardless of . */
147  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
148  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
149  .comment : { *(.comment) }
150  .note : { *(.note) }
151}
arch/mips/boot/compressed/misc.c
1/*
2 * linux/arch/mips/boot/compressed/misc.c
3 *
4 * This is a collection of several routines from gzip-1.0.3
5 * adapted for Linux.
6 *
7 * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
8 *
9 * Adapted for JZSOC by Peter Wei, 2008
10 *
11 */
12
13#define size_t int
14#define NULL 0
15
16/*
17 * gzip declarations
18 */
19
20#define OF(args) args
21#define STATIC static
22
23#undef memset
24#undef memcpy
25#define memzero(s, n) memset ((s), 0, (n))
26
27typedef unsigned char uch;
28typedef unsigned short ush;
29typedef unsigned long ulg;
30
31#define WSIZE 0x8000 /* Window size must be at least 32k, */
32                /* and a power of two */
33
34static uch *inbuf; /* input buffer */
35static uch window[WSIZE]; /* Sliding window buffer */
36
37static unsigned insize = 0; /* valid bytes in inbuf */
38static unsigned inptr = 0; /* index of next byte to be processed in inbuf */
39static unsigned outcnt = 0; /* bytes in output buffer */
40
41/* gzip flag byte */
42#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
43#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
44#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
45#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
46#define COMMENT 0x10 /* bit 4 set: file comment present */
47#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
48#define RESERVED 0xC0 /* bit 6,7: reserved */
49
50#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
51
52/* Diagnostic functions */
53#ifdef DEBUG
54# define Assert(cond,msg) {if(!(cond)) error(msg);}
55# define Trace(x) fprintf x
56# define Tracev(x) {if (verbose) fprintf x ;}
57# define Tracevv(x) {if (verbose>1) fprintf x ;}
58# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
59# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
60#else
61# define Assert(cond,msg)
62# define Trace(x)
63# define Tracev(x)
64# define Tracevv(x)
65# define Tracec(c,x)
66# define Tracecv(c,x)
67#endif
68
69static int fill_inbuf(void);
70static void flush_window(void);
71static void error(char *m);
72static void gzip_mark(void **);
73static void gzip_release(void **);
74
75void* memset(void* s, int c, size_t n);
76void* memcpy(void* __dest, __const void* __src, size_t __n);
77
78extern void flushcaches(void); /* defined in head.S */
79
80char *input_data;
81int input_len;
82
83static long bytes_out = 0;
84static uch *output_data;
85static unsigned long output_ptr = 0;
86
87
88static void *malloc(int size);
89static void free(void *where);
90static void error(char *m);
91static void gzip_mark(void **);
92static void gzip_release(void **);
93
94static void puts(const char *str)
95{
96}
97
98extern unsigned char _end[];
99static unsigned long free_mem_ptr;
100static unsigned long free_mem_end_ptr;
101
102#define HEAP_SIZE 0x10000
103
104#include "../../../../lib/inflate.c"
105
106static void *malloc(int size)
107{
108    void *p;
109
110    if (size <0) error("Malloc error\n");
111    if (free_mem_ptr == 0) error("Memory error\n");
112
113    free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */
114
115    p = (void *)free_mem_ptr;
116    free_mem_ptr += size;
117
118    if (free_mem_ptr >= free_mem_end_ptr)
119        error("\nOut of memory\n");
120
121    return p;
122}
123
124static void free(void *where)
125{ /* Don't care */
126}
127
128static void gzip_mark(void **ptr)
129{
130    *ptr = (void *) free_mem_ptr;
131}
132
133static void gzip_release(void **ptr)
134{
135    free_mem_ptr = (long) *ptr;
136}
137
138void* memset(void* s, int c, size_t n)
139{
140    int i;
141    char *ss = (char*)s;
142
143    for (i=0;i<n;i++) ss[i] = c;
144    return s;
145}
146
147void* memcpy(void* __dest, __const void* __src, size_t __n)
148{
149    int i = 0;
150    unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
151
152    for (i = __n >> 3; i > 0; i--) {
153        *d++ = *s++;
154        *d++ = *s++;
155        *d++ = *s++;
156        *d++ = *s++;
157        *d++ = *s++;
158        *d++ = *s++;
159        *d++ = *s++;
160        *d++ = *s++;
161    }
162
163    if (__n & 1 << 2) {
164        *d++ = *s++;
165        *d++ = *s++;
166        *d++ = *s++;
167        *d++ = *s++;
168    }
169
170    if (__n & 1 << 1) {
171        *d++ = *s++;
172        *d++ = *s++;
173    }
174
175    if (__n & 1)
176        *d++ = *s++;
177
178    return __dest;
179}
180
181/* ===========================================================================
182 * Fill the input buffer. This is called only when the buffer is empty
183 * and at least one byte is really needed.
184 */
185static int fill_inbuf(void)
186{
187    if (insize != 0) {
188        error("ran out of input data\n");
189    }
190
191    inbuf = input_data;
192    insize = input_len;
193    inptr = 1;
194    return inbuf[0];
195}
196
197/* ===========================================================================
198 * Write the output window window[0..outcnt-1] and update crc and bytes_out.
199 * (Used for the decompressed data only.)
200 */
201static void flush_window(void)
202{
203    ulg c = crc; /* temporary variable */
204    unsigned n;
205    uch *in, *out, ch;
206
207    in = window;
208    out = &output_data[output_ptr];
209    for (n = 0; n < outcnt; n++) {
210        ch = *out++ = *in++;
211        c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
212    }
213    crc = c;
214    bytes_out += (ulg)outcnt;
215    output_ptr += (ulg)outcnt;
216    outcnt = 0;
217}
218
219static void error(char *x)
220{
221    puts("\n\n");
222    puts(x);
223    puts("\n\n -- System halted");
224
225    while(1); /* Halt */
226}
227
228void decompress_kernel(unsigned int imageaddr, unsigned int imagesize, unsigned int loadaddr)
229{
230    input_data = (char *)imageaddr;
231    input_len = imagesize;
232    output_ptr = 0;
233    output_data = (uch *)loadaddr;
234    free_mem_ptr = (unsigned long)_end;
235    free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
236
237    makecrc();
238    puts("Uncompressing Linux...");
239    gunzip();
240    flushcaches();
241    puts("Ok, booting the kernel.");
242}
arch/mips/boot/tools/entry
1#!/bin/sh
2
3# grab the kernel_entry address from the vmlinux elf image
4entry=`$1 $2 | grep kernel_entry`
5
6fs=`echo $entry | grep ffffffff` # check toolchain output
7
8if [ -n "$fs" ]; then
9    echo "0x"`$1 $2 | grep kernel_entry | cut -c9- | awk '{print $1}'`
10else
11    echo "0x"`$1 $2 | grep kernel_entry | cut -c1- | awk '{print $1}'`
12fi
arch/mips/boot/tools/filesize
1#!/bin/sh
2HOSTNAME=`uname`
3if [ "$HOSTNAME" = "Linux" ]; then
4echo `ls -l $1 | awk '{print $5}'`
5else
6echo `ls -l $1 | awk '{print $6}'`
7fi
arch/mips/include/asm/mach-jz4740/board-qi_lb60.h
1/*
2 * Copyright (c) 2009 Qi Hardware Inc.,
3 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
4 *
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __ASM_JZ4740_QI_LB60_H__
20#define __ASM_JZ4740_QI_LB60_H__
21
22#include <linux/gpio.h>
23/*
24 * Frequencies of on-board oscillators
25 */
26#define JZ_EXTAL 12000000 /* Main extal freq: 12 MHz */
27#define JZ_EXTAL_RTC 32768 /* RTC extal freq: 32.768 KHz */
28
29/*
30 * GPIO
31 */
32#define GPIO_DC_DETE_N JZ_GPIO_PORTC(26)
33#define GPIO_CHARG_STAT_N JZ_GPIO_PORTC(27)
34#define GPIO_LED_EN JZ_GPIO_PORTC(28)
35#define GPIO_LCD_CS JZ_GPIO_PORTC(21)
36#define GPIO_DISP_OFF_N JZ_GPIO_PORTD(21)
37#define GPIO_PWM JZ_GPIO_PORTD(27)
38#define GPIO_WAKEUP_N JZ_GPIO_PORTD(29)
39
40#define GPIO_AMP_EN JZ_GPIO_PORTD(4)
41
42#define GPIO_SD_CD_N JZ_GPIO_PORTD(0)
43#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2)
44#define GPIO_SD_WP JZ_GPIO_PORTD(16)
45
46#define GPIO_USB_DETE JZ_GPIO_PORTD(28)
47#define GPIO_BUZZ_PWM JZ_GPIO_PORTD(27)
48#define GPIO_UDC_HOTPLUG GPIO_USB_DETE
49
50#define GPIO_AUDIO_POP JZ_GPIO_PORTB(29)
51#define GPIO_COB_TEST JZ_GPIO_PORTB(30)
52
53#define GPIO_KEYOUT_BASE JZ_GPIO_PORTC(10)
54#define GPIO_KEYIN_BASE JZ_GPIO_PORTD(18)
55#define GPIO_KEYIN_8 JZ_GPIO_PORTD(26)
56
57/*
58 * MMC/SD
59 */
60#define MSC_WP_PIN GPIO_SD_WP
61#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
62#define MSC_HOTPLUG_IRQ (JZ_IRQ_GPIO(GPIO_SD_CD_N))
63
64#define __msc_init_io() \
65do { \
66    __gpio_as_output(GPIO_SD_VCC_EN_N); \
67    __gpio_as_input(GPIO_SD_CD_N); \
68} while (0)
69
70#define __msc_enable_power() \
71do { \
72    __gpio_clear_pin(GPIO_SD_VCC_EN_N); \
73} while (0)
74
75#define __msc_disable_power() \
76do { \
77    __gpio_set_pin(GPIO_SD_VCC_EN_N); \
78} while (0)
79
80#define __msc_card_detected(s) \
81({ \
82    int detected = 1; \
83    if (!__gpio_get_pin(GPIO_SD_CD_N)) \
84        detected = 0; \
85    detected; \
86})
87
88#endif /* __ASM_JZ4740_QI_LB60_H__ */
arch/mips/include/asm/mach-jz4740/clock.h
1/*
2 * linux/include/asm-mips/mach-jz4740/clock.h
3 *
4 * JZ4740 clocks definition.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <lhhuang@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_JZ4740_CLOCK_H__
16#define __ASM_JZ4740_CLOCK_H__
17
18#include <asm/mach-jz4740/ops.h>
19
20#ifndef JZ_EXTAL
21//#define JZ_EXTAL 3686400 /* 3.6864 MHz */
22#define JZ_EXTAL 12000000 /* 3.6864 MHz */
23#endif
24#ifndef JZ_EXTAL2
25#define JZ_EXTAL2 32768 /* 32.768 KHz */
26#endif
27
28/*
29 * JZ4740 clocks structure
30 */
31typedef struct {
32    unsigned int cclk; /* CPU clock */
33    unsigned int hclk; /* System bus clock */
34    unsigned int pclk; /* Peripheral bus clock */
35    unsigned int mclk; /* Flash/SRAM/SDRAM clock */
36    unsigned int lcdclk; /* LCDC module clock */
37    unsigned int pixclk; /* LCD pixel clock */
38    unsigned int i2sclk; /* AIC module clock */
39    unsigned int usbclk; /* USB module clock */
40    unsigned int mscclk; /* MSC module clock */
41    unsigned int extalclk; /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
42    unsigned int rtcclk; /* RTC clock for CPM,INTC,RTC,TCU,WDT */
43} jz_clocks_t;
44
45extern jz_clocks_t jz_clocks;
46
47
48/* PLL output frequency */
49static __inline__ unsigned int __cpm_get_pllout(void)
50{
51    unsigned long m, n, no, pllout;
52    unsigned long cppcr = REG_CPM_CPPCR;
53    unsigned long od[4] = {1, 2, 2, 4};
54    if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
55        m = __cpm_get_pllm() + 2;
56        n = __cpm_get_plln() + 2;
57        no = od[__cpm_get_pllod()];
58        pllout = ((JZ_EXTAL) / (n * no)) * m;
59    } else
60        pllout = JZ_EXTAL;
61    return pllout;
62}
63
64/* PLL output frequency for MSC/I2S/LCD/USB */
65static __inline__ unsigned int __cpm_get_pllout2(void)
66{
67    if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
68        return __cpm_get_pllout();
69    else
70        return __cpm_get_pllout()/2;
71}
72
73/* CPU core clock */
74static __inline__ unsigned int __cpm_get_cclk(void)
75{
76    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
77
78    return __cpm_get_pllout() / div[__cpm_get_cdiv()];
79}
80
81/* AHB system bus clock */
82static __inline__ unsigned int __cpm_get_hclk(void)
83{
84    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
85
86    return __cpm_get_pllout() / div[__cpm_get_hdiv()];
87}
88
89/* Memory bus clock */
90static __inline__ unsigned int __cpm_get_mclk(void)
91{
92    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
93
94    return __cpm_get_pllout() / div[__cpm_get_mdiv()];
95}
96
97/* APB peripheral bus clock */
98static __inline__ unsigned int __cpm_get_pclk(void)
99{
100    int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
101
102    return __cpm_get_pllout() / div[__cpm_get_pdiv()];
103}
104
105/* LCDC module clock */
106static __inline__ unsigned int __cpm_get_lcdclk(void)
107{
108    return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
109}
110
111/* LCD pixel clock */
112static __inline__ unsigned int __cpm_get_pixclk(void)
113{
114    return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
115}
116
117/* I2S clock */
118static __inline__ unsigned int __cpm_get_i2sclk(void)
119{
120    if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
121        return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
122    }
123    else {
124        return JZ_EXTAL;
125    }
126}
127
128/* USB clock */
129static __inline__ unsigned int __cpm_get_usbclk(void)
130{
131    if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
132        return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
133    }
134    else {
135        return JZ_EXTAL;
136    }
137}
138
139/* MSC clock */
140static __inline__ unsigned int __cpm_get_mscclk(void)
141{
142    return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
143}
144
145/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
146static __inline__ unsigned int __cpm_get_extalclk(void)
147{
148    return JZ_EXTAL;
149}
150
151/* RTC clock for CPM,INTC,RTC,TCU,WDT */
152static __inline__ unsigned int __cpm_get_rtcclk(void)
153{
154    return JZ_EXTAL2;
155}
156
157/*
158 * Output 24MHz for SD and 16MHz for MMC.
159 */
160static inline void __cpm_select_msc_clk(int sd)
161{
162    unsigned int pllout2 = __cpm_get_pllout2();
163    unsigned int div = 0;
164
165    if (sd) {
166        div = pllout2 / 24000000;
167    }
168    else {
169        div = pllout2 / 16000000;
170    }
171
172    REG_CPM_MSCCDR = div - 1;
173}
174
175int jz_init_clocks(unsigned long ext_rate);
176
177#endif /* __ASM_JZ4740_CLOCK_H__ */
arch/mips/include/asm/mach-jz4740/dma.h
1/*
2 * linux/include/asm-mips/mach-jz4740/dma.h
3 *
4 * JZ4740 DMA definition.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <lhhuang@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_JZ4740_DMA_H__
16#define __ASM_JZ4740_DMA_H__
17
18#include <linux/interrupt.h>
19#include <asm/io.h> /* need byte IO */
20#include <linux/spinlock.h> /* And spinlocks */
21#include <linux/delay.h>
22#include <asm/mach-jz4740/regs.h>
23#include <asm/mach-jz4740/ops.h>
24
25/*
26 * Descriptor structure for JZ4740 DMA engine
27 * Note: this structure must always be aligned to a 16-bytes boundary.
28 */
29
30typedef struct {
31    volatile u32 dcmd; /* DCMD value for the current transfer */
32    volatile u32 dsadr; /* DSAR value for the current transfer */
33    volatile u32 dtadr; /* DTAR value for the current transfer */
34    volatile u32 ddadr; /* Points to the next descriptor + transfer count */
35} jz_dma_desc;
36
37
38/* DMA Device ID's follow */
39enum {
40    DMA_ID_UART0_TX = 0,
41    DMA_ID_UART0_RX,
42    DMA_ID_SSI_TX,
43    DMA_ID_SSI_RX,
44    DMA_ID_AIC_TX,
45    DMA_ID_AIC_RX,
46    DMA_ID_MSC_TX,
47    DMA_ID_MSC_RX,
48    DMA_ID_TCU_OVERFLOW,
49    DMA_ID_AUTO,
50    DMA_ID_RAW_SET,
51    DMA_ID_MAX
52};
53
54/* DMA modes, simulated by sw */
55#define DMA_MODE_READ 0x0 /* I/O to memory, no autoinit, increment, single mode */
56#define DMA_MODE_WRITE 0x1 /* memory to I/O, no autoinit, increment, single mode */
57#define DMA_AUTOINIT 0x2
58#define DMA_MODE_MASK 0x3
59
60struct jz_dma_chan {
61    int dev_id; /* DMA ID: this channel is allocated if >=0, free otherwise */
62    unsigned int io; /* DMA channel number */
63    const char *dev_str; /* string describes the DMA channel */
64    int irq; /* DMA irq number */
65    void *irq_dev; /* DMA private device structure */
66    unsigned int fifo_addr; /* physical fifo address of the requested device */
67    unsigned int cntl; /* DMA controll */
68    unsigned int mode; /* DMA configuration */
69    unsigned int source; /* DMA request source */
70};
71
72extern struct jz_dma_chan jz_dma_table[];
73
74
75#define DMA_8BIT_RX_CMD \
76    DMAC_DCMD_DAI | \
77    DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
78    DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
79
80#define DMA_8BIT_TX_CMD \
81    DMAC_DCMD_SAI | \
82    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
83    DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
84
85#define DMA_16BIT_RX_CMD \
86    DMAC_DCMD_DAI | \
87    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_32 | \
88    DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
89
90#define DMA_16BIT_TX_CMD \
91    DMAC_DCMD_SAI | \
92    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16 | \
93    DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
94
95#define DMA_32BIT_RX_CMD \
96    DMAC_DCMD_DAI | \
97    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
98    DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
99
100#define DMA_32BIT_TX_CMD \
101    DMAC_DCMD_SAI | \
102    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
103    DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
104
105#define DMA_16BYTE_RX_CMD \
106    DMAC_DCMD_DAI | \
107    DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
108    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
109
110#define DMA_16BYTE_TX_CMD \
111    DMAC_DCMD_SAI | \
112    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
113    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
114
115#define DMA_32BYTE_RX_CMD \
116    DMAC_DCMD_DAI | \
117    DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
118    DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
119
120#define DMA_32BYTE_TX_CMD \
121    DMAC_DCMD_SAI | \
122    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
123    DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
124
125#define DMA_AIC_32_16BYTE_TX_CMD \
126    DMAC_DCMD_SAI | \
127    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
128    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
129
130#define DMA_AIC_32_16BYTE_RX_CMD \
131    DMAC_DCMD_DAI | \
132    DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
133    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
134
135#define DMA_AIC_16BIT_TX_CMD \
136    DMAC_DCMD_SAI | \
137    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
138    DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
139
140#define DMA_AIC_16BIT_RX_CMD \
141    DMAC_DCMD_DAI | \
142    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
143    DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
144
145#define DMA_AIC_16BYTE_RX_CMD \
146    DMAC_DCMD_DAI | \
147    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
148    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
149
150#define DMA_AIC_16BYTE_TX_CMD \
151    DMAC_DCMD_SAI | \
152    DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
153    DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
154
155extern int jz_request_dma(int dev_id,
156              const char *dev_str,
157              irqreturn_t (*irqhandler)(int, void *),
158              unsigned long irqflags,
159              void *irq_dev_id);
160extern void jz_free_dma(unsigned int dmanr);
161
162extern int jz_dma_read_proc(char *buf, char **start, off_t fpos,
163                  int length, int *eof, void *data);
164extern void dump_jz_dma_channel(unsigned int dmanr);
165
166extern void enable_dma(unsigned int dmanr);
167extern void disable_dma(unsigned int dmanr);
168extern void set_dma_addr(unsigned int dmanr, unsigned int phyaddr);
169extern void set_dma_count(unsigned int dmanr, unsigned int bytecnt);
170extern void set_dma_mode(unsigned int dmanr, unsigned int mode);
171extern void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
172extern unsigned int get_dma_residue(unsigned int dmanr);
173
174extern spinlock_t dma_spin_lock;
175
176static __inline__ unsigned long claim_dma_lock(void)
177{
178    unsigned long flags;
179    spin_lock_irqsave(&dma_spin_lock, flags);
180    return flags;
181}
182
183static __inline__ void release_dma_lock(unsigned long flags)
184{
185    spin_unlock_irqrestore(&dma_spin_lock, flags);
186}
187
188/* Clear the 'DMA Pointer Flip Flop'.
189 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
190 */
191#define clear_dma_ff(channel)
192
193static __inline__ struct jz_dma_chan *get_dma_chan(unsigned int dmanr)
194{
195    if (dmanr > MAX_DMA_NUM
196        || jz_dma_table[dmanr].dev_id < 0)
197        return NULL;
198    return &jz_dma_table[dmanr];
199}
200
201static __inline__ int dma_halted(unsigned int dmanr)
202{
203    struct jz_dma_chan *chan = get_dma_chan(dmanr);
204    if (!chan)
205        return 1;
206    return __dmac_channel_transmit_halt_detected(dmanr) ? 1 : 0;
207}
208
209static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
210{
211    struct jz_dma_chan *chan = get_dma_chan(dmanr);
212    if (!chan)
213        return 0;
214    return chan->mode;
215}
216
217static __inline__ void clear_dma_done(unsigned int dmanr)
218{
219    struct jz_dma_chan *chan = get_dma_chan(dmanr);
220    if (!chan)
221        return;
222    REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
223}
224
225static __inline__ void clear_dma_halt(unsigned int dmanr)
226{
227    struct jz_dma_chan *chan = get_dma_chan(dmanr);
228    if (!chan)
229        return;
230    REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT);
231    REG_DMAC_DMACR &= ~(DMAC_DMACR_HLT);
232}
233
234static __inline__ void clear_dma_flag(unsigned int dmanr)
235{
236    struct jz_dma_chan *chan = get_dma_chan(dmanr);
237    if (!chan)
238        return;
239    REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
240    REG_DMAC_DMACR &= ~(DMAC_DMACR_HLT | DMAC_DMACR_AR);
241}
242
243static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
244{
245}
246
247static __inline__ unsigned int get_dma_done_status(unsigned int dmanr)
248{
249    unsigned long dccsr;
250    struct jz_dma_chan *chan = get_dma_chan(dmanr);
251    if (!chan)
252        return 0;
253    dccsr = REG_DMAC_DCCSR(chan->io);
254    return dccsr & (DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
255}
256
257static __inline__ int get_dma_done_irq(unsigned int dmanr)
258{
259    struct jz_dma_chan *chan = get_dma_chan(dmanr);
260    if (!chan)
261        return -1;
262    return chan->irq;
263}
264
265#endif /* __ASM_JZ4740_DMA_H__ */
arch/mips/include/asm/mach-jz4740/gpio.h
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 GPIO pin definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef _JZ_GPIO_H
17#define _JZ_GPIO_H
18
19#include <linux/types.h>
20
21enum jz_gpio_function {
22    JZ_GPIO_FUNC_NONE,
23    JZ_GPIO_FUNC1,
24    JZ_GPIO_FUNC2,
25    JZ_GPIO_FUNC3,
26};
27
28
29/*
30 Usually a driver for a SoC component has to request several gpio pins and
31 configure them as funcion pins.
32 jz_gpio_bulk_request can be used to ease this process.
33 Usually one would do something like:
34
35 const static struct jz_gpio_bulk_request i2c_pins[] = {
36    JZ_GPIO_BULK_PIN(I2C_SDA),
37    JZ_GPIO_BULK_PIN(I2C_SCK),
38 };
39
40 inside the probe function:
41
42    ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
43    if (ret) {
44    ...
45
46 inside the remove function:
47
48    jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
49
50
51*/
52struct jz_gpio_bulk_request {
53    int gpio;
54    const char *name;
55    enum jz_gpio_function function;
56};
57
58#define JZ_GPIO_BULK_PIN(pin) { \
59    .gpio = JZ_GPIO_ ## pin, \
60    .name = #pin, \
61    .function = JZ_GPIO_FUNC_ ## pin \
62}
63
64int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
65void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
66void jz_gpio_enable_pullup(unsigned gpio);
67void jz_gpio_disable_pullup(unsigned gpio);
68int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
69
70#include <asm/mach-generic/gpio.h>
71
72#define JZ_GPIO_PORTA(x) (x + 32 * 0)
73#define JZ_GPIO_PORTB(x) (x + 32 * 1)
74#define JZ_GPIO_PORTC(x) (x + 32 * 2)
75#define JZ_GPIO_PORTD(x) (x + 32 * 3)
76
77/* Port A function pins */
78#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
79#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
80#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
81#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
82#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
83#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
84#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
85#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
86#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
87#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
88#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
89#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
90#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
91#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
92#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
93#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
94#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
95#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
96#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
97#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
98#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
99#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
100#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
101#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
102#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
103#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
104#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
105#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
106#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
107#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
108#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
109#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
110
111#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
112#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
113#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
114#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
115#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
116#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
117#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
118#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
119#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
120#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
121#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
122#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
123#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
124#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
125#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
126#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
127#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
128#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
129#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
130#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
131#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
132#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
133#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
134#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
135#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
136#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
137#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
138#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
139#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
140#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
141#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
142#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
143
144/* Port B function pins */
145#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
146#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
147#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
148#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
149#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
150#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
151#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
152#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
153#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
154#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
155#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
156#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
157#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
158#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
159#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
160#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
161#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
162#define JZ_GPIO_MEM_CLS JZ_GPIO_PORTB(17)
163#define JZ_GPIO_MEM_SPL JZ_GPIO_PORTB(18)
164#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
165#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
166#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
167#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
168#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
169#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
170#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
171#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
172#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
173#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
174#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
175#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
176#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
177
178#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
179#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
180#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
181#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
182#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
183#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
184#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
185#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
186#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
187#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
188#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
189#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
190#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
191#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
192#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
193#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
194#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
195#define JZ_GPIO_FUNC_MEM_CLS JZ_GPIO_FUNC1
196#define JZ_GPIO_FUNC_MEM_SPL JZ_GPIO_FUNC1
197#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
198#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
199#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
200#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
201#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
202#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
203#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
204#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
205#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
206#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
207#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
208#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
209#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
210
211
212#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
213#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
214
215#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
216#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
217
218/* Port C function pins */
219#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
220#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
221#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
222#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
223#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
224#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
225#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
226#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
227#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
228#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
229#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
230#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
231#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
232#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
233#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
234#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
235#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
236#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
237#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
238#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
239#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
240#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
241#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
242#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
243#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
244#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
245#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
246#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
247#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
248#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
249
250#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
251#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
252#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
253#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
254#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
255#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
256#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
257#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
258#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
259#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
260#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
261#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
262#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
263#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
264#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
265#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
266#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
267#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
268#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
269#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
270#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
271#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
272#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
273#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
274#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
275#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
276#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
277#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
278#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
279#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
280
281
282#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
283#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
284
285#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
286#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
287
288/* Port D function pins */
289#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
290#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
291#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
292#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
293#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
294#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
295#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
296#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
297#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
298#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
299#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
300#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
301#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
302#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
303#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
304#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
305#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
306#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
307#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
308#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
309#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
310#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
311#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
312#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
313#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
314#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
315#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
316#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
317#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
318#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
319#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
320
321#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC1
322#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC1
323#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC1
324#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC1
325#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC1
326#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC1
327#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC1
328#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC1
329#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
330#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
331#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC1
332#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC1
333#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC1
334#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC1
335#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
336#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
337#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
338#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
339#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
340#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
341#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
342#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
343#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
344#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC1
345#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC1
346#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC1
347#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC1
348#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC1
349#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC1
350#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC1
351
352#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
353#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
354#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
355#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
356#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
357#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
358#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
359#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
360#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
361#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
362#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
363#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
364#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
365
366#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
367#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
368#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
369#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
370#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
371#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
372#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
373#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
374#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
375#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
376#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
377#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
378#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
379
380#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
381#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
382
383#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
384#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
385
386#endif
arch/mips/include/asm/mach-jz4740/irq.h
1#ifndef __JZ4740_IRQ_H__
2#define __JZ4740_IRQ_H__
3
4#define MIPS_CPU_IRQ_BASE 0
5#define JZ_IRQ_BASE 8
6
7// 1st-level interrupts
8#define JZ_IRQ(x) (JZ_IRQ_BASE + (x))
9#define JZ_IRQ_I2C JZ_IRQ(1)
10#define JZ_IRQ_UHC JZ_IRQ(3)
11#define JZ_IRQ_UART1 JZ_IRQ(8)
12#define JZ_IRQ_UART0 JZ_IRQ(9)
13#define JZ_IRQ_SADC JZ_IRQ(12)
14#define JZ_IRQ_MSC JZ_IRQ(14)
15#define JZ_IRQ_RTC JZ_IRQ(15)
16#define JZ_IRQ_SSI JZ_IRQ(16)
17#define JZ_IRQ_CIM JZ_IRQ(17)
18#define JZ_IRQ_AIC JZ_IRQ(18)
19#define JZ_IRQ_ETH JZ_IRQ(19)
20#define JZ_IRQ_DMAC JZ_IRQ(20)
21#define JZ_IRQ_TCU2 JZ_IRQ(21)
22#define JZ_IRQ_TCU1 JZ_IRQ(22)
23#define JZ_IRQ_TCU0 JZ_IRQ(23)
24#define JZ_IRQ_UDC JZ_IRQ(24)
25#define JZ_IRQ_GPIO3 JZ_IRQ(25)
26#define JZ_IRQ_GPIO2 JZ_IRQ(26)
27#define JZ_IRQ_GPIO1 JZ_IRQ(27)
28#define JZ_IRQ_GPIO0 JZ_IRQ(28)
29#define JZ_IRQ_IPU JZ_IRQ(29)
30#define JZ_IRQ_LCD JZ_IRQ(30)
31
32/* 2nd-level interrupts */
33#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
34
35#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
36#define JZ_IRQ_GPIO(x) (JZ_IRQ(48) + (x))
37
38#define NR_IRQS (JZ_IRQ_GPIO(127) + 1)
39
40#endif
arch/mips/include/asm/mach-jz4740/jz4740.h
1/*
2 * linux/include/asm-mips/mach-jz4740/jz4740.h
3 *
4 * JZ4740 common definition.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <lhhuang@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_JZ4740_H__
16#define __ASM_JZ4740_H__
17
18#include <asm/mach-jz4740/regs.h>
19#include <asm/mach-jz4740/ops.h>
20#include <asm/mach-jz4740/dma.h>
21
22/*------------------------------------------------------------------
23 * Platform definitions
24 */
25
26#ifdef CONFIG_JZ4740_QI_LB60
27#include <asm/mach-jz4740/board-qi_lb60.h>
28#endif
29
30/* Add other platform definition here ... */
31
32
33/*------------------------------------------------------------------
34 * Follows are related to platform definitions
35 */
36
37#include <asm/mach-jz4740/clock.h>
38#include <asm/mach-jz4740/serial.h>
39
40#endif /* __ASM_JZ4740_H__ */
arch/mips/include/asm/mach-jz4740/ops.h
1/*
2 * linux/include/asm-mips/mach-jz4740/ops.h
3 *
4 * Ingenic's JZ4740 common include.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <yliu@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15
16#ifndef __JZ4740_OPS_H__
17#define __JZ4740_OPS_H__
18
19#include <asm/mach-jz4740/regs.h>
20
21/*
22 * Definition of Module Operations
23 */
24
25/***************************************************************************
26 * GPIO
27 ***************************************************************************/
28
29//------------------------------------------------------
30// GPIO Pins Description
31//
32// PORT 0:
33//
34// PIN/BIT N FUNC0 FUNC1
35// 0 D0 -
36// 1 D1 -
37// 2 D2 -
38// 3 D3 -
39// 4 D4 -
40// 5 D5 -
41// 6 D6 -
42// 7 D7 -
43// 8 D8 -
44// 9 D9 -
45// 10 D10 -
46// 11 D11 -
47// 12 D12 -
48// 13 D13 -
49// 14 D14 -
50// 15 D15 -
51// 16 D16 -
52// 17 D17 -
53// 18 D18 -
54// 19 D19 -
55// 20 D20 -
56// 21 D21 -
57// 22 D22 -
58// 23 D23 -
59// 24 D24 -
60// 25 D25 -
61// 26 D26 -
62// 27 D27 -
63// 28 D28 -
64// 29 D29 -
65// 30 D30 -
66// 31 D31 -
67//
68//------------------------------------------------------
69// PORT 1:
70//
71// PIN/BIT N FUNC0 FUNC1
72// 0 A0 -
73// 1 A1 -
74// 2 A2 -
75// 3 A3 -
76// 4 A4 -
77// 5 A5 -
78// 6 A6 -
79// 7 A7 -
80// 8 A8 -
81// 9 A9 -
82// 10 A10 -
83// 11 A11 -
84// 12 A12 -
85// 13 A13 -
86// 14 A14 -
87// 15 A15/CL -
88// 16 A16/AL -
89// 17 LCD_CLS A21
90// 18 LCD_SPL A22
91// 19 DCS# -
92// 20 RAS# -
93// 21 CAS# -
94// 22 RDWE#/BUFD# -
95// 23 CKE -
96// 24 CKO -
97// 25 CS1# -
98// 26 CS2# -
99// 27 CS3# -
100// 28 CS4# -
101// 29 RD# -
102// 30 WR# -
103// 31 WE0# -
104//
105// Note: PIN15&16 are CL&AL when connecting to NAND flash.
106//------------------------------------------------------
107// PORT 2:
108//
109// PIN/BIT N FUNC0 FUNC1
110// 0 LCD_D0 -
111// 1 LCD_D1 -
112// 2 LCD_D2 -
113// 3 LCD_D3 -
114// 4 LCD_D4 -
115// 5 LCD_D5 -
116// 6 LCD_D6 -
117// 7 LCD_D7 -
118// 8 LCD_D8 -
119// 9 LCD_D9 -
120// 10 LCD_D10 -
121// 11 LCD_D11 -
122// 12 LCD_D12 -
123// 13 LCD_D13 -
124// 14 LCD_D14 -
125// 15 LCD_D15 -
126// 16 LCD_D16 -
127// 17 LCD_D17 -
128// 18 LCD_PCLK -
129// 19 LCD_HSYNC -
130// 20 LCD_VSYNC -
131// 21 LCD_DE -
132// 22 LCD_PS A19
133// 23 LCD_REV A20
134// 24 WE1# -
135// 25 WE2# -
136// 26 WE3# -
137// 27 WAIT# -
138// 28 FRE# -
139// 29 FWE# -
140// 30(NOTE:FRB#) - -
141// 31 - -
142//
143// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
144//------------------------------------------------------
145// PORT 3:
146//
147// PIN/BIT N FUNC0 FUNC1
148// 0 CIM_D0 -
149// 1 CIM_D1 -
150// 2 CIM_D2 -
151// 3 CIM_D3 -
152// 4 CIM_D4 -
153// 5 CIM_D5 -
154// 6 CIM_D6 -
155// 7 CIM_D7 -
156// 8 MSC_CMD -
157// 9 MSC_CLK -
158// 10 MSC_D0 -
159// 11 MSC_D1 -
160// 12 MSC_D2 -
161// 13 MSC_D3 -
162// 14 CIM_MCLK -
163// 15 CIM_PCLK -
164// 16 CIM_VSYNC -
165// 17 CIM_HSYNC -
166// 18 SSI_CLK SCLK_RSTN
167// 19 SSI_CE0# BIT_CLK(AIC)
168// 20 SSI_DT SDATA_OUT(AIC)
169// 21 SSI_DR SDATA_IN(AIC)
170// 22 SSI_CE1#&GPC SYNC(AIC)
171// 23 PWM0 I2C_SDA
172// 24 PWM1 I2C_SCK
173// 25 PWM2 UART0_TxD
174// 26 PWM3 UART0_RxD
175// 27 PWM4 A17
176// 28 PWM5 A18
177// 29 - -
178// 30 PWM6 UART0_CTS/UART1_RxD
179// 31 PWM7 UART0_RTS/UART1_TxD
180//
181//////////////////////////////////////////////////////////
182
183/*
184 * p is the port number (0,1,2,3)
185 * o is the pin offset (0-31) inside the port
186 * n is the absolute number of a pin (0-127), regardless of the port
187 */
188
189//-------------------------------------------
190// Function Pins Mode
191
192#define __gpio_as_func0(n) \
193do { \
194    unsigned int p, o; \
195    p = (n) / 32; \
196    o = (n) % 32; \
197    REG_GPIO_PXFUNS(p) = (1 << o); \
198    REG_GPIO_PXSELC(p) = (1 << o); \
199} while (0)
200
201#define __gpio_as_func1(n) \
202do { \
203    unsigned int p, o; \
204    p = (n) / 32; \
205    o = (n) % 32; \
206    REG_GPIO_PXFUNS(p) = (1 << o); \
207    REG_GPIO_PXSELS(p) = (1 << o); \
208} while (0)
209
210/*
211 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
212 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
213 */
214#define __gpio_as_sdram_32bit() \
215do { \
216    REG_GPIO_PXFUNS(0) = 0xffffffff; \
217    REG_GPIO_PXSELC(0) = 0xffffffff; \
218    REG_GPIO_PXPES(0) = 0xffffffff; \
219    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
220    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
221    REG_GPIO_PXPES(1) = 0x81f9ffff; \
222    REG_GPIO_PXFUNS(2) = 0x07000000; \
223    REG_GPIO_PXSELC(2) = 0x07000000; \
224    REG_GPIO_PXPES(2) = 0x07000000; \
225} while (0)
226
227/*
228 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
229 * RDWE#, CKO#, WE0#, WE1#
230 */
231#define __gpio_as_sdram_16bit() \
232do { \
233    REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
234    REG_GPIO_PXSELC(0) = 0x5442bfaa; \
235    REG_GPIO_PXPES(0) = 0x5442bfaa; \
236    REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
237    REG_GPIO_PXSELC(1) = 0x81f9ffff; \
238    REG_GPIO_PXPES(1) = 0x81f9ffff; \
239    REG_GPIO_PXFUNS(2) = 0x01000000; \
240    REG_GPIO_PXSELC(2) = 0x01000000; \
241    REG_GPIO_PXPES(2) = 0x01000000; \
242} while (0)
243
244/*
245 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
246 */
247#define __gpio_as_nand() \
248do { \
249    REG_GPIO_PXFUNS(1) = 0x02018000; \
250    REG_GPIO_PXSELC(1) = 0x02018000; \
251    REG_GPIO_PXPES(1) = 0x02018000; \
252    REG_GPIO_PXFUNS(2) = 0x30000000; \
253    REG_GPIO_PXSELC(2) = 0x30000000; \
254    REG_GPIO_PXPES(2) = 0x30000000; \
255    REG_GPIO_PXFUNC(2) = 0x40000000; \
256    REG_GPIO_PXSELC(2) = 0x40000000; \
257    REG_GPIO_PXDIRC(2) = 0x40000000; \
258    REG_GPIO_PXPES(2) = 0x40000000; \
259    REG_GPIO_PXFUNS(1) = 0x00400000; \
260    REG_GPIO_PXSELC(1) = 0x00400000; \
261} while (0)
262
263/*
264 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
265 */
266#define __gpio_as_nor_8bit() \
267do { \
268    REG_GPIO_PXFUNS(0) = 0x000000ff; \
269    REG_GPIO_PXSELC(0) = 0x000000ff; \
270    REG_GPIO_PXPES(0) = 0x000000ff; \
271    REG_GPIO_PXFUNS(1) = 0x7041ffff; \
272    REG_GPIO_PXSELC(1) = 0x7041ffff; \
273    REG_GPIO_PXPES(1) = 0x7041ffff; \
274    REG_GPIO_PXFUNS(1) = 0x00060000; \
275    REG_GPIO_PXSELS(1) = 0x00060000; \
276    REG_GPIO_PXPES(1) = 0x00060000; \
277    REG_GPIO_PXFUNS(2) = 0x08000000; \
278    REG_GPIO_PXSELC(2) = 0x08000000; \
279    REG_GPIO_PXPES(2) = 0x08000000; \
280    REG_GPIO_PXFUNS(2) = 0x00c00000; \
281    REG_GPIO_PXSELS(2) = 0x00c00000; \
282    REG_GPIO_PXPES(2) = 0x00c00000; \
283    REG_GPIO_PXFUNS(3) = 0x18000000; \
284    REG_GPIO_PXSELS(3) = 0x18000000; \
285    REG_GPIO_PXPES(3) = 0x18000000; \
286} while (0)
287
288/*
289 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
290 */
291#define __gpio_as_nor_16bit() \
292do { \
293    REG_GPIO_PXFUNS(0) = 0x0000ffff; \
294    REG_GPIO_PXSELC(0) = 0x0000ffff; \
295    REG_GPIO_PXPES(0) = 0x0000ffff; \
296    REG_GPIO_PXFUNS(1) = 0x7041ffff; \
297    REG_GPIO_PXSELC(1) = 0x7041ffff; \
298    REG_GPIO_PXPES(1) = 0x7041ffff; \
299    REG_GPIO_PXFUNS(1) = 0x00060000; \
300    REG_GPIO_PXSELS(1) = 0x00060000; \
301    REG_GPIO_PXPES(1) = 0x00060000; \
302    REG_GPIO_PXFUNS(2) = 0x08000000; \
303    REG_GPIO_PXSELC(2) = 0x08000000; \
304    REG_GPIO_PXPES(2) = 0x08000000; \
305    REG_GPIO_PXFUNS(2) = 0x00c00000; \
306    REG_GPIO_PXSELS(2) = 0x00c00000; \
307    REG_GPIO_PXPES(2) = 0x00c00000; \
308    REG_GPIO_PXFUNS(3) = 0x18000000; \
309    REG_GPIO_PXSELS(3) = 0x18000000; \
310    REG_GPIO_PXPES(3) = 0x18000000; \
311} while (0)
312
313/*
314 * UART0_TxD, UART_RxD0
315 */
316#define __gpio_as_uart0() \
317do { \
318    REG_GPIO_PXFUNS(3) = 0x06000000; \
319    REG_GPIO_PXSELS(3) = 0x06000000; \
320    REG_GPIO_PXPES(3) = 0x06000000; \
321} while (0)
322
323/*
324 * UART0_CTS, UART0_RTS
325 */
326#define __gpio_as_ctsrts() \
327do { \
328    REG_GPIO_PXFUNS(3) = 0xc0000000; \
329    REG_GPIO_PXSELS(3) = 0xc0000000; \
330    REG_GPIO_PXTRGC(3) = 0xc0000000; \
331    REG_GPIO_PXPES(3) = 0xc0000000; \
332} while (0)
333
334/*
335 * UART1_TxD, UART1_RxD1
336 */
337#define __gpio_as_uart1() \
338do { \
339    REG_GPIO_PXFUNS(3) = 0xc0000000; \
340    REG_GPIO_PXSELC(3) = 0xc0000000; \
341    REG_GPIO_PXTRGS(3) = 0xc0000000; \
342    REG_GPIO_PXPES(3) = 0xc0000000; \
343} while (0)
344
345/*
346 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
347 */
348#define __gpio_as_lcd_16bit() \
349do { \
350    REG_GPIO_PXFUNS(2) = 0x003cffff; \
351    REG_GPIO_PXSELC(2) = 0x003cffff; \
352    REG_GPIO_PXPES(2) = 0x003cffff; \
353} while (0)
354
355/*
356 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
357 */
358#define __gpio_as_lcd_18bit() \
359do { \
360    REG_GPIO_PXFUNS(2) = 0x003fffff; \
361    REG_GPIO_PXSELC(2) = 0x003fffff; \
362    REG_GPIO_PXPES(2) = 0x003fffff; \
363} while (0)
364
365/*
366 * LCD_PS, LCD_REV, LCD_CLS, LCD_SPL
367 */
368#define __gpio_as_lcd_special() \
369do { \
370    REG_GPIO_PXFUNS(1) = 0x00060000; \
371    REG_GPIO_PXSELC(1) = 0x00060000; \
372    REG_GPIO_PXPES(1) = 0x00060000; \
373    REG_GPIO_PXFUNS(2) = 0x00c00000; \
374    REG_GPIO_PXSELC(2) = 0x00c00000; \
375    REG_GPIO_PXPES(2) = 0x00c00000; \
376} while (0)
377
378/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
379#define __gpio_as_slcd_8bit() \
380do { \
381    REG_GPIO_PXFUNS(2) = 0x001800ff; \
382    REG_GPIO_PXSELC(2) = 0x001800ff; \
383} while (0)
384
385/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
386#define __gpio_as_slcd_9bit() \
387do { \
388    REG_GPIO_PXFUNS(2) = 0x001801ff; \
389    REG_GPIO_PXSELC(2) = 0x001801ff; \
390} while (0)
391
392/* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */
393#define __gpio_as_slcd_16bit() \
394do { \
395    REG_GPIO_PXFUNS(2) = 0x0018ffff; \
396    REG_GPIO_PXSELC(2) = 0x0018ffff; \
397} while (0)
398
399/* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */
400#define __gpio_as_slcd_18bit() \
401do { \
402    REG_GPIO_PXFUNS(2) = 0x001bffff; \
403    REG_GPIO_PXSELC(2) = 0x001bffff; \
404} while (0)
405
406/*
407 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
408 */
409#define __gpio_as_cim() \
410do { \
411    REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
412    REG_GPIO_PXSELC(3) = 0x0003c0ff; \
413    REG_GPIO_PXPES(3) = 0x0003c0ff; \
414} while (0)
415
416/*
417 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
418 */
419#define __gpio_as_aic() \
420do { \
421    REG_GPIO_PXFUNS(3) = 0x007c0000; \
422    REG_GPIO_PXSELS(3) = 0x007c0000; \
423    REG_GPIO_PXPES(3) = 0x007c0000; \
424} while (0)
425
426/*
427 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
428 */
429#define __gpio_as_msc() \
430do { \
431    REG_GPIO_PXFUNS(3) = 0x00003f00; \
432    REG_GPIO_PXSELC(3) = 0x00003f00; \
433    REG_GPIO_PXPES(3) = 0x00003f00; \
434} while (0)
435
436/*
437 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
438 */
439#define __gpio_as_ssi() \
440do { \
441    REG_GPIO_PXFUNS(3) = 0x003c0000; \
442    REG_GPIO_PXSELC(3) = 0x003c0000; \
443    REG_GPIO_PXPES(3) = 0x003c0000; \
444} while (0)
445
446/*
447 * I2C_SCK, I2C_SDA
448 */
449#define __gpio_as_i2c() \
450do { \
451    REG_GPIO_PXFUNS(3) = 0x01800000; \
452    REG_GPIO_PXSELS(3) = 0x01800000; \
453    REG_GPIO_PXPES(3) = 0x01800000; \
454} while (0)
455
456/*
457 * PWM0
458 */
459#define __gpio_as_pwm0() \
460do { \
461    REG_GPIO_PXFUNS(3) = 0x00800000; \
462    REG_GPIO_PXSELC(3) = 0x00800000; \
463    REG_GPIO_PXPES(3) = 0x00800000; \
464} while (0)
465
466/*
467 * PWM1
468 */
469#define __gpio_as_pwm1() \
470do { \
471    REG_GPIO_PXFUNS(3) = 0x01000000; \
472    REG_GPIO_PXSELC(3) = 0x01000000; \
473    REG_GPIO_PXPES(3) = 0x01000000; \
474} while (0)
475
476/*
477 * PWM2
478 */
479#define __gpio_as_pwm2() \
480do { \
481    REG_GPIO_PXFUNS(3) = 0x02000000; \
482    REG_GPIO_PXSELC(3) = 0x02000000; \
483    REG_GPIO_PXPES(3) = 0x02000000; \
484} while (0)
485
486/*
487 * PWM3
488 */
489#define __gpio_as_pwm3() \
490do { \
491    REG_GPIO_PXFUNS(3) = 0x04000000; \
492    REG_GPIO_PXSELC(3) = 0x04000000; \
493    REG_GPIO_PXPES(3) = 0x04000000; \
494} while (0)
495
496/*
497 * PWM4
498 */
499#define __gpio_as_pwm4() \
500do { \
501    REG_GPIO_PXFUNS(3) = 0x08000000; \
502    REG_GPIO_PXSELC(3) = 0x08000000; \
503    REG_GPIO_PXPES(3) = 0x08000000; \
504} while (0)
505
506/*
507 * PWM5
508 */
509#define __gpio_as_pwm5() \
510do { \
511    REG_GPIO_PXFUNS(3) = 0x10000000; \
512    REG_GPIO_PXSELC(3) = 0x10000000; \
513    REG_GPIO_PXPES(3) = 0x10000000; \
514} while (0)
515
516/*
517 * PWM6
518 */
519#define __gpio_as_pwm6() \
520do { \
521    REG_GPIO_PXFUNS(3) = 0x40000000; \
522    REG_GPIO_PXSELC(3) = 0x40000000; \
523    REG_GPIO_PXPES(3) = 0x40000000; \
524} while (0)
525
526/*
527 * PWM7
528 */
529#define __gpio_as_pwm7() \
530do { \
531    REG_GPIO_PXFUNS(3) = 0x80000000; \
532    REG_GPIO_PXSELC(3) = 0x80000000; \
533    REG_GPIO_PXPES(3) = 0x80000000; \
534} while (0)
535
536/*
537 * n = 0 ~ 7
538 */
539#define __gpio_as_pwm(n) __gpio_as_pwm##n()
540
541//-------------------------------------------
542// GPIO or Interrupt Mode
543
544#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
545
546#define __gpio_port_as_output(p, o) \
547do { \
548    REG_GPIO_PXFUNC(p) = (1 << (o)); \
549    REG_GPIO_PXSELC(p) = (1 << (o)); \
550    REG_GPIO_PXDIRS(p) = (1 << (o)); \
551} while (0)
552
553#define __gpio_port_as_input(p, o) \
554do { \
555    REG_GPIO_PXFUNC(p) = (1 << (o)); \
556    REG_GPIO_PXSELC(p) = (1 << (o)); \
557    REG_GPIO_PXDIRC(p) = (1 << (o)); \
558} while (0)
559
560#define __gpio_as_output(n) \
561do { \
562    unsigned int p, o; \
563    p = (n) / 32; \
564    o = (n) % 32; \
565    __gpio_port_as_output(p, o); \
566} while (0)
567
568#define __gpio_as_input(n) \
569do { \
570    unsigned int p, o; \
571    p = (n) / 32; \
572    o = (n) % 32; \
573    __gpio_port_as_input(p, o); \
574} while (0)
575
576#define __gpio_set_pin(n) \
577do { \
578    unsigned int p, o; \
579    p = (n) / 32; \
580    o = (n) % 32; \
581    REG_GPIO_PXDATS(p) = (1 << o); \
582} while (0)
583
584#define __gpio_clear_pin(n) \
585do { \
586    unsigned int p, o; \
587    p = (n) / 32; \
588    o = (n) % 32; \
589    REG_GPIO_PXDATC(p) = (1 << o); \
590} while (0)
591
592#define __gpio_get_pin(n) \
593({ \
594    unsigned int p, o, v; \
595    p = (n) / 32; \
596    o = (n) % 32; \
597    if (__gpio_get_port(p) & (1 << o)) \
598        v = 1; \
599    else \
600        v = 0; \
601    v; \
602})
603
604#define __gpio_as_irq_high_level(n) \
605do { \
606    unsigned int p, o; \
607    p = (n) / 32; \
608    o = (n) % 32; \
609    REG_GPIO_PXIMS(p) = (1 << o); \
610    REG_GPIO_PXTRGC(p) = (1 << o); \
611    REG_GPIO_PXFUNC(p) = (1 << o); \
612    REG_GPIO_PXSELS(p) = (1 << o); \
613    REG_GPIO_PXDIRS(p) = (1 << o); \
614    REG_GPIO_PXFLGC(p) = (1 << o); \
615    REG_GPIO_PXIMC(p) = (1 << o); \
616} while (0)
617
618#define __gpio_as_irq_low_level(n) \
619do { \
620    unsigned int p, o; \
621    p = (n) / 32; \
622    o = (n) % 32; \
623    REG_GPIO_PXIMS(p) = (1 << o); \
624    REG_GPIO_PXTRGC(p) = (1 << o); \
625    REG_GPIO_PXFUNC(p) = (1 << o); \
626    REG_GPIO_PXSELS(p) = (1 << o); \
627    REG_GPIO_PXDIRC(p) = (1 << o); \
628    REG_GPIO_PXFLGC(p) = (1 << o); \
629    REG_GPIO_PXIMC(p) = (1 << o); \
630} while (0)
631
632#define __gpio_as_irq_rise_edge(n) \
633do { \
634    unsigned int p, o; \
635    p = (n) / 32; \
636    o = (n) % 32; \
637    REG_GPIO_PXIMS(p) = (1 << o); \
638    REG_GPIO_PXTRGS(p) = (1 << o); \
639    REG_GPIO_PXFUNC(p) = (1 << o); \
640    REG_GPIO_PXSELS(p) = (1 << o); \
641    REG_GPIO_PXDIRS(p) = (1 << o); \
642    REG_GPIO_PXFLGC(p) = (1 << o); \
643    REG_GPIO_PXIMC(p) = (1 << o); \
644} while (0)
645
646#define __gpio_as_irq_fall_edge(n) \
647do { \
648    unsigned int p, o; \
649    p = (n) / 32; \
650    o = (n) % 32; \
651    REG_GPIO_PXIMS(p) = (1 << o); \
652    REG_GPIO_PXTRGS(p) = (1 << o); \
653    REG_GPIO_PXFUNC(p) = (1 << o); \
654    REG_GPIO_PXSELS(p) = (1 << o); \
655    REG_GPIO_PXDIRC(p) = (1 << o); \
656    REG_GPIO_PXFLGC(p) = (1 << o); \
657    REG_GPIO_PXIMC(p) = (1 << o); \
658} while (0)
659
660#define __gpio_mask_irq(n) \
661do { \
662    unsigned int p, o; \
663    p = (n) / 32; \
664    o = (n) % 32; \
665    REG_GPIO_PXIMS(p) = (1 << o); \
666} while (0)
667
668#define __gpio_unmask_irq(n) \
669do { \
670    unsigned int p, o; \
671    p = (n) / 32; \
672    o = (n) % 32; \
673    REG_GPIO_PXIMC(p) = (1 << o); \
674} while (0)
675
676#define __gpio_ack_irq(n) \
677do { \
678    unsigned int p, o; \
679    p = (n) / 32; \
680    o = (n) % 32; \
681    REG_GPIO_PXFLGC(p) = (1 << o); \
682} while (0)
683
684#define __gpio_get_irq() \
685({ \
686    unsigned int p, i, tmp, v = 0; \
687    for (p = 3; p >= 0; p--) { \
688        tmp = REG_GPIO_PXFLG(p); \
689        for (i = 0; i < 32; i++) \
690            if (tmp & (1 << i)) \
691                v = (32*p + i); \
692    } \
693    v; \
694})
695
696#define __gpio_group_irq(n) \
697({ \
698    register int tmp, i; \
699    tmp = REG_GPIO_PXFLG((n)); \
700    for (i=31;i>=0;i--) \
701        if (tmp & (1 << i)) \
702            break; \
703    i; \
704})
705
706#define __gpio_enable_pull(n) \
707do { \
708    unsigned int p, o; \
709    p = (n) / 32; \
710    o = (n) % 32; \
711    REG_GPIO_PXPEC(p) = (1 << o); \
712} while (0)
713
714#define __gpio_disable_pull(n) \
715do { \
716    unsigned int p, o; \
717    p = (n) / 32; \
718    o = (n) % 32; \
719    REG_GPIO_PXPES(p) = (1 << o); \
720} while (0)
721
722
723/***************************************************************************
724 * CPM
725 ***************************************************************************/
726#define __cpm_get_pllm() \
727    ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
728#define __cpm_get_plln() \
729    ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
730#define __cpm_get_pllod() \
731    ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
732
733#define __cpm_get_cdiv() \
734    ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
735#define __cpm_get_hdiv() \
736    ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
737#define __cpm_get_pdiv() \
738    ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
739#define __cpm_get_mdiv() \
740    ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
741#define __cpm_get_ldiv() \
742    ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
743#define __cpm_get_udiv() \
744    ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
745#define __cpm_get_i2sdiv() \
746    ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
747#define __cpm_get_pixdiv() \
748    ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
749#define __cpm_get_mscdiv() \
750    ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
751#define __cpm_get_uhcdiv() \
752    ((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT)
753#define __cpm_get_ssidiv() \
754    ((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
755
756#define __cpm_set_cdiv(v) \
757    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
758#define __cpm_set_hdiv(v) \
759    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
760#define __cpm_set_pdiv(v) \
761    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
762#define __cpm_set_mdiv(v) \
763    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
764#define __cpm_set_ldiv(v) \
765    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
766#define __cpm_set_udiv(v) \
767    (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
768#define __cpm_set_i2sdiv(v) \
769    (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
770#define __cpm_set_pixdiv(v) \
771    (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
772#define __cpm_set_mscdiv(v) \
773    (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
774#define __cpm_set_uhcdiv(v) \
775    (REG_CPM_UHCCDR = (REG_CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | ((v) << (CPM_UHCCDR_UHCDIV_BIT)))
776#define __cpm_ssiclk_select_exclk() \
777    (REG_CPM_SSICDR &= ~CPM_SSICDR_SCS)
778#define __cpm_ssiclk_select_pllout() \
779    (REG_CPM_SSICDR |= CPM_SSICDR_SCS)
780#define __cpm_set_ssidiv(v) \
781    (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
782
783#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
784#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
785#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
786#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
787#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
788#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
789#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
790#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
791
792#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
793#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
794#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
795
796#define __cpm_get_cclk_doze_duty() \
797    ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
798#define __cpm_set_cclk_doze_duty(v) \
799    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
800
801#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
802#define __cpm_idle_mode() \
803    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
804#define __cpm_sleep_mode() \
805    (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
806
807#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
808#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
809#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
810#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
811#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
812#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
813#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
814#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
815#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
816#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
817#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
818#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
819#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
820#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
821#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
822#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
823#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
824
825#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
826#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
827#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
828#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
829#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
830#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
831#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
832#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
833#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
834#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
835#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
836#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
837#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
838#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
839#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
840#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
841#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
842
843#define __cpm_get_o1st() \
844    ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
845#define __cpm_set_o1st(v) \
846    (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
847#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
848#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
849
850
851/***************************************************************************
852 * TCU
853 ***************************************************************************/
854// where 'n' is the TCU channel
855#define __tcu_select_extalclk(n) \
856    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
857#define __tcu_select_rtcclk(n) \
858    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
859#define __tcu_select_pclk(n) \
860    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
861
862#define __tcu_select_clk_div1(n) \
863    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
864#define __tcu_select_clk_div4(n) \
865    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
866#define __tcu_select_clk_div16(n) \
867    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
868#define __tcu_select_clk_div64(n) \
869    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
870#define __tcu_select_clk_div256(n) \
871    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
872#define __tcu_select_clk_div1024(n) \
873    (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
874
875#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
876#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
877
878#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
879#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
880
881#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
882#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
883
884#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
885#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
886
887#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
888#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
889#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
890#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
891#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
892#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
893#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
894#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
895#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
896#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
897
898#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
899#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
900
901#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
902#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
903
904#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
905#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
906
907#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
908#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
909#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
910#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
911
912
913/***************************************************************************
914 * WDT
915 ***************************************************************************/
916#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
917#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
918#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
919#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
920
921#define __wdt_select_extalclk() \
922    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
923#define __wdt_select_rtcclk() \
924    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
925#define __wdt_select_pclk() \
926    (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
927
928#define __wdt_select_clk_div1() \
929    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
930#define __wdt_select_clk_div4() \
931    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
932#define __wdt_select_clk_div16() \
933    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
934#define __wdt_select_clk_div64() \
935    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
936#define __wdt_select_clk_div256() \
937    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
938#define __wdt_select_clk_div1024() \
939    (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
940
941
942/***************************************************************************
943 * UART
944 ***************************************************************************/
945
946#define __uart_enable(n) \
947  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE )
948#define __uart_disable(n) \
949  ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE )
950
951#define __uart_enable_transmit_irq(n) \
952  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE )
953#define __uart_disable_transmit_irq(n) \
954  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE )
955
956#define __uart_enable_receive_irq(n) \
957  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
958#define __uart_disable_receive_irq(n) \
959  ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
960
961#define __uart_enable_loopback(n) \
962  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP )
963#define __uart_disable_loopback(n) \
964  ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP )
965
966#define __uart_set_8n1(n) \
967  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 )
968
969#define __uart_set_baud(n, devclk, baud) \
970  do { \
971    REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \
972    REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \
973    REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
974    REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \
975  } while (0)
976
977#define __uart_parity_error(n) \
978  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 )
979
980#define __uart_clear_errors(n) \
981  ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
982
983#define __uart_transmit_fifo_empty(n) \
984  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 )
985
986#define __uart_transmit_end(n) \
987  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 )
988
989#define __uart_transmit_char(n, ch) \
990  REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch)
991
992#define __uart_receive_fifo_full(n) \
993  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
994
995#define __uart_receive_ready(n) \
996  ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
997
998#define __uart_receive_char(n) \
999  REG8(UART_BASE + UART_OFF*(n) + OFF_RDR)
1000
1001#define __uart_disable_irda() \
1002  ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
1003#define __uart_enable_irda() \
1004  /* Tx high pulse as 0, Rx low pulse as 0 */ \
1005  ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
1006
1007
1008/***************************************************************************
1009 * DMAC
1010 ***************************************************************************/
1011
1012/* n is the DMA channel (0 - 5) */
1013
1014#define __dmac_enable_module() \
1015  ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
1016#define __dmac_disable_module() \
1017  ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
1018
1019/* p=0,1,2,3 */
1020#define __dmac_set_priority(p) \
1021do { \
1022    REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
1023    REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
1024} while (0)
1025
1026#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
1027#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
1028
1029#define __dmac_enable_descriptor(n) \
1030  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
1031#define __dmac_disable_descriptor(n) \
1032  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
1033
1034#define __dmac_enable_channel(n) \
1035  ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
1036#define __dmac_disable_channel(n) \
1037  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
1038#define __dmac_channel_enabled(n) \
1039  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
1040
1041#define __dmac_channel_enable_irq(n) \
1042  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
1043#define __dmac_channel_disable_irq(n) \
1044  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
1045
1046#define __dmac_channel_transmit_halt_detected(n) \
1047  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
1048#define __dmac_channel_transmit_end_detected(n) \
1049  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
1050#define __dmac_channel_address_error_detected(n) \
1051  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
1052#define __dmac_channel_count_terminated_detected(n) \
1053  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
1054#define __dmac_channel_descriptor_invalid_detected(n) \
1055  ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
1056
1057#define __dmac_channel_clear_transmit_halt(n) \
1058  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
1059#define __dmac_channel_clear_transmit_end(n) \
1060  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
1061#define __dmac_channel_clear_address_error(n) \
1062  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
1063#define __dmac_channel_clear_count_terminated(n) \
1064  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
1065#define __dmac_channel_clear_descriptor_invalid(n) \
1066  ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
1067
1068#define __dmac_channel_set_single_mode(n) \
1069  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
1070#define __dmac_channel_set_block_mode(n) \
1071  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
1072
1073#define __dmac_channel_set_transfer_unit_32bit(n) \
1074do { \
1075    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1076    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
1077} while (0)
1078
1079#define __dmac_channel_set_transfer_unit_16bit(n) \
1080do { \
1081    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1082    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
1083} while (0)
1084
1085#define __dmac_channel_set_transfer_unit_8bit(n) \
1086do { \
1087    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1088    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
1089} while (0)
1090
1091#define __dmac_channel_set_transfer_unit_16byte(n) \
1092do { \
1093    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1094    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
1095} while (0)
1096
1097#define __dmac_channel_set_transfer_unit_32byte(n) \
1098do { \
1099    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1100    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
1101} while (0)
1102
1103/* w=8,16,32 */
1104#define __dmac_channel_set_dest_port_width(n,w) \
1105do { \
1106    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
1107    REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
1108} while (0)
1109
1110/* w=8,16,32 */
1111#define __dmac_channel_set_src_port_width(n,w) \
1112do { \
1113    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
1114    REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
1115} while (0)
1116
1117/* v=0-15 */
1118#define __dmac_channel_set_rdil(n,v) \
1119do { \
1120    REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
1121    REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
1122} while (0)
1123
1124#define __dmac_channel_dest_addr_fixed(n) \
1125  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
1126#define __dmac_channel_dest_addr_increment(n) \
1127  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
1128
1129#define __dmac_channel_src_addr_fixed(n) \
1130  ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
1131#define __dmac_channel_src_addr_increment(n) \
1132  ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
1133
1134#define __dmac_channel_set_doorbell(n) \
1135  ( REG_DMAC_DMADBSR = (1 << (n)) )
1136
1137#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
1138#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
1139
1140static __inline__ int __dmac_get_irq(void)
1141{
1142    int i;
1143    for (i = 0; i < MAX_DMA_NUM; i++)
1144        if (__dmac_channel_irq_detected(i))
1145            return i;
1146    return -1;
1147}
1148
1149
1150/***************************************************************************
1151 * AIC (AC'97 & I2S Controller)
1152 ***************************************************************************/
1153
1154#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
1155#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
1156
1157#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
1158#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
1159
1160#define __aic_play_zero() ( REG_AIC_FR &= ~AIC_FR_LSMP )
1161#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
1162
1163#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
1164#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
1165#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
1166
1167#define __aic_reset() \
1168do { \
1169        REG_AIC_FR |= AIC_FR_RST; \
1170} while(0)
1171
1172
1173#define __aic_set_transmit_trigger(n) \
1174do { \
1175    REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
1176    REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
1177} while(0)
1178
1179#define __aic_set_receive_trigger(n) \
1180do { \
1181    REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
1182    REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
1183} while(0)
1184
1185#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
1186#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
1187#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
1188#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
1189#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
1190#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
1191
1192#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
1193#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
1194
1195#define __aic_enable_transmit_intr() \
1196  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
1197#define __aic_disable_transmit_intr() \
1198  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
1199#define __aic_enable_receive_intr() \
1200  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
1201#define __aic_disable_receive_intr() \
1202  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
1203
1204#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
1205#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
1206#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
1207#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
1208
1209#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
1210#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
1211#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
1212#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
1213#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
1214#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
1215
1216#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
1217#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
1218#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
1219#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
1220#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
1221#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
1222
1223#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
1224#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
1225#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
1226#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
1227#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
1228#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
1229
1230#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
1231#define __ac97_set_xs_mono() \
1232do { \
1233    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
1234    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
1235} while(0)
1236#define __ac97_set_xs_stereo() \
1237do { \
1238    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
1239    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
1240} while(0)
1241
1242/* In fact, only stereo is support now. */
1243#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
1244#define __ac97_set_rs_mono() \
1245do { \
1246    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
1247    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
1248} while(0)
1249#define __ac97_set_rs_stereo() \
1250do { \
1251    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
1252    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
1253} while(0)
1254
1255#define __ac97_warm_reset_codec() \
1256 do { \
1257    REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
1258    REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
1259    udelay(2); \
1260    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
1261    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
1262 } while (0)
1263
1264#define __ac97_cold_reset_codec() \
1265 do { \
1266    REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
1267    udelay(2); \
1268    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
1269 } while (0)
1270
1271/* n=8,16,18,20 */
1272#define __ac97_set_iass(n) \
1273 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
1274#define __ac97_set_oass(n) \
1275 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
1276
1277#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
1278#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
1279
1280/* n=8,16,18,20,24 */
1281/*#define __i2s_set_sample_size(n) \
1282 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
1283
1284#define __i2s_set_oss_sample_size(n) \
1285 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
1286#define __i2s_set_iss_sample_size(n) \
1287 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
1288
1289#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
1290#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
1291
1292#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
1293#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
1294#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
1295#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
1296
1297#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
1298
1299#define __aic_get_transmit_resident() \
1300  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
1301#define __aic_get_receive_count() \
1302  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
1303
1304#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
1305#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
1306#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
1307#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
1308#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
1309#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
1310#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
1311
1312#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
1313
1314#define CODEC_READ_CMD (1 << 19)
1315#define CODEC_WRITE_CMD (0 << 19)
1316#define CODEC_REG_INDEX_BIT 12
1317#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
1318#define CODEC_REG_DATA_BIT 4
1319#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
1320
1321#define __ac97_out_rcmd_addr(reg) \
1322do { \
1323    REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
1324} while (0)
1325
1326#define __ac97_out_wcmd_addr(reg) \
1327do { \
1328    REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
1329} while (0)
1330
1331#define __ac97_out_data(value) \
1332do { \
1333    REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
1334} while (0)
1335
1336#define __ac97_in_data() \
1337 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
1338
1339#define __ac97_in_status_addr() \
1340 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
1341
1342#define __i2s_set_sample_rate(i2sclk, sync) \
1343  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
1344
1345#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
1346#define __aic_read_rfifo() ( REG_AIC_DR )
1347
1348#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
1349#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
1350
1351//
1352// Define next ops for AC97 compatible
1353//
1354
1355#define AC97_ACSR AIC_ACSR
1356
1357#define __ac97_enable() __aic_enable(); __aic_select_ac97()
1358#define __ac97_disable() __aic_disable()
1359#define __ac97_reset() __aic_reset()
1360
1361#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
1362#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
1363
1364#define __ac97_enable_record() __aic_enable_record()
1365#define __ac97_disable_record() __aic_disable_record()
1366#define __ac97_enable_replay() __aic_enable_replay()
1367#define __ac97_disable_replay() __aic_disable_replay()
1368#define __ac97_enable_loopback() __aic_enable_loopback()
1369#define __ac97_disable_loopback() __aic_disable_loopback()
1370
1371#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
1372#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
1373#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
1374#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
1375
1376#define __ac97_transmit_request() __aic_transmit_request()
1377#define __ac97_receive_request() __aic_receive_request()
1378#define __ac97_transmit_underrun() __aic_transmit_underrun()
1379#define __ac97_receive_overrun() __aic_receive_overrun()
1380
1381#define __ac97_clear_errors() __aic_clear_errors()
1382
1383#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
1384#define __ac97_get_receive_count() __aic_get_receive_count()
1385
1386#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
1387#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
1388#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
1389#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
1390
1391#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
1392#define __ac97_read_rfifo() __aic_read_rfifo()
1393
1394//
1395// Define next ops for I2S compatible
1396//
1397
1398#define I2S_ACSR AIC_I2SSR
1399
1400#define __i2s_enable() __aic_enable(); __aic_select_i2s()
1401#define __i2s_disable() __aic_disable()
1402#define __i2s_reset() __aic_reset()
1403
1404#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
1405#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
1406
1407#define __i2s_enable_record() __aic_enable_record()
1408#define __i2s_disable_record() __aic_disable_record()
1409#define __i2s_enable_replay() __aic_enable_replay()
1410#define __i2s_disable_replay() __aic_disable_replay()
1411#define __i2s_enable_loopback() __aic_enable_loopback()
1412#define __i2s_disable_loopback() __aic_disable_loopback()
1413
1414#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
1415#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
1416#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
1417#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
1418
1419#define __i2s_transmit_request() __aic_transmit_request()
1420#define __i2s_receive_request() __aic_receive_request()
1421#define __i2s_transmit_underrun() __aic_transmit_underrun()
1422#define __i2s_receive_overrun() __aic_receive_overrun()
1423
1424#define __i2s_clear_errors() __aic_clear_errors()
1425
1426#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
1427#define __i2s_get_receive_count() __aic_get_receive_count()
1428
1429#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
1430#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
1431#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
1432#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
1433
1434#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
1435#define __i2s_read_rfifo() __aic_read_rfifo()
1436
1437#define __i2s_reset_codec() \
1438 do { \
1439 } while (0)
1440
1441
1442/***************************************************************************
1443 * ICDC
1444 ***************************************************************************/
1445#define __i2s_internal_codec() __aic_internal_codec()
1446#define __i2s_external_codec() __aic_external_codec()
1447
1448/***************************************************************************
1449 * INTC
1450 ***************************************************************************/
1451#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
1452#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
1453#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
1454
1455
1456/***************************************************************************
1457 * I2C
1458 ***************************************************************************/
1459
1460#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
1461#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
1462
1463#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
1464#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
1465#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
1466#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
1467
1468#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
1469#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
1470#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
1471
1472#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
1473#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
1474#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
1475
1476#define __i2c_set_clk(dev_clk, i2c_clk) \
1477  ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
1478
1479#define __i2c_read() ( REG_I2C_DR )
1480#define __i2c_write(val) ( REG_I2C_DR = (val) )
1481
1482
1483/***************************************************************************
1484 * MSC
1485 ***************************************************************************/
1486
1487#define __msc_start_op() \
1488  ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
1489
1490#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
1491#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
1492#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
1493#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
1494#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
1495#define __msc_get_nob() ( REG_MSC_NOB )
1496#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
1497#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
1498#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
1499#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
1500
1501#define __msc_set_cmdat_bus_width1() \
1502do { \
1503    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
1504    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
1505} while(0)
1506
1507#define __msc_set_cmdat_bus_width4() \
1508do { \
1509    REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
1510    REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
1511} while(0)
1512
1513#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
1514#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
1515#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
1516#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
1517#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
1518#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
1519#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
1520#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
1521
1522/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
1523#define __msc_set_cmdat_res_format(r) \
1524do { \
1525    REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
1526    REG_MSC_CMDAT |= (r); \
1527} while(0)
1528
1529#define __msc_clear_cmdat() \
1530  REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
1531  MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
1532  MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
1533
1534#define __msc_get_imask() ( REG_MSC_IMASK )
1535#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
1536#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
1537#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
1538#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
1539#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
1540#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
1541#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
1542#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
1543#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
1544#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
1545#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
1546#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
1547
1548/* n=0,1,2,3,4,5,6,7 */
1549#define __msc_set_clkrt(n) \
1550do { \
1551    REG_MSC_CLKRT = n; \
1552} while(0)
1553
1554#define __msc_get_ireg() ( REG_MSC_IREG )
1555#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
1556#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
1557#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
1558#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
1559#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
1560#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
1561#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
1562#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
1563
1564#define __msc_get_stat() ( REG_MSC_STAT )
1565#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
1566#define __msc_stat_crc_err() \
1567  ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
1568#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
1569#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
1570#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
1571#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
1572#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
1573
1574#define __msc_rd_resfifo() ( REG_MSC_RES )
1575#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
1576#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
1577
1578#define __msc_reset() \
1579do { \
1580    REG_MSC_STRPCL = MSC_STRPCL_RESET; \
1581     while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
1582} while (0)
1583
1584#define __msc_start_clk() \
1585do { \
1586    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
1587} while (0)
1588
1589#define __msc_stop_clk() \
1590do { \
1591    REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
1592} while (0)
1593
1594#define MMC_CLK 19169200
1595#define SD_CLK 24576000
1596
1597/* msc_clk should little than pclk and little than clk retrieve from card */
1598#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
1599do { \
1600    unsigned int rate, pclk, i; \
1601    pclk = dev_clk; \
1602    rate = type?SD_CLK:MMC_CLK; \
1603      if (msc_clk && msc_clk < pclk) \
1604            pclk = msc_clk; \
1605    i = 0; \
1606      while (pclk < rate) \
1607        { \
1608              i ++; \
1609              rate >>= 1; \
1610        } \
1611      lv = i; \
1612} while(0)
1613
1614/* divide rate to little than or equal to 400kHz */
1615#define __msc_calc_slow_clk_divisor(type, lv) \
1616do { \
1617    unsigned int rate, i; \
1618    rate = (type?SD_CLK:MMC_CLK)/1000/400; \
1619    i = 0; \
1620    while (rate > 0) \
1621        { \
1622              rate >>= 1; \
1623              i ++; \
1624        } \
1625      lv = i; \
1626} while(0)
1627
1628
1629/***************************************************************************
1630 * SSI
1631 ***************************************************************************/
1632
1633#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
1634#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
1635#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
1636
1637#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
1638
1639#define __ssi_select_ce2() \
1640do { \
1641    REG_SSI_CR0 |= SSI_CR0_FSEL; \
1642    REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
1643} while (0)
1644
1645#define __ssi_select_gpc() \
1646do { \
1647    REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
1648    REG_SSI_CR1 |= SSI_CR1_MULTS; \
1649} while (0)
1650
1651#define __ssi_enable_tx_intr() \
1652  ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
1653
1654#define __ssi_disable_tx_intr() \
1655  ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
1656
1657#define __ssi_enable_rx_intr() \
1658  ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
1659
1660#define __ssi_disable_rx_intr() \
1661  ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
1662
1663#define __ssi_enable_txfifo_half_empty_intr() \
1664    ( REG_SSI_CR0 |= SSI_CR0_TIE )
1665#define __ssi_disable_txfifo_half_empty_intr() \
1666    ( REG_SSI_CR0 &= ~SSI_CR0_TIE )
1667#define __ssi_enable_tx_error_intr() \
1668    ( REG_SSI_CR0 |= SSI_CR0_TEIE )
1669#define __ssi_disable_tx_error_intr() \
1670    ( REG_SSI_CR0 &= ~SSI_CR0_TEIE )
1671
1672#define __ssi_enable_rxfifo_half_full_intr() \
1673    ( REG_SSI_CR0 |= SSI_CR0_RIE )
1674#define __ssi_disable_rxfifo_half_full_intr() \
1675    ( REG_SSI_CR0 &= ~SSI_CR0_RIE )
1676#define __ssi_enable_rx_error_intr() \
1677    ( REG_SSI_CR0 |= SSI_CR0_REIE )
1678#define __ssi_disable_rx_error_intr() \
1679    ( REG_SSI_CR0 &= ~SSI_CR0_REIE )
1680
1681#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
1682#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
1683
1684#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
1685#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
1686
1687#define __ssi_finish_receive() \
1688  ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
1689
1690#define __ssi_disable_recvfinish() \
1691  ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
1692
1693#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
1694#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
1695
1696#define __ssi_flush_fifo() \
1697  ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
1698
1699#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
1700#define __ssi_wait_transmit() ( REG_SSI_CR1 |= SSI_CR1_UNFIN )
1701
1702#define __ssi_spi_format() \
1703do { \
1704    REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
1705    REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
1706    REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
1707    REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
1708} while (0)
1709
1710/* TI's SSP format, must clear SSI_CR1.UNFIN */
1711#define __ssi_ssp_format() \
1712do { \
1713    REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
1714    REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
1715} while (0)
1716
1717/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
1718#define __ssi_microwire_format() \
1719do { \
1720    REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
1721    REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
1722    REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
1723    REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
1724    REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
1725} while (0)
1726
1727/* CE# level (FRMHL), CE# in interval time (ITFRM),
1728   clock phase and polarity (PHA POL),
1729   interval time (SSIITR), interval characters/frame (SSIICR) */
1730
1731 /* frmhl,endian,mcom,flen,pha,pol MASK */
1732#define SSICR1_MISC_MASK \
1733    ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
1734    | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
1735
1736#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
1737do { \
1738    REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
1739    REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
1740         (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
1741             ((pha) << 1) | (pol); \
1742} while(0)
1743
1744/* Transfer with MSB or LSB first */
1745#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
1746#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
1747
1748#define __ssi_set_frame_length(n) \
1749    REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
1750
1751/* n = 1 - 16 */
1752#define __ssi_set_microwire_command_length(n) \
1753    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
1754
1755/* Set the clock phase for SPI */
1756#define __ssi_set_spi_clock_phase(n) \
1757    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | ((n&0x1)<< 1)))
1758
1759/* Set the clock polarity for SPI */
1760#define __ssi_set_spi_clock_polarity(n) \
1761    ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
1762
1763/* n = ix8 */
1764#define __ssi_set_tx_trigger(n) \
1765do { \
1766    REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
1767    REG_SSI_CR1 |= (n/8)<<SSI_CR1_TTRG_BIT; \
1768} while (0)
1769
1770/* n = ix8 */
1771#define __ssi_set_rx_trigger(n) \
1772do { \
1773    REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
1774    REG_SSI_CR1 |= (n/8)<<SSI_CR1_RTRG_BIT; \
1775} while (0)
1776
1777#define __ssi_get_txfifo_count() \
1778    ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
1779
1780#define __ssi_get_rxfifo_count() \
1781    ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
1782
1783#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
1784#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
1785
1786#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
1787#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
1788#define __ssi_rxfifo_half_full() ( REG_SSI_SR & SSI_SR_RFHF )
1789#define __ssi_txfifo_half_empty() ( REG_SSI_SR & SSI_SR_TFHE )
1790#define __ssi_underrun() ( REG_SSI_SR & SSI_SR_UNDR )
1791#define __ssi_overrun() ( REG_SSI_SR & SSI_SR_OVER )
1792#define __ssi_clear_underrun() ( REG_SSI_SR = ~SSI_SR_UNDR )
1793#define __ssi_clear_overrun() ( REG_SSI_SR = ~SSI_SR_OVER )
1794#define __ssi_clear_errors() \
1795    ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
1796
1797
1798#define __ssi_set_clk(dev_clk, ssi_clk) \
1799  ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
1800
1801#define __ssi_receive_data() REG_SSI_DR
1802#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
1803
1804
1805/***************************************************************************
1806 * CIM
1807 ***************************************************************************/
1808
1809#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
1810#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
1811
1812#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
1813#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
1814
1815#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
1816#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
1817
1818#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
1819#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
1820
1821#define __cim_sample_data_at_pclk_falling_edge() \
1822  ( REG_CIM_CFG |= CIM_CFG_PCP )
1823#define __cim_sample_data_at_pclk_rising_edge() \
1824  ( REG_CIM_CFG &= ~CIM_CFG_PCP )
1825
1826#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
1827#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
1828
1829#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
1830#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
1831
1832/* n=0-7 */
1833#define __cim_set_data_packing_mode(n) \
1834do { \
1835    REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
1836    REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
1837} while (0)
1838
1839#define __cim_enable_ccir656_progressive_mode() \
1840do { \
1841    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1842    REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
1843} while (0)
1844
1845#define __cim_enable_ccir656_interlace_mode() \
1846do { \
1847    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1848    REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
1849} while (0)
1850
1851#define __cim_enable_gated_clock_mode() \
1852do { \
1853    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1854    REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
1855} while (0)
1856
1857#define __cim_enable_nongated_clock_mode() \
1858do { \
1859    REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1860    REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
1861} while (0)
1862
1863/* sclk:system bus clock
1864 * mclk: CIM master clock
1865 */
1866#define __cim_set_master_clk(sclk, mclk) \
1867do { \
1868    REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
1869    REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
1870} while (0)
1871
1872#define __cim_enable_sof_intr() \
1873  ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
1874#define __cim_disable_sof_intr() \
1875  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
1876
1877#define __cim_enable_eof_intr() \
1878  ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
1879#define __cim_disable_eof_intr() \
1880  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
1881
1882#define __cim_enable_stop_intr() \
1883  ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
1884#define __cim_disable_stop_intr() \
1885  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
1886
1887#define __cim_enable_trig_intr() \
1888  ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
1889#define __cim_disable_trig_intr() \
1890  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
1891
1892#define __cim_enable_rxfifo_overflow_intr() \
1893  ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
1894#define __cim_disable_rxfifo_overflow_intr() \
1895  ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
1896
1897/* n=1-16 */
1898#define __cim_set_frame_rate(n) \
1899do { \
1900    REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
1901    REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
1902} while (0)
1903
1904#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
1905#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
1906
1907#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
1908#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
1909
1910/* n=4,8,12,16,20,24,28,32 */
1911#define __cim_set_rxfifo_trigger(n) \
1912do { \
1913    REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
1914    REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
1915} while (0)
1916
1917#define __cim_clear_state() ( REG_CIM_STATE = 0 )
1918
1919#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
1920#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
1921#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
1922#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
1923#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
1924#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
1925#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
1926#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
1927
1928#define __cim_get_iid() ( REG_CIM_IID )
1929#define __cim_get_image_data() ( REG_CIM_RXFIFO )
1930#define __cim_get_dam_cmd() ( REG_CIM_CMD )
1931
1932#define __cim_set_da(a) ( REG_CIM_DA = (a) )
1933
1934/***************************************************************************
1935 * LCD
1936 ***************************************************************************/
1937#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
1938#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
1939
1940#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
1941#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
1942
1943#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
1944#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
1945
1946/* n=1,2,4,8,16 */
1947#define __lcd_set_bpp(n) \
1948  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
1949
1950/* n=4,8,16 */
1951#define __lcd_set_burst_length(n) \
1952do { \
1953    REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
1954    REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
1955} while (0)
1956
1957#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
1958#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
1959
1960#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
1961#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
1962
1963/* n=2,4,16 */
1964#define __lcd_set_stn_frc(n) \
1965do { \
1966    REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
1967    REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
1968} while (0)
1969
1970
1971#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
1972#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
1973
1974#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
1975#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
1976
1977#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
1978#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
1979
1980#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
1981#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
1982
1983#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
1984#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
1985
1986#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
1987#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
1988
1989#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
1990#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
1991
1992#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
1993#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
1994
1995#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
1996#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
1997
1998
1999/* LCD status register indication */
2000
2001#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
2002#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
2003#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
2004#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
2005#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
2006#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
2007#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
2008
2009#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
2010#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
2011#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
2012
2013#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
2014#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
2015
2016/* n=1,2,4,8 for single mono-STN
2017 * n=4,8 for dual mono-STN
2018 */
2019#define __lcd_set_panel_datawidth(n) \
2020do { \
2021    REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
2022    REG_LCD_CFG |= LCD_CFG_PDW_n##; \
2023} while (0)
2024
2025/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
2026#define __lcd_set_panel_mode(m) \
2027do { \
2028    REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
2029    REG_LCD_CFG |= (m); \
2030} while(0)
2031
2032/* n = 0-255 */
2033#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
2034#define __lcd_set_ac_bias(n) \
2035do { \
2036    REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
2037    REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
2038} while(0)
2039
2040#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
2041#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
2042
2043#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
2044#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
2045
2046#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
2047#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
2048
2049#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
2050#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
2051
2052#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
2053#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
2054
2055#define __lcd_vsync_get_vps() \
2056  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
2057
2058#define __lcd_vsync_get_vpe() \
2059  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
2060#define __lcd_vsync_set_vpe(n) \
2061do { \
2062    REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
2063    REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
2064} while (0)
2065
2066#define __lcd_hsync_get_hps() \
2067  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
2068#define __lcd_hsync_set_hps(n) \
2069do { \
2070    REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
2071    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
2072} while (0)
2073
2074#define __lcd_hsync_get_hpe() \
2075  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
2076#define __lcd_hsync_set_hpe(n) \
2077do { \
2078    REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
2079    REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
2080} while (0)
2081
2082#define __lcd_vat_get_ht() \
2083  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
2084#define __lcd_vat_set_ht(n) \
2085do { \
2086    REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
2087    REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
2088} while (0)
2089
2090#define __lcd_vat_get_vt() \
2091  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
2092#define __lcd_vat_set_vt(n) \
2093do { \
2094    REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
2095    REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
2096} while (0)
2097
2098#define __lcd_dah_get_hds() \
2099  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
2100#define __lcd_dah_set_hds(n) \
2101do { \
2102    REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
2103    REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
2104} while (0)
2105
2106#define __lcd_dah_get_hde() \
2107  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
2108#define __lcd_dah_set_hde(n) \
2109do { \
2110    REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
2111    REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
2112} while (0)
2113
2114#define __lcd_dav_get_vds() \
2115  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
2116#define __lcd_dav_set_vds(n) \
2117do { \
2118    REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
2119    REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
2120} while (0)
2121
2122#define __lcd_dav_get_vde() \
2123  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
2124#define __lcd_dav_set_vde(n) \
2125do { \
2126    REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
2127    REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
2128} while (0)
2129
2130#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
2131#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
2132#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
2133#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
2134
2135#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
2136#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
2137#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
2138#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
2139
2140#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
2141#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
2142
2143#define __lcd_cmd0_get_len() \
2144  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
2145#define __lcd_cmd1_get_len() \
2146  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
2147
2148/*******************************************************
2149 * SMART LCD
2150 *******************************************************/
2151
2152#define __slcd_dma_enable() (REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN)
2153#define __slcd_dma_disable() \
2154do {\
2155    while (REG_SLCD_STATE & SLCD_STATE_BUSY); \
2156    REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; \
2157} while(0)
2158
2159/*******************************************************
2160 * SMART LCD
2161 *******************************************************/
2162
2163#define __slcd_dma_enable() (REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN)
2164#define __slcd_dma_disable() \
2165do {\
2166    while (REG_SLCD_STATE & SLCD_STATE_BUSY); \
2167    REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; \
2168} while(0)
2169
2170/***************************************************************************
2171 * RTC ops
2172 ***************************************************************************/
2173
2174#define __rtc_write_ready() ( (REG_RTC_RCR & RTC_RCR_WRDY) >> RTC_RCR_WRDY_BIT )
2175#define __rtc_enabled() ( REG_RTC_RCR |= RTC_RCR_RTCE )
2176#define __rtc_disabled() ( REG_RTC_RCR &= ~RTC_RCR_RTCE )
2177#define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE )
2178#define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE )
2179#define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE )
2180#define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE )
2181#define __rtc_enable_1Hz_irq() ( REG_RTC_RCR |= RTC_RCR_1HZIE )
2182#define __rtc_disable_1Hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_1HZIE )
2183
2184#define __rtc_get_1Hz_flag() ( (REG_RTC_RCR >> RTC_RCR_1HZ_BIT) & 0x1 )
2185#define __rtc_clear_1Hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_1HZ )
2186#define __rtc_get_alarm_flag() ( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 )
2187#define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF )
2188
2189#define __rtc_get_second() ( REG_RTC_RSR )
2190#define __rtc_set_second(v) ( REG_RTC_RSR = v )
2191
2192#define __rtc_get_alarm_second() ( REG_RTC_RSAR )
2193#define __rtc_set_alarm_second(v) ( REG_RTC_RSAR = v )
2194
2195#define __rtc_RGR_is_locked() ( (REG_RTC_RGR >> RTC_RGR_LOCK) )
2196#define __rtc_lock_RGR() ( REG_RTC_RGR |= RTC_RGR_LOCK )
2197#define __rtc_unlock_RGR() ( REG_RTC_RGR &= ~RTC_RGR_LOCK )
2198#define __rtc_get_adjc_val() ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT )
2199#define __rtc_set_adjc_val(v) \
2200       ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) ))
2201#define __rtc_get_nc1Hz_val() ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
2202#define __rtc_set_nc1Hz_val(v) \
2203       ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) ))
2204
2205#define __rtc_power_down() ( REG_RTC_HCR |= RTC_HCR_PD )
2206
2207#define __rtc_get_hwfcr_val() ( REG_RTC_HWFCR & RTC_HWFCR_MASK )
2208#define __rtc_set_hwfcr_val(v) ( REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK )
2209#define __rtc_get_hrcr_val() ( REG_RTC_HRCR & RTC_HRCR_MASK )
2210#define __rtc_set_hrcr_val(v) ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK )
2211
2212#define __rtc_enable_alarm_wakeup() ( REG_RTC_HWCR |= RTC_HWCR_EALM )
2213#define __rtc_disable_alarm_wakeup() ( REG_RTC_HWCR &= ~RTC_HWCR_EALM )
2214
2215#define __rtc_status_hib_reset_occur() ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 )
2216#define __rtc_status_ppr_reset_occur() ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 )
2217#define __rtc_status_wakeup_pin_waken_up() ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 )
2218#define __rtc_status_alarm_waken_up() ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 )
2219#define __rtc_clear_hib_stat_all() ( REG_RTC_HWRSR = 0 )
2220
2221#define __rtc_get_scratch_pattern() (REG_RTC_HSPR)
2222#define __rtc_set_scratch_pattern(n) (REG_RTC_HSPR = n )
2223
2224
2225
2226#endif /* __JZ4740_OPS_H__ */
arch/mips/include/asm/mach-jz4740/platform.h
1
2#ifndef __JZ4740_PLATFORM_H
3#define __JZ4740_PLATFORM_H
4
5#include <linux/platform_device.h>
6
7extern struct platform_device jz4740_usb_ohci_device;
8extern struct platform_device jz4740_usb_gdt_device;
9extern struct platform_device jz4740_mmc_device;
10extern struct platform_device jz4740_rtc_device;
11extern struct platform_device jz4740_i2c_device;
12extern struct platform_device jz4740_nand_device;
13extern struct platform_device jz4740_framebuffer_device;
14extern struct platform_device jz4740_i2s_device;
15extern struct platform_device jz4740_codec_device;
16extern struct platform_device jz4740_adc_device;
17extern struct platform_device jz4740_battery_device;
18
19#endif
arch/mips/include/asm/mach-jz4740/regs.h
1/*
2 * linux/include/asm-mips/mach-jz4740/regs.h
3 *
4 * Ingenic's JZ4740 common include.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <yliu@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __JZ4740_REGS_H__
16#define __JZ4740_REGS_H__
17
18#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)
19#define REG8(addr) (addr)
20#define REG16(addr) (addr)
21#define REG32(addr) (addr)
22#else
23#define REG8(addr) *((volatile unsigned char *)(addr))
24#define REG16(addr) *((volatile unsigned short *)(addr))
25#define REG32(addr) *((volatile unsigned int *)(addr))
26#endif
27
28/*
29 * Define the module base addresses
30 */
31#define CPM_BASE 0xB0000000
32#define INTC_BASE 0xB0001000
33#define TCU_BASE 0xB0002000
34#define WDT_BASE 0xB0002000
35#define RTC_BASE 0xB0003000
36#define GPIO_BASE 0xB0010000
37#define AIC_BASE 0xB0020000
38#define ICDC_BASE 0xB0020000
39#define MSC_BASE 0xB0021000
40#define UART0_BASE 0xB0030000
41#define UART1_BASE 0xB0031000
42#define I2C_BASE 0xB0042000
43#define SSI_BASE 0xB0043000
44#define SADC_BASE 0xB0070000
45#define EMC_BASE 0xB3010000
46#define DMAC_BASE 0xB3020000
47#define UHC_BASE 0xB3030000
48#define UDC_BASE 0xB3040000
49#define LCD_BASE 0xB3050000
50#define SLCD_BASE 0xB3050000
51#define CIM_BASE 0xB3060000
52#define IPU_BASE 0xB3080000
53#define ETH_BASE 0xB3100000
54
55
56/*************************************************************************
57 * INTC (Interrupt Controller)
58 *************************************************************************/
59#define INTC_ISR (INTC_BASE + 0x00)
60#define INTC_IMR (INTC_BASE + 0x04)
61#define INTC_IMSR (INTC_BASE + 0x08)
62#define INTC_IMCR (INTC_BASE + 0x0c)
63#define INTC_IPR (INTC_BASE + 0x10)
64
65#define REG_INTC_ISR REG32(INTC_ISR)
66#define REG_INTC_IMR REG32(INTC_IMR)
67#define REG_INTC_IMSR REG32(INTC_IMSR)
68#define REG_INTC_IMCR REG32(INTC_IMCR)
69#define REG_INTC_IPR REG32(INTC_IPR)
70
71#define NUM_DMA 6
72#define NUM_GPIO 128
73/*************************************************************************
74 * RTC
75 *************************************************************************/
76#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
77#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
78#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
79#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
80
81#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
82#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
83#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
84#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
85#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
86#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
87
88#define REG_RTC_RCR REG32(RTC_RCR)
89#define REG_RTC_RSR REG32(RTC_RSR)
90#define REG_RTC_RSAR REG32(RTC_RSAR)
91#define REG_RTC_RGR REG32(RTC_RGR)
92#define REG_RTC_HCR REG32(RTC_HCR)
93#define REG_RTC_HWFCR REG32(RTC_HWFCR)
94#define REG_RTC_HRCR REG32(RTC_HRCR)
95#define REG_RTC_HWCR REG32(RTC_HWCR)
96#define REG_RTC_HWRSR REG32(RTC_HWRSR)
97#define REG_RTC_HSPR REG32(RTC_HSPR)
98
99/* RTC Control Register */
100#define RTC_RCR_WRDY_BIT 7
101#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
102#define RTC_RCR_1HZ_BIT 6
103#define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */
104#define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */
105#define RTC_RCR_AF_BIT 4
106#define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */
107#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
108#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
109#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
110
111/* RTC Regulator Register */
112#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
113#define RTC_RGR_ADJC_BIT 16
114#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
115#define RTC_RGR_NC1HZ_BIT 0
116#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
117
118/* Hibernate Control Register */
119#define RTC_HCR_PD (1 << 0) /* Power Down */
120
121/* Hibernate Wakeup Filter Counter Register */
122#define RTC_HWFCR_BIT 5
123#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
124
125/* Hibernate Reset Counter Register */
126#define RTC_HRCR_BIT 5
127#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
128
129/* Hibernate Wakeup Control Register */
130#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
131
132/* Hibernate Wakeup Status Register */
133#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
134#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
135#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
136#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
137
138
139/*************************************************************************
140 * CPM (Clock reset and Power control Management)
141 *************************************************************************/
142#define CPM_CPCCR (CPM_BASE+0x00)
143#define CPM_CPPCR (CPM_BASE+0x10)
144#define CPM_I2SCDR (CPM_BASE+0x60)
145#define CPM_LPCDR (CPM_BASE+0x64)
146#define CPM_MSCCDR (CPM_BASE+0x68)
147#define CPM_UHCCDR (CPM_BASE+0x6C)
148#define CPM_SSICDR (CPM_BASE+0x74)
149
150#define CPM_LCR (CPM_BASE+0x04)
151#define CPM_CLKGR (CPM_BASE+0x20)
152#define CPM_SCR (CPM_BASE+0x24)
153
154#define CPM_HCR (CPM_BASE+0x30)
155#define CPM_HWFCR (CPM_BASE+0x34)
156#define CPM_HRCR (CPM_BASE+0x38)
157#define CPM_HWCR (CPM_BASE+0x3c)
158#define CPM_HWSR (CPM_BASE+0x40)
159#define CPM_HSPR (CPM_BASE+0x44)
160
161#define CPM_RSR (CPM_BASE+0x08)
162
163
164#define REG_CPM_CPCCR REG32(CPM_CPCCR)
165#define REG_CPM_CPPCR REG32(CPM_CPPCR)
166#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
167#define REG_CPM_LPCDR REG32(CPM_LPCDR)
168#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
169#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
170#define REG_CPM_SSICDR REG32(CPM_SSICDR)
171
172#define REG_CPM_LCR REG32(CPM_LCR)
173#define REG_CPM_CLKGR REG32(CPM_CLKGR)
174#define REG_CPM_SCR REG32(CPM_SCR)
175#define REG_CPM_HCR REG32(CPM_HCR)
176#define REG_CPM_HWFCR REG32(CPM_HWFCR)
177#define REG_CPM_HRCR REG32(CPM_HRCR)
178#define REG_CPM_HWCR REG32(CPM_HWCR)
179#define REG_CPM_HWSR REG32(CPM_HWSR)
180#define REG_CPM_HSPR REG32(CPM_HSPR)
181
182#define REG_CPM_RSR REG32(CPM_RSR)
183
184
185/* Clock Control Register */
186#define CPM_CPCCR_I2CS (1 << 31)
187#define CPM_CPCCR_CLKOEN (1 << 30)
188#define CPM_CPCCR_UCS (1 << 29)
189#define CPM_CPCCR_UDIV_BIT 23
190#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
191#define CPM_CPCCR_CE (1 << 22)
192#define CPM_CPCCR_PCS (1 << 21)
193#define CPM_CPCCR_LDIV_BIT 16
194#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
195#define CPM_CPCCR_MDIV_BIT 12
196#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
197#define CPM_CPCCR_PDIV_BIT 8
198#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
199#define CPM_CPCCR_HDIV_BIT 4
200#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
201#define CPM_CPCCR_CDIV_BIT 0
202#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
203
204/* I2S Clock Divider Register */
205#define CPM_I2SCDR_I2SDIV_BIT 0
206#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
207
208/* LCD Pixel Clock Divider Register */
209#define CPM_LPCDR_PIXDIV_BIT 0
210#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
211
212/* MSC Clock Divider Register */
213#define CPM_MSCCDR_MSCDIV_BIT 0
214#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
215
216/* UHC Clock Divider Register */
217#define CPM_UHCCDR_UHCDIV_BIT 0
218#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
219
220/* SSI Clock Divider Register */
221#define CPM_SSICDR_SCS (1<<31) /* SSI clock source selection, 0:EXCLK, 1: PLL */
222#define CPM_SSICDR_SSIDIV_BIT 0
223#define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT)
224
225/* PLL Control Register */
226#define CPM_CPPCR_PLLM_BIT 23
227#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
228#define CPM_CPPCR_PLLN_BIT 18
229#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
230#define CPM_CPPCR_PLLOD_BIT 16
231#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
232#define CPM_CPPCR_PLLS (1 << 10)
233#define CPM_CPPCR_PLLBP (1 << 9)
234#define CPM_CPPCR_PLLEN (1 << 8)
235#define CPM_CPPCR_PLLST_BIT 0
236#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
237
238/* Low Power Control Register */
239#define CPM_LCR_DOZE_DUTY_BIT 3
240#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
241#define CPM_LCR_DOZE_ON (1 << 2)
242#define CPM_LCR_LPM_BIT 0
243#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
244  #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
245  #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
246
247/* Clock Gate Register */
248#define CPM_CLKGR_UART1 (1 << 15)
249#define CPM_CLKGR_UHC (1 << 14)
250#define CPM_CLKGR_IPU (1 << 13)
251#define CPM_CLKGR_DMAC (1 << 12)
252#define CPM_CLKGR_UDC (1 << 11)
253#define CPM_CLKGR_LCD (1 << 10)
254#define CPM_CLKGR_CIM (1 << 9)
255#define CPM_CLKGR_SADC (1 << 8)
256#define CPM_CLKGR_MSC (1 << 7)
257#define CPM_CLKGR_AIC1 (1 << 6)
258#define CPM_CLKGR_AIC2 (1 << 5)
259#define CPM_CLKGR_SSI (1 << 4)
260#define CPM_CLKGR_I2C (1 << 3)
261#define CPM_CLKGR_RTC (1 << 2)
262#define CPM_CLKGR_TCU (1 << 1)
263#define CPM_CLKGR_UART0 (1 << 0)
264
265/* Sleep Control Register */
266#define CPM_SCR_O1ST_BIT 8
267#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
268#define CPM_SCR_USBPHY_ENABLE (1 << 6)
269#define CPM_SCR_OSC_ENABLE (1 << 4)
270
271/* Hibernate Control Register */
272#define CPM_HCR_PD (1 << 0)
273
274/* Wakeup Filter Counter Register in Hibernate Mode */
275#define CPM_HWFCR_TIME_BIT 0
276#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
277
278/* Reset Counter Register in Hibernate Mode */
279#define CPM_HRCR_TIME_BIT 0
280#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
281
282/* Wakeup Control Register in Hibernate Mode */
283#define CPM_HWCR_WLE_LOW (0 << 2)
284#define CPM_HWCR_WLE_HIGH (1 << 2)
285#define CPM_HWCR_PIN_WAKEUP (1 << 1)
286#define CPM_HWCR_RTC_WAKEUP (1 << 0)
287
288/* Wakeup Status Register in Hibernate Mode */
289#define CPM_HWSR_WSR_PIN (1 << 1)
290#define CPM_HWSR_WSR_RTC (1 << 0)
291
292/* Reset Status Register */
293#define CPM_RSR_HR (1 << 2)
294#define CPM_RSR_WR (1 << 1)
295#define CPM_RSR_PR (1 << 0)
296
297
298/*************************************************************************
299 * TCU (Timer Counter Unit)
300 *************************************************************************/
301#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
302#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
303#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
304#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
305#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
306#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
307#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
308#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
309#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
310#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
311#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
312#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
313#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
314#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
315#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
316#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
317#define TCU_TDFR1 (TCU_BASE + 0x50)
318#define TCU_TDHR1 (TCU_BASE + 0x54)
319#define TCU_TCNT1 (TCU_BASE + 0x58)
320#define TCU_TCSR1 (TCU_BASE + 0x5C)
321#define TCU_TDFR2 (TCU_BASE + 0x60)
322#define TCU_TDHR2 (TCU_BASE + 0x64)
323#define TCU_TCNT2 (TCU_BASE + 0x68)
324#define TCU_TCSR2 (TCU_BASE + 0x6C)
325#define TCU_TDFR3 (TCU_BASE + 0x70)
326#define TCU_TDHR3 (TCU_BASE + 0x74)
327#define TCU_TCNT3 (TCU_BASE + 0x78)
328#define TCU_TCSR3 (TCU_BASE + 0x7C)
329#define TCU_TDFR4 (TCU_BASE + 0x80)
330#define TCU_TDHR4 (TCU_BASE + 0x84)
331#define TCU_TCNT4 (TCU_BASE + 0x88)
332#define TCU_TCSR4 (TCU_BASE + 0x8C)
333#define TCU_TDFR5 (TCU_BASE + 0x90)
334#define TCU_TDHR5 (TCU_BASE + 0x94)
335#define TCU_TCNT5 (TCU_BASE + 0x98)
336#define TCU_TCSR5 (TCU_BASE + 0x9C)
337
338#define REG_TCU_TSR REG32(TCU_TSR)
339#define REG_TCU_TSSR REG32(TCU_TSSR)
340#define REG_TCU_TSCR REG32(TCU_TSCR)
341#define REG_TCU_TER REG8(TCU_TER)
342#define REG_TCU_TESR REG8(TCU_TESR)
343#define REG_TCU_TECR REG8(TCU_TECR)
344#define REG_TCU_TFR REG32(TCU_TFR)
345#define REG_TCU_TFSR REG32(TCU_TFSR)
346#define REG_TCU_TFCR REG32(TCU_TFCR)
347#define REG_TCU_TMR REG32(TCU_TMR)
348#define REG_TCU_TMSR REG32(TCU_TMSR)
349#define REG_TCU_TMCR REG32(TCU_TMCR)
350#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
351#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
352#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
353#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
354#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
355#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
356#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
357#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
358#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
359#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
360#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
361#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
362#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
363#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
364#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
365#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
366#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
367#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
368#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
369#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
370
371// n = 0,1,2,3,4,5
372#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
373#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
374#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
375#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
376
377#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
378#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
379#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
380#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
381
382// Register definitions
383#define TCU_TCSR_PWM_SD (1 << 9)
384#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
385#define TCU_TCSR_PWM_EN (1 << 7)
386#define TCU_TCSR_PRESCALE_BIT 3
387#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
388  #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
389  #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
390  #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
391  #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
392  #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
393  #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
394#define TCU_TCSR_EXT_EN (1 << 2)
395#define TCU_TCSR_RTC_EN (1 << 1)
396#define TCU_TCSR_PCK_EN (1 << 0)
397
398#define TCU_TER_TCEN5 (1 << 5)
399#define TCU_TER_TCEN4 (1 << 4)
400#define TCU_TER_TCEN3 (1 << 3)
401#define TCU_TER_TCEN2 (1 << 2)
402#define TCU_TER_TCEN1 (1 << 1)
403#define TCU_TER_TCEN0 (1 << 0)
404
405#define TCU_TESR_TCST5 (1 << 5)
406#define TCU_TESR_TCST4 (1 << 4)
407#define TCU_TESR_TCST3 (1 << 3)
408#define TCU_TESR_TCST2 (1 << 2)
409#define TCU_TESR_TCST1 (1 << 1)
410#define TCU_TESR_TCST0 (1 << 0)
411
412#define TCU_TECR_TCCL5 (1 << 5)
413#define TCU_TECR_TCCL4 (1 << 4)
414#define TCU_TECR_TCCL3 (1 << 3)
415#define TCU_TECR_TCCL2 (1 << 2)
416#define TCU_TECR_TCCL1 (1 << 1)
417#define TCU_TECR_TCCL0 (1 << 0)
418
419#define TCU_TFR_HFLAG5 (1 << 21)
420#define TCU_TFR_HFLAG4 (1 << 20)
421#define TCU_TFR_HFLAG3 (1 << 19)
422#define TCU_TFR_HFLAG2 (1 << 18)
423#define TCU_TFR_HFLAG1 (1 << 17)
424#define TCU_TFR_HFLAG0 (1 << 16)
425#define TCU_TFR_FFLAG5 (1 << 5)
426#define TCU_TFR_FFLAG4 (1 << 4)
427#define TCU_TFR_FFLAG3 (1 << 3)
428#define TCU_TFR_FFLAG2 (1 << 2)
429#define TCU_TFR_FFLAG1 (1 << 1)
430#define TCU_TFR_FFLAG0 (1 << 0)
431
432#define TCU_TFSR_HFLAG5 (1 << 21)
433#define TCU_TFSR_HFLAG4 (1 << 20)
434#define TCU_TFSR_HFLAG3 (1 << 19)
435#define TCU_TFSR_HFLAG2 (1 << 18)
436#define TCU_TFSR_HFLAG1 (1 << 17)
437#define TCU_TFSR_HFLAG0 (1 << 16)
438#define TCU_TFSR_FFLAG5 (1 << 5)
439#define TCU_TFSR_FFLAG4 (1 << 4)
440#define TCU_TFSR_FFLAG3 (1 << 3)
441#define TCU_TFSR_FFLAG2 (1 << 2)
442#define TCU_TFSR_FFLAG1 (1 << 1)
443#define TCU_TFSR_FFLAG0 (1 << 0)
444
445#define TCU_TFCR_HFLAG5 (1 << 21)
446#define TCU_TFCR_HFLAG4 (1 << 20)
447#define TCU_TFCR_HFLAG3 (1 << 19)
448#define TCU_TFCR_HFLAG2 (1 << 18)
449#define TCU_TFCR_HFLAG1 (1 << 17)
450#define TCU_TFCR_HFLAG0 (1 << 16)
451#define TCU_TFCR_FFLAG5 (1 << 5)
452#define TCU_TFCR_FFLAG4 (1 << 4)
453#define TCU_TFCR_FFLAG3 (1 << 3)
454#define TCU_TFCR_FFLAG2 (1 << 2)
455#define TCU_TFCR_FFLAG1 (1 << 1)
456#define TCU_TFCR_FFLAG0 (1 << 0)
457
458#define TCU_TMR_HMASK5 (1 << 21)
459#define TCU_TMR_HMASK4 (1 << 20)
460#define TCU_TMR_HMASK3 (1 << 19)
461#define TCU_TMR_HMASK2 (1 << 18)
462#define TCU_TMR_HMASK1 (1 << 17)
463#define TCU_TMR_HMASK0 (1 << 16)
464#define TCU_TMR_FMASK5 (1 << 5)
465#define TCU_TMR_FMASK4 (1 << 4)
466#define TCU_TMR_FMASK3 (1 << 3)
467#define TCU_TMR_FMASK2 (1 << 2)
468#define TCU_TMR_FMASK1 (1 << 1)
469#define TCU_TMR_FMASK0 (1 << 0)
470
471#define TCU_TMSR_HMST5 (1 << 21)
472#define TCU_TMSR_HMST4 (1 << 20)
473#define TCU_TMSR_HMST3 (1 << 19)
474#define TCU_TMSR_HMST2 (1 << 18)
475#define TCU_TMSR_HMST1 (1 << 17)
476#define TCU_TMSR_HMST0 (1 << 16)
477#define TCU_TMSR_FMST5 (1 << 5)
478#define TCU_TMSR_FMST4 (1 << 4)
479#define TCU_TMSR_FMST3 (1 << 3)
480#define TCU_TMSR_FMST2 (1 << 2)
481#define TCU_TMSR_FMST1 (1 << 1)
482#define TCU_TMSR_FMST0 (1 << 0)
483
484#define TCU_TMCR_HMCL5 (1 << 21)
485#define TCU_TMCR_HMCL4 (1 << 20)
486#define TCU_TMCR_HMCL3 (1 << 19)
487#define TCU_TMCR_HMCL2 (1 << 18)
488#define TCU_TMCR_HMCL1 (1 << 17)
489#define TCU_TMCR_HMCL0 (1 << 16)
490#define TCU_TMCR_FMCL5 (1 << 5)
491#define TCU_TMCR_FMCL4 (1 << 4)
492#define TCU_TMCR_FMCL3 (1 << 3)
493#define TCU_TMCR_FMCL2 (1 << 2)
494#define TCU_TMCR_FMCL1 (1 << 1)
495#define TCU_TMCR_FMCL0 (1 << 0)
496
497#define TCU_TSR_WDTS (1 << 16)
498#define TCU_TSR_STOP5 (1 << 5)
499#define TCU_TSR_STOP4 (1 << 4)
500#define TCU_TSR_STOP3 (1 << 3)
501#define TCU_TSR_STOP2 (1 << 2)
502#define TCU_TSR_STOP1 (1 << 1)
503#define TCU_TSR_STOP0 (1 << 0)
504
505#define TCU_TSSR_WDTSS (1 << 16)
506#define TCU_TSSR_STPS5 (1 << 5)
507#define TCU_TSSR_STPS4 (1 << 4)
508#define TCU_TSSR_STPS3 (1 << 3)
509#define TCU_TSSR_STPS2 (1 << 2)
510#define TCU_TSSR_STPS1 (1 << 1)
511#define TCU_TSSR_STPS0 (1 << 0)
512
513#define TCU_TSSR_WDTSC (1 << 16)
514#define TCU_TSSR_STPC5 (1 << 5)
515#define TCU_TSSR_STPC4 (1 << 4)
516#define TCU_TSSR_STPC3 (1 << 3)
517#define TCU_TSSR_STPC2 (1 << 2)
518#define TCU_TSSR_STPC1 (1 << 1)
519#define TCU_TSSR_STPC0 (1 << 0)
520
521
522/*************************************************************************
523 * WDT (WatchDog Timer)
524 *************************************************************************/
525#define WDT_TDR (WDT_BASE + 0x00)
526#define WDT_TCER (WDT_BASE + 0x04)
527#define WDT_TCNT (WDT_BASE + 0x08)
528#define WDT_TCSR (WDT_BASE + 0x0C)
529
530#define REG_WDT_TDR REG16(WDT_TDR)
531#define REG_WDT_TCER REG8(WDT_TCER)
532#define REG_WDT_TCNT REG16(WDT_TCNT)
533#define REG_WDT_TCSR REG16(WDT_TCSR)
534
535// Register definition
536#define WDT_TCSR_PRESCALE_BIT 3
537#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
538  #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
539  #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
540  #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
541  #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
542  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
543  #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
544#define WDT_TCSR_EXT_EN (1 << 2)
545#define WDT_TCSR_RTC_EN (1 << 1)
546#define WDT_TCSR_PCK_EN (1 << 0)
547
548#define WDT_TCER_TCEN (1 << 0)
549
550
551/*************************************************************************
552 * DMAC (DMA Controller)
553 *************************************************************************/
554
555#define MAX_DMA_NUM 6 /* max 6 channels */
556
557#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
558#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
559#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
560#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
561#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
562#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
563#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
564#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
565#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
566#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
567#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
568
569// channel 0
570#define DMAC_DSAR0 DMAC_DSAR(0)
571#define DMAC_DTAR0 DMAC_DTAR(0)
572#define DMAC_DTCR0 DMAC_DTCR(0)
573#define DMAC_DRSR0 DMAC_DRSR(0)
574#define DMAC_DCCSR0 DMAC_DCCSR(0)
575#define DMAC_DCMD0 DMAC_DCMD(0)
576#define DMAC_DDA0 DMAC_DDA(0)
577
578// channel 1
579#define DMAC_DSAR1 DMAC_DSAR(1)
580#define DMAC_DTAR1 DMAC_DTAR(1)
581#define DMAC_DTCR1 DMAC_DTCR(1)
582#define DMAC_DRSR1 DMAC_DRSR(1)
583#define DMAC_DCCSR1 DMAC_DCCSR(1)
584#define DMAC_DCMD1 DMAC_DCMD(1)
585#define DMAC_DDA1 DMAC_DDA(1)
586
587// channel 2
588#define DMAC_DSAR2 DMAC_DSAR(2)
589#define DMAC_DTAR2 DMAC_DTAR(2)
590#define DMAC_DTCR2 DMAC_DTCR(2)
591#define DMAC_DRSR2 DMAC_DRSR(2)
592#define DMAC_DCCSR2 DMAC_DCCSR(2)
593#define DMAC_DCMD2 DMAC_DCMD(2)
594#define DMAC_DDA2 DMAC_DDA(2)
595
596// channel 3
597#define DMAC_DSAR3 DMAC_DSAR(3)
598#define DMAC_DTAR3 DMAC_DTAR(3)
599#define DMAC_DTCR3 DMAC_DTCR(3)
600#define DMAC_DRSR3 DMAC_DRSR(3)
601#define DMAC_DCCSR3 DMAC_DCCSR(3)
602#define DMAC_DCMD3 DMAC_DCMD(3)
603#define DMAC_DDA3 DMAC_DDA(3)
604
605// channel 4
606#define DMAC_DSAR4 DMAC_DSAR(4)
607#define DMAC_DTAR4 DMAC_DTAR(4)
608#define DMAC_DTCR4 DMAC_DTCR(4)
609#define DMAC_DRSR4 DMAC_DRSR(4)
610#define DMAC_DCCSR4 DMAC_DCCSR(4)
611#define DMAC_DCMD4 DMAC_DCMD(4)
612#define DMAC_DDA4 DMAC_DDA(4)
613
614// channel 5
615#define DMAC_DSAR5 DMAC_DSAR(5)
616#define DMAC_DTAR5 DMAC_DTAR(5)
617#define DMAC_DTCR5 DMAC_DTCR(5)
618#define DMAC_DRSR5 DMAC_DRSR(5)
619#define DMAC_DCCSR5 DMAC_DCCSR(5)
620#define DMAC_DCMD5 DMAC_DCMD(5)
621#define DMAC_DDA5 DMAC_DDA(5)
622
623#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
624#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
625#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
626#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
627#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
628#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
629#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
630#define REG_DMAC_DMACR REG32(DMAC_DMACR)
631#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
632#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
633#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
634
635// DMA request source register
636#define DMAC_DRSR_RS_BIT 0
637#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
638  #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
639  #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
640  #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
641  #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
642  #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
643  #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
644  #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
645  #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
646  #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
647  #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
648  #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
649  #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
650
651// DMA channel control/status register
652#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
653#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
654#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
655#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
656#define DMAC_DCCSR_AR (1 << 4) /* address error */
657#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
658#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
659#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
660#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
661
662// DMA channel command register
663#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
664#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
665#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
666#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
667  #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
668  #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
669  #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
670  #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
671  #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
672  #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
673  #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
674  #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
675  #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
676  #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
677  #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
678  #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
679  #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
680  #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
681  #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
682  #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
683#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
684#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
685  #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
686  #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
687  #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
688#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
689#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
690  #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
691  #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
692  #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
693#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
694#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
695  #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
696  #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
697  #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
698  #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
699  #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
700#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
701#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
702#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
703#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
704#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
705#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
706
707// DMA descriptor address register
708#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
709#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
710#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
711#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
712
713// DMA control register
714#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
715#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
716  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
717  #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
718  #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
719  #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
720#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
721#define DMAC_DMACR_AR (1 << 2) /* address error flag */
722#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
723
724// DMA doorbell register
725#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
726#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
727#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
728#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
729#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
730#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
731
732// DMA doorbell set register
733#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
734#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
735#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
736#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
737#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
738#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
739
740// DMA interrupt pending register
741#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
742#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
743#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
744#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
745#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
746#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
747
748
749/*************************************************************************
750 * GPIO (General-Purpose I/O Ports)
751 *************************************************************************/
752#define MAX_GPIO_NUM 128
753
754//n = 0,1,2,3
755#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
756#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
757#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
758#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
759#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
760#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
761#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
762#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
763#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
764#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
765#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
766#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
767#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
768#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
769#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
770#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
771#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
772#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
773#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
774#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
775#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
776#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
777#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
778#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag Clear Register */
779
780#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
781#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
782#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
783#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
784#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
785#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
786#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
787#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
788#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
789#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
790#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
791#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
792#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
793#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
794#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
795#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
796#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
797#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
798#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
799#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
800#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
801#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
802#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
803#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
804
805
806/*************************************************************************
807 * UART
808 *************************************************************************/
809
810#define IRDA_BASE UART0_BASE
811#define UART_BASE UART0_BASE
812#define UART_OFF 0x1000
813
814/* Register Offset */
815#define OFF_RDR (0x00) /* R 8b H'xx */
816#define OFF_TDR (0x00) /* W 8b H'xx */
817#define OFF_DLLR (0x00) /* RW 8b H'00 */
818#define OFF_DLHR (0x04) /* RW 8b H'00 */
819#define OFF_IER (0x04) /* RW 8b H'00 */
820#define OFF_ISR (0x08) /* R 8b H'01 */
821#define OFF_FCR (0x08) /* W 8b H'00 */
822#define OFF_LCR (0x0C) /* RW 8b H'00 */
823#define OFF_MCR (0x10) /* RW 8b H'00 */
824#define OFF_LSR (0x14) /* R 8b H'00 */
825#define OFF_MSR (0x18) /* R 8b H'00 */
826#define OFF_SPR (0x1C) /* RW 8b H'00 */
827#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
828#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
829#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
830
831/* Register Address */
832#define UART0_RDR (UART0_BASE + OFF_RDR)
833#define UART0_TDR (UART0_BASE + OFF_TDR)
834#define UART0_DLLR (UART0_BASE + OFF_DLLR)
835#define UART0_DLHR (UART0_BASE + OFF_DLHR)
836#define UART0_IER (UART0_BASE + OFF_IER)
837#define UART0_ISR (UART0_BASE + OFF_ISR)
838#define UART0_FCR (UART0_BASE + OFF_FCR)
839#define UART0_LCR (UART0_BASE + OFF_LCR)
840#define UART0_MCR (UART0_BASE + OFF_MCR)
841#define UART0_LSR (UART0_BASE + OFF_LSR)
842#define UART0_MSR (UART0_BASE + OFF_MSR)
843#define UART0_SPR (UART0_BASE + OFF_SPR)
844#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
845#define UART0_UMR (UART0_BASE + OFF_UMR)
846#define UART0_UACR (UART0_BASE + OFF_UACR)
847
848/*
849 * Define macros for UARTIER
850 * UART Interrupt Enable Register
851 */
852#define UARTIER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
853#define UARTIER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
854#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
855#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
856#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
857
858/*
859 * Define macros for UARTISR
860 * UART Interrupt Status Register
861 */
862#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
863#define UARTISR_IID (7 << 1) /* Source of Interrupt */
864#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
865#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
866#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
867#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
868#define UARTISR_IID_RTO (6 << 1) /* Receive timeout */
869#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
870#define UARTISR_FFMS_NO_FIFO (0 << 6)
871#define UARTISR_FFMS_FIFO_MODE (3 << 6)
872
873/*
874 * Define macros for UARTFCR
875 * UART FIFO Control Register
876 */
877#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
878#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
879#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
880#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
881#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
882#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
883#define UARTFCR_RTRG_1 (0 << 6)
884#define UARTFCR_RTRG_4 (1 << 6)
885#define UARTFCR_RTRG_8 (2 << 6)
886#define UARTFCR_RTRG_15 (3 << 6)
887
888/*
889 * Define macros for UARTLCR
890 * UART Line Control Register
891 */
892#define UARTLCR_WLEN (3 << 0) /* word length */
893#define UARTLCR_WLEN_5 (0 << 0)
894#define UARTLCR_WLEN_6 (1 << 0)
895#define UARTLCR_WLEN_7 (2 << 0)
896#define UARTLCR_WLEN_8 (3 << 0)
897#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
898                       1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
899#define UARTLCR_STOP1 (0 << 2)
900#define UARTLCR_STOP2 (1 << 2)
901#define UARTLCR_PE (1 << 3) /* 0: parity disable */
902#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
903#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
904#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
905#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */
906
907/*
908 * Define macros for UARTLSR
909 * UART Line Status Register
910 */
911#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
912#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
913#define UARTLSR_PER (1 << 2) /* 0: no parity error */
914#define UARTLSR_FER (1 << 3) /* 0; no framing error */
915#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
916#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
917#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
918#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
919
920/*
921 * Define macros for UARTMCR
922 * UART Modem Control Register
923 */
924#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high, 1: RTS_ output low */
925#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
926#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
927
928/*
929 * Define macros for UARTMSR
930 * UART Modem Status Register
931 */
932#define UARTMSR_CCTS (1 << 0) /* 1: a change on CTS_ pin */
933#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
934
935/*
936 * Define macros for SIRCR
937 * Slow IrDA Control Register
938 */
939#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: SIR mode */
940#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: SIR mode */
941#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
942                       1: 0 pulse width is 1.6us for 115.2Kbps */
943#define SIRCR_TDPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
944#define SIRCR_RDPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
945
946
947/*************************************************************************
948 * AIC (AC97/I2S Controller)
949 *************************************************************************/
950#define AIC_FR (AIC_BASE + 0x000)
951#define AIC_CR (AIC_BASE + 0x004)
952#define AIC_ACCR1 (AIC_BASE + 0x008)
953#define AIC_ACCR2 (AIC_BASE + 0x00C)
954#define AIC_I2SCR (AIC_BASE + 0x010)
955#define AIC_SR (AIC_BASE + 0x014)
956#define AIC_ACSR (AIC_BASE + 0x018)
957#define AIC_I2SSR (AIC_BASE + 0x01C)
958#define AIC_ACCAR (AIC_BASE + 0x020)
959#define AIC_ACCDR (AIC_BASE + 0x024)
960#define AIC_ACSAR (AIC_BASE + 0x028)
961#define AIC_ACSDR (AIC_BASE + 0x02C)
962#define AIC_I2SDIV (AIC_BASE + 0x030)
963#define AIC_DR (AIC_BASE + 0x034)
964
965#define REG_AIC_FR REG32(AIC_FR)
966#define REG_AIC_CR REG32(AIC_CR)
967#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
968#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
969#define REG_AIC_I2SCR REG32(AIC_I2SCR)
970#define REG_AIC_SR REG32(AIC_SR)
971#define REG_AIC_ACSR REG32(AIC_ACSR)
972#define REG_AIC_I2SSR REG32(AIC_I2SSR)
973#define REG_AIC_ACCAR REG32(AIC_ACCAR)
974#define REG_AIC_ACCDR REG32(AIC_ACCDR)
975#define REG_AIC_ACSAR REG32(AIC_ACSAR)
976#define REG_AIC_ACSDR REG32(AIC_ACSDR)
977#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
978#define REG_AIC_DR REG32(AIC_DR)
979
980/* AIC Controller Configuration Register (AIC_FR) */
981
982#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
983#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
984#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
985#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
986#define AIC_FR_LSMP (1 << 6) /* Play Zero sample or last sample */
987#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
988#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
989#define AIC_FR_RST (1 << 3) /* AIC registers reset */
990#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
991#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
992#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
993
994/* AIC Controller Common Control Register (AIC_CR) */
995
996#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
997#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
998  #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
999  #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1000  #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1001  #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1002  #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1003#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1004#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1005  #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1006  #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1007  #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1008  #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1009  #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1010#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1011#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1012#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1013#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1014#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1015#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1016#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1017#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1018#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1019#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1020#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1021#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1022#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1023
1024/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1025
1026#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1027#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1028  #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1029  #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1030  #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1031  #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1032  #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1033  #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1034  #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1035  #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1036  #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1037  #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1038#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1039#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1040  #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1041  #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1042  #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1043  #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1044  #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1045  #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1046  #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1047  #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1048  #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1049  #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1050
1051/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1052
1053#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1054#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1055#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1056#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1057#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1058  #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1059  #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1060  #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1061  #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1062#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1063#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1064  #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1065  #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1066  #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1067  #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1068#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1069#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1070#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1071#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1072
1073/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1074
1075#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1076#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1077#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1078  #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1079  #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1080  #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1081  #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1082  #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1083#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1084
1085/* AIC Controller FIFO Status Register (AIC_SR) */
1086
1087#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1088#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1089#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1090#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1091#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1092#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1093#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1094#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1095
1096/* AIC Controller AC-link Status Register (AIC_ACSR) */
1097
1098#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1099#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1100#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1101#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1102#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1103#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1104
1105/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1106
1107#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1108
1109/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1110
1111#define AIC_ACCAR_CAR_BIT 0
1112#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1113
1114/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1115
1116#define AIC_ACCDR_CDR_BIT 0
1117#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1118
1119/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1120
1121#define AIC_ACSAR_SAR_BIT 0
1122#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1123
1124/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1125
1126#define AIC_ACSDR_SDR_BIT 0
1127#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1128
1129/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1130
1131#define AIC_I2SDIV_DIV_BIT 0
1132#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1133  #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1134  #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1135  #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1136  #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1137  #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1138  #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1139
1140
1141/*************************************************************************
1142 * ICDC (Internal CODEC)
1143 *************************************************************************/
1144#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1145#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1146#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1147#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1148#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1149#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1150#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1151
1152#define REG_ICDC_CR REG32(ICDC_CR)
1153#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1154#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1155#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1156#define REG_ICDC_APSR REG32(ICDC_APSR)
1157#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1158#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1159
1160/* ICDC Control Register */
1161#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1162#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1163#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1164#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1165  #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1166  #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1167  #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1168  #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1169  #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1170  #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1171  #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1172  #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1173  #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1174#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1175#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1176  #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1177  #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1178  #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1179  #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1180#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1181#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1182  #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1183  #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1184  #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1185  #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1186#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1187#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1188#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1189#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1190#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1191#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1192#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1193#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1194#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1195#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1196#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1197#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1198
1199/* Anti-Pop WAIT Stage Timing Control Register */
1200#define ICDC_APWAIT_WAITSN_BIT 0
1201#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1202
1203/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1204#define ICDC_APPRE_PRESN_BIT 0
1205#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1206
1207/* Anti-Pop HPEN Stage Timing Control Register */
1208#define ICDC_APHPEN_HPENSN_BIT 0
1209#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1210
1211/* Anti-Pop Status Register */
1212#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1213#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1214#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1215#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1216  #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1217#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1218  #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1219  #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1220  #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1221  #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1222#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1223#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1224
1225
1226/*************************************************************************
1227 * I2C
1228 *************************************************************************/
1229#define I2C_DR (I2C_BASE + 0x000)
1230#define I2C_CR (I2C_BASE + 0x004)
1231#define I2C_SR (I2C_BASE + 0x008)
1232#define I2C_GR (I2C_BASE + 0x00C)
1233
1234#define REG_I2C_DR REG8(I2C_DR)
1235#define REG_I2C_CR REG8(I2C_CR)
1236#define REG_I2C_SR REG8(I2C_SR)
1237#define REG_I2C_GR REG16(I2C_GR)
1238
1239/* I2C Control Register (I2C_CR) */
1240
1241#define I2C_CR_IEN (1 << 4)
1242#define I2C_CR_STA (1 << 3)
1243#define I2C_CR_STO (1 << 2)
1244#define I2C_CR_AC (1 << 1)
1245#define I2C_CR_I2CE (1 << 0)
1246
1247/* I2C Status Register (I2C_SR) */
1248
1249#define I2C_SR_STX (1 << 4)
1250#define I2C_SR_BUSY (1 << 3)
1251#define I2C_SR_TEND (1 << 2)
1252#define I2C_SR_DRF (1 << 1)
1253#define I2C_SR_ACKF (1 << 0)
1254
1255
1256/*************************************************************************
1257 * SSI
1258 *************************************************************************/
1259#define SSI_DR (SSI_BASE + 0x000)
1260#define SSI_CR0 (SSI_BASE + 0x004)
1261#define SSI_CR1 (SSI_BASE + 0x008)
1262#define SSI_SR (SSI_BASE + 0x00C)
1263#define SSI_ITR (SSI_BASE + 0x010)
1264#define SSI_ICR (SSI_BASE + 0x014)
1265#define SSI_GR (SSI_BASE + 0x018)
1266
1267#define REG_SSI_DR REG32(SSI_DR)
1268#define REG_SSI_CR0 REG16(SSI_CR0)
1269#define REG_SSI_CR1 REG32(SSI_CR1)
1270#define REG_SSI_SR REG32(SSI_SR)
1271#define REG_SSI_ITR REG16(SSI_ITR)
1272#define REG_SSI_ICR REG8(SSI_ICR)
1273#define REG_SSI_GR REG16(SSI_GR)
1274
1275/* SSI Data Register (SSI_DR) */
1276
1277#define SSI_DR_GPC_BIT 0
1278#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1279
1280/* SSI Control Register 0 (SSI_CR0) */
1281
1282#define SSI_CR0_SSIE (1 << 15)
1283#define SSI_CR0_TIE (1 << 14)
1284#define SSI_CR0_RIE (1 << 13)
1285#define SSI_CR0_TEIE (1 << 12)
1286#define SSI_CR0_REIE (1 << 11)
1287#define SSI_CR0_LOOP (1 << 10)
1288#define SSI_CR0_RFINE (1 << 9)
1289#define SSI_CR0_RFINC (1 << 8)
1290#define SSI_CR0_FSEL (1 << 6)
1291#define SSI_CR0_TFLUSH (1 << 2)
1292#define SSI_CR0_RFLUSH (1 << 1)
1293#define SSI_CR0_DISREV (1 << 0)
1294
1295/* SSI Control Register 1 (SSI_CR1) */
1296
1297#define SSI_CR1_FRMHL_BIT 30
1298#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1299  #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1300  #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1301  #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1302  #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1303#define SSI_CR1_TFVCK_BIT 28
1304#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1305  #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1306  #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1307  #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1308  #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1309#define SSI_CR1_TCKFI_BIT 26
1310#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1311  #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1312  #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1313  #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1314  #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1315#define SSI_CR1_LFST (1 << 25)
1316#define SSI_CR1_ITFRM (1 << 24)
1317#define SSI_CR1_UNFIN (1 << 23)
1318#define SSI_CR1_MULTS (1 << 22)
1319#define SSI_CR1_FMAT_BIT 20
1320#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1321  #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1322  #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1323  #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1324  #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1325#define SSI_CR1_TTRG_BIT 16
1326#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1327  #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1328  #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1329  #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1330  #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1331  #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1332  #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1333  #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1334  #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1335  #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1336  #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1337  #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1338  #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1339  #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1340  #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1341  #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1342  #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1343#define SSI_CR1_MCOM_BIT 12
1344#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1345  #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1346  #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1347  #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1348  #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1349  #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1350  #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1351  #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1352  #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1353  #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1354  #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1355  #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1356  #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1357  #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1358  #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1359  #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1360  #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1361#define SSI_CR1_RTRG_BIT 8
1362#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1363  #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1364  #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1365  #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1366  #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1367  #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1368  #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1369  #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1370  #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1371  #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1372  #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1373  #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1374  #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1375  #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1376  #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1377  #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1378  #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1379#define SSI_CR1_FLEN_BIT 4
1380#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1381  #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1382  #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1383  #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1384  #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1385  #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1386  #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1387  #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1388  #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1389  #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1390  #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1391  #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1392  #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1393  #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1394  #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1395  #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1396  #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1397#define SSI_CR1_PHA (1 << 1)
1398#define SSI_CR1_POL (1 << 0)
1399
1400/* SSI Status Register (SSI_SR) */
1401
1402#define SSI_SR_TFIFONUM_BIT 16
1403#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1404#define SSI_SR_RFIFONUM_BIT 8
1405#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1406#define SSI_SR_END (1 << 7)
1407#define SSI_SR_BUSY (1 << 6)
1408#define SSI_SR_TFF (1 << 5)
1409#define SSI_SR_RFE (1 << 4)
1410#define SSI_SR_TFHE (1 << 3)
1411#define SSI_SR_RFHF (1 << 2)
1412#define SSI_SR_UNDR (1 << 1)
1413#define SSI_SR_OVER (1 << 0)
1414
1415/* SSI Interval Time Control Register (SSI_ITR) */
1416
1417#define SSI_ITR_CNTCLK (1 << 15)
1418#define SSI_ITR_IVLTM_BIT 0
1419#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1420
1421
1422/*************************************************************************
1423 * MSC
1424 *************************************************************************/
1425#define MSC_STRPCL (MSC_BASE + 0x000)
1426#define MSC_STAT (MSC_BASE + 0x004)
1427#define MSC_CLKRT (MSC_BASE + 0x008)
1428#define MSC_CMDAT (MSC_BASE + 0x00C)
1429#define MSC_RESTO (MSC_BASE + 0x010)
1430#define MSC_RDTO (MSC_BASE + 0x014)
1431#define MSC_BLKLEN (MSC_BASE + 0x018)
1432#define MSC_NOB (MSC_BASE + 0x01C)
1433#define MSC_SNOB (MSC_BASE + 0x020)
1434#define MSC_IMASK (MSC_BASE + 0x024)
1435#define MSC_IREG (MSC_BASE + 0x028)
1436#define MSC_CMD (MSC_BASE + 0x02C)
1437#define MSC_ARG (MSC_BASE + 0x030)
1438#define MSC_RES (MSC_BASE + 0x034)
1439#define MSC_RXFIFO (MSC_BASE + 0x038)
1440#define MSC_TXFIFO (MSC_BASE + 0x03C)
1441
1442#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1443#define REG_MSC_STAT REG32(MSC_STAT)
1444#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1445#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1446#define REG_MSC_RESTO REG16(MSC_RESTO)
1447#define REG_MSC_RDTO REG16(MSC_RDTO)
1448#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1449#define REG_MSC_NOB REG16(MSC_NOB)
1450#define REG_MSC_SNOB REG16(MSC_SNOB)
1451#define REG_MSC_IMASK REG16(MSC_IMASK)
1452#define REG_MSC_IREG REG16(MSC_IREG)
1453#define REG_MSC_CMD REG8(MSC_CMD)
1454#define REG_MSC_ARG REG32(MSC_ARG)
1455#define REG_MSC_RES REG16(MSC_RES)
1456#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1457#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1458
1459/* MSC Clock and Control Register (MSC_STRPCL) */
1460
1461#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1462#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1463#define MSC_STRPCL_START_READWAIT (1 << 5)
1464#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1465#define MSC_STRPCL_RESET (1 << 3)
1466#define MSC_STRPCL_START_OP (1 << 2)
1467#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1468#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1469  #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1470  #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1471
1472/* MSC Status Register (MSC_STAT) */
1473
1474#define MSC_STAT_IS_RESETTING (1 << 15)
1475#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1476#define MSC_STAT_PRG_DONE (1 << 13)
1477#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1478#define MSC_STAT_END_CMD_RES (1 << 11)
1479#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1480#define MSC_STAT_IS_READWAIT (1 << 9)
1481#define MSC_STAT_CLK_EN (1 << 8)
1482#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1483#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1484#define MSC_STAT_CRC_RES_ERR (1 << 5)
1485#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1486#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1487#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1488  #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1489  #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1490  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1491#define MSC_STAT_TIME_OUT_RES (1 << 1)
1492#define MSC_STAT_TIME_OUT_READ (1 << 0)
1493
1494/* MSC Bus Clock Control Register (MSC_CLKRT) */
1495
1496#define MSC_CLKRT_CLK_RATE_BIT 0
1497#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1498  #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1499  #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1500  #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1501  #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1502  #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1503  #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1504  #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1505  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1506
1507/* MSC Command Sequence Control Register (MSC_CMDAT) */
1508
1509#define MSC_CMDAT_IO_ABORT (1 << 11)
1510#define MSC_CMDAT_BUS_WIDTH_BIT 9
1511#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1512  #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1513  #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1514  #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1515  #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1516#define MSC_CMDAT_DMA_EN (1 << 8)
1517#define MSC_CMDAT_INIT (1 << 7)
1518#define MSC_CMDAT_BUSY (1 << 6)
1519#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1520#define MSC_CMDAT_WRITE (1 << 4)
1521#define MSC_CMDAT_READ (0 << 4)
1522#define MSC_CMDAT_DATA_EN (1 << 3)
1523#define MSC_CMDAT_RESPONSE_BIT 0
1524#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1525  #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1526  #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1527  #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1528  #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1529  #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1530  #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1531  #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1532
1533#define CMDAT_DMA_EN (1 << 8)
1534#define CMDAT_INIT (1 << 7)
1535#define CMDAT_BUSY (1 << 6)
1536#define CMDAT_STREAM (1 << 5)
1537#define CMDAT_WRITE (1 << 4)
1538#define CMDAT_DATA_EN (1 << 3)
1539
1540/* MSC Interrupts Mask Register (MSC_IMASK) */
1541
1542#define MSC_IMASK_SDIO (1 << 7)
1543#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1544#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1545#define MSC_IMASK_END_CMD_RES (1 << 2)
1546#define MSC_IMASK_PRG_DONE (1 << 1)
1547#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1548
1549
1550/* MSC Interrupts Status Register (MSC_IREG) */
1551
1552#define MSC_IREG_SDIO (1 << 7)
1553#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1554#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1555#define MSC_IREG_END_CMD_RES (1 << 2)
1556#define MSC_IREG_PRG_DONE (1 << 1)
1557#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1558
1559
1560/*************************************************************************
1561 * EMC (External Memory Controller)
1562 *************************************************************************/
1563#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1564#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1565#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1566#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1567#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1568#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1569#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1570#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1571#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1572#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1573
1574#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1575#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1576#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1577#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1578#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1579#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1580#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1581#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1582#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1583#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1584#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1585#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1586
1587#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1588#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1589#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1590#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1591#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1592#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1593
1594
1595#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1596#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1597#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1598#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1599#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1600#define REG_EMC_SACR0 REG32(EMC_SACR0)
1601#define REG_EMC_SACR1 REG32(EMC_SACR1)
1602#define REG_EMC_SACR2 REG32(EMC_SACR2)
1603#define REG_EMC_SACR3 REG32(EMC_SACR3)
1604#define REG_EMC_SACR4 REG32(EMC_SACR4)
1605
1606#define REG_EMC_NFCSR REG32(EMC_NFCSR)
1607#define REG_EMC_NFECR REG32(EMC_NFECR)
1608#define REG_EMC_NFECC REG32(EMC_NFECC)
1609#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1610#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1611#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1612#define REG_EMC_NFINTS REG32(EMC_NFINTS)
1613#define REG_EMC_NFINTE REG32(EMC_NFINTE)
1614#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1615#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1616#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1617#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1618
1619#define REG_EMC_DMCR REG32(EMC_DMCR)
1620#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1621#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1622#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1623#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1624
1625/* Static Memory Control Register */
1626#define EMC_SMCR_STRV_BIT 24
1627#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1628#define EMC_SMCR_TAW_BIT 20
1629#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1630#define EMC_SMCR_TBP_BIT 16
1631#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1632#define EMC_SMCR_TAH_BIT 12
1633#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1634#define EMC_SMCR_TAS_BIT 8
1635#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1636#define EMC_SMCR_BW_BIT 6
1637#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1638  #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1639  #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1640  #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1641#define EMC_SMCR_BCM (1 << 3)
1642#define EMC_SMCR_BL_BIT 1
1643#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1644  #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1645  #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1646  #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1647  #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1648#define EMC_SMCR_SMT (1 << 0)
1649
1650/* Static Memory Bank Addr Config Reg */
1651#define EMC_SACR_BASE_BIT 8
1652#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1653#define EMC_SACR_MASK_BIT 0
1654#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1655
1656/* NAND Flash Control/Status Register */
1657#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1658#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1659#define EMC_NFCSR_NFCE3 (1 << 5)
1660#define EMC_NFCSR_NFE3 (1 << 4)
1661#define EMC_NFCSR_NFCE2 (1 << 3)
1662#define EMC_NFCSR_NFE2 (1 << 2)
1663#define EMC_NFCSR_NFCE1 (1 << 1)
1664#define EMC_NFCSR_NFE1 (1 << 0)
1665
1666/* NAND Flash ECC Control Register */
1667#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1668#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1669#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1670#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1671#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1672#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1673#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1674
1675/* NAND Flash ECC Data Register */
1676#define EMC_NFECC_ECC2_BIT 16
1677#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1678#define EMC_NFECC_ECC1_BIT 8
1679#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1680#define EMC_NFECC_ECC0_BIT 0
1681#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1682
1683/* NAND Flash Interrupt Status Register */
1684#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1685#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1686#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1687#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1688#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1689#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1690#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1691
1692/* NAND Flash Interrupt Enable Register */
1693#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1694#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1695#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1696#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1697#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1698
1699/* NAND Flash RS Error Report Register */
1700#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1701#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1702#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1703#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1704
1705
1706/* DRAM Control Register */
1707#define EMC_DMCR_BW_BIT 31
1708#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1709#define EMC_DMCR_CA_BIT 26
1710#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1711  #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1712  #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1713  #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1714  #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1715  #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1716#define EMC_DMCR_RMODE (1 << 25)
1717#define EMC_DMCR_RFSH (1 << 24)
1718#define EMC_DMCR_MRSET (1 << 23)
1719#define EMC_DMCR_RA_BIT 20
1720#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1721  #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1722  #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1723  #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1724#define EMC_DMCR_BA_BIT 19
1725#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1726#define EMC_DMCR_PDM (1 << 18)
1727#define EMC_DMCR_EPIN (1 << 17)
1728#define EMC_DMCR_TRAS_BIT 13
1729#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1730#define EMC_DMCR_RCD_BIT 11
1731#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1732#define EMC_DMCR_TPC_BIT 8
1733#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1734#define EMC_DMCR_TRWL_BIT 5
1735#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1736#define EMC_DMCR_TRC_BIT 2
1737#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1738#define EMC_DMCR_TCL_BIT 0
1739#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1740
1741/* Refresh Time Control/Status Register */
1742#define EMC_RTCSR_CMF (1 << 7)
1743#define EMC_RTCSR_CKS_BIT 0
1744#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1745  #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1746  #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1747  #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1748  #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1749  #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1750  #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1751  #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1752  #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1753
1754/* SDRAM Bank Address Configuration Register */
1755#define EMC_DMAR_BASE_BIT 8
1756#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1757#define EMC_DMAR_MASK_BIT 0
1758#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1759
1760/* Mode Register of SDRAM bank 0 */
1761#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1762#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1763#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1764  #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1765#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1766#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1767  #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1768  #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1769  #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1770#define EMC_SDMR_BT_BIT 3 /* Burst Type */
1771#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1772  #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1773  #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1774#define EMC_SDMR_BL_BIT 0 /* Burst Length */
1775#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1776  #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1777  #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1778  #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1779  #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1780
1781#define EMC_SDMR_CAS2_16BIT \
1782  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1783#define EMC_SDMR_CAS2_32BIT \
1784  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1785#define EMC_SDMR_CAS3_16BIT \
1786  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1787#define EMC_SDMR_CAS3_32BIT \
1788  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1789
1790
1791/*************************************************************************
1792 * CIM
1793 *************************************************************************/
1794#define CIM_CFG (CIM_BASE + 0x0000)
1795#define CIM_CTRL (CIM_BASE + 0x0004)
1796#define CIM_STATE (CIM_BASE + 0x0008)
1797#define CIM_IID (CIM_BASE + 0x000C)
1798#define CIM_RXFIFO (CIM_BASE + 0x0010)
1799#define CIM_DA (CIM_BASE + 0x0020)
1800#define CIM_FA (CIM_BASE + 0x0024)
1801#define CIM_FID (CIM_BASE + 0x0028)
1802#define CIM_CMD (CIM_BASE + 0x002C)
1803
1804#define REG_CIM_CFG REG32(CIM_CFG)
1805#define REG_CIM_CTRL REG32(CIM_CTRL)
1806#define REG_CIM_STATE REG32(CIM_STATE)
1807#define REG_CIM_IID REG32(CIM_IID)
1808#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1809#define REG_CIM_DA REG32(CIM_DA)
1810#define REG_CIM_FA REG32(CIM_FA)
1811#define REG_CIM_FID REG32(CIM_FID)
1812#define REG_CIM_CMD REG32(CIM_CMD)
1813
1814/* CIM Configuration Register (CIM_CFG) */
1815
1816#define CIM_CFG_INV_DAT (1 << 15)
1817#define CIM_CFG_VSP (1 << 14)
1818#define CIM_CFG_HSP (1 << 13)
1819#define CIM_CFG_PCP (1 << 12)
1820#define CIM_CFG_DUMMY_ZERO (1 << 9)
1821#define CIM_CFG_EXT_VSYNC (1 << 8)
1822#define CIM_CFG_PACK_BIT 4
1823#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1824  #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1825  #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1826  #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1827  #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1828  #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1829  #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1830  #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1831  #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1832#define CIM_CFG_DSM_BIT 0
1833#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1834  #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1835  #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1836  #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1837  #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1838
1839/* CIM Control Register (CIM_CTRL) */
1840
1841#define CIM_CTRL_MCLKDIV_BIT 24
1842#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1843#define CIM_CTRL_FRC_BIT 16
1844#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1845  #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1846  #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1847  #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1848  #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1849  #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1850  #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1851  #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1852  #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1853  #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1854  #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1855  #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1856  #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1857  #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1858  #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1859  #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1860  #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1861#define CIM_CTRL_VDDM (1 << 13)
1862#define CIM_CTRL_DMA_SOFM (1 << 12)
1863#define CIM_CTRL_DMA_EOFM (1 << 11)
1864#define CIM_CTRL_DMA_STOPM (1 << 10)
1865#define CIM_CTRL_RXF_TRIGM (1 << 9)
1866#define CIM_CTRL_RXF_OFM (1 << 8)
1867#define CIM_CTRL_RXF_TRIG_BIT 4
1868#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1869  #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1870  #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1871  #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1872  #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1873  #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1874  #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1875  #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1876  #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1877#define CIM_CTRL_DMA_EN (1 << 2)
1878#define CIM_CTRL_RXF_RST (1 << 1)
1879#define CIM_CTRL_ENA (1 << 0)
1880
1881/* CIM State Register (CIM_STATE) */
1882
1883#define CIM_STATE_DMA_SOF (1 << 6)
1884#define CIM_STATE_DMA_EOF (1 << 5)
1885#define CIM_STATE_DMA_STOP (1 << 4)
1886#define CIM_STATE_RXF_OF (1 << 3)
1887#define CIM_STATE_RXF_TRIG (1 << 2)
1888#define CIM_STATE_RXF_EMPTY (1 << 1)
1889#define CIM_STATE_VDD (1 << 0)
1890
1891/* CIM DMA Command Register (CIM_CMD) */
1892
1893#define CIM_CMD_SOFINT (1 << 31)
1894#define CIM_CMD_EOFINT (1 << 30)
1895#define CIM_CMD_STOP (1 << 28)
1896#define CIM_CMD_LEN_BIT 0
1897#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
1898
1899
1900/*************************************************************************
1901 * SADC (Smart A/D Controller)
1902 *************************************************************************/
1903
1904#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
1905#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
1906#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
1907#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
1908#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
1909#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
1910#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
1911#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
1912#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
1913
1914#define REG_SADC_ENA REG8(SADC_ENA)
1915#define REG_SADC_CFG REG32(SADC_CFG)
1916#define REG_SADC_CTRL REG8(SADC_CTRL)
1917#define REG_SADC_STATE REG8(SADC_STATE)
1918#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
1919#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
1920#define REG_SADC_TSDAT REG32(SADC_TSDAT)
1921#define REG_SADC_BATDAT REG16(SADC_BATDAT)
1922#define REG_SADC_SADDAT REG16(SADC_SADDAT)
1923
1924/* ADC Enable Register */
1925#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
1926#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
1927#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
1928#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
1929
1930/* ADC Configure Register */
1931#define SADC_CFG_EXIN (1 << 30)
1932#define SADC_CFG_CLKOUT_NUM_BIT 16
1933#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
1934#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
1935#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
1936#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
1937  #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
1938  #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
1939  #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
1940#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
1941#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
1942  #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
1943  #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
1944  #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
1945  #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
1946  #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
1947  #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
1948  #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
1949  #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
1950#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
1951#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
1952#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
1953#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
1954#define SADC_CFG_CMD_BIT 0 /* ADC Command */
1955#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
1956  #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
1957  #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
1958  #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
1959  #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
1960  #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
1961  #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
1962  #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
1963  #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
1964  #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
1965  #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
1966  #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
1967  #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
1968  #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
1969
1970/* ADC Control Register */
1971#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
1972#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
1973#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
1974#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
1975#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
1976
1977/* ADC Status Register */
1978#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
1979#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
1980#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
1981#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
1982#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
1983#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
1984#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
1985#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
1986
1987/* ADC Touch Screen Data Register */
1988#define SADC_TSDAT_DATA0_BIT 0
1989#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
1990#define SADC_TSDAT_TYPE0 (1 << 15)
1991#define SADC_TSDAT_DATA1_BIT 16
1992#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
1993#define SADC_TSDAT_TYPE1 (1 << 31)
1994
1995
1996/*************************************************************************
1997 * SLCD (Smart LCD Controller)
1998 *************************************************************************/
1999
2000#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2001#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2002#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2003#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2004#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2005
2006#define REG_SLCD_CFG REG32(SLCD_CFG)
2007#define REG_SLCD_CTRL REG8(SLCD_CTRL)
2008#define REG_SLCD_STATE REG8(SLCD_STATE)
2009#define REG_SLCD_DATA REG32(SLCD_DATA)
2010#define REG_SLCD_FIFO REG32(SLCD_FIFO)
2011
2012/* SLCD Configure Register */
2013#define SLCD_CFG_BURST_BIT 14
2014#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2015  #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2016  #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2017#define SLCD_CFG_DWIDTH_BIT 10
2018#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2019  #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2020  #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2021  #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2022  #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2023  #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
2024  #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT)
2025#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2026#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2027#define SLCD_CFG_CWIDTH_18BIT (2 << 8)
2028#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2029#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2030#define SLCD_CFG_RS_CMD_LOW (0 << 3)
2031#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2032#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2033#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2034#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2035#define SLCD_CFG_TYPE_SERIAL (1 << 0)
2036
2037/* SLCD Control Register */
2038#define SLCD_CTRL_DMA_EN (1 << 0)
2039
2040/* SLCD Status Register */
2041#define SLCD_STATE_BUSY (1 << 0)
2042
2043/* SLCD Data Register */
2044#define SLCD_DATA_RS_DATA (0 << 31)
2045#define SLCD_DATA_RS_COMMAND (1 << 31)
2046
2047/* SLCD FIFO Register */
2048#define SLCD_FIFO_RS_DATA (0 << 31)
2049#define SLCD_FIFO_RS_COMMAND (1 << 31)
2050
2051
2052/*************************************************************************
2053 * LCD (LCD Controller)
2054 *************************************************************************/
2055#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2056#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2057#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2058#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2059#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2060#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2061#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2062#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2063#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2064#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2065#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2066#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2067#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2068#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2069#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2070#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2071#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2072#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2073#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2074#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2075#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2076
2077#define REG_LCD_CFG REG32(LCD_CFG)
2078#define REG_LCD_VSYNC REG32(LCD_VSYNC)
2079#define REG_LCD_HSYNC REG32(LCD_HSYNC)
2080#define REG_LCD_VAT REG32(LCD_VAT)
2081#define REG_LCD_DAH REG32(LCD_DAH)
2082#define REG_LCD_DAV REG32(LCD_DAV)
2083#define REG_LCD_PS REG32(LCD_PS)
2084#define REG_LCD_CLS REG32(LCD_CLS)
2085#define REG_LCD_SPL REG32(LCD_SPL)
2086#define REG_LCD_REV REG32(LCD_REV)
2087#define REG_LCD_CTRL REG32(LCD_CTRL)
2088#define REG_LCD_STATE REG32(LCD_STATE)
2089#define REG_LCD_IID REG32(LCD_IID)
2090#define REG_LCD_DA0 REG32(LCD_DA0)
2091#define REG_LCD_SA0 REG32(LCD_SA0)
2092#define REG_LCD_FID0 REG32(LCD_FID0)
2093#define REG_LCD_CMD0 REG32(LCD_CMD0)
2094#define REG_LCD_DA1 REG32(LCD_DA1)
2095#define REG_LCD_SA1 REG32(LCD_SA1)
2096#define REG_LCD_FID1 REG32(LCD_FID1)
2097#define REG_LCD_CMD1 REG32(LCD_CMD1)
2098
2099/* LCD Configure Register */
2100#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2101#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2102  #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2103  #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2104#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2105#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2106#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2107#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2108#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2109#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2110#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2111#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2112#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2113#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2114#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2115#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2116#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2117#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2118#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2119#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2120#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2121#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2122#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2123  #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2124  #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2125  #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2126#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2127#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2128  #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2129  #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2130  #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2131  #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2132  #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2133  #define LCD_CFG_MODE_INTER_CCIR656 (6 << LCD_CFG_MODE_BIT)
2134  #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2135  #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2136  #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2137  #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2138  #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2139  /* JZ47XX defines */
2140  #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2141  #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2142  #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2143
2144
2145
2146/* Vertical Synchronize Register */
2147#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2148#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2149#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2150#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2151
2152/* Horizontal Synchronize Register */
2153#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2154#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2155#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2156#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2157
2158/* Virtual Area Setting Register */
2159#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2160#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2161#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2162#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2163
2164/* Display Area Horizontal Start/End Point Register */
2165#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2166#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2167#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2168#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2169
2170/* Display Area Vertical Start/End Point Register */
2171#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2172#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2173#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2174#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2175
2176/* PS Signal Setting */
2177#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2178#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2179#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2180#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2181
2182/* CLS Signal Setting */
2183#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2184#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2185#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2186#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2187
2188/* SPL Signal Setting */
2189#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2190#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2191#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2192#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2193
2194/* REV Signal Setting */
2195#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2196#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2197
2198/* LCD Control Register */
2199#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2200#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2201  #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2202  #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2203  #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2204#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2205#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2206#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2207#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2208#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2209  #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2210  #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2211  #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2212#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2213#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2214#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2215#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2216#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2217#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2218#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2219#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2220#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2221#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2222#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2223#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2224#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2225#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2226#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2227  #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2228  #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2229  #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2230  #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2231  #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2232  #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2233
2234/* LCD Status Register */
2235#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2236#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2237#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2238#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2239#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2240#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2241#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2242
2243/* DMA Command Register */
2244#define LCD_CMD_SOFINT (1 << 31)
2245#define LCD_CMD_EOFINT (1 << 30)
2246#define LCD_CMD_PAL (1 << 28)
2247#define LCD_CMD_LEN_BIT 0
2248#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2249
2250
2251/*************************************************************************
2252 * USB Device
2253 *************************************************************************/
2254#define USB_BASE UDC_BASE
2255
2256#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2257#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2258#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2259#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2260#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2261#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2262#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2263#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2264#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2265#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2266#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2267
2268#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2269#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2270#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2271#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2272#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2273#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2274#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2275#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2276
2277#define USB_FIFO_EP0 (USB_BASE + 0x20)
2278#define USB_FIFO_EP1 (USB_BASE + 0x24)
2279#define USB_FIFO_EP2 (USB_BASE + 0x28)
2280
2281#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2282#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2283
2284#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2285#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2286#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2287#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2288#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2289#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2290#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2291
2292
2293/* Power register bit masks */
2294#define USB_POWER_SUSPENDM 0x01
2295#define USB_POWER_RESUME 0x04
2296#define USB_POWER_HSMODE 0x10
2297#define USB_POWER_HSENAB 0x20
2298#define USB_POWER_SOFTCONN 0x40
2299
2300/* Interrupt register bit masks */
2301#define USB_INTR_SUSPEND 0x01
2302#define USB_INTR_RESUME 0x02
2303#define USB_INTR_RESET 0x04
2304
2305#define USB_INTR_EP0 0x0001
2306#define USB_INTR_INEP1 0x0002
2307#define USB_INTR_INEP2 0x0004
2308#define USB_INTR_OUTEP1 0x0002
2309
2310/* CSR0 bit masks */
2311#define USB_CSR0_OUTPKTRDY 0x01
2312#define USB_CSR0_INPKTRDY 0x02
2313#define USB_CSR0_SENTSTALL 0x04
2314#define USB_CSR0_DATAEND 0x08
2315#define USB_CSR0_SETUPEND 0x10
2316#define USB_CSR0_SENDSTALL 0x20
2317#define USB_CSR0_SVDOUTPKTRDY 0x40
2318#define USB_CSR0_SVDSETUPEND 0x80
2319
2320/* Endpoint CSR register bits */
2321#define USB_INCSRH_AUTOSET 0x80
2322#define USB_INCSRH_ISO 0x40
2323#define USB_INCSRH_MODE 0x20
2324#define USB_INCSRH_DMAREQENAB 0x10
2325#define USB_INCSRH_DMAREQMODE 0x04
2326#define USB_INCSR_CDT 0x40
2327#define USB_INCSR_SENTSTALL 0x20
2328#define USB_INCSR_SENDSTALL 0x10
2329#define USB_INCSR_FF 0x08
2330#define USB_INCSR_UNDERRUN 0x04
2331#define USB_INCSR_FFNOTEMPT 0x02
2332#define USB_INCSR_INPKTRDY 0x01
2333#define USB_OUTCSRH_AUTOCLR 0x80
2334#define USB_OUTCSRH_ISO 0x40
2335#define USB_OUTCSRH_DMAREQENAB 0x20
2336#define USB_OUTCSRH_DNYT 0x10
2337#define USB_OUTCSRH_DMAREQMODE 0x08
2338#define USB_OUTCSR_CDT 0x80
2339#define USB_OUTCSR_SENTSTALL 0x40
2340#define USB_OUTCSR_SENDSTALL 0x20
2341#define USB_OUTCSR_FF 0x10
2342#define USB_OUTCSR_DATAERR 0x08
2343#define USB_OUTCSR_OVERRUN 0x04
2344#define USB_OUTCSR_FFFULL 0x02
2345#define USB_OUTCSR_OUTPKTRDY 0x01
2346
2347/* Testmode register bits */
2348#define USB_TEST_SE0NAK 0x01
2349#define USB_TEST_J 0x02
2350#define USB_TEST_K 0x04
2351#define USB_TEST_PACKET 0x08
2352
2353/* DMA control bits */
2354#define USB_CNTL_ENA 0x01
2355#define USB_CNTL_DIR_IN 0x02
2356#define USB_CNTL_MODE_1 0x04
2357#define USB_CNTL_INTR_EN 0x08
2358#define USB_CNTL_EP(n) ((n) << 4)
2359#define USB_CNTL_BURST_0 (0 << 9)
2360#define USB_CNTL_BURST_4 (1 << 9)
2361#define USB_CNTL_BURST_8 (2 << 9)
2362#define USB_CNTL_BURST_16 (3 << 9)
2363
2364#endif /* __JZ4740_REGS_H__ */
arch/mips/include/asm/mach-jz4740/serial.h
1/*
2 * linux/include/asm-mips/mach-jz4740/serial.h
3 *
4 * Ingenic's JZ4740 common include.
5 *
6 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
7 *
8 * Author: <yliu@ingenic.cn>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_BOARD_SERIAL_H__
16#define __ASM_BOARD_SERIAL_H__
17
18#ifndef CONFIG_SERIAL_MANY_PORTS
19#undef RS_TABLE_SIZE
20#define RS_TABLE_SIZE 1
21#endif
22
23#define JZ_BASE_BAUD (12000000/16)
24
25#define JZ_SERIAL_PORT_DEFNS \
26    { .baud_base = JZ_BASE_BAUD, .irq = IRQ_UART0, \
27      .flags = STD_COM_FLAGS, .iomem_base = (u8 *)UART0_BASE, \
28      .iomem_reg_shift = 2, .io_type = SERIAL_IO_MEM },
29
30#endif /* __ASM_BORAD_SERIAL_H__ */
arch/mips/include/asm/mach-jz4740/war.h
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
9#define __ASM_MIPS_MACH_JZ4740_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
arch/mips/jz4740/Kconfig
1choice
2    prompt "Machine type"
3    depends on MACH_JZ
4    default JZ4740_QI_LB60
5
6config JZ4740_QI_LB60
7    bool "Qi Hardware Ben NanoNote"
8    select DMA_NONCOHERENT
9    select SOC_JZ4740
10
11endchoice
12
13config SOC_JZ4740
14    bool
15    select JZSOC
16    select GENERIC_GPIO
17    select ARCH_REQUIRE_GPIOLIB
18    select SYS_HAS_EARLY_PRINTK
19    select SYS_SUPPORTS_LITTLE_ENDIAN
20    select IRQ_CPU
21
22config JZSOC
23    bool
24    select JZRISC
25    select SYS_HAS_CPU_MIPS32_R1
26    select SYS_SUPPORTS_32BIT_KERNEL
27
28config JZRISC
29    bool
arch/mips/jz4740/Makefile
1#
2# Makefile for the Ingenic JZ4740.
3#
4
5# Object file lists.
6
7obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
8    gpio.o clock.o platform.o
9
10obj-$(CONFIG_PROC_FS) += proc.o
11
12# board specific support
13
14obj-$(CONFIG_JZ4740_PAVO) += board-pavo.o
15obj-$(CONFIG_JZ4740_LEO) += board-leo.o
16obj-$(CONFIG_JZ4740_LYRA) += board-lyra.o
17obj-$(CONFIG_JZ4725_DIPPER) += board-dipper.o
18obj-$(CONFIG_JZ4720_VIRGO) += board-virgo.o
19obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
20
21# PM support
22
23obj-$(CONFIG_PM) +=pm.o
24
25# CPU Frequency scaling support
26
27obj-$(CONFIG_CPU_FREQ_JZ) +=cpufreq.o
arch/mips/jz4740/board-qi_lb60.c
1/*
2 * linux/arch/mips/jz4740/board-qi_lb60.c
3 *
4 * QI_LB60 setup routines.
5 *
6 * Copyright (c) 2009 Qi Hardware inc.,
7 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 or later
11 * as published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/gpio.h>
17
18#include <asm/mach-jz4740/board-qi_lb60.h>
19#include <asm/mach-jz4740/platform.h>
20
21#include <linux/input.h>
22#include <linux/gpio_keys.h>
23#include <linux/mtd/jz4740_nand.h>
24#include <linux/jz4740_fb.h>
25#include <linux/input/matrix_keypad.h>
26#include <linux/mtd/jz4740_nand.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/spi_gpio.h>
29#include <linux/power_supply.h>
30#include <linux/power/jz4740-battery.h>
31#include <linux/mmc/jz4740_mmc.h>
32
33
34/* NAND */
35static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
36    .eccbytes = 36,
37    .eccpos = {
38        6, 7, 8, 9, 10, 11, 12, 13,
39        14, 15, 16, 17, 18, 19, 20, 21,
40        22, 23, 24, 25, 26, 27, 28, 29,
41        30, 31, 32, 33, 34, 35, 36, 37,
42        38, 39, 40, 41},
43    .oobfree = {
44        {.offset = 2,
45         .length = 4},
46        {.offset = 42,
47         .length = 22}}
48};
49
50static struct mtd_partition qi_lb60_partitions_1gb[] = {
51    { .name = "NAND BOOT partition",
52      .offset = 0 * 0x100000,
53      .size = 4 * 0x100000,
54     },
55    { .name = "NAND KERNEL partition",
56      .offset = 4 * 0x100000,
57      .size = 4 * 0x100000,
58     },
59    { .name = "NAND ROOTFS partition",
60      .offset = 8 * 0x100000,
61      .size = 504 * 0x100000,
62     },
63    { .name = "NAND DATA partition",
64      .offset = 512 * 0x100000,
65      .size = 512 * 0x100000,
66     },
67};
68
69static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
70    .eccbytes = 72,
71    .eccpos = {
72        12, 13, 14, 15, 16, 17, 18, 19,
73        20, 21, 22, 23, 24, 25, 26, 27,
74        28, 29, 30, 31, 32, 33, 34, 35,
75        36, 37, 38, 39, 40, 41, 42, 43,
76        44, 45, 46, 47, 48, 49, 50, 51,
77        52, 53, 54, 55, 56, 57, 58, 59,
78        60, 61, 62, 63, 64, 65, 66, 67,
79        68, 69, 70, 71, 72, 73, 74, 75,
80        76, 77, 78, 79, 80, 81, 82, 83},
81    .oobfree = {
82         {.offset = 2,
83         .length = 10},
84        {.offset = 84,
85         .length = 44}}
86};
87
88static struct mtd_partition qi_lb60_partitions_2gb[] = {
89    { .name = "NAND BOOT partition",
90      .offset = 0 * 0x100000,
91      .size = 4 * 0x100000,
92     },
93    { .name = "NAND KERNEL partition",
94      .offset = 4 * 0x100000,
95      .size = 4 * 0x100000,
96     },
97    { .name = "NAND ROOTFS partition",
98      .offset = 8 * 0x100000,
99      .size = 504 * 0x100000,
100     },
101    { .name = "NAND DATA partition",
102      .offset = 512 * 0x100000,
103      .size = (512 + 1024) * 0x100000,
104     },
105};
106
107static void qi_lb60_nand_ident(struct platform_device *pdev,
108                struct nand_chip *chip,
109                struct mtd_partition **partitions,
110                int *num_partitions)
111{
112    if (chip->page_shift == 12) {
113        chip->ecc.layout = &qi_lb60_ecclayout_2gb;
114        *partitions = qi_lb60_partitions_2gb;
115        *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb);
116    } else {
117        chip->ecc.layout = &qi_lb60_ecclayout_1gb;
118        *partitions = qi_lb60_partitions_1gb;
119        *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb);
120    }
121}
122
123static struct jz_nand_platform_data qi_lb60_nand_pdata = {
124    .ident_callback = qi_lb60_nand_ident,
125    .busy_gpio = 94,
126};
127
128
129/* Keyboard*/
130
131/* #define KEEP_UART_ALIVE
132 * don't define this. the keyboard and keyboard both work
133 */
134
135#define KEY_QI_QI KEY_F13
136#define KEY_QI_UPRED KEY_RIGHTSHIFT
137#define KEY_QI_VOLUP KEY_F15
138#define KEY_QI_VOLDOWN KEY_F16
139#define KEY_QI_FN KEY_RIGHTCTRL
140
141static const uint32_t qi_lb60_keymap[] = {
142    KEY(0, 0, KEY_F1), /* S2 */
143    KEY(0, 1, KEY_F2), /* S3 */
144    KEY(0, 2, KEY_F3), /* S4 */
145    KEY(0, 3, KEY_F4), /* S5 */
146    KEY(0, 4, KEY_F5), /* S6 */
147    KEY(0, 5, KEY_F6), /* S7 */
148    KEY(0, 6, KEY_F7), /* S8 */
149
150    KEY(1, 0, KEY_Q), /* S10 */
151    KEY(1, 1, KEY_W), /* S11 */
152    KEY(1, 2, KEY_E), /* S12 */
153    KEY(1, 3, KEY_R), /* S13 */
154    KEY(1, 4, KEY_T), /* S14 */
155    KEY(1, 5, KEY_Y), /* S15 */
156    KEY(1, 6, KEY_U), /* S16 */
157    KEY(1, 7, KEY_I), /* S17 */
158    KEY(2, 0, KEY_A), /* S18 */
159    KEY(2, 1, KEY_S), /* S19 */
160    KEY(2, 2, KEY_D), /* S20 */
161    KEY(2, 3, KEY_F), /* S21 */
162    KEY(2, 4, KEY_G), /* S22 */
163    KEY(2, 5, KEY_H), /* S23 */
164    KEY(2, 6, KEY_J), /* S24 */
165    KEY(2, 7, KEY_K), /* S25 */
166    KEY(3, 0, KEY_ESC), /* S26 */
167    KEY(3, 1, KEY_Z), /* S27 */
168    KEY(3, 2, KEY_X), /* S28 */
169    KEY(3, 3, KEY_C), /* S29 */
170    KEY(3, 4, KEY_V), /* S30 */
171    KEY(3, 5, KEY_B), /* S31 */
172    KEY(3, 6, KEY_N), /* S32 */
173    KEY(3, 7, KEY_M), /* S33 */
174    KEY(4, 0, KEY_TAB), /* S34 */
175    KEY(4, 1, KEY_CAPSLOCK), /* S35 */
176    KEY(4, 2, KEY_BACKSLASH), /* S36 */
177    KEY(4, 3, KEY_APOSTROPHE), /* S37 */
178    KEY(4, 4, KEY_COMMA), /* S38 */
179    KEY(4, 5, KEY_DOT), /* S39 */
180    KEY(4, 6, KEY_SLASH), /* S40 */
181    KEY(4, 7, KEY_UP), /* S41 */
182    KEY(5, 0, KEY_O), /* S42 */
183    KEY(5, 1, KEY_L), /* S43 */
184    KEY(5, 2, KEY_EQUAL), /* S44 */
185    KEY(5, 3, KEY_QI_UPRED), /* S45 */
186    KEY(5, 4, KEY_SPACE), /* S46 */
187    KEY(5, 5, KEY_QI_QI), /* S47 */
188    KEY(5, 6, KEY_LEFTCTRL), /* S48 */
189    KEY(5, 7, KEY_LEFT), /* S49 */
190    KEY(6, 0, KEY_F8), /* S50 */
191    KEY(6, 1, KEY_P), /* S51 */
192    KEY(6, 2, KEY_BACKSPACE),/* S52 */
193    KEY(6, 3, KEY_ENTER), /* S53 */
194    KEY(6, 4, KEY_QI_VOLUP), /* S54 */
195    KEY(6, 5, KEY_QI_VOLDOWN), /* S55 */
196    KEY(6, 6, KEY_DOWN), /* S56 */
197    KEY(6, 7, KEY_RIGHT), /* S57 */
198
199#ifndef KEEP_UART_ALIVE
200    KEY(7, 0, KEY_LEFTSHIFT), /* S58 */
201    KEY(7, 1, KEY_LEFTALT), /* S59 */
202    KEY(7, 2, KEY_QI_FN), /* S60 */
203#endif
204};
205
206static const struct matrix_keymap_data qi_lb60_keymap_data = {
207    .keymap = qi_lb60_keymap,
208    .keymap_size = ARRAY_SIZE(qi_lb60_keymap),
209};
210
211static const unsigned int qi_lb60_keypad_cols[] = {
212    74, 75, 76, 77, 78, 79, 80, 81,
213};
214
215static const unsigned int qi_lb60_keypad_rows[] = {
216    114, 115, 116, 117, 118, 119, 120,
217#ifndef KEEP_UART_ALIVE
218    122,
219#endif
220};
221
222static struct matrix_keypad_platform_data qi_lb60_pdata = {
223    .keymap_data = &qi_lb60_keymap_data,
224    .col_gpios = qi_lb60_keypad_cols,
225    .row_gpios = qi_lb60_keypad_rows,
226    .num_col_gpios = ARRAY_SIZE(qi_lb60_keypad_cols),
227    .num_row_gpios = ARRAY_SIZE(qi_lb60_keypad_rows),
228    .col_scan_delay_us = 10,
229    .debounce_ms = 10,
230    .wakeup = 1,
231    .active_low = 1,
232};
233
234static struct platform_device qi_lb60_keypad = {
235    .name = "matrix-keypad",
236    .id = -1,
237    .dev = {
238        .platform_data = &qi_lb60_pdata,
239    },
240};
241
242/* Display */
243static struct fb_videomode qi_lb60_video_modes[] = {
244    {
245        .name = "320x240",
246        .xres = 320,
247        .yres = 240,
248        .pixclock = 700000,
249        .left_margin = 140,
250        .right_margin = 273,
251        .upper_margin = 20,
252        .lower_margin = 2,
253        .hsync_len = 1,
254        .vsync_len = 1,
255        .sync = 0,
256        .vmode = FB_VMODE_NONINTERLACED,
257    },
258};
259
260static struct jz4740_fb_platform_data qi_lb60_fb_pdata = {
261    .width = 60,
262    .height = 45,
263    .num_modes = ARRAY_SIZE(qi_lb60_video_modes),
264    .modes = qi_lb60_video_modes,
265    .bpp = 24,
266    .lcd_type = JZ_LCD_TYPE_8BIT_SERIAL,
267};
268
269
270struct spi_gpio_platform_data spigpio_platform_data = {
271    .sck = JZ_GPIO_PORTC(23),
272    .mosi = JZ_GPIO_PORTC(22),
273    .miso = JZ_GPIO_PORTC(22),
274    .num_chipselect = 1,
275};
276
277static struct platform_device spigpio_device = {
278    .name = "spi_gpio",
279    .id = 1,
280    .dev = {
281        .platform_data = &spigpio_platform_data,
282    },
283};
284
285static struct spi_board_info qi_lb60_spi_board_info[] = {
286    {
287        .modalias = "gpm940b0",
288        .controller_data = (void*)JZ_GPIO_PORTC(21),
289        .chip_select = 0,
290        .bus_num = 1,
291        .max_speed_hz = 30 * 1000,
292    },
293};
294
295/* Battery */
296static struct jz_batt_info qi_lb60_battery_pdata = {
297    .dc_dect_gpio = GPIO_DC_DETE_N,
298    .usb_dect_gpio = GPIO_USB_DETE,
299    .charg_stat_gpio = GPIO_CHARG_STAT_N,
300
301    .min_voltag = 3600000,
302    .max_voltag = 4200000,
303    .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO,
304};
305
306/* GPIO Key: power */
307static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
308    [0] = {
309        .code = KEY_POWER,
310        .gpio = GPIO_WAKEUP_N,
311        .active_low = 1,
312        .desc = "Power",
313        .wakeup = 1,
314    },
315};
316
317static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
318    .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
319    .buttons = qi_lb60_gpio_keys_buttons,
320};
321
322static struct platform_device qi_lb60_gpio_keys = {
323    .name = "gpio-keys",
324    .id = -1,
325    .dev = {
326        .platform_data = &qi_lb60_gpio_keys_data,
327    }
328};
329
330static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
331    .gpio_card_detect = JZ_GPIO_PORTD(0),
332    .gpio_read_only = JZ_GPIO_PORTD(16),
333    .gpio_power = JZ_GPIO_PORTD(2),
334};
335
336static struct platform_device *jz_platform_devices[] __initdata = {
337    &jz4740_usb_ohci_device,
338    &jz4740_usb_gdt_device,
339    &jz4740_mmc_device,
340