Date:2011-03-05 15:48:46 (9 years 2 months ago)
Author:Peter Zotov
Commit:fc705e74b51166f3b0fefc5e28776a430609b80a
Message:MIPS: JZ47xx: Generalize clock framework.

Files: arch/mips/include/asm/mach-jz47xx/clock.h (1 diff)
arch/mips/include/asm/mach-jz47xx/jz4740/clock.h (1 diff)
arch/mips/jz47xx/clock.h (2 diffs)
arch/mips/jz47xx/jz4740/board-qi_lb60.c (1 diff)
arch/mips/jz47xx/jz4740/clock.c (14 diffs)
arch/mips/jz47xx/jz4740/platform.c (1 diff)
arch/mips/jz47xx/jz4750/board-xz0032.c (1 diff)
arch/mips/jz47xx/jz4750/clock.c (23 diffs)
arch/mips/jz47xx/jz4750/platform.c (1 diff)
arch/mips/jz47xx/ost.c (1 diff)
arch/mips/jz47xx/timer-cevt.c (1 diff)
arch/mips/jz47xx/timer-csrc.c (1 diff)

Change Details

arch/mips/include/asm/mach-jz47xx/clock.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __ASM_JZ47XX_CLOCK_H__
16#define __ASM_JZ47XX_CLOCK_H__
17
18enum jz47xx_wait_mode {
19    JZ47XX_WAIT_MODE_IDLE,
20    JZ47XX_WAIT_MODE_SLEEP,
21};
22
23void jz47xx_clock_set_wait_mode(enum jz47xx_wait_mode mode);
24
25#endif
arch/mips/include/asm/mach-jz47xx/jz4740/clock.h
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __ASM_JZ4740_CLOCK_H__
16#define __ASM_JZ4740_CLOCK_H__
17
18enum jz4740_wait_mode {
19    JZ4740_WAIT_MODE_IDLE,
20    JZ4740_WAIT_MODE_SLEEP,
21};
22
23void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
24
25void jz4740_clock_udc_enable_auto_suspend(void);
26void jz4740_clock_udc_disable_auto_suspend(void);
27
28#endif
arch/mips/jz47xx/clock.h
1818
1919#include <linux/list.h>
2020
21struct jz4740_clock_board_data {
21struct jz47xx_clock_board_data {
2222    unsigned long ext_rate;
2323    unsigned long rtc_rate;
2424};
2525
26extern struct jz4740_clock_board_data jz4740_clock_bdata;
26extern struct jz47xx_clock_board_data jz47xx_clock_bdata;
2727
28void jz4740_clock_suspend(void);
29void jz4740_clock_resume(void);
28void jz47xx_clock_suspend(void);
29void jz47xx_clock_resume(void);
3030
3131struct clk;
3232
...... 
5959
6060};
6161
62#define JZ4740_CLK_NOT_GATED ((uint32_t)-1)
62#define JZ47XX_CLK_NOT_GATED ((uint32_t)-1)
6363
6464int clk_is_enabled(struct clk *clk);
6565
arch/mips/jz47xx/jz4740/board-qi_lb60.c
465465
466466}
467467
468struct jz4740_clock_board_data jz4740_clock_bdata = {
468struct jz47xx_clock_board_data jz47xx_clock_bdata = {
469469    .ext_rate = 12000000,
470470    .rtc_rate = 32768,
471471};
arch/mips/jz47xx/jz4740/clock.c
2222#include <linux/list.h>
2323#include <linux/err.h>
2424
25#include <jz4740/clock.h>
25#include <asm/mach-jz47xx/clock.h>
2626#include <asm/mach-jz47xx/base.h>
2727
2828#include "../clock.h"
...... 
158158
159159static int jz_clk_enable_gating(struct clk *clk)
160160{
161    if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
161    if (clk->gate_bit == JZ47XX_CLK_NOT_GATED)
162162        return -EINVAL;
163163
164164    jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
...... 
167167
168168static int jz_clk_disable_gating(struct clk *clk)
169169{
170    if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
170    if (clk->gate_bit == JZ47XX_CLK_NOT_GATED)
171171        return -EINVAL;
172172
173173    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
...... 
176176
177177static int jz_clk_is_enabled_gating(struct clk *clk)
178178{
179    if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
179    if (clk->gate_bit == JZ47XX_CLK_NOT_GATED)
180180        return 1;
181181
182182    return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
...... 
300300static struct static_clk jz_clk_ext = {
301301    .clk = {
302302        .name = "ext",
303        .gate_bit = JZ4740_CLK_NOT_GATED,
303        .gate_bit = JZ47XX_CLK_NOT_GATED,
304304        .ops = &jz_clk_static_ops,
305305    },
306306};
...... 
408408    return 0;
409409}
410410
411static int jz_clk_udc_enable(struct clk *clk)
411static int jz_clk_udc_phy_enable(struct clk *clk)
412412{
413413    jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
414414            JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
...... 
416416    return 0;
417417}
418418
419static int jz_clk_udc_disable(struct clk *clk)
419static int jz_clk_udc_phy_disable(struct clk *clk)
420420{
421421    jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
422422            JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
...... 
424424    return 0;
425425}
426426
427static int jz_clk_udc_is_enabled(struct clk *clk)
427static int jz_clk_udc_phy_is_enabled(struct clk *clk)
428428{
429429    return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
430430            JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
431431}
432432
433static int jz_clk_udc_enable(struct clk *clk)
434{
435    jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
436
437    return 0;
438}
439
440static int jz_clk_udc_disable(struct clk *clk)
441{
442    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
443
444    return 0;
445}
446
447static int jz_clk_udc_is_enabled(struct clk *clk)
448{
449    return !!(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & JZ_CLOCK_GATE_UDC);
450}
451
433452static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
434453{
435454    if (parent == &jz_clk_pll_half)
...... 
623642        .clk = {
624643            .name = "lcd_pclk",
625644            .parent = &jz_clk_pll_half,
626            .gate_bit = JZ4740_CLK_NOT_GATED,
645            .gate_bit = JZ47XX_CLK_NOT_GATED,
627646            .ops = &jz_clk_divided_ops,
628647        },
629648        .reg = JZ_REG_CLOCK_LCD,
...... 
651670    },
652671};
653672
673static const struct clk_ops jz_clk_udc_phy_ops = {
674    .enable = jz_clk_udc_phy_enable,
675    .disable = jz_clk_udc_phy_disable,
676    .is_enabled = jz_clk_udc_phy_is_enabled,
677};
678
654679static const struct clk_ops jz_clk_udc_ops = {
655680    .set_parent = jz_clk_udc_set_parent,
656681    .set_rate = jz_clk_udc_set_rate,
...... 
714739        .gate_bit = JZ_CLOCK_GATE_AIC,
715740        .ops = &jz_clk_simple_ops,
716741    },
742    [8] = {
743        .name = "udc-phy",
744        .parent = &jz4740_clock_simple_clks[0], /* udc */
745        .ops = &jz_clk_udc_phy_ops,
746    },
717747};
718748
719749static struct static_clk jz_clk_rtc = {
...... 
843873        clk_add(&jz4740_clock_simple_clks[i]);
844874}
845875
846void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
876void jz47xx_clock_set_wait_mode(enum jz47xx_wait_mode mode)
847877{
848878    switch (mode) {
849    case JZ4740_WAIT_MODE_IDLE:
879    case JZ47XX_WAIT_MODE_IDLE:
850880        jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
851881        break;
852    case JZ4740_WAIT_MODE_SLEEP:
882    case JZ47XX_WAIT_MODE_SLEEP:
853883        jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
854884        break;
855885    }
856886}
857887
858void jz4740_clock_udc_disable_auto_suspend(void)
859{
860    jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
861}
862EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
863
864void jz4740_clock_udc_enable_auto_suspend(void)
865{
866    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
867}
868EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
869
870void jz4740_clock_suspend(void)
888void jz47xx_clock_suspend(void)
871889{
872890    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
873891        JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
...... 
875893    jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
876894}
877895
878void jz4740_clock_resume(void)
896void jz47xx_clock_resume(void)
879897{
880898    uint32_t pll;
881899
...... 
899917
900918    spin_lock_init(&jz_clock_lock);
901919
902    jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
903    jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
920    jz_clk_ext.rate = jz47xx_clock_bdata.ext_rate;
921    jz_clk_rtc.rate = jz47xx_clock_bdata.rtc_rate;
904922
905923    val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
906924
arch/mips/jz47xx/jz4740/platform.c
286286    struct plat_serial8250_port *p;
287287
288288    for (p = jz4740_uart_data; p->flags != 0; ++p)
289        p->uartclk = jz4740_clock_bdata.ext_rate;
289        p->uartclk = jz47xx_clock_bdata.ext_rate;
290290
291291    platform_device_register(&jz4740_uart_device);
292292}
arch/mips/jz47xx/jz4750/board-xz0032.c
3434
3535}
3636
37struct jz4740_clock_board_data jz4740_clock_bdata = {
37struct jz47xx_clock_board_data jz47xx_clock_bdata = {
3838    .ext_rate = 12000000,
3939    .rtc_rate = 32768,
4040};
arch/mips/jz47xx/jz4750/clock.c
11/*
22 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC clock support
3 * JZ4750 SoC clock support
44 *
55 * This program is free software; you can redistribute it and/or modify it
66 * under the terms of the GNU General Public License as published by the
...... 
2222#include <linux/list.h>
2323#include <linux/err.h>
2424
25#include <jz4740/clock.h>
26
25#include <asm/mach-jz47xx/clock.h>
2726#include <asm/mach-jz47xx/base.h>
2827
2928#include "../clock.h"
...... 
4039#define JZ_REG_CLOCK_SPI 0x74
4140
4241#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31)
43#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30)
4442#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29)
4543#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000
4644#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22)
...... 
159157
160158static int jz_clk_enable_gating(struct clk *clk)
161159{
162    if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
160    if (clk->gate_bit == JZ47XX_CLK_NOT_GATED)
163161        return -EINVAL;
164162
165163    jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
...... 
168166
169167static int jz_clk_disable_gating(struct clk *clk)
170168{
171    if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
169    if (clk->gate_bit == JZ47XX_CLK_NOT_GATED)
172170        return -EINVAL;
173171
174172    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
...... 
177175
178176static int jz_clk_is_enabled_gating(struct clk *clk)
179177{
180    if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
178    if (clk->gate_bit == JZ47XX_CLK_NOT_GATED)
181179        return 1;
182180
183181    return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
...... 
188186    return ((struct static_clk *)clk)->rate;
189187}
190188
191static int jz_clk_ko_enable(struct clk *clk)
192{
193    jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
194    return 0;
195}
196
197static int jz_clk_ko_disable(struct clk *clk)
198{
199    jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
200    return 0;
201}
202
203static int jz_clk_ko_is_enabled(struct clk *clk)
204{
205    return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
206}
207
208189static const int pllno[] = {1, 2, 2, 4};
209190
210191static unsigned long jz_clk_pll_get_rate(struct clk *clk)
...... 
301282static struct static_clk jz_clk_ext = {
302283    .clk = {
303284        .name = "ext",
304        .gate_bit = JZ4740_CLK_NOT_GATED,
285        .gate_bit = JZ47XX_CLK_NOT_GATED,
305286        .ops = &jz_clk_static_ops,
306287    },
307288};
...... 
341322    .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
342323};
343324
344static struct main_clk jz_clk_memory = {
345    .clk = {
346        .name = "mclk",
347        .parent = &jz_clk_pll,
348        .ops = &jz_clk_main_ops,
349    },
350    .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
351};
352
353325static struct main_clk jz_clk_high_speed_peripheral = {
354326    .clk = {
355327        .name = "hclk",
...... 
369341    .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
370342};
371343
372static const struct clk_ops jz_clk_ko_ops = {
373    .enable = jz_clk_ko_enable,
374    .disable = jz_clk_ko_disable,
375    .is_enabled = jz_clk_ko_is_enabled,
376};
377
378static struct clk jz_clk_ko = {
379    .name = "cko",
380    .parent = &jz_clk_memory.clk,
381    .ops = &jz_clk_ko_ops,
382};
383
384344static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
385345{
386346    if (parent == &jz_clk_pll)
...... 
409369    return 0;
410370}
411371
412static int jz_clk_udc_enable(struct clk *clk)
372static int jz_clk_udc_phy_enable(struct clk *clk)
413373{
414374    jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
415375            JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
...... 
417377    return 0;
418378}
419379
420static int jz_clk_udc_disable(struct clk *clk)
380static int jz_clk_udc_phy_disable(struct clk *clk)
421381{
422382    jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
423383            JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
...... 
425385    return 0;
426386}
427387
428static int jz_clk_udc_is_enabled(struct clk *clk)
388static int jz_clk_udc_phy_is_enabled(struct clk *clk)
429389{
430390    return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
431391            JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
432392}
433393
394static int jz_clk_udc_enable(struct clk *clk)
395{
396    jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
397
398    return 0;
399}
400
401static int jz_clk_udc_disable(struct clk *clk)
402{
403    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
404
405    return 0;
406}
407
408static int jz_clk_udc_is_enabled(struct clk *clk)
409{
410    return !!(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & JZ_CLOCK_GATE_UDC);
411}
412
434413static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
435414{
436415    if (parent == &jz_clk_pll_half)
...... 
599578    .is_enabled = jz_clk_is_enabled_gating,
600579};
601580
602static struct divided_clk jz4740_clock_divided_clks[] = {
581static struct divided_clk jz4750_clock_divided_clks[] = {
603582    [0] = {
604583        .clk = {
605584            .name = "i2s",
...... 
624603        .clk = {
625604            .name = "lcd_pclk",
626605            .parent = &jz_clk_pll_half,
627            .gate_bit = JZ4740_CLK_NOT_GATED,
606            .gate_bit = JZ47XX_CLK_NOT_GATED,
628607            .ops = &jz_clk_divided_ops,
629608        },
630609        .reg = JZ_REG_CLOCK_LCD,
...... 
652631    },
653632};
654633
634static const struct clk_ops jz_clk_udc_phy_ops = {
635    .enable = jz_clk_udc_phy_enable,
636    .disable = jz_clk_udc_phy_disable,
637    .is_enabled = jz_clk_udc_phy_is_enabled,
638};
639
655640static const struct clk_ops jz_clk_udc_ops = {
656641    .set_parent = jz_clk_udc_set_parent,
657642    .set_rate = jz_clk_udc_set_rate,
...... 
667652    .is_enabled = jz_clk_is_enabled_gating,
668653};
669654
670static struct clk jz4740_clock_simple_clks[] = {
655static struct clk jz4750_clock_simple_clks[] = {
671656    [0] = {
672657        .name = "udc",
673658        .parent = &jz_clk_ext.clk,
...... 
715700        .gate_bit = JZ_CLOCK_GATE_AIC,
716701        .ops = &jz_clk_simple_ops,
717702    },
703    [8] = {
704        .name = "udc-phy",
705        .parent = &jz4750_clock_simple_clks[0], /* udc */
706        .ops = &jz_clk_udc_phy_ops,
707    },
718708};
719709
720710static struct static_clk jz_clk_rtc = {
...... 
833823    clk_add(&jz_clk_cpu.clk);
834824    clk_add(&jz_clk_high_speed_peripheral.clk);
835825    clk_add(&jz_clk_low_speed_peripheral.clk);
836    clk_add(&jz_clk_ko);
837826    clk_add(&jz_clk_ld);
838827    clk_add(&jz_clk_rtc.clk);
839828
840    for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
841        clk_add(&jz4740_clock_divided_clks[i].clk);
829    for (i = 0; i < ARRAY_SIZE(jz4750_clock_divided_clks); ++i)
830        clk_add(&jz4750_clock_divided_clks[i].clk);
842831
843    for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i)
844        clk_add(&jz4740_clock_simple_clks[i]);
832    for (i = 0; i < ARRAY_SIZE(jz4750_clock_simple_clks); ++i)
833        clk_add(&jz4750_clock_simple_clks[i]);
845834}
846835
847void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
836void jz47xx_clock_set_wait_mode(enum jz47xx_wait_mode mode)
848837{
849838    switch (mode) {
850    case JZ4740_WAIT_MODE_IDLE:
839    case JZ47XX_WAIT_MODE_IDLE:
851840        jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
852841        break;
853    case JZ4740_WAIT_MODE_SLEEP:
842    case JZ47XX_WAIT_MODE_SLEEP:
854843        jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
855844        break;
856845    }
857846}
858847
859void jz4740_clock_udc_disable_auto_suspend(void)
860{
861    jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
862}
863EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
864
865void jz4740_clock_udc_enable_auto_suspend(void)
866{
867    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
868}
869EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
870
871void jz4740_clock_suspend(void)
848void jz47xx_clock_suspend(void)
872849{
873850    jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
874851        JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
...... 
876853    jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
877854}
878855
879void jz4740_clock_resume(void)
856void jz47xx_clock_resume(void)
880857{
881858    uint32_t pll;
882859
...... 
890867        JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
891868}
892869
893static int jz4740_clock_init(void)
870static int jz4750_clock_init(void)
894871{
895872    uint32_t val;
896873
...... 
900877
901878    spin_lock_init(&jz_clock_lock);
902879
903    jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
904    jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
880    jz_clk_ext.rate = jz47xx_clock_bdata.ext_rate;
881    jz_clk_rtc.rate = jz47xx_clock_bdata.rtc_rate;
905882
906883    val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
907884
908885    if (val & JZ_CLOCK_SPI_SRC_PLL)
909        jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
886        jz4750_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
910887
911888    val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
912889
913890    if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
914        jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
891        jz4750_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
915892
916893    if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
917        jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
894        jz4750_clock_simple_clks[0].parent = &jz_clk_pll_half;
918895
919896    jz4740_clock_debugfs_init();
920897
...... 
922899
923900    return 0;
924901}
925arch_initcall(jz4740_clock_init);
902arch_initcall(jz4750_clock_init);
arch/mips/jz47xx/jz4750/platform.c
8383    struct plat_serial8250_port *p;
8484
8585    for (p = jz4750_uart_data; p->flags != 0; ++p)
86        p->uartclk = jz4740_clock_bdata.ext_rate;
86        p->uartclk = jz47xx_clock_bdata.ext_rate;
8787
8888    platform_device_register(&jz4740_uart_device);
8989}
arch/mips/jz47xx/ost.c
125125
126126    jz47xx_ost_clockevent.irq = irq;
127127
128    clk_rate = jz4740_clock_bdata.ext_rate >> 4;
128    clk_rate = jz47xx_clock_bdata.ext_rate >> 4;
129129
130130    clocksource_set_clock(&jz47xx_ost_clocksource, clk_rate);
131131    ret = clocksource_register(&jz47xx_ost_clocksource);
arch/mips/jz47xx/timer-cevt.c
9696
9797    jz47xx_clockevent.irq = irq;
9898
99    clk_rate = jz4740_clock_bdata.ext_rate >> 4;
99    clk_rate = jz47xx_clock_bdata.ext_rate >> 4;
100100    jz47xx_ticks_per_jiffy = DIV_ROUND_CLOSEST(clk_rate, HZ);
101101
102102    clockevent_set_clock(&jz47xx_clockevent, clk_rate);
arch/mips/jz47xx/timer-csrc.c
4545
4646    jz47xx_timer_clocksource = timer_id;
4747
48    clk_rate = jz4740_clock_bdata.ext_rate >> 4;
48    clk_rate = jz47xx_clock_bdata.ext_rate >> 4;
4949
5050    clocksource_set_clock(&jz47xx_clocksource, clk_rate);
5151    ret = clocksource_register(&jz47xx_clocksource);

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