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Source at commit 01698f4eb74c5987b6eaf2229d28a2efea143b4d created 11 years 10 months ago. By Paul Cercueil, MIPS: JZ4740: LCD: Fixed LCD_CMD consts and completed LCD_STATE consts | |
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1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 SoC LCD framebuffer driver |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | */ |
15 | |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> |
18 | #include <linux/mutex.h> |
19 | #include <linux/platform_device.h> |
20 | |
21 | #include <linux/clk.h> |
22 | #include <linux/delay.h> |
23 | |
24 | #include <linux/console.h> |
25 | #include <linux/fb.h> |
26 | |
27 | #include <linux/dma-mapping.h> |
28 | |
29 | #include <asm/mach-jz4740/jz4740_fb.h> |
30 | #include <asm/mach-jz4740/gpio.h> |
31 | |
32 | #define JZ_REG_LCD_CFG 0x00 |
33 | #define JZ_REG_LCD_VSYNC 0x04 |
34 | #define JZ_REG_LCD_HSYNC 0x08 |
35 | #define JZ_REG_LCD_VAT 0x0C |
36 | #define JZ_REG_LCD_DAH 0x10 |
37 | #define JZ_REG_LCD_DAV 0x14 |
38 | #define JZ_REG_LCD_PS 0x18 |
39 | #define JZ_REG_LCD_CLS 0x1C |
40 | #define JZ_REG_LCD_SPL 0x20 |
41 | #define JZ_REG_LCD_REV 0x24 |
42 | #define JZ_REG_LCD_CTRL 0x30 |
43 | #define JZ_REG_LCD_STATE 0x34 |
44 | #define JZ_REG_LCD_IID 0x38 |
45 | #define JZ_REG_LCD_DA0 0x40 |
46 | #define JZ_REG_LCD_SA0 0x44 |
47 | #define JZ_REG_LCD_FID0 0x48 |
48 | #define JZ_REG_LCD_CMD0 0x4C |
49 | #define JZ_REG_LCD_DA1 0x50 |
50 | #define JZ_REG_LCD_SA1 0x54 |
51 | #define JZ_REG_LCD_FID1 0x58 |
52 | #define JZ_REG_LCD_CMD1 0x5C |
53 | |
54 | #define JZ_LCD_CFG_SLCD BIT(31) |
55 | #define JZ_LCD_CFG_PS_DISABLE BIT(23) |
56 | #define JZ_LCD_CFG_CLS_DISABLE BIT(22) |
57 | #define JZ_LCD_CFG_SPL_DISABLE BIT(21) |
58 | #define JZ_LCD_CFG_REV_DISABLE BIT(20) |
59 | #define JZ_LCD_CFG_HSYNCM BIT(19) |
60 | #define JZ_LCD_CFG_PCLKM BIT(18) |
61 | #define JZ_LCD_CFG_INV BIT(17) |
62 | #define JZ_LCD_CFG_SYNC_DIR BIT(16) |
63 | #define JZ_LCD_CFG_PS_POLARITY BIT(15) |
64 | #define JZ_LCD_CFG_CLS_POLARITY BIT(14) |
65 | #define JZ_LCD_CFG_SPL_POLARITY BIT(13) |
66 | #define JZ_LCD_CFG_REV_POLARITY BIT(12) |
67 | #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) |
68 | #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) |
69 | #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) |
70 | #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) |
71 | #define JZ_LCD_CFG_18_BIT BIT(7) |
72 | #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) |
73 | #define JZ_LCD_CFG_MODE_MASK 0xf |
74 | |
75 | #define JZ_LCD_CTRL_BURST_4 (0x0 << 28) |
76 | #define JZ_LCD_CTRL_BURST_8 (0x1 << 28) |
77 | #define JZ_LCD_CTRL_BURST_16 (0x2 << 28) |
78 | #define JZ_LCD_CTRL_RGB555 BIT(27) |
79 | #define JZ_LCD_CTRL_OFUP BIT(26) |
80 | #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) |
81 | #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) |
82 | #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) |
83 | #define JZ_LCD_CTRL_PDD_MASK (0xff << 16) |
84 | #define JZ_LCD_CTRL_EOF_IRQ BIT(13) |
85 | #define JZ_LCD_CTRL_SOF_IRQ BIT(12) |
86 | #define JZ_LCD_CTRL_OFU_IRQ BIT(11) |
87 | #define JZ_LCD_CTRL_IFU0_IRQ BIT(10) |
88 | #define JZ_LCD_CTRL_IFU1_IRQ BIT(9) |
89 | #define JZ_LCD_CTRL_DD_IRQ BIT(8) |
90 | #define JZ_LCD_CTRL_QDD_IRQ BIT(7) |
91 | #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) |
92 | #define JZ_LCD_CTRL_LSB_FISRT BIT(5) |
93 | #define JZ_LCD_CTRL_DISABLE BIT(4) |
94 | #define JZ_LCD_CTRL_ENABLE BIT(3) |
95 | #define JZ_LCD_CTRL_BPP_1 0x0 |
96 | #define JZ_LCD_CTRL_BPP_2 0x1 |
97 | #define JZ_LCD_CTRL_BPP_4 0x2 |
98 | #define JZ_LCD_CTRL_BPP_8 0x3 |
99 | #define JZ_LCD_CTRL_BPP_15_16 0x4 |
100 | #define JZ_LCD_CTRL_BPP_18_24 0x5 |
101 | |
102 | #define JZ_LCD_CMD_SOF_IRQ BIT(31) |
103 | #define JZ_LCD_CMD_EOF_IRQ BIT(30) |
104 | #define JZ_LCD_CMD_ENABLE_PAL BIT(28) |
105 | |
106 | #define JZ_LCD_SYNC_MASK 0x3ff |
107 | |
108 | #define JZ_LCD_STATE_QUICK_DISABLED BIT(7) |
109 | #define JZ_LCD_STATE_EOF BIT(5) |
110 | #define JZ_LCD_STATE_SOF BIT(4) |
111 | #define JZ_LCD_STATE_OUT_FIFO_UNDERRUN BIT(3) |
112 | #define JZ_LCD_STATE_FIFO0_UNDERRUN BIT(2) |
113 | #define JZ_LCD_STATE_FIFO1_UNDERRUN BIT(1) |
114 | #define JZ_LCD_STATE_DISABLED BIT(0) |
115 | |
116 | struct jzfb_framedesc { |
117 | uint32_t next; |
118 | uint32_t addr; |
119 | uint32_t id; |
120 | uint32_t cmd; |
121 | } __packed; |
122 | |
123 | struct jzfb { |
124 | struct fb_info *fb; |
125 | struct platform_device *pdev; |
126 | void __iomem *base; |
127 | struct resource *mem; |
128 | struct jz4740_fb_platform_data *pdata; |
129 | |
130 | size_t vidmem_size; |
131 | void *vidmem; |
132 | dma_addr_t vidmem_phys; |
133 | struct jzfb_framedesc *framedesc; |
134 | dma_addr_t framedesc_phys; |
135 | |
136 | struct clk *ldclk; |
137 | struct clk *lpclk; |
138 | |
139 | unsigned is_enabled:1; |
140 | struct mutex lock; |
141 | |
142 | uint32_t pseudo_palette[16]; |
143 | }; |
144 | |
145 | static const struct fb_fix_screeninfo jzfb_fix = { |
146 | .id = "JZ4740 FB", |
147 | .type = FB_TYPE_PACKED_PIXELS, |
148 | .visual = FB_VISUAL_TRUECOLOR, |
149 | .xpanstep = 0, |
150 | .ypanstep = 0, |
151 | .ywrapstep = 0, |
152 | .accel = FB_ACCEL_NONE, |
153 | }; |
154 | |
155 | static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = { |
156 | JZ_GPIO_BULK_PIN(LCD_PCLK), |
157 | JZ_GPIO_BULK_PIN(LCD_HSYNC), |
158 | JZ_GPIO_BULK_PIN(LCD_VSYNC), |
159 | JZ_GPIO_BULK_PIN(LCD_DE), |
160 | JZ_GPIO_BULK_PIN(LCD_PS), |
161 | JZ_GPIO_BULK_PIN(LCD_REV), |
162 | JZ_GPIO_BULK_PIN(LCD_CLS), |
163 | JZ_GPIO_BULK_PIN(LCD_SPL), |
164 | }; |
165 | |
166 | static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = { |
167 | JZ_GPIO_BULK_PIN(LCD_DATA0), |
168 | JZ_GPIO_BULK_PIN(LCD_DATA1), |
169 | JZ_GPIO_BULK_PIN(LCD_DATA2), |
170 | JZ_GPIO_BULK_PIN(LCD_DATA3), |
171 | JZ_GPIO_BULK_PIN(LCD_DATA4), |
172 | JZ_GPIO_BULK_PIN(LCD_DATA5), |
173 | JZ_GPIO_BULK_PIN(LCD_DATA6), |
174 | JZ_GPIO_BULK_PIN(LCD_DATA7), |
175 | JZ_GPIO_BULK_PIN(LCD_DATA8), |
176 | JZ_GPIO_BULK_PIN(LCD_DATA9), |
177 | JZ_GPIO_BULK_PIN(LCD_DATA10), |
178 | JZ_GPIO_BULK_PIN(LCD_DATA11), |
179 | JZ_GPIO_BULK_PIN(LCD_DATA12), |
180 | JZ_GPIO_BULK_PIN(LCD_DATA13), |
181 | JZ_GPIO_BULK_PIN(LCD_DATA14), |
182 | JZ_GPIO_BULK_PIN(LCD_DATA15), |
183 | JZ_GPIO_BULK_PIN(LCD_DATA16), |
184 | JZ_GPIO_BULK_PIN(LCD_DATA17), |
185 | }; |
186 | |
187 | static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb) |
188 | { |
189 | unsigned int num; |
190 | |
191 | switch (jzfb->pdata->lcd_type) { |
192 | case JZ_LCD_TYPE_GENERIC_16_BIT: |
193 | num = 4; |
194 | break; |
195 | case JZ_LCD_TYPE_GENERIC_18_BIT: |
196 | num = 4; |
197 | break; |
198 | case JZ_LCD_TYPE_8BIT_SERIAL: |
199 | num = 3; |
200 | break; |
201 | case JZ_LCD_TYPE_SPECIAL_TFT_1: |
202 | case JZ_LCD_TYPE_SPECIAL_TFT_2: |
203 | case JZ_LCD_TYPE_SPECIAL_TFT_3: |
204 | num = 8; |
205 | break; |
206 | default: |
207 | num = 0; |
208 | break; |
209 | } |
210 | return num; |
211 | } |
212 | |
213 | static unsigned int jzfb_num_data_pins(struct jzfb *jzfb) |
214 | { |
215 | unsigned int num; |
216 | |
217 | switch (jzfb->pdata->lcd_type) { |
218 | case JZ_LCD_TYPE_GENERIC_16_BIT: |
219 | num = 16; |
220 | break; |
221 | case JZ_LCD_TYPE_GENERIC_18_BIT: |
222 | num = 18; |
223 | break; |
224 | case JZ_LCD_TYPE_8BIT_SERIAL: |
225 | num = 8; |
226 | break; |
227 | case JZ_LCD_TYPE_SPECIAL_TFT_1: |
228 | case JZ_LCD_TYPE_SPECIAL_TFT_2: |
229 | case JZ_LCD_TYPE_SPECIAL_TFT_3: |
230 | if (jzfb->pdata->bpp == 18) |
231 | num = 18; |
232 | else |
233 | num = 16; |
234 | break; |
235 | default: |
236 | num = 0; |
237 | break; |
238 | } |
239 | return num; |
240 | } |
241 | |
242 | /* Based on CNVT_TOHW macro from skeletonfb.c */ |
243 | static inline uint32_t jzfb_convert_color_to_hw(unsigned val, |
244 | struct fb_bitfield *bf) |
245 | { |
246 | return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset; |
247 | } |
248 | |
249 | static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, |
250 | unsigned blue, unsigned transp, struct fb_info *fb) |
251 | { |
252 | uint32_t color; |
253 | |
254 | if (regno >= 16) |
255 | return -EINVAL; |
256 | |
257 | color = jzfb_convert_color_to_hw(red, &fb->var.red); |
258 | color |= jzfb_convert_color_to_hw(green, &fb->var.green); |
259 | color |= jzfb_convert_color_to_hw(blue, &fb->var.blue); |
260 | color |= jzfb_convert_color_to_hw(transp, &fb->var.transp); |
261 | |
262 | ((uint32_t *)(fb->pseudo_palette))[regno] = color; |
263 | |
264 | return 0; |
265 | } |
266 | |
267 | static int jzfb_get_controller_bpp(struct jzfb *jzfb) |
268 | { |
269 | switch (jzfb->pdata->bpp) { |
270 | case 18: |
271 | case 24: |
272 | return 32; |
273 | case 15: |
274 | return 16; |
275 | default: |
276 | return jzfb->pdata->bpp; |
277 | } |
278 | } |
279 | |
280 | static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb, |
281 | struct fb_var_screeninfo *var) |
282 | { |
283 | size_t i; |
284 | struct fb_videomode *mode = jzfb->pdata->modes; |
285 | |
286 | for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) { |
287 | if (mode->xres == var->xres && mode->yres == var->yres) |
288 | return mode; |
289 | } |
290 | |
291 | return NULL; |
292 | } |
293 | |
294 | static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb) |
295 | { |
296 | struct jzfb *jzfb = fb->par; |
297 | struct fb_videomode *mode; |
298 | |
299 | if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) && |
300 | var->bits_per_pixel != jzfb->pdata->bpp) |
301 | return -EINVAL; |
302 | |
303 | mode = jzfb_get_mode(jzfb, var); |
304 | if (mode == NULL) |
305 | return -EINVAL; |
306 | |
307 | fb_videomode_to_var(var, mode); |
308 | |
309 | switch (jzfb->pdata->bpp) { |
310 | case 8: |
311 | break; |
312 | case 15: |
313 | var->red.offset = 10; |
314 | var->red.length = 5; |
315 | var->green.offset = 6; |
316 | var->green.length = 5; |
317 | var->blue.offset = 0; |
318 | var->blue.length = 5; |
319 | break; |
320 | case 16: |
321 | var->red.offset = 11; |
322 | var->red.length = 5; |
323 | var->green.offset = 5; |
324 | var->green.length = 6; |
325 | var->blue.offset = 0; |
326 | var->blue.length = 5; |
327 | break; |
328 | case 18: |
329 | var->red.offset = 16; |
330 | var->red.length = 6; |
331 | var->green.offset = 8; |
332 | var->green.length = 6; |
333 | var->blue.offset = 0; |
334 | var->blue.length = 6; |
335 | var->bits_per_pixel = 32; |
336 | break; |
337 | case 32: |
338 | case 24: |
339 | var->transp.offset = 24; |
340 | var->transp.length = 8; |
341 | var->red.offset = 16; |
342 | var->red.length = 8; |
343 | var->green.offset = 8; |
344 | var->green.length = 8; |
345 | var->blue.offset = 0; |
346 | var->blue.length = 8; |
347 | var->bits_per_pixel = 32; |
348 | break; |
349 | default: |
350 | break; |
351 | } |
352 | |
353 | return 0; |
354 | } |
355 | |
356 | static int jzfb_set_par(struct fb_info *info) |
357 | { |
358 | struct jzfb *jzfb = info->par; |
359 | struct jz4740_fb_platform_data *pdata = jzfb->pdata; |
360 | struct fb_var_screeninfo *var = &info->var; |
361 | struct fb_videomode *mode; |
362 | uint16_t hds, vds; |
363 | uint16_t hde, vde; |
364 | uint16_t ht, vt; |
365 | uint32_t ctrl; |
366 | uint32_t cfg; |
367 | unsigned long rate; |
368 | |
369 | mode = jzfb_get_mode(jzfb, var); |
370 | if (mode == NULL) |
371 | return -EINVAL; |
372 | |
373 | if (mode == info->mode) |
374 | return 0; |
375 | |
376 | info->mode = mode; |
377 | |
378 | hds = mode->hsync_len + mode->left_margin; |
379 | hde = hds + mode->xres; |
380 | ht = hde + mode->right_margin; |
381 | |
382 | vds = mode->vsync_len + mode->upper_margin; |
383 | vde = vds + mode->yres; |
384 | vt = vde + mode->lower_margin; |
385 | |
386 | ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16; |
387 | |
388 | switch (pdata->bpp) { |
389 | case 1: |
390 | ctrl |= JZ_LCD_CTRL_BPP_1; |
391 | break; |
392 | case 2: |
393 | ctrl |= JZ_LCD_CTRL_BPP_2; |
394 | break; |
395 | case 4: |
396 | ctrl |= JZ_LCD_CTRL_BPP_4; |
397 | break; |
398 | case 8: |
399 | ctrl |= JZ_LCD_CTRL_BPP_8; |
400 | break; |
401 | case 15: |
402 | ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */ |
403 | case 16: |
404 | ctrl |= JZ_LCD_CTRL_BPP_15_16; |
405 | break; |
406 | case 18: |
407 | case 24: |
408 | case 32: |
409 | ctrl |= JZ_LCD_CTRL_BPP_18_24; |
410 | break; |
411 | default: |
412 | break; |
413 | } |
414 | |
415 | cfg = pdata->lcd_type & 0xf; |
416 | |
417 | if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) |
418 | cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; |
419 | |
420 | if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) |
421 | cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; |
422 | |
423 | if (pdata->pixclk_falling_edge) |
424 | cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; |
425 | |
426 | if (pdata->date_enable_active_low) |
427 | cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; |
428 | |
429 | if (pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT) |
430 | cfg |= JZ_LCD_CFG_18_BIT; |
431 | |
432 | if (mode->pixclock) { |
433 | rate = PICOS2KHZ(mode->pixclock) * 1000; |
434 | mode->refresh = rate / vt / ht; |
435 | } else { |
436 | if (pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL) |
437 | rate = mode->refresh * (vt + 2 * mode->xres) * ht; |
438 | else |
439 | rate = mode->refresh * vt * ht; |
440 | |
441 | mode->pixclock = KHZ2PICOS(rate / 1000); |
442 | } |
443 | |
444 | mutex_lock(&jzfb->lock); |
445 | if (!jzfb->is_enabled) |
446 | clk_enable(jzfb->ldclk); |
447 | else |
448 | ctrl |= JZ_LCD_CTRL_ENABLE; |
449 | |
450 | switch (pdata->lcd_type) { |
451 | case JZ_LCD_TYPE_SPECIAL_TFT_1: |
452 | case JZ_LCD_TYPE_SPECIAL_TFT_2: |
453 | case JZ_LCD_TYPE_SPECIAL_TFT_3: |
454 | writel(pdata->special_tft_config.spl, jzfb->base + JZ_REG_LCD_SPL); |
455 | writel(pdata->special_tft_config.cls, jzfb->base + JZ_REG_LCD_CLS); |
456 | writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_PS); |
457 | writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_REV); |
458 | break; |
459 | default: |
460 | cfg |= JZ_LCD_CFG_PS_DISABLE; |
461 | cfg |= JZ_LCD_CFG_CLS_DISABLE; |
462 | cfg |= JZ_LCD_CFG_SPL_DISABLE; |
463 | cfg |= JZ_LCD_CFG_REV_DISABLE; |
464 | break; |
465 | } |
466 | |
467 | writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC); |
468 | writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC); |
469 | |
470 | writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT); |
471 | |
472 | writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH); |
473 | writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV); |
474 | |
475 | writel(cfg, jzfb->base + JZ_REG_LCD_CFG); |
476 | |
477 | writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); |
478 | |
479 | if (!jzfb->is_enabled) |
480 | clk_disable(jzfb->ldclk); |
481 | |
482 | mutex_unlock(&jzfb->lock); |
483 | |
484 | clk_set_rate(jzfb->lpclk, rate); |
485 | clk_set_rate(jzfb->ldclk, rate * 3); |
486 | |
487 | return 0; |
488 | } |
489 | |
490 | static void jzfb_enable(struct jzfb *jzfb) |
491 | { |
492 | uint32_t ctrl; |
493 | |
494 | clk_enable(jzfb->ldclk); |
495 | |
496 | jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
497 | jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); |
498 | |
499 | writel(0, jzfb->base + JZ_REG_LCD_STATE); |
500 | |
501 | writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); |
502 | |
503 | ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); |
504 | ctrl |= JZ_LCD_CTRL_ENABLE; |
505 | ctrl &= ~JZ_LCD_CTRL_DISABLE; |
506 | writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); |
507 | } |
508 | |
509 | static void jzfb_disable(struct jzfb *jzfb) |
510 | { |
511 | uint32_t ctrl; |
512 | |
513 | ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); |
514 | ctrl |= JZ_LCD_CTRL_DISABLE; |
515 | writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); |
516 | do { |
517 | ctrl = readl(jzfb->base + JZ_REG_LCD_STATE); |
518 | } while (!(ctrl & JZ_LCD_STATE_DISABLED)); |
519 | |
520 | jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
521 | jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); |
522 | |
523 | clk_disable(jzfb->ldclk); |
524 | } |
525 | |
526 | static int jzfb_blank(int blank_mode, struct fb_info *info) |
527 | { |
528 | struct jzfb *jzfb = info->par; |
529 | |
530 | switch (blank_mode) { |
531 | case FB_BLANK_UNBLANK: |
532 | mutex_lock(&jzfb->lock); |
533 | if (jzfb->is_enabled) { |
534 | mutex_unlock(&jzfb->lock); |
535 | return 0; |
536 | } |
537 | |
538 | jzfb_enable(jzfb); |
539 | jzfb->is_enabled = 1; |
540 | |
541 | mutex_unlock(&jzfb->lock); |
542 | break; |
543 | default: |
544 | mutex_lock(&jzfb->lock); |
545 | if (!jzfb->is_enabled) { |
546 | mutex_unlock(&jzfb->lock); |
547 | return 0; |
548 | } |
549 | |
550 | jzfb_disable(jzfb); |
551 | jzfb->is_enabled = 0; |
552 | |
553 | mutex_unlock(&jzfb->lock); |
554 | break; |
555 | } |
556 | |
557 | return 0; |
558 | } |
559 | |
560 | static int jzfb_alloc_devmem(struct jzfb *jzfb) |
561 | { |
562 | int max_videosize = 0; |
563 | struct fb_videomode *mode = jzfb->pdata->modes; |
564 | void *page; |
565 | int i; |
566 | |
567 | for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) { |
568 | if (max_videosize < mode->xres * mode->yres) |
569 | max_videosize = mode->xres * mode->yres; |
570 | } |
571 | |
572 | max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3; |
573 | |
574 | jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev, |
575 | sizeof(*jzfb->framedesc), |
576 | &jzfb->framedesc_phys, GFP_KERNEL); |
577 | |
578 | if (!jzfb->framedesc) |
579 | return -ENOMEM; |
580 | |
581 | jzfb->vidmem_size = PAGE_ALIGN(max_videosize); |
582 | jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev, |
583 | jzfb->vidmem_size, |
584 | &jzfb->vidmem_phys, GFP_KERNEL); |
585 | |
586 | if (!jzfb->vidmem) |
587 | goto err_free_framedesc; |
588 | |
589 | for (page = jzfb->vidmem; |
590 | page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size); |
591 | page += PAGE_SIZE) { |
592 | SetPageReserved(virt_to_page(page)); |
593 | } |
594 | |
595 | jzfb->framedesc->next = jzfb->framedesc_phys; |
596 | jzfb->framedesc->addr = jzfb->vidmem_phys; |
597 | jzfb->framedesc->id = 0xdeafbead; |
598 | jzfb->framedesc->cmd = 0; |
599 | jzfb->framedesc->cmd |= max_videosize / 4; |
600 | |
601 | return 0; |
602 | |
603 | err_free_framedesc: |
604 | dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), |
605 | jzfb->framedesc, jzfb->framedesc_phys); |
606 | return -ENOMEM; |
607 | } |
608 | |
609 | static void jzfb_free_devmem(struct jzfb *jzfb) |
610 | { |
611 | dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size, |
612 | jzfb->vidmem, jzfb->vidmem_phys); |
613 | dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc), |
614 | jzfb->framedesc, jzfb->framedesc_phys); |
615 | } |
616 | |
617 | static struct fb_ops jzfb_ops = { |
618 | .owner = THIS_MODULE, |
619 | .fb_check_var = jzfb_check_var, |
620 | .fb_set_par = jzfb_set_par, |
621 | .fb_blank = jzfb_blank, |
622 | .fb_fillrect = sys_fillrect, |
623 | .fb_copyarea = sys_copyarea, |
624 | .fb_imageblit = sys_imageblit, |
625 | .fb_setcolreg = jzfb_setcolreg, |
626 | }; |
627 | |
628 | static int jzfb_probe(struct platform_device *pdev) |
629 | { |
630 | int ret; |
631 | struct jzfb *jzfb; |
632 | struct fb_info *fb; |
633 | struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data; |
634 | struct resource *mem; |
635 | |
636 | if (!pdata) { |
637 | dev_err(&pdev->dev, "Missing platform data\n"); |
638 | return -ENXIO; |
639 | } |
640 | |
641 | fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev); |
642 | if (!fb) { |
643 | dev_err(&pdev->dev, "Failed to allocate framebuffer device\n"); |
644 | return -ENOMEM; |
645 | } |
646 | |
647 | fb->fbops = &jzfb_ops; |
648 | fb->flags = FBINFO_DEFAULT; |
649 | |
650 | jzfb = fb->par; |
651 | jzfb->pdev = pdev; |
652 | jzfb->pdata = pdata; |
653 | |
654 | jzfb->ldclk = devm_clk_get(&pdev->dev, "lcd"); |
655 | if (IS_ERR(jzfb->ldclk)) { |
656 | ret = PTR_ERR(jzfb->ldclk); |
657 | dev_err(&pdev->dev, "Failed to get lcd clock: %d\n", ret); |
658 | goto err_framebuffer_release; |
659 | } |
660 | |
661 | jzfb->lpclk = devm_clk_get(&pdev->dev, "lcd_pclk"); |
662 | if (IS_ERR(jzfb->lpclk)) { |
663 | ret = PTR_ERR(jzfb->lpclk); |
664 | dev_err(&pdev->dev, "Failed to get lcd pixel clock: %d\n", ret); |
665 | goto err_framebuffer_release; |
666 | } |
667 | |
668 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
669 | jzfb->base = devm_ioremap_resource(&pdev->dev, mem); |
670 | if (IS_ERR(jzfb->base)) { |
671 | ret = PTR_ERR(jzfb->base); |
672 | goto err_framebuffer_release; |
673 | } |
674 | |
675 | platform_set_drvdata(pdev, jzfb); |
676 | |
677 | mutex_init(&jzfb->lock); |
678 | |
679 | fb_videomode_to_modelist(pdata->modes, pdata->num_modes, |
680 | &fb->modelist); |
681 | fb_videomode_to_var(&fb->var, pdata->modes); |
682 | fb->var.bits_per_pixel = pdata->bpp; |
683 | jzfb_check_var(&fb->var, fb); |
684 | |
685 | ret = jzfb_alloc_devmem(jzfb); |
686 | if (ret) { |
687 | dev_err(&pdev->dev, "Failed to allocate video memory\n"); |
688 | goto err_framebuffer_release; |
689 | } |
690 | |
691 | fb->fix = jzfb_fix; |
692 | fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8; |
693 | fb->fix.mmio_start = mem->start; |
694 | fb->fix.mmio_len = resource_size(mem); |
695 | fb->fix.smem_start = jzfb->vidmem_phys; |
696 | fb->fix.smem_len = fb->fix.line_length * fb->var.yres; |
697 | fb->screen_base = jzfb->vidmem; |
698 | fb->pseudo_palette = jzfb->pseudo_palette; |
699 | |
700 | fb_alloc_cmap(&fb->cmap, 256, 0); |
701 | |
702 | clk_enable(jzfb->ldclk); |
703 | jzfb->is_enabled = 1; |
704 | |
705 | writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); |
706 | |
707 | fb->mode = NULL; |
708 | jzfb_set_par(fb); |
709 | |
710 | jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
711 | jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); |
712 | |
713 | ret = register_framebuffer(fb); |
714 | if (ret) { |
715 | dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret); |
716 | goto err_free_devmem; |
717 | } |
718 | |
719 | jzfb->fb = fb; |
720 | |
721 | return 0; |
722 | |
723 | err_free_devmem: |
724 | jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
725 | jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); |
726 | |
727 | fb_dealloc_cmap(&fb->cmap); |
728 | jzfb_free_devmem(jzfb); |
729 | err_framebuffer_release: |
730 | framebuffer_release(fb); |
731 | return ret; |
732 | } |
733 | |
734 | static int jzfb_remove(struct platform_device *pdev) |
735 | { |
736 | struct jzfb *jzfb = platform_get_drvdata(pdev); |
737 | |
738 | jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb); |
739 | |
740 | jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
741 | jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); |
742 | |
743 | fb_dealloc_cmap(&jzfb->fb->cmap); |
744 | jzfb_free_devmem(jzfb); |
745 | |
746 | platform_set_drvdata(pdev, NULL); |
747 | |
748 | framebuffer_release(jzfb->fb); |
749 | |
750 | return 0; |
751 | } |
752 | |
753 | #ifdef CONFIG_PM |
754 | |
755 | static int jzfb_suspend(struct device *dev) |
756 | { |
757 | struct jzfb *jzfb = dev_get_drvdata(dev); |
758 | |
759 | console_lock(); |
760 | fb_set_suspend(jzfb->fb, 1); |
761 | console_unlock(); |
762 | |
763 | mutex_lock(&jzfb->lock); |
764 | if (jzfb->is_enabled) |
765 | jzfb_disable(jzfb); |
766 | mutex_unlock(&jzfb->lock); |
767 | |
768 | return 0; |
769 | } |
770 | |
771 | static int jzfb_resume(struct device *dev) |
772 | { |
773 | struct jzfb *jzfb = dev_get_drvdata(dev); |
774 | clk_enable(jzfb->ldclk); |
775 | |
776 | mutex_lock(&jzfb->lock); |
777 | if (jzfb->is_enabled) |
778 | jzfb_enable(jzfb); |
779 | mutex_unlock(&jzfb->lock); |
780 | |
781 | console_lock(); |
782 | fb_set_suspend(jzfb->fb, 0); |
783 | console_unlock(); |
784 | |
785 | return 0; |
786 | } |
787 | |
788 | static const struct dev_pm_ops jzfb_pm_ops = { |
789 | .suspend = jzfb_suspend, |
790 | .resume = jzfb_resume, |
791 | .poweroff = jzfb_suspend, |
792 | .restore = jzfb_resume, |
793 | }; |
794 | |
795 | #define JZFB_PM_OPS (&jzfb_pm_ops) |
796 | |
797 | #else |
798 | #define JZFB_PM_OPS NULL |
799 | #endif |
800 | |
801 | static struct platform_driver jzfb_driver = { |
802 | .probe = jzfb_probe, |
803 | .remove = jzfb_remove, |
804 | .driver = { |
805 | .name = "jz4740-fb", |
806 | .pm = JZFB_PM_OPS, |
807 | }, |
808 | }; |
809 | |
810 | static int __init jzfb_init(void) |
811 | { |
812 | return platform_driver_register(&jzfb_driver); |
813 | } |
814 | module_init(jzfb_init); |
815 | |
816 | static void __exit jzfb_exit(void) |
817 | { |
818 | platform_driver_unregister(&jzfb_driver); |
819 | } |
820 | module_exit(jzfb_exit); |
821 | |
822 | MODULE_LICENSE("GPL"); |
823 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |
824 | MODULE_DESCRIPTION("JZ4740 SoC LCD framebuffer driver"); |
825 | MODULE_ALIAS("platform:jz4740-fb"); |
826 |
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
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