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Source at commit 0c14655c8589bf91be352079120c64c1971502db created 13 years 10 months ago. By Lars-Peter Clausen, jz4740-udc: probe and remove should be in __dev{init,exit} sections | |
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1 | /* |
2 | * linux/drivers/usb/gadget/jz4740_udc.c |
3 | * |
4 | * Ingenic JZ4740 on-chip high speed USB device controller |
5 | * |
6 | * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc. |
7 | * Author: <jlwei@ingenic.cn> |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or |
12 | * (at your option) any later version. |
13 | */ |
14 | |
15 | /* |
16 | * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint. |
17 | * |
18 | * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk. |
19 | * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints. |
20 | */ |
21 | |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> |
24 | #include <linux/platform_device.h> |
25 | #include <linux/delay.h> |
26 | #include <linux/ioport.h> |
27 | #include <linux/slab.h> |
28 | #include <linux/errno.h> |
29 | #include <linux/init.h> |
30 | #include <linux/list.h> |
31 | #include <linux/interrupt.h> |
32 | #include <linux/proc_fs.h> |
33 | #include <linux/usb.h> |
34 | #include <linux/usb/gadget.h> |
35 | #include <linux/clk.h> |
36 | |
37 | #include <asm/byteorder.h> |
38 | #include <asm/io.h> |
39 | #include <asm/irq.h> |
40 | #include <asm/system.h> |
41 | #include <asm/mach-jz4740/clock.h> |
42 | |
43 | #include "jz4740_udc.h" |
44 | |
45 | #define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */ |
46 | #define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */ |
47 | #define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */ |
48 | #define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */ |
49 | #define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */ |
50 | #define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */ |
51 | #define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */ |
52 | #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */ |
53 | #define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */ |
54 | #define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */ |
55 | #define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */ |
56 | |
57 | #define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */ |
58 | #define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */ |
59 | #define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */ |
60 | #define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */ |
61 | #define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */ |
62 | #define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */ |
63 | #define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */ |
64 | #define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */ |
65 | |
66 | #define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20) |
67 | |
68 | #define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */ |
69 | #define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */ |
70 | |
71 | #define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */ |
72 | #define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */ |
73 | #define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */ |
74 | #define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */ |
75 | #define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */ |
76 | #define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */ |
77 | #define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */ |
78 | |
79 | /* Power register bit masks */ |
80 | #define USB_POWER_SUSPENDM 0x01 |
81 | #define USB_POWER_RESUME 0x04 |
82 | #define USB_POWER_HSMODE 0x10 |
83 | #define USB_POWER_HSENAB 0x20 |
84 | #define USB_POWER_SOFTCONN 0x40 |
85 | |
86 | /* Interrupt register bit masks */ |
87 | #define USB_INTR_SUSPEND 0x01 |
88 | #define USB_INTR_RESUME 0x02 |
89 | #define USB_INTR_RESET 0x04 |
90 | |
91 | #define USB_INTR_EP0 0x0001 |
92 | #define USB_INTR_INEP1 0x0002 |
93 | #define USB_INTR_INEP2 0x0004 |
94 | #define USB_INTR_OUTEP1 0x0002 |
95 | |
96 | /* CSR0 bit masks */ |
97 | #define USB_CSR0_OUTPKTRDY 0x01 |
98 | #define USB_CSR0_INPKTRDY 0x02 |
99 | #define USB_CSR0_SENTSTALL 0x04 |
100 | #define USB_CSR0_DATAEND 0x08 |
101 | #define USB_CSR0_SETUPEND 0x10 |
102 | #define USB_CSR0_SENDSTALL 0x20 |
103 | #define USB_CSR0_SVDOUTPKTRDY 0x40 |
104 | #define USB_CSR0_SVDSETUPEND 0x80 |
105 | |
106 | /* Endpoint CSR register bits */ |
107 | #define USB_INCSRH_AUTOSET 0x80 |
108 | #define USB_INCSRH_ISO 0x40 |
109 | #define USB_INCSRH_MODE 0x20 |
110 | #define USB_INCSRH_DMAREQENAB 0x10 |
111 | #define USB_INCSRH_DMAREQMODE 0x04 |
112 | #define USB_INCSR_CDT 0x40 |
113 | #define USB_INCSR_SENTSTALL 0x20 |
114 | #define USB_INCSR_SENDSTALL 0x10 |
115 | #define USB_INCSR_FF 0x08 |
116 | #define USB_INCSR_UNDERRUN 0x04 |
117 | #define USB_INCSR_FFNOTEMPT 0x02 |
118 | #define USB_INCSR_INPKTRDY 0x01 |
119 | #define USB_OUTCSRH_AUTOCLR 0x80 |
120 | #define USB_OUTCSRH_ISO 0x40 |
121 | #define USB_OUTCSRH_DMAREQENAB 0x20 |
122 | #define USB_OUTCSRH_DNYT 0x10 |
123 | #define USB_OUTCSRH_DMAREQMODE 0x08 |
124 | #define USB_OUTCSR_CDT 0x80 |
125 | #define USB_OUTCSR_SENTSTALL 0x40 |
126 | #define USB_OUTCSR_SENDSTALL 0x20 |
127 | #define USB_OUTCSR_FF 0x10 |
128 | #define USB_OUTCSR_DATAERR 0x08 |
129 | #define USB_OUTCSR_OVERRUN 0x04 |
130 | #define USB_OUTCSR_FFFULL 0x02 |
131 | #define USB_OUTCSR_OUTPKTRDY 0x01 |
132 | |
133 | /* Testmode register bits */ |
134 | #define USB_TEST_SE0NAK 0x01 |
135 | #define USB_TEST_J 0x02 |
136 | #define USB_TEST_K 0x04 |
137 | #define USB_TEST_PACKET 0x08 |
138 | |
139 | /* DMA control bits */ |
140 | #define USB_CNTL_ENA 0x01 |
141 | #define USB_CNTL_DIR_IN 0x02 |
142 | #define USB_CNTL_MODE_1 0x04 |
143 | #define USB_CNTL_INTR_EN 0x08 |
144 | #define USB_CNTL_EP(n) ((n) << 4) |
145 | #define USB_CNTL_BURST_0 (0 << 9) |
146 | #define USB_CNTL_BURST_4 (1 << 9) |
147 | #define USB_CNTL_BURST_8 (2 << 9) |
148 | #define USB_CNTL_BURST_16 (3 << 9) |
149 | |
150 | |
151 | #ifndef DEBUG |
152 | # define DEBUG(fmt,args...) do {} while(0) |
153 | #endif |
154 | #ifndef DEBUG_EP0 |
155 | # define NO_STATES |
156 | # define DEBUG_EP0(fmt,args...) do {} while(0) |
157 | #endif |
158 | #ifndef DEBUG_SETUP |
159 | # define DEBUG_SETUP(fmt,args...) do {} while(0) |
160 | #endif |
161 | |
162 | static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */ |
163 | |
164 | module_param(use_dma, int, 0); |
165 | MODULE_PARM_DESC(use_dma, "DMA mode enable flag"); |
166 | |
167 | struct jz4740_udc *the_controller; |
168 | |
169 | /* |
170 | * Local declarations. |
171 | */ |
172 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep); |
173 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr); |
174 | |
175 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, |
176 | int status); |
177 | static void pio_irq_enable(struct jz4740_ep *ep); |
178 | static void pio_irq_disable(struct jz4740_ep *ep); |
179 | static void stop_activity(struct jz4740_udc *dev, |
180 | struct usb_gadget_driver *driver); |
181 | static void nuke(struct jz4740_ep *ep, int status); |
182 | static void flush(struct jz4740_ep *ep); |
183 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address); |
184 | |
185 | /*-------------------------------------------------------------------------*/ |
186 | |
187 | /* inline functions of register read/write/set/clear */ |
188 | |
189 | static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg) |
190 | { |
191 | return readb(udc->base + reg); |
192 | } |
193 | |
194 | static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg) |
195 | { |
196 | return readw(udc->base + reg); |
197 | } |
198 | |
199 | static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg) |
200 | { |
201 | return readl(udc->base + reg); |
202 | } |
203 | |
204 | static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val) |
205 | { |
206 | writeb(val, udc->base + reg); |
207 | } |
208 | |
209 | static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val) |
210 | { |
211 | writew(val, udc->base + reg); |
212 | } |
213 | |
214 | static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val) |
215 | { |
216 | writel(val, udc->base + reg); |
217 | } |
218 | |
219 | static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
220 | { |
221 | usb_writeb(udc, reg, usb_readb(udc, reg) | mask); |
222 | } |
223 | |
224 | static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
225 | { |
226 | usb_writew(udc, reg, usb_readw(udc, reg) | mask); |
227 | } |
228 | |
229 | static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask) |
230 | { |
231 | usb_writel(udc, reg, usb_readl(udc, reg) | mask); |
232 | } |
233 | |
234 | static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask) |
235 | { |
236 | usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask); |
237 | } |
238 | |
239 | static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask) |
240 | { |
241 | usb_writew(udc, reg, usb_readw(udc, reg) & ~mask); |
242 | } |
243 | |
244 | static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask) |
245 | { |
246 | usb_writel(udc, reg, usb_readl(udc, reg) & ~mask); |
247 | } |
248 | |
249 | /*-------------------------------------------------------------------------*/ |
250 | |
251 | static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index) |
252 | { |
253 | usb_writeb(udc, JZ_REG_UDC_INDEX, index); |
254 | } |
255 | |
256 | static inline void jz_udc_select_ep(struct jz4740_ep *ep) |
257 | { |
258 | jz_udc_set_index(ep->dev, ep_index(ep)); |
259 | } |
260 | |
261 | static inline int write_packet(struct jz4740_ep *ep, |
262 | struct jz4740_request *req, int max) |
263 | { |
264 | uint8_t *buf; |
265 | int length, nlong, nbyte; |
266 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
267 | |
268 | buf = req->req.buf + req->req.actual; |
269 | prefetch(buf); |
270 | |
271 | length = req->req.length - req->req.actual; |
272 | length = min(length, max); |
273 | req->req.actual += length; |
274 | |
275 | DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo); |
276 | |
277 | nlong = length >> 2; |
278 | nbyte = length & 0x3; |
279 | while (nlong--) { |
280 | usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf)); |
281 | buf += 4; |
282 | } |
283 | while (nbyte--) { |
284 | usb_writeb(ep->dev, ep->fifo, *buf++); |
285 | } |
286 | |
287 | return length; |
288 | } |
289 | |
290 | static inline int read_packet(struct jz4740_ep *ep, |
291 | struct jz4740_request *req, int count) |
292 | { |
293 | uint8_t *buf; |
294 | int length, nlong, nbyte; |
295 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
296 | |
297 | buf = req->req.buf + req->req.actual; |
298 | prefetchw(buf); |
299 | |
300 | length = req->req.length - req->req.actual; |
301 | length = min(length, count); |
302 | req->req.actual += length; |
303 | |
304 | DEBUG("Read %d, fifo %x\n", length, ep->fifo); |
305 | |
306 | nlong = length >> 2; |
307 | nbyte = length & 0x3; |
308 | while (nlong--) { |
309 | *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo); |
310 | buf += 4; |
311 | } |
312 | while (nbyte--) { |
313 | *buf++ = usb_readb(ep->dev, ep->fifo); |
314 | } |
315 | |
316 | return length; |
317 | } |
318 | |
319 | /*-------------------------------------------------------------------------*/ |
320 | |
321 | /* |
322 | * udc_disable - disable USB device controller |
323 | */ |
324 | static void udc_disable(struct jz4740_udc *dev) |
325 | { |
326 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
327 | |
328 | udc_set_address(dev, 0); |
329 | |
330 | /* Disable interrupts */ |
331 | usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
332 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
333 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0); |
334 | |
335 | /* Disable DMA */ |
336 | usb_writel(dev, JZ_REG_UDC_CNTL1, 0); |
337 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
338 | |
339 | /* Disconnect from usb */ |
340 | usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
341 | |
342 | /* Disable the USB PHY */ |
343 | clk_disable(dev->clk); |
344 | |
345 | dev->ep0state = WAIT_FOR_SETUP; |
346 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
347 | |
348 | return; |
349 | } |
350 | |
351 | /* |
352 | * udc_reinit - initialize software state |
353 | */ |
354 | static void udc_reinit(struct jz4740_udc *dev) |
355 | { |
356 | int i; |
357 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
358 | |
359 | /* device/ep0 records init */ |
360 | INIT_LIST_HEAD(&dev->gadget.ep_list); |
361 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); |
362 | dev->ep0state = WAIT_FOR_SETUP; |
363 | |
364 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
365 | struct jz4740_ep *ep = &dev->ep[i]; |
366 | |
367 | if (i != 0) |
368 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); |
369 | |
370 | INIT_LIST_HEAD(&ep->queue); |
371 | ep->desc = 0; |
372 | ep->stopped = 0; |
373 | ep->pio_irqs = 0; |
374 | } |
375 | } |
376 | |
377 | /* until it's enabled, this UDC should be completely invisible |
378 | * to any USB host. |
379 | */ |
380 | static void udc_enable(struct jz4740_udc *dev) |
381 | { |
382 | int i; |
383 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
384 | |
385 | /* UDC state is incorrect - Added by River */ |
386 | if (dev->state != UDC_STATE_ENABLE) { |
387 | return; |
388 | } |
389 | |
390 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
391 | |
392 | /* Flush FIFO for each */ |
393 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
394 | struct jz4740_ep *ep = &dev->ep[i]; |
395 | |
396 | jz_udc_set_index(dev, ep_index(ep)); |
397 | flush(ep); |
398 | } |
399 | |
400 | /* Set this bit to allow the UDC entering low-power mode when |
401 | * there are no actions on the USB bus. |
402 | * UDC still works during this bit was set. |
403 | */ |
404 | jz4740_clock_udc_enable_auto_suspend(); |
405 | |
406 | /* Enable the USB PHY */ |
407 | clk_enable(dev->clk); |
408 | |
409 | /* Disable interrupts */ |
410 | /* usb_writew(dev, JZ_REG_UDC_INTRINE, 0); |
411 | usb_writew(dev, JZ_REG_UDC_INTROUTE, 0); |
412 | usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/ |
413 | |
414 | /* Enable interrupts */ |
415 | usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0); |
416 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET); |
417 | /* Don't enable rest of the interrupts */ |
418 | /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2); |
419 | usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */ |
420 | |
421 | /* Enable SUSPEND */ |
422 | /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */ |
423 | |
424 | /* Enable HS Mode */ |
425 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB); |
426 | |
427 | /* Let host detect UDC: |
428 | * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this |
429 | * transistor on and pull the USBDP pin HIGH. |
430 | */ |
431 | usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN); |
432 | |
433 | return; |
434 | } |
435 | |
436 | /*-------------------------------------------------------------------------*/ |
437 | |
438 | /* keeping it simple: |
439 | * - one bus driver, initted first; |
440 | * - one function driver, initted second |
441 | */ |
442 | |
443 | /* |
444 | * Register entry point for the peripheral controller driver. |
445 | */ |
446 | |
447 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) |
448 | { |
449 | struct jz4740_udc *dev = the_controller; |
450 | int retval; |
451 | |
452 | if (!driver || !driver->bind) { |
453 | return -EINVAL; |
454 | } |
455 | |
456 | if (!dev) { |
457 | return -ENODEV; |
458 | } |
459 | |
460 | if (dev->driver) { |
461 | return -EBUSY; |
462 | } |
463 | |
464 | /* hook up the driver */ |
465 | dev->driver = driver; |
466 | dev->gadget.dev.driver = &driver->driver; |
467 | |
468 | retval = driver->bind(&dev->gadget); |
469 | if (retval) { |
470 | DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name, |
471 | driver->driver.name, retval); |
472 | dev->driver = 0; |
473 | return retval; |
474 | } |
475 | |
476 | /* then enable host detection and ep0; and we're ready |
477 | * for set_configuration as well as eventual disconnect. |
478 | */ |
479 | udc_enable(dev); |
480 | |
481 | DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name, |
482 | driver->driver.name); |
483 | |
484 | return 0; |
485 | } |
486 | |
487 | EXPORT_SYMBOL(usb_gadget_register_driver); |
488 | |
489 | static void stop_activity(struct jz4740_udc *dev, |
490 | struct usb_gadget_driver *driver) |
491 | { |
492 | int i; |
493 | |
494 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
495 | |
496 | /* don't disconnect drivers more than once */ |
497 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) |
498 | driver = 0; |
499 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
500 | |
501 | /* prevent new request submissions, kill any outstanding requests */ |
502 | for (i = 0; i < UDC_MAX_ENDPOINTS; i++) { |
503 | struct jz4740_ep *ep = &dev->ep[i]; |
504 | |
505 | ep->stopped = 1; |
506 | |
507 | jz_udc_set_index(dev, ep_index(ep)); |
508 | nuke(ep, -ESHUTDOWN); |
509 | } |
510 | |
511 | /* report disconnect; the driver is already quiesced */ |
512 | if (driver) { |
513 | spin_unlock(&dev->lock); |
514 | driver->disconnect(&dev->gadget); |
515 | spin_lock(&dev->lock); |
516 | } |
517 | |
518 | /* re-init driver-visible data structures */ |
519 | udc_reinit(dev); |
520 | } |
521 | |
522 | |
523 | /* |
524 | * Unregister entry point for the peripheral controller driver. |
525 | */ |
526 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
527 | { |
528 | struct jz4740_udc *dev = the_controller; |
529 | unsigned long flags; |
530 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
531 | |
532 | if (!dev) |
533 | return -ENODEV; |
534 | if (!driver || driver != dev->driver) |
535 | return -EINVAL; |
536 | if (!driver->unbind) |
537 | return -EBUSY; |
538 | |
539 | spin_lock_irqsave(&dev->lock, flags); |
540 | dev->driver = 0; |
541 | stop_activity(dev, driver); |
542 | spin_unlock_irqrestore(&dev->lock, flags); |
543 | |
544 | driver->unbind(&dev->gadget); |
545 | |
546 | udc_disable(dev); |
547 | |
548 | DEBUG("unregistered driver '%s'\n", driver->driver.name); |
549 | |
550 | return 0; |
551 | } |
552 | |
553 | EXPORT_SYMBOL(usb_gadget_unregister_driver); |
554 | |
555 | /*-------------------------------------------------------------------------*/ |
556 | |
557 | /* |
558 | * Starting DMA using mode 1 |
559 | */ |
560 | static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req) |
561 | { |
562 | struct jz4740_udc *dev = ep->dev; |
563 | uint32_t count = req->req.length; |
564 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
565 | |
566 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
567 | |
568 | jz_udc_select_ep(ep); |
569 | |
570 | if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */ |
571 | ep->reg_addr = JZ_REG_UDC_ADDR1; |
572 | |
573 | dma_cache_wback_inv((unsigned long)req->req.buf, count); |
574 | |
575 | pio_irq_enable(ep); |
576 | |
577 | usb_writeb(dev, JZ_REG_UDC_INCSRH, |
578 | USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE); |
579 | |
580 | usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr); |
581 | usb_writel(dev, JZ_REG_UDC_COUNT1, count); |
582 | usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 | |
583 | USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep))); |
584 | } |
585 | else { /* Bulk-OUT transfer using DMA channel 2 */ |
586 | ep->reg_addr = JZ_REG_UDC_ADDR2; |
587 | |
588 | dma_cache_wback_inv((unsigned long)req->req.buf, count); |
589 | |
590 | pio_irq_enable(ep); |
591 | |
592 | usb_setb(dev, JZ_REG_UDC_OUTCSRH, |
593 | USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE); |
594 | |
595 | usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr); |
596 | usb_writel(dev, JZ_REG_UDC_COUNT2, count); |
597 | usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 | |
598 | USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep))); |
599 | } |
600 | } |
601 | |
602 | /*-------------------------------------------------------------------------*/ |
603 | |
604 | /** Write request to FIFO (max write == maxp size) |
605 | * Return: 0 = still running, 1 = completed, negative = errno |
606 | * NOTE: INDEX register must be set for EP |
607 | */ |
608 | static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
609 | { |
610 | struct jz4740_udc *dev = ep->dev; |
611 | uint32_t max, csr; |
612 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
613 | |
614 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
615 | max = le16_to_cpu(ep->desc->wMaxPacketSize); |
616 | |
617 | if (use_dma) { |
618 | uint32_t dma_count; |
619 | |
620 | /* DMA interrupt generated due to the last packet loaded into the FIFO */ |
621 | |
622 | dma_count = usb_readl(dev, ep->reg_addr) - physaddr; |
623 | req->req.actual += dma_count; |
624 | |
625 | if (dma_count % max) { |
626 | /* If the last packet is less than MAXP, set INPKTRDY manually */ |
627 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
628 | } |
629 | |
630 | done(ep, req, 0); |
631 | if (list_empty(&ep->queue)) { |
632 | pio_irq_disable(ep); |
633 | return 1; |
634 | } |
635 | else { |
636 | /* advance the request queue */ |
637 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
638 | kick_dma(ep, req); |
639 | return 0; |
640 | } |
641 | } |
642 | |
643 | /* |
644 | * PIO mode handling starts here ... |
645 | */ |
646 | |
647 | csr = usb_readb(dev, ep->csr); |
648 | |
649 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
650 | unsigned count; |
651 | int is_last, is_short; |
652 | |
653 | count = write_packet(ep, req, max); |
654 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
655 | |
656 | /* last packet is usually short (or a zlp) */ |
657 | if (unlikely(count != max)) |
658 | is_last = is_short = 1; |
659 | else { |
660 | if (likely(req->req.length != req->req.actual) |
661 | || req->req.zero) |
662 | is_last = 0; |
663 | else |
664 | is_last = 1; |
665 | /* interrupt/iso maxpacket may not fill the fifo */ |
666 | is_short = unlikely(max < ep_maxpacket(ep)); |
667 | } |
668 | |
669 | DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__, |
670 | ep->ep.name, count, |
671 | is_last ? "/L" : "", is_short ? "/S" : "", |
672 | req->req.length - req->req.actual, req); |
673 | |
674 | /* requests complete when all IN data is in the FIFO */ |
675 | if (is_last) { |
676 | done(ep, req, 0); |
677 | if (list_empty(&ep->queue)) { |
678 | pio_irq_disable(ep); |
679 | } |
680 | return 1; |
681 | } |
682 | } else { |
683 | DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep)); |
684 | } |
685 | |
686 | return 0; |
687 | } |
688 | |
689 | /** Read to request from FIFO (max read == bytes in fifo) |
690 | * Return: 0 = still running, 1 = completed, negative = errno |
691 | * NOTE: INDEX register must be set for EP |
692 | */ |
693 | static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req) |
694 | { |
695 | struct jz4740_udc *dev = ep->dev; |
696 | uint32_t csr; |
697 | unsigned count, is_short; |
698 | uint32_t physaddr = virt_to_phys((void *)req->req.buf); |
699 | |
700 | if (use_dma) { |
701 | uint32_t dma_count; |
702 | |
703 | /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */ |
704 | |
705 | dma_count = usb_readl(dev, ep->reg_addr) - physaddr; |
706 | req->req.actual += dma_count; |
707 | |
708 | /* Disable interrupt and DMA */ |
709 | pio_irq_disable(ep); |
710 | usb_writel(dev, JZ_REG_UDC_CNTL2, 0); |
711 | |
712 | /* Read all bytes from this packet */ |
713 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
714 | count = read_packet(ep, req, count); |
715 | |
716 | if (count) { |
717 | /* If the last packet is greater than zero, clear OUTPKTRDY manually */ |
718 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
719 | } |
720 | done(ep, req, 0); |
721 | |
722 | if (!list_empty(&ep->queue)) { |
723 | /* advance the request queue */ |
724 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
725 | kick_dma(ep, req); |
726 | } |
727 | |
728 | return 1; |
729 | } |
730 | |
731 | /* |
732 | * PIO mode handling starts here ... |
733 | */ |
734 | |
735 | /* make sure there's a packet in the FIFO. */ |
736 | csr = usb_readb(dev, ep->csr); |
737 | if (!(csr & USB_OUTCSR_OUTPKTRDY)) { |
738 | DEBUG("%s: Packet NOT ready!\n", __FUNCTION__); |
739 | return -EINVAL; |
740 | } |
741 | |
742 | /* read all bytes from this packet */ |
743 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
744 | |
745 | is_short = (count < ep->ep.maxpacket); |
746 | |
747 | count = read_packet(ep, req, count); |
748 | |
749 | DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n", |
750 | ep->ep.name, csr, count, |
751 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
752 | |
753 | /* Clear OutPktRdy */ |
754 | usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY); |
755 | |
756 | /* completion */ |
757 | if (is_short || req->req.actual == req->req.length) { |
758 | done(ep, req, 0); |
759 | |
760 | if (list_empty(&ep->queue)) |
761 | pio_irq_disable(ep); |
762 | return 1; |
763 | } |
764 | |
765 | /* finished that packet. the next one may be waiting... */ |
766 | return 0; |
767 | } |
768 | |
769 | /* |
770 | * done - retire a request; caller blocked irqs |
771 | * INDEX register is preserved to keep same |
772 | */ |
773 | static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status) |
774 | { |
775 | unsigned int stopped = ep->stopped; |
776 | unsigned long flags; |
777 | uint32_t index; |
778 | |
779 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
780 | list_del_init(&req->queue); |
781 | |
782 | if (likely(req->req.status == -EINPROGRESS)) |
783 | req->req.status = status; |
784 | else |
785 | status = req->req.status; |
786 | |
787 | if (status && status != -ESHUTDOWN) |
788 | DEBUG("complete %s req %p stat %d len %u/%u\n", |
789 | ep->ep.name, &req->req, status, |
790 | req->req.actual, req->req.length); |
791 | |
792 | /* don't modify queue heads during completion callback */ |
793 | ep->stopped = 1; |
794 | /* Read current index (completion may modify it) */ |
795 | spin_lock_irqsave(&ep->dev->lock, flags); |
796 | index = usb_readb(ep->dev, JZ_REG_UDC_INDEX); |
797 | |
798 | req->req.complete(&ep->ep, &req->req); |
799 | |
800 | /* Restore index */ |
801 | jz_udc_set_index(ep->dev, index); |
802 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
803 | ep->stopped = stopped; |
804 | } |
805 | |
806 | /** Enable EP interrupt */ |
807 | static void pio_irq_enable(struct jz4740_ep *ep) |
808 | { |
809 | uint8_t index = ep_index(ep); |
810 | struct jz4740_udc *dev = ep->dev; |
811 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
812 | |
813 | if (ep_is_in(ep)) { |
814 | switch (index) { |
815 | case 1: |
816 | case 2: |
817 | usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index)); |
818 | dev->in_mask |= BIT(index); |
819 | break; |
820 | default: |
821 | DEBUG("Unknown endpoint: %d\n", index); |
822 | break; |
823 | } |
824 | } |
825 | else { |
826 | switch (index) { |
827 | case 1: |
828 | usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index)); |
829 | dev->out_mask |= BIT(index); |
830 | break; |
831 | default: |
832 | DEBUG("Unknown endpoint: %d\n", index); |
833 | break; |
834 | } |
835 | } |
836 | } |
837 | |
838 | /** Disable EP interrupt */ |
839 | static void pio_irq_disable(struct jz4740_ep *ep) |
840 | { |
841 | uint8_t index = ep_index(ep); |
842 | struct jz4740_udc *dev = ep->dev; |
843 | |
844 | DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT"); |
845 | |
846 | if (ep_is_in(ep)) { |
847 | switch (ep_index(ep)) { |
848 | case 1: |
849 | case 2: |
850 | usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index)); |
851 | dev->in_mask &= ~BIT(index); |
852 | break; |
853 | default: |
854 | DEBUG("Unknown endpoint: %d\n", index); |
855 | break; |
856 | } |
857 | } |
858 | else { |
859 | switch (ep_index(ep)) { |
860 | case 1: |
861 | usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index)); |
862 | dev->out_mask &= ~BIT(index); |
863 | break; |
864 | default: |
865 | DEBUG("Unknown endpoint: %d\n", index); |
866 | break; |
867 | } |
868 | } |
869 | } |
870 | |
871 | /* |
872 | * nuke - dequeue ALL requests |
873 | */ |
874 | static void nuke(struct jz4740_ep *ep, int status) |
875 | { |
876 | struct jz4740_request *req; |
877 | |
878 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
879 | |
880 | /* Flush FIFO */ |
881 | flush(ep); |
882 | |
883 | /* called with irqs blocked */ |
884 | while (!list_empty(&ep->queue)) { |
885 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
886 | done(ep, req, status); |
887 | } |
888 | |
889 | /* Disable IRQ if EP is enabled (has descriptor) */ |
890 | if (ep->desc) |
891 | pio_irq_disable(ep); |
892 | } |
893 | |
894 | /** Flush EP FIFO |
895 | * NOTE: INDEX register must be set before this call |
896 | */ |
897 | static void flush(struct jz4740_ep *ep) |
898 | { |
899 | DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name); |
900 | |
901 | switch (ep->type) { |
902 | case ep_bulk_in: |
903 | case ep_interrupt: |
904 | usb_setb(ep->dev, ep->csr, USB_INCSR_FF); |
905 | break; |
906 | case ep_bulk_out: |
907 | usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF); |
908 | break; |
909 | case ep_control: |
910 | break; |
911 | } |
912 | } |
913 | |
914 | /** |
915 | * jz4740_in_epn - handle IN interrupt |
916 | */ |
917 | static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
918 | { |
919 | uint32_t csr; |
920 | struct jz4740_ep *ep = &dev->ep[ep_idx + 1]; |
921 | struct jz4740_request *req; |
922 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
923 | |
924 | jz_udc_set_index(dev, ep_index(ep)); |
925 | |
926 | csr = usb_readb(dev, ep->csr); |
927 | DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr); |
928 | |
929 | if (csr & USB_INCSR_SENTSTALL) { |
930 | DEBUG("USB_INCSR_SENTSTALL\n"); |
931 | usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL); |
932 | return; |
933 | } |
934 | |
935 | if (!ep->desc) { |
936 | DEBUG("%s: NO EP DESC\n", __FUNCTION__); |
937 | return; |
938 | } |
939 | |
940 | if (list_empty(&ep->queue)) |
941 | req = 0; |
942 | else |
943 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
944 | |
945 | DEBUG("req: %p\n", req); |
946 | |
947 | if (!req) |
948 | return; |
949 | |
950 | write_fifo(ep, req); |
951 | } |
952 | |
953 | /* |
954 | * Bulk OUT (recv) |
955 | */ |
956 | static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr) |
957 | { |
958 | struct jz4740_ep *ep = &dev->ep[ep_idx]; |
959 | struct jz4740_request *req; |
960 | |
961 | DEBUG("%s: %d\n", __FUNCTION__, ep_idx); |
962 | |
963 | jz_udc_set_index(dev, ep_index(ep)); |
964 | if (ep->desc) { |
965 | uint32_t csr; |
966 | |
967 | if (use_dma) { |
968 | /* DMA starts here ... */ |
969 | if (list_empty(&ep->queue)) |
970 | req = 0; |
971 | else |
972 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
973 | |
974 | if (req) |
975 | read_fifo(ep, req); |
976 | return; |
977 | } |
978 | |
979 | /* |
980 | * PIO mode starts here ... |
981 | */ |
982 | |
983 | while ((csr = usb_readb(dev, ep->csr)) & |
984 | (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) { |
985 | DEBUG("%s: %x\n", __FUNCTION__, csr); |
986 | |
987 | if (csr & USB_OUTCSR_SENTSTALL) { |
988 | DEBUG("%s: stall sent, flush fifo\n", |
989 | __FUNCTION__); |
990 | /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */ |
991 | flush(ep); |
992 | } else if (csr & USB_OUTCSR_OUTPKTRDY) { |
993 | if (list_empty(&ep->queue)) |
994 | req = 0; |
995 | else |
996 | req = |
997 | list_entry(ep->queue.next, |
998 | struct jz4740_request, |
999 | queue); |
1000 | |
1001 | if (!req) { |
1002 | DEBUG("%s: NULL REQ %d\n", |
1003 | __FUNCTION__, ep_idx); |
1004 | break; |
1005 | } else { |
1006 | read_fifo(ep, req); |
1007 | } |
1008 | } |
1009 | } |
1010 | } else { |
1011 | /* Throw packet away.. */ |
1012 | DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx); |
1013 | flush(ep); |
1014 | } |
1015 | } |
1016 | |
1017 | /** Halt specific EP |
1018 | * Return 0 if success |
1019 | * NOTE: Sets INDEX register to EP ! |
1020 | */ |
1021 | static int jz4740_set_halt(struct usb_ep *_ep, int value) |
1022 | { |
1023 | struct jz4740_udc *dev; |
1024 | struct jz4740_ep *ep; |
1025 | unsigned long flags; |
1026 | |
1027 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1028 | |
1029 | ep = container_of(_ep, struct jz4740_ep, ep); |
1030 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
1031 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1032 | return -EINVAL; |
1033 | } |
1034 | |
1035 | dev = ep->dev; |
1036 | |
1037 | spin_lock_irqsave(&dev->lock, flags); |
1038 | |
1039 | jz_udc_select_ep(ep); |
1040 | |
1041 | DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value); |
1042 | |
1043 | if (ep_index(ep) == 0) { |
1044 | /* EP0 */ |
1045 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL); |
1046 | } else if (ep_is_in(ep)) { |
1047 | uint32_t csr = usb_readb(dev, ep->csr); |
1048 | if (value && ((csr & USB_INCSR_FFNOTEMPT) |
1049 | || !list_empty(&ep->queue))) { |
1050 | /* |
1051 | * Attempts to halt IN endpoints will fail (returning -EAGAIN) |
1052 | * if any transfer requests are still queued, or if the controller |
1053 | * FIFO still holds bytes that the host hasnÂ’t collected. |
1054 | */ |
1055 | spin_unlock_irqrestore(&dev->lock, flags); |
1056 | DEBUG |
1057 | ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n", |
1058 | (csr & USB_INCSR_FFNOTEMPT), |
1059 | !list_empty(&ep->queue)); |
1060 | return -EAGAIN; |
1061 | } |
1062 | flush(ep); |
1063 | if (value) { |
1064 | usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL); |
1065 | } |
1066 | else { |
1067 | usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL); |
1068 | usb_setb(dev, ep->csr, USB_INCSR_CDT); |
1069 | } |
1070 | } else { |
1071 | |
1072 | flush(ep); |
1073 | if (value) { |
1074 | usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
1075 | } |
1076 | else { |
1077 | usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL); |
1078 | usb_setb(dev, ep->csr, USB_OUTCSR_CDT); |
1079 | } |
1080 | } |
1081 | |
1082 | if (value) { |
1083 | ep->stopped = 1; |
1084 | } else { |
1085 | ep->stopped = 0; |
1086 | } |
1087 | |
1088 | spin_unlock_irqrestore(&dev->lock, flags); |
1089 | |
1090 | DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS"); |
1091 | |
1092 | return 0; |
1093 | } |
1094 | |
1095 | |
1096 | static int jz4740_ep_enable(struct usb_ep *_ep, |
1097 | const struct usb_endpoint_descriptor *desc) |
1098 | { |
1099 | struct jz4740_ep *ep; |
1100 | struct jz4740_udc *dev; |
1101 | unsigned long flags; |
1102 | uint32_t max, csrh = 0; |
1103 | |
1104 | DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name); |
1105 | |
1106 | if (!_ep || !desc) |
1107 | return -EINVAL; |
1108 | |
1109 | ep = container_of(_ep, struct jz4740_ep, ep); |
1110 | if (ep->desc || ep->type == ep_control |
1111 | || desc->bDescriptorType != USB_DT_ENDPOINT |
1112 | || ep->bEndpointAddress != desc->bEndpointAddress) { |
1113 | DEBUG("%s, bad ep or descriptor\n", __FUNCTION__); |
1114 | return -EINVAL; |
1115 | } |
1116 | |
1117 | /* xfer types must match, except that interrupt ~= bulk */ |
1118 | if (ep->bmAttributes != desc->bmAttributes |
1119 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK |
1120 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { |
1121 | DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); |
1122 | return -EINVAL; |
1123 | } |
1124 | |
1125 | dev = ep->dev; |
1126 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { |
1127 | DEBUG("%s, bogus device state\n", __FUNCTION__); |
1128 | return -ESHUTDOWN; |
1129 | } |
1130 | |
1131 | max = le16_to_cpu(desc->wMaxPacketSize); |
1132 | |
1133 | spin_lock_irqsave(&ep->dev->lock, flags); |
1134 | |
1135 | /* Configure the endpoint */ |
1136 | jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F); |
1137 | if (ep_is_in(ep)) { |
1138 | usb_writew(dev, JZ_REG_UDC_INMAXP, max); |
1139 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
1140 | case USB_ENDPOINT_XFER_BULK: |
1141 | case USB_ENDPOINT_XFER_INT: |
1142 | csrh &= ~USB_INCSRH_ISO; |
1143 | break; |
1144 | case USB_ENDPOINT_XFER_ISOC: |
1145 | csrh |= USB_INCSRH_ISO; |
1146 | break; |
1147 | } |
1148 | usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh); |
1149 | } |
1150 | else { |
1151 | usb_writew(dev, JZ_REG_UDC_OUTMAXP, max); |
1152 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
1153 | case USB_ENDPOINT_XFER_BULK: |
1154 | csrh &= ~USB_OUTCSRH_ISO; |
1155 | break; |
1156 | case USB_ENDPOINT_XFER_INT: |
1157 | csrh &= ~USB_OUTCSRH_ISO; |
1158 | csrh |= USB_OUTCSRH_DNYT; |
1159 | break; |
1160 | case USB_ENDPOINT_XFER_ISOC: |
1161 | csrh |= USB_OUTCSRH_ISO; |
1162 | break; |
1163 | } |
1164 | usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh); |
1165 | } |
1166 | |
1167 | |
1168 | ep->stopped = 0; |
1169 | ep->desc = desc; |
1170 | ep->pio_irqs = 0; |
1171 | ep->ep.maxpacket = max; |
1172 | |
1173 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1174 | |
1175 | /* Reset halt state (does flush) */ |
1176 | jz4740_set_halt(_ep, 0); |
1177 | |
1178 | DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name); |
1179 | |
1180 | return 0; |
1181 | } |
1182 | |
1183 | /** Disable EP |
1184 | * NOTE: Sets INDEX register |
1185 | */ |
1186 | static int jz4740_ep_disable(struct usb_ep *_ep) |
1187 | { |
1188 | struct jz4740_ep *ep; |
1189 | unsigned long flags; |
1190 | |
1191 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1192 | |
1193 | ep = container_of(_ep, struct jz4740_ep, ep); |
1194 | if (!_ep || !ep->desc) { |
1195 | DEBUG("%s, %s not enabled\n", __FUNCTION__, |
1196 | _ep ? ep->ep.name : NULL); |
1197 | return -EINVAL; |
1198 | } |
1199 | |
1200 | spin_lock_irqsave(&ep->dev->lock, flags); |
1201 | |
1202 | jz_udc_select_ep(ep); |
1203 | |
1204 | /* Nuke all pending requests (does flush) */ |
1205 | nuke(ep, -ESHUTDOWN); |
1206 | |
1207 | /* Disable ep IRQ */ |
1208 | pio_irq_disable(ep); |
1209 | |
1210 | ep->desc = 0; |
1211 | ep->stopped = 1; |
1212 | |
1213 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1214 | |
1215 | DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name); |
1216 | return 0; |
1217 | } |
1218 | |
1219 | static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
1220 | { |
1221 | struct jz4740_request *req; |
1222 | |
1223 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
1224 | |
1225 | req = kzalloc(sizeof(*req), gfp_flags); |
1226 | if (!req) |
1227 | return 0; |
1228 | |
1229 | INIT_LIST_HEAD(&req->queue); |
1230 | |
1231 | return &req->req; |
1232 | } |
1233 | |
1234 | static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req) |
1235 | { |
1236 | struct jz4740_request *req; |
1237 | |
1238 | DEBUG("%s, %p\n", __FUNCTION__, ep); |
1239 | |
1240 | req = container_of(_req, struct jz4740_request, req); |
1241 | WARN_ON(!list_empty(&req->queue)); |
1242 | kfree(req); |
1243 | } |
1244 | |
1245 | /*--------------------------------------------------------------------*/ |
1246 | |
1247 | /** Queue one request |
1248 | * Kickstart transfer if needed |
1249 | * NOTE: Sets INDEX register |
1250 | */ |
1251 | static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req, |
1252 | gfp_t gfp_flags) |
1253 | { |
1254 | struct jz4740_request *req; |
1255 | struct jz4740_ep *ep; |
1256 | struct jz4740_udc *dev; |
1257 | unsigned long flags; |
1258 | |
1259 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1260 | |
1261 | req = container_of(_req, struct jz4740_request, req); |
1262 | if (unlikely |
1263 | (!_req || !_req->complete || !_req->buf |
1264 | || !list_empty(&req->queue))) { |
1265 | DEBUG("%s, bad params\n", __FUNCTION__); |
1266 | return -EINVAL; |
1267 | } |
1268 | |
1269 | ep = container_of(_ep, struct jz4740_ep, ep); |
1270 | if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) { |
1271 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1272 | return -EINVAL; |
1273 | } |
1274 | |
1275 | dev = ep->dev; |
1276 | if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { |
1277 | DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver); |
1278 | return -ESHUTDOWN; |
1279 | } |
1280 | |
1281 | DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length, |
1282 | _req->buf); |
1283 | |
1284 | spin_lock_irqsave(&dev->lock, flags); |
1285 | |
1286 | _req->status = -EINPROGRESS; |
1287 | _req->actual = 0; |
1288 | |
1289 | /* kickstart this i/o queue? */ |
1290 | DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue), |
1291 | ep->stopped); |
1292 | if (list_empty(&ep->queue) && likely(!ep->stopped)) { |
1293 | uint32_t csr; |
1294 | |
1295 | if (unlikely(ep_index(ep) == 0)) { |
1296 | /* EP0 */ |
1297 | list_add_tail(&req->queue, &ep->queue); |
1298 | jz4740_ep0_kick(dev, ep); |
1299 | req = 0; |
1300 | } else if (use_dma) { |
1301 | /* DMA */ |
1302 | kick_dma(ep, req); |
1303 | } |
1304 | /* PIO */ |
1305 | else if (ep_is_in(ep)) { |
1306 | /* EP1 & EP2 */ |
1307 | jz_udc_set_index(dev, ep_index(ep)); |
1308 | csr = usb_readb(dev, ep->csr); |
1309 | pio_irq_enable(ep); |
1310 | if (!(csr & USB_INCSR_FFNOTEMPT)) { |
1311 | if (write_fifo(ep, req) == 1) |
1312 | req = 0; |
1313 | } |
1314 | } else { |
1315 | /* EP1 */ |
1316 | jz_udc_set_index(dev, ep_index(ep)); |
1317 | csr = usb_readb(dev, ep->csr); |
1318 | pio_irq_enable(ep); |
1319 | if (csr & USB_OUTCSR_OUTPKTRDY) { |
1320 | if (read_fifo(ep, req) == 1) |
1321 | req = 0; |
1322 | } |
1323 | } |
1324 | } |
1325 | |
1326 | /* pio or dma irq handler advances the queue. */ |
1327 | if (likely(req != 0)) |
1328 | list_add_tail(&req->queue, &ep->queue); |
1329 | |
1330 | spin_unlock_irqrestore(&dev->lock, flags); |
1331 | |
1332 | return 0; |
1333 | } |
1334 | |
1335 | /* dequeue JUST ONE request */ |
1336 | static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
1337 | { |
1338 | struct jz4740_ep *ep; |
1339 | struct jz4740_request *req; |
1340 | unsigned long flags; |
1341 | |
1342 | DEBUG("%s, %p\n", __FUNCTION__, _ep); |
1343 | |
1344 | ep = container_of(_ep, struct jz4740_ep, ep); |
1345 | if (!_ep || ep->type == ep_control) |
1346 | return -EINVAL; |
1347 | |
1348 | spin_lock_irqsave(&ep->dev->lock, flags); |
1349 | |
1350 | /* make sure it's actually queued on this endpoint */ |
1351 | list_for_each_entry(req, &ep->queue, queue) { |
1352 | if (&req->req == _req) |
1353 | break; |
1354 | } |
1355 | if (&req->req != _req) { |
1356 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1357 | return -EINVAL; |
1358 | } |
1359 | done(ep, req, -ECONNRESET); |
1360 | |
1361 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1362 | return 0; |
1363 | } |
1364 | |
1365 | /** Return bytes in EP FIFO |
1366 | * NOTE: Sets INDEX register to EP |
1367 | */ |
1368 | static int jz4740_fifo_status(struct usb_ep *_ep) |
1369 | { |
1370 | uint32_t csr; |
1371 | int count = 0; |
1372 | struct jz4740_ep *ep; |
1373 | unsigned long flags; |
1374 | |
1375 | ep = container_of(_ep, struct jz4740_ep, ep); |
1376 | if (!_ep) { |
1377 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1378 | return -ENODEV; |
1379 | } |
1380 | |
1381 | DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep)); |
1382 | |
1383 | /* LPD can't report unclaimed bytes from IN fifos */ |
1384 | if (ep_is_in(ep)) |
1385 | return -EOPNOTSUPP; |
1386 | |
1387 | spin_lock_irqsave(&ep->dev->lock, flags); |
1388 | jz_udc_set_index(ep->dev, ep_index(ep)); |
1389 | |
1390 | csr = usb_readb(ep->dev, ep->csr); |
1391 | if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN || |
1392 | csr & 0x1) { |
1393 | count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1394 | } |
1395 | |
1396 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1397 | |
1398 | return count; |
1399 | } |
1400 | |
1401 | /** Flush EP FIFO |
1402 | * NOTE: Sets INDEX register to EP |
1403 | */ |
1404 | static void jz4740_fifo_flush(struct usb_ep *_ep) |
1405 | { |
1406 | struct jz4740_ep *ep; |
1407 | unsigned long flags; |
1408 | |
1409 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1410 | |
1411 | ep = container_of(_ep, struct jz4740_ep, ep); |
1412 | if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) { |
1413 | DEBUG("%s, bad ep\n", __FUNCTION__); |
1414 | return; |
1415 | } |
1416 | |
1417 | spin_lock_irqsave(&ep->dev->lock, flags); |
1418 | |
1419 | jz_udc_set_index(ep->dev, ep_index(ep)); |
1420 | flush(ep); |
1421 | |
1422 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
1423 | } |
1424 | |
1425 | /****************************************************************/ |
1426 | /* End Point 0 related functions */ |
1427 | /****************************************************************/ |
1428 | |
1429 | /* return: 0 = still running, 1 = completed, negative = errno */ |
1430 | static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1431 | { |
1432 | uint32_t max; |
1433 | unsigned count; |
1434 | int is_last; |
1435 | |
1436 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1437 | max = ep_maxpacket(ep); |
1438 | |
1439 | count = write_packet(ep, req, max); |
1440 | |
1441 | /* last packet is usually short (or a zlp) */ |
1442 | if (unlikely(count != max)) |
1443 | is_last = 1; |
1444 | else { |
1445 | if (likely(req->req.length != req->req.actual) || req->req.zero) |
1446 | is_last = 0; |
1447 | else |
1448 | is_last = 1; |
1449 | } |
1450 | |
1451 | DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__, |
1452 | ep->ep.name, count, |
1453 | is_last ? "/L" : "", req->req.length - req->req.actual, req); |
1454 | |
1455 | /* requests complete when all IN data is in the FIFO */ |
1456 | if (is_last) { |
1457 | done(ep, req, 0); |
1458 | return 1; |
1459 | } |
1460 | |
1461 | return 0; |
1462 | } |
1463 | |
1464 | static inline int jz4740_fifo_read(struct jz4740_ep *ep, |
1465 | unsigned char *cp, int max) |
1466 | { |
1467 | int bytes; |
1468 | int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT); |
1469 | |
1470 | if (count > max) |
1471 | count = max; |
1472 | bytes = count; |
1473 | while (count--) |
1474 | *cp++ = usb_readb(ep->dev, ep->fifo); |
1475 | |
1476 | return bytes; |
1477 | } |
1478 | |
1479 | static inline void jz4740_fifo_write(struct jz4740_ep *ep, |
1480 | unsigned char *cp, int count) |
1481 | { |
1482 | DEBUG("fifo_write: %d %d\n", ep_index(ep), count); |
1483 | while (count--) |
1484 | usb_writeb(ep->dev, ep->fifo, *cp++); |
1485 | } |
1486 | |
1487 | static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req) |
1488 | { |
1489 | struct jz4740_udc *dev = ep->dev; |
1490 | uint32_t csr; |
1491 | uint8_t *buf; |
1492 | unsigned bufferspace, count, is_short; |
1493 | |
1494 | DEBUG_EP0("%s\n", __FUNCTION__); |
1495 | |
1496 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1497 | if (!(csr & USB_CSR0_OUTPKTRDY)) |
1498 | return 0; |
1499 | |
1500 | buf = req->req.buf + req->req.actual; |
1501 | prefetchw(buf); |
1502 | bufferspace = req->req.length - req->req.actual; |
1503 | |
1504 | /* read all bytes from this packet */ |
1505 | if (likely(csr & USB_CSR0_OUTPKTRDY)) { |
1506 | count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT); |
1507 | req->req.actual += min(count, bufferspace); |
1508 | } else /* zlp */ |
1509 | count = 0; |
1510 | |
1511 | is_short = (count < ep->ep.maxpacket); |
1512 | DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n", |
1513 | ep->ep.name, csr, count, |
1514 | is_short ? "/S" : "", req, req->req.actual, req->req.length); |
1515 | |
1516 | while (likely(count-- != 0)) { |
1517 | uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo); |
1518 | |
1519 | if (unlikely(bufferspace == 0)) { |
1520 | /* this happens when the driver's buffer |
1521 | * is smaller than what the host sent. |
1522 | * discard the extra data. |
1523 | */ |
1524 | if (req->req.status != -EOVERFLOW) |
1525 | DEBUG_EP0("%s overflow %d\n", ep->ep.name, |
1526 | count); |
1527 | req->req.status = -EOVERFLOW; |
1528 | } else { |
1529 | *buf++ = byte; |
1530 | bufferspace--; |
1531 | } |
1532 | } |
1533 | |
1534 | /* completion */ |
1535 | if (is_short || req->req.actual == req->req.length) { |
1536 | done(ep, req, 0); |
1537 | return 1; |
1538 | } |
1539 | |
1540 | /* finished that packet. the next one may be waiting... */ |
1541 | return 0; |
1542 | } |
1543 | |
1544 | /** |
1545 | * udc_set_address - set the USB address for this device |
1546 | * @address: |
1547 | * |
1548 | * Called from control endpoint function after it decodes a set address setup packet. |
1549 | */ |
1550 | static void udc_set_address(struct jz4740_udc *dev, unsigned char address) |
1551 | { |
1552 | DEBUG_EP0("%s: %d\n", __FUNCTION__, address); |
1553 | |
1554 | dev->usb_address = address; |
1555 | usb_writeb(dev, JZ_REG_UDC_FADDR, address); |
1556 | } |
1557 | |
1558 | /* |
1559 | * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY) |
1560 | * - if error |
1561 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1562 | * - else |
1563 | * set USB_CSR0_SVDOUTPKTRDY bit |
1564 | if last set USB_CSR0_DATAEND bit |
1565 | */ |
1566 | static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart) |
1567 | { |
1568 | struct jz4740_request *req; |
1569 | struct jz4740_ep *ep = &dev->ep[0]; |
1570 | int ret; |
1571 | |
1572 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1573 | |
1574 | if (list_empty(&ep->queue)) |
1575 | req = 0; |
1576 | else |
1577 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1578 | |
1579 | if (req) { |
1580 | if (req->req.length == 0) { |
1581 | DEBUG_EP0("ZERO LENGTH OUT!\n"); |
1582 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1583 | dev->ep0state = WAIT_FOR_SETUP; |
1584 | return; |
1585 | } else if (kickstart) { |
1586 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY)); |
1587 | return; |
1588 | } |
1589 | ret = read_fifo_ep0(ep, req); |
1590 | if (ret) { |
1591 | /* Done! */ |
1592 | DEBUG_EP0("%s: finished, waiting for status\n", |
1593 | __FUNCTION__); |
1594 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1595 | dev->ep0state = WAIT_FOR_SETUP; |
1596 | } else { |
1597 | /* Not done yet.. */ |
1598 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1599 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1600 | } |
1601 | } else { |
1602 | DEBUG_EP0("NO REQ??!\n"); |
1603 | } |
1604 | } |
1605 | |
1606 | /* |
1607 | * DATA_STATE_XMIT |
1608 | */ |
1609 | static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr) |
1610 | { |
1611 | struct jz4740_request *req; |
1612 | struct jz4740_ep *ep = &dev->ep[0]; |
1613 | int ret, need_zlp = 0; |
1614 | |
1615 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1616 | |
1617 | if (list_empty(&ep->queue)) |
1618 | req = 0; |
1619 | else |
1620 | req = list_entry(ep->queue.next, struct jz4740_request, queue); |
1621 | |
1622 | if (!req) { |
1623 | DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__); |
1624 | return 0; |
1625 | } |
1626 | |
1627 | if (req->req.length == 0) { |
1628 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1629 | dev->ep0state = WAIT_FOR_SETUP; |
1630 | return 1; |
1631 | } |
1632 | |
1633 | if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) { |
1634 | /* Next write will end with the packet size, */ |
1635 | /* so we need zero-length-packet */ |
1636 | need_zlp = 1; |
1637 | } |
1638 | |
1639 | ret = write_fifo_ep0(ep, req); |
1640 | |
1641 | if (ret == 1 && !need_zlp) { |
1642 | /* Last packet */ |
1643 | DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__); |
1644 | |
1645 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1646 | dev->ep0state = WAIT_FOR_SETUP; |
1647 | } else { |
1648 | DEBUG_EP0("%s: not finished\n", __FUNCTION__); |
1649 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1650 | } |
1651 | |
1652 | if (need_zlp) { |
1653 | DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__); |
1654 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY); |
1655 | dev->ep0state = DATA_STATE_NEED_ZLP; |
1656 | } |
1657 | |
1658 | return 1; |
1659 | } |
1660 | |
1661 | static int jz4740_handle_get_status(struct jz4740_udc *dev, |
1662 | struct usb_ctrlrequest *ctrl) |
1663 | { |
1664 | struct jz4740_ep *ep0 = &dev->ep[0]; |
1665 | struct jz4740_ep *qep; |
1666 | int reqtype = (ctrl->bRequestType & USB_RECIP_MASK); |
1667 | uint16_t val = 0; |
1668 | |
1669 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1670 | |
1671 | if (reqtype == USB_RECIP_INTERFACE) { |
1672 | /* This is not supported. |
1673 | * And according to the USB spec, this one does nothing.. |
1674 | * Just return 0 |
1675 | */ |
1676 | DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n"); |
1677 | } else if (reqtype == USB_RECIP_DEVICE) { |
1678 | DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n"); |
1679 | val |= (1 << 0); /* Self powered */ |
1680 | /*val |= (1<<1); *//* Remote wakeup */ |
1681 | } else if (reqtype == USB_RECIP_ENDPOINT) { |
1682 | int ep_num = (ctrl->wIndex & ~USB_DIR_IN); |
1683 | |
1684 | DEBUG_SETUP |
1685 | ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n", |
1686 | ep_num, ctrl->wLength); |
1687 | |
1688 | if (ctrl->wLength > 2 || ep_num > 3) |
1689 | return -EOPNOTSUPP; |
1690 | |
1691 | qep = &dev->ep[ep_num]; |
1692 | if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0) |
1693 | && ep_index(qep) != 0) { |
1694 | return -EOPNOTSUPP; |
1695 | } |
1696 | |
1697 | jz_udc_set_index(dev, ep_index(qep)); |
1698 | |
1699 | /* Return status on next IN token */ |
1700 | switch (qep->type) { |
1701 | case ep_control: |
1702 | val = |
1703 | (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) == |
1704 | USB_CSR0_SENDSTALL; |
1705 | break; |
1706 | case ep_bulk_in: |
1707 | case ep_interrupt: |
1708 | val = |
1709 | (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) == |
1710 | USB_INCSR_SENDSTALL; |
1711 | break; |
1712 | case ep_bulk_out: |
1713 | val = |
1714 | (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) == |
1715 | USB_OUTCSR_SENDSTALL; |
1716 | break; |
1717 | } |
1718 | |
1719 | /* Back to EP0 index */ |
1720 | jz_udc_set_index(dev, 0); |
1721 | |
1722 | DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num, |
1723 | ctrl->wIndex, val); |
1724 | } else { |
1725 | DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype); |
1726 | return -EOPNOTSUPP; |
1727 | } |
1728 | |
1729 | /* Clear "out packet ready" */ |
1730 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1731 | /* Put status to FIFO */ |
1732 | jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val)); |
1733 | /* Issue "In packet ready" */ |
1734 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1735 | |
1736 | return 0; |
1737 | } |
1738 | |
1739 | /* |
1740 | * WAIT_FOR_SETUP (OUTPKTRDY) |
1741 | * - read data packet from EP0 FIFO |
1742 | * - decode command |
1743 | * - if error |
1744 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits |
1745 | * - else |
1746 | * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits |
1747 | */ |
1748 | static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr) |
1749 | { |
1750 | struct jz4740_ep *ep = &dev->ep[0]; |
1751 | struct usb_ctrlrequest ctrl; |
1752 | int i; |
1753 | |
1754 | DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr); |
1755 | |
1756 | /* Nuke all previous transfers */ |
1757 | nuke(ep, -EPROTO); |
1758 | |
1759 | /* read control req from fifo (8 bytes) */ |
1760 | jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8); |
1761 | |
1762 | DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n", |
1763 | ctrl.bRequestType, ctrl.bRequest, |
1764 | ctrl.wValue, ctrl.wIndex, ctrl.wLength); |
1765 | |
1766 | /* Set direction of EP0 */ |
1767 | if (likely(ctrl.bRequestType & USB_DIR_IN)) { |
1768 | ep->bEndpointAddress |= USB_DIR_IN; |
1769 | } else { |
1770 | ep->bEndpointAddress &= ~USB_DIR_IN; |
1771 | } |
1772 | |
1773 | /* Handle some SETUP packets ourselves */ |
1774 | switch (ctrl.bRequest) { |
1775 | case USB_REQ_SET_ADDRESS: |
1776 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1777 | break; |
1778 | |
1779 | DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue); |
1780 | udc_set_address(dev, ctrl.wValue); |
1781 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1782 | return; |
1783 | |
1784 | case USB_REQ_SET_CONFIGURATION: |
1785 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1786 | break; |
1787 | |
1788 | DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue); |
1789 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1790 | |
1791 | /* Enable RESUME and SUSPEND interrupts */ |
1792 | usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND)); |
1793 | break; |
1794 | |
1795 | case USB_REQ_SET_INTERFACE: |
1796 | if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) |
1797 | break; |
1798 | |
1799 | DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue); |
1800 | /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/ |
1801 | break; |
1802 | |
1803 | case USB_REQ_GET_STATUS: |
1804 | if (jz4740_handle_get_status(dev, &ctrl) == 0) |
1805 | return; |
1806 | |
1807 | case USB_REQ_CLEAR_FEATURE: |
1808 | case USB_REQ_SET_FEATURE: |
1809 | if (ctrl.bRequestType == USB_RECIP_ENDPOINT) { |
1810 | struct jz4740_ep *qep; |
1811 | int ep_num = (ctrl.wIndex & 0x0f); |
1812 | |
1813 | /* Support only HALT feature */ |
1814 | if (ctrl.wValue != 0 || ctrl.wLength != 0 |
1815 | || ep_num > 3 || ep_num < 1) |
1816 | break; |
1817 | |
1818 | qep = &dev->ep[ep_num]; |
1819 | spin_unlock(&dev->lock); |
1820 | if (ctrl.bRequest == USB_REQ_SET_FEATURE) { |
1821 | DEBUG_SETUP("SET_FEATURE (%d)\n", |
1822 | ep_num); |
1823 | jz4740_set_halt(&qep->ep, 1); |
1824 | } else { |
1825 | DEBUG_SETUP("CLR_FEATURE (%d)\n", |
1826 | ep_num); |
1827 | jz4740_set_halt(&qep->ep, 0); |
1828 | } |
1829 | spin_lock(&dev->lock); |
1830 | |
1831 | jz_udc_set_index(dev, 0); |
1832 | |
1833 | /* Reply with a ZLP on next IN token */ |
1834 | usb_setb(dev, JZ_REG_UDC_CSR0, |
1835 | (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND)); |
1836 | return; |
1837 | } |
1838 | break; |
1839 | |
1840 | default: |
1841 | break; |
1842 | } |
1843 | |
1844 | /* gadget drivers see class/vendor specific requests, |
1845 | * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, |
1846 | * and more. |
1847 | */ |
1848 | if (dev->driver) { |
1849 | /* device-2-host (IN) or no data setup command, process immediately */ |
1850 | spin_unlock(&dev->lock); |
1851 | |
1852 | i = dev->driver->setup(&dev->gadget, &ctrl); |
1853 | spin_lock(&dev->lock); |
1854 | |
1855 | if (unlikely(i < 0)) { |
1856 | /* setup processing failed, force stall */ |
1857 | DEBUG_SETUP |
1858 | (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n", |
1859 | i); |
1860 | jz_udc_set_index(dev, 0); |
1861 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL)); |
1862 | |
1863 | /* ep->stopped = 1; */ |
1864 | dev->ep0state = WAIT_FOR_SETUP; |
1865 | } |
1866 | else { |
1867 | DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength); |
1868 | /* if (!ctrl.wLength) { |
1869 | usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
1870 | }*/ |
1871 | } |
1872 | } |
1873 | } |
1874 | |
1875 | /* |
1876 | * DATA_STATE_NEED_ZLP |
1877 | */ |
1878 | static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr) |
1879 | { |
1880 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
1881 | |
1882 | usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND)); |
1883 | dev->ep0state = WAIT_FOR_SETUP; |
1884 | } |
1885 | |
1886 | /* |
1887 | * handle ep0 interrupt |
1888 | */ |
1889 | static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr) |
1890 | { |
1891 | struct jz4740_ep *ep = &dev->ep[0]; |
1892 | uint32_t csr; |
1893 | |
1894 | DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__); |
1895 | /* Set index 0 */ |
1896 | jz_udc_set_index(dev, 0); |
1897 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
1898 | |
1899 | DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]); |
1900 | |
1901 | /* |
1902 | * if SENT_STALL is set |
1903 | * - clear the SENT_STALL bit |
1904 | */ |
1905 | if (csr & USB_CSR0_SENTSTALL) { |
1906 | DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr); |
1907 | usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL); |
1908 | nuke(ep, -ECONNABORTED); |
1909 | dev->ep0state = WAIT_FOR_SETUP; |
1910 | return; |
1911 | } |
1912 | |
1913 | /* |
1914 | * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear |
1915 | * - fill EP0 FIFO |
1916 | * - if last packet |
1917 | * - set IN_PKT_RDY | DATA_END |
1918 | * - else |
1919 | * set IN_PKT_RDY |
1920 | */ |
1921 | if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) { |
1922 | DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n", |
1923 | __FUNCTION__); |
1924 | |
1925 | switch (dev->ep0state) { |
1926 | case DATA_STATE_XMIT: |
1927 | DEBUG_EP0("continue with DATA_STATE_XMIT\n"); |
1928 | jz4740_ep0_in(dev, csr); |
1929 | return; |
1930 | case DATA_STATE_NEED_ZLP: |
1931 | DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n"); |
1932 | jz4740_ep0_in_zlp(dev, csr); |
1933 | return; |
1934 | default: |
1935 | /* Stall? */ |
1936 | // DEBUG_EP0("Odd state!! state = %s\n", |
1937 | // state_names[dev->ep0state]); |
1938 | dev->ep0state = WAIT_FOR_SETUP; |
1939 | /* nuke(ep, 0); */ |
1940 | /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */ |
1941 | // break; |
1942 | return; |
1943 | } |
1944 | } |
1945 | |
1946 | /* |
1947 | * if SETUPEND is set |
1948 | * - abort the last transfer |
1949 | * - set SERVICED_SETUP_END_BIT |
1950 | */ |
1951 | if (csr & USB_CSR0_SETUPEND) { |
1952 | DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr); |
1953 | |
1954 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND); |
1955 | nuke(ep, 0); |
1956 | dev->ep0state = WAIT_FOR_SETUP; |
1957 | } |
1958 | |
1959 | /* |
1960 | * if USB_CSR0_OUTPKTRDY is set |
1961 | * - read data packet from EP0 FIFO |
1962 | * - decode command |
1963 | * - if error |
1964 | * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits |
1965 | * - else |
1966 | * set SVDOUTPKTRDY | DATAEND bits |
1967 | */ |
1968 | if (csr & USB_CSR0_OUTPKTRDY) { |
1969 | |
1970 | DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__, |
1971 | csr); |
1972 | |
1973 | switch (dev->ep0state) { |
1974 | case WAIT_FOR_SETUP: |
1975 | DEBUG_EP0("WAIT_FOR_SETUP\n"); |
1976 | jz4740_ep0_setup(dev, csr); |
1977 | break; |
1978 | |
1979 | case DATA_STATE_RECV: |
1980 | DEBUG_EP0("DATA_STATE_RECV\n"); |
1981 | jz4740_ep0_out(dev, csr, 0); |
1982 | break; |
1983 | |
1984 | default: |
1985 | /* send stall? */ |
1986 | DEBUG_EP0("strange state!! 2. send stall? state = %d\n", |
1987 | dev->ep0state); |
1988 | break; |
1989 | } |
1990 | } |
1991 | } |
1992 | |
1993 | static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep) |
1994 | { |
1995 | uint32_t csr; |
1996 | |
1997 | jz_udc_set_index(dev, 0); |
1998 | |
1999 | DEBUG_EP0("%s: %x\n", __FUNCTION__, csr); |
2000 | |
2001 | /* Clear "out packet ready" */ |
2002 | |
2003 | if (ep_is_in(ep)) { |
2004 | usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY); |
2005 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
2006 | dev->ep0state = DATA_STATE_XMIT; |
2007 | jz4740_ep0_in(dev, csr); |
2008 | } else { |
2009 | csr = usb_readb(dev, JZ_REG_UDC_CSR0); |
2010 | dev->ep0state = DATA_STATE_RECV; |
2011 | jz4740_ep0_out(dev, csr, 1); |
2012 | } |
2013 | } |
2014 | |
2015 | /** Handle USB RESET interrupt |
2016 | */ |
2017 | static void jz4740_reset_irq(struct jz4740_udc *dev) |
2018 | { |
2019 | dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ? |
2020 | USB_SPEED_HIGH : USB_SPEED_FULL; |
2021 | |
2022 | DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address, |
2023 | (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" ); |
2024 | } |
2025 | |
2026 | /* |
2027 | * jz4740 usb device interrupt handler. |
2028 | */ |
2029 | static irqreturn_t jz4740_udc_irq(int irq, void *_dev) |
2030 | { |
2031 | struct jz4740_udc *dev = _dev; |
2032 | uint8_t index; |
2033 | |
2034 | uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */ |
2035 | uint32_t intr_in = usb_readw(dev, JZ_REG_UDC_INTRIN); |
2036 | uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT); |
2037 | uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR); |
2038 | |
2039 | if (!intr_usb && !intr_in && !intr_out && !intr_dma) |
2040 | return IRQ_HANDLED; |
2041 | |
2042 | |
2043 | DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n", |
2044 | intr_out, intr_in, intr_usb); |
2045 | |
2046 | spin_lock(&dev->lock); |
2047 | index = usb_readb(dev, JZ_REG_UDC_INDEX); |
2048 | |
2049 | /* Check for resume from suspend mode */ |
2050 | if ((intr_usb & USB_INTR_RESUME) && |
2051 | (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) { |
2052 | DEBUG("USB resume\n"); |
2053 | dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */ |
2054 | } |
2055 | |
2056 | /* Check for system interrupts */ |
2057 | if (intr_usb & USB_INTR_RESET) { |
2058 | DEBUG("USB reset\n"); |
2059 | jz4740_reset_irq(dev); |
2060 | } |
2061 | |
2062 | /* Check for endpoint 0 interrupt */ |
2063 | if (intr_in & USB_INTR_EP0) { |
2064 | DEBUG("USB_INTR_EP0 (control)\n"); |
2065 | jz4740_handle_ep0(dev, intr_in); |
2066 | } |
2067 | |
2068 | /* Check for Bulk-IN DMA interrupt */ |
2069 | if (intr_dma & 0x1) { |
2070 | int ep_num; |
2071 | struct jz4740_ep *ep; |
2072 | ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf; |
2073 | ep = &dev->ep[ep_num + 1]; |
2074 | jz_udc_set_index(dev, ep_num); |
2075 | usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY); |
2076 | /* jz4740_in_epn(dev, ep_num, intr_in);*/ |
2077 | } |
2078 | |
2079 | /* Check for Bulk-OUT DMA interrupt */ |
2080 | if (intr_dma & 0x2) { |
2081 | int ep_num; |
2082 | ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf; |
2083 | jz4740_out_epn(dev, ep_num, intr_out); |
2084 | } |
2085 | |
2086 | /* Check for each configured endpoint interrupt */ |
2087 | if (intr_in & USB_INTR_INEP1) { |
2088 | DEBUG("USB_INTR_INEP1\n"); |
2089 | jz4740_in_epn(dev, 1, intr_in); |
2090 | } |
2091 | |
2092 | if (intr_in & USB_INTR_INEP2) { |
2093 | DEBUG("USB_INTR_INEP2\n"); |
2094 | jz4740_in_epn(dev, 2, intr_in); |
2095 | } |
2096 | |
2097 | if (intr_out & USB_INTR_OUTEP1) { |
2098 | DEBUG("USB_INTR_OUTEP1\n"); |
2099 | jz4740_out_epn(dev, 1, intr_out); |
2100 | } |
2101 | |
2102 | /* Check for suspend mode */ |
2103 | if ((intr_usb & USB_INTR_SUSPEND) && |
2104 | (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) { |
2105 | DEBUG("USB suspend\n"); |
2106 | dev->driver->suspend(&dev->gadget); |
2107 | /* Host unloaded from us, can do something, such as flushing |
2108 | the NAND block cache etc. */ |
2109 | } |
2110 | |
2111 | jz_udc_set_index(dev, index); |
2112 | |
2113 | spin_unlock(&dev->lock); |
2114 | |
2115 | return IRQ_HANDLED; |
2116 | } |
2117 | |
2118 | |
2119 | |
2120 | /*-------------------------------------------------------------------------*/ |
2121 | |
2122 | /* Common functions - Added by River */ |
2123 | static struct jz4740_udc udc_dev; |
2124 | |
2125 | static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget) |
2126 | { |
2127 | return container_of(gadget, struct jz4740_udc, gadget); |
2128 | } |
2129 | /* End added */ |
2130 | |
2131 | static int jz4740_udc_get_frame(struct usb_gadget *_gadget) |
2132 | { |
2133 | DEBUG("%s, %p\n", __FUNCTION__, _gadget); |
2134 | return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME); |
2135 | } |
2136 | |
2137 | static int jz4740_udc_wakeup(struct usb_gadget *_gadget) |
2138 | { |
2139 | /* host may not have enabled remote wakeup */ |
2140 | /*if ((UDCCS0 & UDCCS0_DRWF) == 0) |
2141 | return -EHOSTUNREACH; |
2142 | udc_set_mask_UDCCR(UDCCR_RSM); */ |
2143 | return -ENOTSUPP; |
2144 | } |
2145 | |
2146 | static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on) |
2147 | { |
2148 | struct jz4740_udc *udc = gadget_to_udc(_gadget); |
2149 | unsigned long flags; |
2150 | |
2151 | local_irq_save(flags); |
2152 | |
2153 | if (on) { |
2154 | udc->state = UDC_STATE_ENABLE; |
2155 | udc_enable(udc); |
2156 | } else { |
2157 | udc->state = UDC_STATE_DISABLE; |
2158 | udc_disable(udc); |
2159 | } |
2160 | |
2161 | local_irq_restore(flags); |
2162 | |
2163 | return 0; |
2164 | } |
2165 | |
2166 | |
2167 | static const struct usb_gadget_ops jz4740_udc_ops = { |
2168 | .get_frame = jz4740_udc_get_frame, |
2169 | .wakeup = jz4740_udc_wakeup, |
2170 | .pullup = jz4740_udc_pullup, |
2171 | /* current versions must always be self-powered */ |
2172 | }; |
2173 | |
2174 | static struct usb_ep_ops jz4740_ep_ops = { |
2175 | .enable = jz4740_ep_enable, |
2176 | .disable = jz4740_ep_disable, |
2177 | |
2178 | .alloc_request = jz4740_alloc_request, |
2179 | .free_request = jz4740_free_request, |
2180 | |
2181 | .queue = jz4740_queue, |
2182 | .dequeue = jz4740_dequeue, |
2183 | |
2184 | .set_halt = jz4740_set_halt, |
2185 | .fifo_status = jz4740_fifo_status, |
2186 | .fifo_flush = jz4740_fifo_flush, |
2187 | }; |
2188 | |
2189 | |
2190 | /*-------------------------------------------------------------------------*/ |
2191 | |
2192 | static struct jz4740_udc udc_dev = { |
2193 | .usb_address = 0, |
2194 | .gadget = { |
2195 | .ops = &jz4740_udc_ops, |
2196 | .ep0 = &udc_dev.ep[0].ep, |
2197 | .name = "jz-udc", |
2198 | .dev = { |
2199 | .init_name = "gadget", |
2200 | }, |
2201 | }, |
2202 | |
2203 | /* control endpoint */ |
2204 | .ep[0] = { |
2205 | .ep = { |
2206 | .name = "ep0", |
2207 | .ops = &jz4740_ep_ops, |
2208 | .maxpacket = EP0_MAXPACKETSIZE, |
2209 | }, |
2210 | .dev = &udc_dev, |
2211 | |
2212 | .bEndpointAddress = 0, |
2213 | .bmAttributes = 0, |
2214 | |
2215 | .type = ep_control, |
2216 | .fifo = JZ_REG_UDC_EP_FIFO(0), |
2217 | .csr = JZ_REG_UDC_CSR0, |
2218 | }, |
2219 | |
2220 | /* bulk out endpoint */ |
2221 | .ep[1] = { |
2222 | .ep = { |
2223 | .name = "ep1out-bulk", |
2224 | .ops = &jz4740_ep_ops, |
2225 | .maxpacket = EPBULK_MAXPACKETSIZE, |
2226 | }, |
2227 | .dev = &udc_dev, |
2228 | |
2229 | .bEndpointAddress = 1, |
2230 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2231 | |
2232 | .type = ep_bulk_out, |
2233 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2234 | .csr = JZ_REG_UDC_OUTCSR, |
2235 | }, |
2236 | |
2237 | /* bulk in endpoint */ |
2238 | .ep[2] = { |
2239 | .ep = { |
2240 | .name = "ep1in-bulk", |
2241 | .ops = &jz4740_ep_ops, |
2242 | .maxpacket = EPBULK_MAXPACKETSIZE, |
2243 | }, |
2244 | .dev = &udc_dev, |
2245 | |
2246 | .bEndpointAddress = 1 | USB_DIR_IN, |
2247 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2248 | |
2249 | .type = ep_bulk_in, |
2250 | .fifo = JZ_REG_UDC_EP_FIFO(1), |
2251 | .csr = JZ_REG_UDC_INCSR, |
2252 | }, |
2253 | |
2254 | /* interrupt in endpoint */ |
2255 | .ep[3] = { |
2256 | .ep = { |
2257 | .name = "ep2in-int", |
2258 | .ops = &jz4740_ep_ops, |
2259 | .maxpacket = EPINTR_MAXPACKETSIZE, |
2260 | }, |
2261 | .dev = &udc_dev, |
2262 | |
2263 | .bEndpointAddress = 2 | USB_DIR_IN, |
2264 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2265 | |
2266 | .type = ep_interrupt, |
2267 | .fifo = JZ_REG_UDC_EP_FIFO(2), |
2268 | .csr = JZ_REG_UDC_INCSR, |
2269 | }, |
2270 | }; |
2271 | |
2272 | static void gadget_release(struct device *_dev) |
2273 | { |
2274 | } |
2275 | |
2276 | |
2277 | static int __devinit jz4740_udc_probe(struct platform_device *pdev) |
2278 | { |
2279 | struct jz4740_udc *dev = &udc_dev; |
2280 | int ret; |
2281 | |
2282 | spin_lock_init(&dev->lock); |
2283 | the_controller = dev; |
2284 | |
2285 | dev->dev = &pdev->dev; |
2286 | dev_set_name(&dev->gadget.dev, "gadget"); |
2287 | dev->gadget.dev.parent = &pdev->dev; |
2288 | dev->gadget.dev.dma_mask = pdev->dev.dma_mask; |
2289 | dev->gadget.dev.release = gadget_release; |
2290 | |
2291 | ret = device_register(&dev->gadget.dev); |
2292 | if (ret) |
2293 | return ret; |
2294 | |
2295 | dev->clk = clk_get(&pdev->dev, "udc"); |
2296 | if (IS_ERR(dev->clk)) { |
2297 | ret = PTR_ERR(dev->clk); |
2298 | dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret); |
2299 | goto err_device_unregister; |
2300 | } |
2301 | |
2302 | platform_set_drvdata(pdev, dev); |
2303 | |
2304 | dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2305 | |
2306 | if (!dev->mem) { |
2307 | ret = -ENOENT; |
2308 | dev_err(&pdev->dev, "Failed to get mmio memory resource\n"); |
2309 | goto err_clk_put; |
2310 | } |
2311 | |
2312 | dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name); |
2313 | |
2314 | if (!dev->mem) { |
2315 | ret = -EBUSY; |
2316 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
2317 | goto err_device_unregister; |
2318 | } |
2319 | |
2320 | dev->base = ioremap(dev->mem->start, resource_size(dev->mem)); |
2321 | |
2322 | if (!dev->base) { |
2323 | ret = -EBUSY; |
2324 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
2325 | goto err_release_mem_region; |
2326 | } |
2327 | |
2328 | dev->irq = platform_get_irq(pdev, 0); |
2329 | |
2330 | ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED, |
2331 | pdev->name, dev); |
2332 | if (ret) { |
2333 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
2334 | goto err_iounmap; |
2335 | } |
2336 | |
2337 | udc_disable(dev); |
2338 | udc_reinit(dev); |
2339 | |
2340 | return 0; |
2341 | |
2342 | err_iounmap: |
2343 | iounmap(dev->base); |
2344 | err_release_mem_region: |
2345 | release_mem_region(dev->mem->start, resource_size(dev->mem)); |
2346 | err_clk_put: |
2347 | clk_put(dev->clk); |
2348 | err_device_unregister: |
2349 | device_unregister(&dev->gadget.dev); |
2350 | platform_set_drvdata(pdev, NULL); |
2351 | |
2352 | the_controller = 0; |
2353 | |
2354 | return ret; |
2355 | } |
2356 | |
2357 | static int __devexit jz4740_udc_remove(struct platform_device *pdev) |
2358 | { |
2359 | struct jz4740_udc *dev = platform_get_drvdata(pdev); |
2360 | |
2361 | if (dev->driver) |
2362 | return -EBUSY; |
2363 | |
2364 | udc_disable(dev); |
2365 | |
2366 | free_irq(dev->irq, dev); |
2367 | iounmap(dev->base); |
2368 | release_mem_region(dev->mem->start, resource_size(dev->mem)); |
2369 | clk_put(dev->clk); |
2370 | |
2371 | platform_set_drvdata(pdev, NULL); |
2372 | device_unregister(&dev->gadget.dev); |
2373 | the_controller = NULL; |
2374 | |
2375 | return 0; |
2376 | } |
2377 | |
2378 | #ifdef CONFIG_PM |
2379 | |
2380 | static int jz4740_udc_suspend(struct device *dev) |
2381 | { |
2382 | struct jz4740_udc *udc = dev_get_drvdata(dev); |
2383 | |
2384 | if (udc->state == UDC_STATE_ENABLE) |
2385 | udc_disable(udc); |
2386 | |
2387 | return 0; |
2388 | } |
2389 | |
2390 | static int jz4740_udc_resume(struct device *dev) |
2391 | { |
2392 | struct jz4740_udc *udc = dev_get_drvdata(dev); |
2393 | |
2394 | if (udc->state == UDC_STATE_ENABLE) |
2395 | udc_enable(udc); |
2396 | |
2397 | return 0; |
2398 | } |
2399 | |
2400 | static struct dev_pm_ops jz4740_udc_pm_ops = { |
2401 | .suspend = jz4740_udc_suspend, |
2402 | .resume = jz4740_udc_resume, |
2403 | }; |
2404 | |
2405 | #define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops) |
2406 | |
2407 | #else |
2408 | |
2409 | #define JZ4740_UDC_PM_OPS NULL |
2410 | |
2411 | #endif |
2412 | |
2413 | static struct platform_driver udc_driver = { |
2414 | .probe = jz4740_udc_probe, |
2415 | .remove = __devexit_p(jz4740_udc_remove), |
2416 | .driver = { |
2417 | .name = "jz-udc", |
2418 | .owner = THIS_MODULE, |
2419 | .pm = JZ4740_UDC_PM_OPS, |
2420 | }, |
2421 | }; |
2422 | |
2423 | /*-------------------------------------------------------------------------*/ |
2424 | |
2425 | static int __init udc_init (void) |
2426 | { |
2427 | return platform_driver_register(&udc_driver); |
2428 | } |
2429 | module_init(udc_init); |
2430 | |
2431 | static void __exit udc_exit (void) |
2432 | { |
2433 | platform_driver_unregister(&udc_driver); |
2434 | } |
2435 | module_exit(udc_exit); |
2436 | |
2437 | MODULE_DESCRIPTION("JZ4740 USB Device Controller"); |
2438 | MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>"); |
2439 | MODULE_LICENSE("GPL"); |
2440 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9