Root/
Source at commit 1b5331d9c6ae1f68db6359d227531ec42bc40d47 created 13 years 11 months ago. By Jerome Glisse, drm/radeon/kms: print GPU family and device id when loading | |
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1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
26 | * Jerome Glisse |
27 | */ |
28 | #include <linux/console.h> |
29 | #include <drm/drmP.h> |
30 | #include <drm/drm_crtc_helper.h> |
31 | #include <drm/radeon_drm.h> |
32 | #include <linux/vgaarb.h> |
33 | #include <linux/vga_switcheroo.h> |
34 | #include "radeon_reg.h" |
35 | #include "radeon.h" |
36 | #include "atom.h" |
37 | |
38 | static const char radeon_family_name[][16] = { |
39 | "R100", |
40 | "RV100", |
41 | "RS100", |
42 | "RV200", |
43 | "RS200", |
44 | "R200", |
45 | "RV250", |
46 | "RS300", |
47 | "RV280", |
48 | "R300", |
49 | "R350", |
50 | "RV350", |
51 | "RV380", |
52 | "R420", |
53 | "R423", |
54 | "RV410", |
55 | "RS400", |
56 | "RS480", |
57 | "RS600", |
58 | "RS690", |
59 | "RS740", |
60 | "RV515", |
61 | "R520", |
62 | "RV530", |
63 | "RV560", |
64 | "RV570", |
65 | "R580", |
66 | "R600", |
67 | "RV610", |
68 | "RV630", |
69 | "RV670", |
70 | "RV620", |
71 | "RV635", |
72 | "RS780", |
73 | "RS880", |
74 | "RV770", |
75 | "RV730", |
76 | "RV710", |
77 | "RV740", |
78 | "CEDAR", |
79 | "REDWOOD", |
80 | "JUNIPER", |
81 | "CYPRESS", |
82 | "HEMLOCK", |
83 | "LAST", |
84 | }; |
85 | |
86 | /* |
87 | * Clear GPU surface registers. |
88 | */ |
89 | void radeon_surface_init(struct radeon_device *rdev) |
90 | { |
91 | /* FIXME: check this out */ |
92 | if (rdev->family < CHIP_R600) { |
93 | int i; |
94 | |
95 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
96 | if (rdev->surface_regs[i].bo) |
97 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
98 | else |
99 | radeon_clear_surface_reg(rdev, i); |
100 | } |
101 | /* enable surfaces */ |
102 | WREG32(RADEON_SURFACE_CNTL, 0); |
103 | } |
104 | } |
105 | |
106 | /* |
107 | * GPU scratch registers helpers function. |
108 | */ |
109 | void radeon_scratch_init(struct radeon_device *rdev) |
110 | { |
111 | int i; |
112 | |
113 | /* FIXME: check this out */ |
114 | if (rdev->family < CHIP_R300) { |
115 | rdev->scratch.num_reg = 5; |
116 | } else { |
117 | rdev->scratch.num_reg = 7; |
118 | } |
119 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
120 | rdev->scratch.free[i] = true; |
121 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
122 | } |
123 | } |
124 | |
125 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
126 | { |
127 | int i; |
128 | |
129 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
130 | if (rdev->scratch.free[i]) { |
131 | rdev->scratch.free[i] = false; |
132 | *reg = rdev->scratch.reg[i]; |
133 | return 0; |
134 | } |
135 | } |
136 | return -EINVAL; |
137 | } |
138 | |
139 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
140 | { |
141 | int i; |
142 | |
143 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
144 | if (rdev->scratch.reg[i] == reg) { |
145 | rdev->scratch.free[i] = true; |
146 | return; |
147 | } |
148 | } |
149 | } |
150 | |
151 | /** |
152 | * radeon_vram_location - try to find VRAM location |
153 | * @rdev: radeon device structure holding all necessary informations |
154 | * @mc: memory controller structure holding memory informations |
155 | * @base: base address at which to put VRAM |
156 | * |
157 | * Function will place try to place VRAM at base address provided |
158 | * as parameter (which is so far either PCI aperture address or |
159 | * for IGP TOM base address). |
160 | * |
161 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
162 | * address space then we limit the VRAM size to the aperture. |
163 | * |
164 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
165 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
166 | * size and print a warning. |
167 | * |
168 | * This function will never fails, worst case are limiting VRAM. |
169 | * |
170 | * Note: GTT start, end, size should be initialized before calling this |
171 | * function on AGP platform. |
172 | * |
173 | * Note: We don't explictly enforce VRAM start to be aligned on VRAM size, |
174 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
175 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
176 | * not IGP. |
177 | * |
178 | * Note: we use mc_vram_size as on some board we need to program the mc to |
179 | * cover the whole aperture even if VRAM size is inferior to aperture size |
180 | * Novell bug 204882 + along with lots of ubuntu ones |
181 | * |
182 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
183 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
184 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
185 | * ones) |
186 | * |
187 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
188 | * explicitly check for that thought. |
189 | * |
190 | * FIXME: when reducing VRAM size align new size on power of 2. |
191 | */ |
192 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
193 | { |
194 | mc->vram_start = base; |
195 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
196 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
197 | mc->real_vram_size = mc->aper_size; |
198 | mc->mc_vram_size = mc->aper_size; |
199 | } |
200 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
201 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { |
202 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
203 | mc->real_vram_size = mc->aper_size; |
204 | mc->mc_vram_size = mc->aper_size; |
205 | } |
206 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
207 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
208 | mc->mc_vram_size >> 20, mc->vram_start, |
209 | mc->vram_end, mc->real_vram_size >> 20); |
210 | } |
211 | |
212 | /** |
213 | * radeon_gtt_location - try to find GTT location |
214 | * @rdev: radeon device structure holding all necessary informations |
215 | * @mc: memory controller structure holding memory informations |
216 | * |
217 | * Function will place try to place GTT before or after VRAM. |
218 | * |
219 | * If GTT size is bigger than space left then we ajust GTT size. |
220 | * Thus function will never fails. |
221 | * |
222 | * FIXME: when reducing GTT size align new size on power of 2. |
223 | */ |
224 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
225 | { |
226 | u64 size_af, size_bf; |
227 | |
228 | size_af = 0xFFFFFFFF - mc->vram_end; |
229 | size_bf = mc->vram_start; |
230 | if (size_bf > size_af) { |
231 | if (mc->gtt_size > size_bf) { |
232 | dev_warn(rdev->dev, "limiting GTT\n"); |
233 | mc->gtt_size = size_bf; |
234 | } |
235 | mc->gtt_start = mc->vram_start - mc->gtt_size; |
236 | } else { |
237 | if (mc->gtt_size > size_af) { |
238 | dev_warn(rdev->dev, "limiting GTT\n"); |
239 | mc->gtt_size = size_af; |
240 | } |
241 | mc->gtt_start = mc->vram_end + 1; |
242 | } |
243 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
244 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", |
245 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
246 | } |
247 | |
248 | /* |
249 | * GPU helpers function. |
250 | */ |
251 | bool radeon_card_posted(struct radeon_device *rdev) |
252 | { |
253 | uint32_t reg; |
254 | |
255 | /* first check CRTCs */ |
256 | if (ASIC_IS_DCE4(rdev)) { |
257 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
258 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
259 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
260 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
261 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
262 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
263 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
264 | return true; |
265 | } else if (ASIC_IS_AVIVO(rdev)) { |
266 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
267 | RREG32(AVIVO_D2CRTC_CONTROL); |
268 | if (reg & AVIVO_CRTC_EN) { |
269 | return true; |
270 | } |
271 | } else { |
272 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
273 | RREG32(RADEON_CRTC2_GEN_CNTL); |
274 | if (reg & RADEON_CRTC_EN) { |
275 | return true; |
276 | } |
277 | } |
278 | |
279 | /* then check MEM_SIZE, in case the crtcs are off */ |
280 | if (rdev->family >= CHIP_R600) |
281 | reg = RREG32(R600_CONFIG_MEMSIZE); |
282 | else |
283 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
284 | |
285 | if (reg) |
286 | return true; |
287 | |
288 | return false; |
289 | |
290 | } |
291 | |
292 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
293 | { |
294 | fixed20_12 a; |
295 | u32 sclk, mclk; |
296 | |
297 | if (rdev->flags & RADEON_IS_IGP) { |
298 | sclk = radeon_get_engine_clock(rdev); |
299 | mclk = rdev->clock.default_mclk; |
300 | |
301 | a.full = rfixed_const(100); |
302 | rdev->pm.sclk.full = rfixed_const(sclk); |
303 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
304 | rdev->pm.mclk.full = rfixed_const(mclk); |
305 | rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); |
306 | |
307 | a.full = rfixed_const(16); |
308 | /* core_bandwidth = sclk(Mhz) * 16 */ |
309 | rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); |
310 | } else { |
311 | sclk = radeon_get_engine_clock(rdev); |
312 | mclk = radeon_get_memory_clock(rdev); |
313 | |
314 | a.full = rfixed_const(100); |
315 | rdev->pm.sclk.full = rfixed_const(sclk); |
316 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
317 | rdev->pm.mclk.full = rfixed_const(mclk); |
318 | rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); |
319 | } |
320 | } |
321 | |
322 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
323 | { |
324 | if (radeon_card_posted(rdev)) |
325 | return true; |
326 | |
327 | if (rdev->bios) { |
328 | DRM_INFO("GPU not posted. posting now...\n"); |
329 | if (rdev->is_atom_bios) |
330 | atom_asic_init(rdev->mode_info.atom_context); |
331 | else |
332 | radeon_combios_asic_init(rdev->ddev); |
333 | return true; |
334 | } else { |
335 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
336 | return false; |
337 | } |
338 | } |
339 | |
340 | int radeon_dummy_page_init(struct radeon_device *rdev) |
341 | { |
342 | if (rdev->dummy_page.page) |
343 | return 0; |
344 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
345 | if (rdev->dummy_page.page == NULL) |
346 | return -ENOMEM; |
347 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, |
348 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
349 | if (!rdev->dummy_page.addr) { |
350 | __free_page(rdev->dummy_page.page); |
351 | rdev->dummy_page.page = NULL; |
352 | return -ENOMEM; |
353 | } |
354 | return 0; |
355 | } |
356 | |
357 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
358 | { |
359 | if (rdev->dummy_page.page == NULL) |
360 | return; |
361 | pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, |
362 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
363 | __free_page(rdev->dummy_page.page); |
364 | rdev->dummy_page.page = NULL; |
365 | } |
366 | |
367 | |
368 | /* ATOM accessor methods */ |
369 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
370 | { |
371 | struct radeon_device *rdev = info->dev->dev_private; |
372 | uint32_t r; |
373 | |
374 | r = rdev->pll_rreg(rdev, reg); |
375 | return r; |
376 | } |
377 | |
378 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
379 | { |
380 | struct radeon_device *rdev = info->dev->dev_private; |
381 | |
382 | rdev->pll_wreg(rdev, reg, val); |
383 | } |
384 | |
385 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
386 | { |
387 | struct radeon_device *rdev = info->dev->dev_private; |
388 | uint32_t r; |
389 | |
390 | r = rdev->mc_rreg(rdev, reg); |
391 | return r; |
392 | } |
393 | |
394 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
395 | { |
396 | struct radeon_device *rdev = info->dev->dev_private; |
397 | |
398 | rdev->mc_wreg(rdev, reg, val); |
399 | } |
400 | |
401 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
402 | { |
403 | struct radeon_device *rdev = info->dev->dev_private; |
404 | |
405 | WREG32(reg*4, val); |
406 | } |
407 | |
408 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
409 | { |
410 | struct radeon_device *rdev = info->dev->dev_private; |
411 | uint32_t r; |
412 | |
413 | r = RREG32(reg*4); |
414 | return r; |
415 | } |
416 | |
417 | int radeon_atombios_init(struct radeon_device *rdev) |
418 | { |
419 | struct card_info *atom_card_info = |
420 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
421 | |
422 | if (!atom_card_info) |
423 | return -ENOMEM; |
424 | |
425 | rdev->mode_info.atom_card_info = atom_card_info; |
426 | atom_card_info->dev = rdev->ddev; |
427 | atom_card_info->reg_read = cail_reg_read; |
428 | atom_card_info->reg_write = cail_reg_write; |
429 | atom_card_info->mc_read = cail_mc_read; |
430 | atom_card_info->mc_write = cail_mc_write; |
431 | atom_card_info->pll_read = cail_pll_read; |
432 | atom_card_info->pll_write = cail_pll_write; |
433 | |
434 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
435 | mutex_init(&rdev->mode_info.atom_context->mutex); |
436 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
437 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
438 | return 0; |
439 | } |
440 | |
441 | void radeon_atombios_fini(struct radeon_device *rdev) |
442 | { |
443 | if (rdev->mode_info.atom_context) { |
444 | kfree(rdev->mode_info.atom_context->scratch); |
445 | kfree(rdev->mode_info.atom_context); |
446 | } |
447 | kfree(rdev->mode_info.atom_card_info); |
448 | } |
449 | |
450 | int radeon_combios_init(struct radeon_device *rdev) |
451 | { |
452 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
453 | return 0; |
454 | } |
455 | |
456 | void radeon_combios_fini(struct radeon_device *rdev) |
457 | { |
458 | } |
459 | |
460 | /* if we get transitioned to only one device, tak VGA back */ |
461 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
462 | { |
463 | struct radeon_device *rdev = cookie; |
464 | radeon_vga_set_state(rdev, state); |
465 | if (state) |
466 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
467 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
468 | else |
469 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
470 | } |
471 | |
472 | void radeon_check_arguments(struct radeon_device *rdev) |
473 | { |
474 | /* vramlimit must be a power of two */ |
475 | switch (radeon_vram_limit) { |
476 | case 0: |
477 | case 4: |
478 | case 8: |
479 | case 16: |
480 | case 32: |
481 | case 64: |
482 | case 128: |
483 | case 256: |
484 | case 512: |
485 | case 1024: |
486 | case 2048: |
487 | case 4096: |
488 | break; |
489 | default: |
490 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
491 | radeon_vram_limit); |
492 | radeon_vram_limit = 0; |
493 | break; |
494 | } |
495 | radeon_vram_limit = radeon_vram_limit << 20; |
496 | /* gtt size must be power of two and greater or equal to 32M */ |
497 | switch (radeon_gart_size) { |
498 | case 4: |
499 | case 8: |
500 | case 16: |
501 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
502 | radeon_gart_size); |
503 | radeon_gart_size = 512; |
504 | break; |
505 | case 32: |
506 | case 64: |
507 | case 128: |
508 | case 256: |
509 | case 512: |
510 | case 1024: |
511 | case 2048: |
512 | case 4096: |
513 | break; |
514 | default: |
515 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
516 | radeon_gart_size); |
517 | radeon_gart_size = 512; |
518 | break; |
519 | } |
520 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
521 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
522 | switch (radeon_agpmode) { |
523 | case -1: |
524 | case 0: |
525 | case 1: |
526 | case 2: |
527 | case 4: |
528 | case 8: |
529 | break; |
530 | default: |
531 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
532 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
533 | radeon_agpmode = 0; |
534 | break; |
535 | } |
536 | } |
537 | |
538 | static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
539 | { |
540 | struct drm_device *dev = pci_get_drvdata(pdev); |
541 | struct radeon_device *rdev = dev->dev_private; |
542 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
543 | if (state == VGA_SWITCHEROO_ON) { |
544 | printk(KERN_INFO "radeon: switched on\n"); |
545 | /* don't suspend or resume card normally */ |
546 | rdev->powered_down = false; |
547 | radeon_resume_kms(dev); |
548 | } else { |
549 | printk(KERN_INFO "radeon: switched off\n"); |
550 | radeon_suspend_kms(dev, pmm); |
551 | /* don't suspend or resume card normally */ |
552 | rdev->powered_down = true; |
553 | } |
554 | } |
555 | |
556 | static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) |
557 | { |
558 | struct drm_device *dev = pci_get_drvdata(pdev); |
559 | bool can_switch; |
560 | |
561 | spin_lock(&dev->count_lock); |
562 | can_switch = (dev->open_count == 0); |
563 | spin_unlock(&dev->count_lock); |
564 | return can_switch; |
565 | } |
566 | |
567 | |
568 | int radeon_device_init(struct radeon_device *rdev, |
569 | struct drm_device *ddev, |
570 | struct pci_dev *pdev, |
571 | uint32_t flags) |
572 | { |
573 | int r; |
574 | int dma_bits; |
575 | |
576 | rdev->shutdown = false; |
577 | rdev->dev = &pdev->dev; |
578 | rdev->ddev = ddev; |
579 | rdev->pdev = pdev; |
580 | rdev->flags = flags; |
581 | rdev->family = flags & RADEON_FAMILY_MASK; |
582 | rdev->is_atom_bios = false; |
583 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
584 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
585 | rdev->gpu_lockup = false; |
586 | rdev->accel_working = false; |
587 | |
588 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", |
589 | radeon_family_name[rdev->family], pdev->vendor, pdev->device); |
590 | |
591 | /* mutex initialization are all done here so we |
592 | * can recall function without having locking issues */ |
593 | mutex_init(&rdev->cs_mutex); |
594 | mutex_init(&rdev->ib_pool.mutex); |
595 | mutex_init(&rdev->cp.mutex); |
596 | mutex_init(&rdev->dc_hw_i2c_mutex); |
597 | if (rdev->family >= CHIP_R600) |
598 | spin_lock_init(&rdev->ih.lock); |
599 | mutex_init(&rdev->gem.mutex); |
600 | mutex_init(&rdev->pm.mutex); |
601 | rwlock_init(&rdev->fence_drv.lock); |
602 | INIT_LIST_HEAD(&rdev->gem.objects); |
603 | init_waitqueue_head(&rdev->irq.vblank_queue); |
604 | |
605 | /* setup workqueue */ |
606 | rdev->wq = create_workqueue("radeon"); |
607 | if (rdev->wq == NULL) |
608 | return -ENOMEM; |
609 | |
610 | /* Set asic functions */ |
611 | r = radeon_asic_init(rdev); |
612 | if (r) |
613 | return r; |
614 | radeon_check_arguments(rdev); |
615 | |
616 | /* all of the newer IGP chips have an internal gart |
617 | * However some rs4xx report as AGP, so remove that here. |
618 | */ |
619 | if ((rdev->family >= CHIP_RS400) && |
620 | (rdev->flags & RADEON_IS_IGP)) { |
621 | rdev->flags &= ~RADEON_IS_AGP; |
622 | } |
623 | |
624 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
625 | radeon_agp_disable(rdev); |
626 | } |
627 | |
628 | /* set DMA mask + need_dma32 flags. |
629 | * PCIE - can handle 40-bits. |
630 | * IGP - can handle 40-bits (in theory) |
631 | * AGP - generally dma32 is safest |
632 | * PCI - only dma32 |
633 | */ |
634 | rdev->need_dma32 = false; |
635 | if (rdev->flags & RADEON_IS_AGP) |
636 | rdev->need_dma32 = true; |
637 | if (rdev->flags & RADEON_IS_PCI) |
638 | rdev->need_dma32 = true; |
639 | |
640 | dma_bits = rdev->need_dma32 ? 32 : 40; |
641 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
642 | if (r) { |
643 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
644 | } |
645 | |
646 | /* Registers mapping */ |
647 | /* TODO: block userspace mapping of io register */ |
648 | rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); |
649 | rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); |
650 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
651 | if (rdev->rmmio == NULL) { |
652 | return -ENOMEM; |
653 | } |
654 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
655 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
656 | |
657 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
658 | /* this will fail for cards that aren't VGA class devices, just |
659 | * ignore it */ |
660 | vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
661 | vga_switcheroo_register_client(rdev->pdev, |
662 | radeon_switcheroo_set_state, |
663 | radeon_switcheroo_can_switch); |
664 | |
665 | r = radeon_init(rdev); |
666 | if (r) |
667 | return r; |
668 | |
669 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
670 | /* Acceleration not working on AGP card try again |
671 | * with fallback to PCI or PCIE GART |
672 | */ |
673 | radeon_gpu_reset(rdev); |
674 | radeon_fini(rdev); |
675 | radeon_agp_disable(rdev); |
676 | r = radeon_init(rdev); |
677 | if (r) |
678 | return r; |
679 | } |
680 | if (radeon_testing) { |
681 | radeon_test_moves(rdev); |
682 | } |
683 | if (radeon_benchmarking) { |
684 | radeon_benchmark(rdev); |
685 | } |
686 | return 0; |
687 | } |
688 | |
689 | void radeon_device_fini(struct radeon_device *rdev) |
690 | { |
691 | DRM_INFO("radeon: finishing device.\n"); |
692 | rdev->shutdown = true; |
693 | radeon_fini(rdev); |
694 | destroy_workqueue(rdev->wq); |
695 | vga_switcheroo_unregister_client(rdev->pdev); |
696 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
697 | iounmap(rdev->rmmio); |
698 | rdev->rmmio = NULL; |
699 | } |
700 | |
701 | |
702 | /* |
703 | * Suspend & resume. |
704 | */ |
705 | int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) |
706 | { |
707 | struct radeon_device *rdev; |
708 | struct drm_crtc *crtc; |
709 | int r; |
710 | |
711 | if (dev == NULL || dev->dev_private == NULL) { |
712 | return -ENODEV; |
713 | } |
714 | if (state.event == PM_EVENT_PRETHAW) { |
715 | return 0; |
716 | } |
717 | rdev = dev->dev_private; |
718 | |
719 | if (rdev->powered_down) |
720 | return 0; |
721 | /* unpin the front buffers */ |
722 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
723 | struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); |
724 | struct radeon_bo *robj; |
725 | |
726 | if (rfb == NULL || rfb->obj == NULL) { |
727 | continue; |
728 | } |
729 | robj = rfb->obj->driver_private; |
730 | if (robj != rdev->fbdev_rbo) { |
731 | r = radeon_bo_reserve(robj, false); |
732 | if (unlikely(r == 0)) { |
733 | radeon_bo_unpin(robj); |
734 | radeon_bo_unreserve(robj); |
735 | } |
736 | } |
737 | } |
738 | /* evict vram memory */ |
739 | radeon_bo_evict_vram(rdev); |
740 | /* wait for gpu to finish processing current batch */ |
741 | radeon_fence_wait_last(rdev); |
742 | |
743 | radeon_save_bios_scratch_regs(rdev); |
744 | |
745 | radeon_suspend(rdev); |
746 | radeon_hpd_fini(rdev); |
747 | /* evict remaining vram memory */ |
748 | radeon_bo_evict_vram(rdev); |
749 | |
750 | pci_save_state(dev->pdev); |
751 | if (state.event == PM_EVENT_SUSPEND) { |
752 | /* Shut down the device */ |
753 | pci_disable_device(dev->pdev); |
754 | pci_set_power_state(dev->pdev, PCI_D3hot); |
755 | } |
756 | acquire_console_sem(); |
757 | fb_set_suspend(rdev->fbdev_info, 1); |
758 | release_console_sem(); |
759 | return 0; |
760 | } |
761 | |
762 | int radeon_resume_kms(struct drm_device *dev) |
763 | { |
764 | struct radeon_device *rdev = dev->dev_private; |
765 | |
766 | if (rdev->powered_down) |
767 | return 0; |
768 | |
769 | acquire_console_sem(); |
770 | pci_set_power_state(dev->pdev, PCI_D0); |
771 | pci_restore_state(dev->pdev); |
772 | if (pci_enable_device(dev->pdev)) { |
773 | release_console_sem(); |
774 | return -1; |
775 | } |
776 | pci_set_master(dev->pdev); |
777 | /* resume AGP if in use */ |
778 | radeon_agp_resume(rdev); |
779 | radeon_resume(rdev); |
780 | radeon_restore_bios_scratch_regs(rdev); |
781 | fb_set_suspend(rdev->fbdev_info, 0); |
782 | release_console_sem(); |
783 | |
784 | /* reset hpd state */ |
785 | radeon_hpd_init(rdev); |
786 | /* blat the mode back in */ |
787 | drm_helper_resume_force_mode(dev); |
788 | return 0; |
789 | } |
790 | |
791 | |
792 | /* |
793 | * Debugfs |
794 | */ |
795 | struct radeon_debugfs { |
796 | struct drm_info_list *files; |
797 | unsigned num_files; |
798 | }; |
799 | static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES]; |
800 | static unsigned _radeon_debugfs_count = 0; |
801 | |
802 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
803 | struct drm_info_list *files, |
804 | unsigned nfiles) |
805 | { |
806 | unsigned i; |
807 | |
808 | for (i = 0; i < _radeon_debugfs_count; i++) { |
809 | if (_radeon_debugfs[i].files == files) { |
810 | /* Already registered */ |
811 | return 0; |
812 | } |
813 | } |
814 | if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) { |
815 | DRM_ERROR("Reached maximum number of debugfs files.\n"); |
816 | DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n"); |
817 | return -EINVAL; |
818 | } |
819 | _radeon_debugfs[_radeon_debugfs_count].files = files; |
820 | _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles; |
821 | _radeon_debugfs_count++; |
822 | #if defined(CONFIG_DEBUG_FS) |
823 | drm_debugfs_create_files(files, nfiles, |
824 | rdev->ddev->control->debugfs_root, |
825 | rdev->ddev->control); |
826 | drm_debugfs_create_files(files, nfiles, |
827 | rdev->ddev->primary->debugfs_root, |
828 | rdev->ddev->primary); |
829 | #endif |
830 | return 0; |
831 | } |
832 | |
833 | #if defined(CONFIG_DEBUG_FS) |
834 | int radeon_debugfs_init(struct drm_minor *minor) |
835 | { |
836 | return 0; |
837 | } |
838 | |
839 | void radeon_debugfs_cleanup(struct drm_minor *minor) |
840 | { |
841 | unsigned i; |
842 | |
843 | for (i = 0; i < _radeon_debugfs_count; i++) { |
844 | drm_debugfs_remove_files(_radeon_debugfs[i].files, |
845 | _radeon_debugfs[i].num_files, minor); |
846 | } |
847 | } |
848 | #endif |
849 |
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v2.6.34-rc5
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