Root/drivers/mmc/host/jz4740_mmc.c

Source at commit 1be551a8eb58178b009ac645c537deb68ada70f9 created 7 years 2 months ago.
By Lars-Peter Clausen, mmc: jz4740: Use a regulator for power control
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/mmc/host.h>
17#include <linux/mmc/slot-gpio.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/delay.h>
25#include <linux/scatterlist.h>
26#include <linux/clk.h>
27#include <linux/cpufreq.h>
28
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <asm/mach-jz4740/gpio.h>
32#include <asm/cacheflush.h>
33#include <linux/dma-mapping.h>
34
35#include <asm/mach-jz4740/jz4740_mmc.h>
36
37#define JZ_REG_MMC_STRPCL 0x00
38#define JZ_REG_MMC_STATUS 0x04
39#define JZ_REG_MMC_CLKRT 0x08
40#define JZ_REG_MMC_CMDAT 0x0C
41#define JZ_REG_MMC_RESTO 0x10
42#define JZ_REG_MMC_RDTO 0x14
43#define JZ_REG_MMC_BLKLEN 0x18
44#define JZ_REG_MMC_NOB 0x1C
45#define JZ_REG_MMC_SNOB 0x20
46#define JZ_REG_MMC_IMASK 0x24
47#define JZ_REG_MMC_IREG 0x28
48#define JZ_REG_MMC_CMD 0x2C
49#define JZ_REG_MMC_ARG 0x30
50#define JZ_REG_MMC_RESP_FIFO 0x34
51#define JZ_REG_MMC_RXFIFO 0x38
52#define JZ_REG_MMC_TXFIFO 0x3C
53
54#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
55#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
56#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
57#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
58#define JZ_MMC_STRPCL_RESET BIT(3)
59#define JZ_MMC_STRPCL_START_OP BIT(2)
60#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
61#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
62#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
63
64
65#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
66#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
67#define JZ_MMC_STATUS_PRG_DONE BIT(13)
68#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
69#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
70#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
71#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
72#define JZ_MMC_STATUS_CLK_EN BIT(8)
73#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
74#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
75#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
76#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
77#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
78#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
79#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
80#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
81
82#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
83#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
84
85
86#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
87#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
88#define JZ_MMC_CMDAT_DMA_EN BIT(8)
89#define JZ_MMC_CMDAT_INIT BIT(7)
90#define JZ_MMC_CMDAT_BUSY BIT(6)
91#define JZ_MMC_CMDAT_STREAM BIT(5)
92#define JZ_MMC_CMDAT_WRITE BIT(4)
93#define JZ_MMC_CMDAT_DATA_EN BIT(3)
94#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
95#define JZ_MMC_CMDAT_RSP_R1 1
96#define JZ_MMC_CMDAT_RSP_R2 2
97#define JZ_MMC_CMDAT_RSP_R3 3
98
99#define JZ_MMC_IRQ_SDIO BIT(7)
100#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
101#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
102#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
103#define JZ_MMC_IRQ_PRG_DONE BIT(1)
104#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
105
106
107#define JZ_MMC_CLK_RATE 24000000
108
109enum jz4740_mmc_state {
110    JZ4740_MMC_STATE_READ_RESPONSE,
111    JZ4740_MMC_STATE_TRANSFER_DATA,
112    JZ4740_MMC_STATE_SEND_STOP,
113    JZ4740_MMC_STATE_DONE,
114};
115
116struct jz4740_mmc_host {
117    struct mmc_host *mmc;
118    struct platform_device *pdev;
119    struct jz4740_mmc_platform_data *pdata;
120    struct clk *clk;
121
122    int irq;
123    int card_detect_irq;
124
125    void __iomem *base;
126    struct mmc_request *req;
127    struct mmc_command *cmd;
128
129    unsigned long waiting;
130
131    uint32_t cmdat;
132
133    uint16_t irq_mask;
134
135    spinlock_t lock;
136
137    struct timer_list timeout_timer;
138    struct sg_mapping_iter miter;
139    enum jz4740_mmc_state state;
140};
141
142static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
143    unsigned int irq, bool enabled)
144{
145    unsigned long flags;
146
147    spin_lock_irqsave(&host->lock, flags);
148    if (enabled)
149        host->irq_mask &= ~irq;
150    else
151        host->irq_mask |= irq;
152    spin_unlock_irqrestore(&host->lock, flags);
153
154    writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
155}
156
157static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
158    bool start_transfer)
159{
160    uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
161
162    if (start_transfer)
163        val |= JZ_MMC_STRPCL_START_OP;
164
165    writew(val, host->base + JZ_REG_MMC_STRPCL);
166}
167
168static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
169{
170    uint32_t status;
171    unsigned int timeout = 1000;
172
173    writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
174    do {
175        status = readl(host->base + JZ_REG_MMC_STATUS);
176    } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
177}
178
179static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
180{
181    uint32_t status;
182    unsigned int timeout = 1000;
183
184    writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
185    udelay(10);
186    do {
187        status = readl(host->base + JZ_REG_MMC_STATUS);
188    } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
189}
190
191static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
192{
193    struct mmc_request *req;
194
195    req = host->req;
196    host->req = NULL;
197
198    mmc_request_done(host->mmc, req);
199}
200
201static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
202    unsigned int irq)
203{
204    unsigned int timeout = 0x800;
205    uint16_t status;
206
207    do {
208        status = readw(host->base + JZ_REG_MMC_IREG);
209    } while (!(status & irq) && --timeout);
210
211    if (timeout == 0) {
212        set_bit(0, &host->waiting);
213        mod_timer(&host->timeout_timer, jiffies + 5*HZ);
214        jz4740_mmc_set_irq_enabled(host, irq, true);
215        return true;
216    }
217
218    return false;
219}
220
221static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
222    struct mmc_data *data)
223{
224    int status;
225
226    status = readl(host->base + JZ_REG_MMC_STATUS);
227    if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
228        if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
229            host->req->cmd->error = -ETIMEDOUT;
230            data->error = -ETIMEDOUT;
231        } else {
232            host->req->cmd->error = -EIO;
233            data->error = -EIO;
234        }
235    } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
236        if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
237            host->req->cmd->error = -ETIMEDOUT;
238            data->error = -ETIMEDOUT;
239        } else {
240            host->req->cmd->error = -EIO;
241            data->error = -EIO;
242        }
243    }
244}
245
246static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
247    struct mmc_data *data)
248{
249    struct sg_mapping_iter *miter = &host->miter;
250    void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
251    uint32_t *buf;
252    bool timeout;
253    size_t i, j;
254
255    while (sg_miter_next(miter)) {
256        buf = miter->addr;
257        i = miter->length / 4;
258        j = i / 8;
259        i = i & 0x7;
260        while (j) {
261            timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
262            if (unlikely(timeout))
263                goto poll_timeout;
264
265            writel(buf[0], fifo_addr);
266            writel(buf[1], fifo_addr);
267            writel(buf[2], fifo_addr);
268            writel(buf[3], fifo_addr);
269            writel(buf[4], fifo_addr);
270            writel(buf[5], fifo_addr);
271            writel(buf[6], fifo_addr);
272            writel(buf[7], fifo_addr);
273            buf += 8;
274            --j;
275        }
276        if (unlikely(i)) {
277            timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
278            if (unlikely(timeout))
279                goto poll_timeout;
280
281            while (i) {
282                writel(*buf, fifo_addr);
283                ++buf;
284                --i;
285            }
286        }
287        data->bytes_xfered += miter->length;
288    }
289    sg_miter_stop(miter);
290
291    return false;
292
293poll_timeout:
294    miter->consumed = (void *)buf - miter->addr;
295    data->bytes_xfered += miter->consumed;
296    sg_miter_stop(miter);
297
298    return true;
299}
300
301static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
302                struct mmc_data *data)
303{
304    struct sg_mapping_iter *miter = &host->miter;
305    void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
306    uint32_t *buf;
307    uint32_t d;
308    uint16_t status;
309    size_t i, j;
310    unsigned int timeout;
311
312    while (sg_miter_next(miter)) {
313        buf = miter->addr;
314        i = miter->length;
315        j = i / 32;
316        i = i & 0x1f;
317        while (j) {
318            timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
319            if (unlikely(timeout))
320                goto poll_timeout;
321
322            buf[0] = readl(fifo_addr);
323            buf[1] = readl(fifo_addr);
324            buf[2] = readl(fifo_addr);
325            buf[3] = readl(fifo_addr);
326            buf[4] = readl(fifo_addr);
327            buf[5] = readl(fifo_addr);
328            buf[6] = readl(fifo_addr);
329            buf[7] = readl(fifo_addr);
330
331            buf += 8;
332            --j;
333        }
334
335        if (unlikely(i)) {
336            timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
337            if (unlikely(timeout))
338                goto poll_timeout;
339
340            while (i >= 4) {
341                *buf++ = readl(fifo_addr);
342                i -= 4;
343            }
344            if (unlikely(i > 0)) {
345                d = readl(fifo_addr);
346                memcpy(buf, &d, i);
347            }
348        }
349        data->bytes_xfered += miter->length;
350
351        /* This can go away once MIPS implements
352         * flush_kernel_dcache_page */
353        flush_dcache_page(miter->page);
354    }
355    sg_miter_stop(miter);
356
357    /* For whatever reason there is sometime one word more in the fifo then
358     * requested */
359    timeout = 1000;
360    status = readl(host->base + JZ_REG_MMC_STATUS);
361    while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
362        d = readl(fifo_addr);
363        status = readl(host->base + JZ_REG_MMC_STATUS);
364    }
365
366    return false;
367
368poll_timeout:
369    miter->consumed = (void *)buf - miter->addr;
370    data->bytes_xfered += miter->consumed;
371    sg_miter_stop(miter);
372
373    return true;
374}
375
376static void jz4740_mmc_timeout(unsigned long data)
377{
378    struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
379
380    if (!test_and_clear_bit(0, &host->waiting))
381        return;
382
383    jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
384
385    host->req->cmd->error = -ETIMEDOUT;
386    jz4740_mmc_request_done(host);
387}
388
389static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
390    struct mmc_command *cmd)
391{
392    int i;
393    uint16_t tmp;
394    void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
395
396    if (cmd->flags & MMC_RSP_136) {
397        tmp = readw(fifo_addr);
398        for (i = 0; i < 4; ++i) {
399            cmd->resp[i] = tmp << 24;
400            tmp = readw(fifo_addr);
401            cmd->resp[i] |= tmp << 8;
402            tmp = readw(fifo_addr);
403            cmd->resp[i] |= tmp >> 8;
404        }
405    } else {
406        cmd->resp[0] = readw(fifo_addr) << 24;
407        cmd->resp[0] |= readw(fifo_addr) << 8;
408        cmd->resp[0] |= readw(fifo_addr) & 0xff;
409    }
410}
411
412static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
413    struct mmc_command *cmd)
414{
415    uint32_t cmdat = host->cmdat;
416
417    host->cmdat &= ~JZ_MMC_CMDAT_INIT;
418    jz4740_mmc_clock_disable(host);
419
420    host->cmd = cmd;
421
422    if (cmd->flags & MMC_RSP_BUSY)
423        cmdat |= JZ_MMC_CMDAT_BUSY;
424
425    switch (mmc_resp_type(cmd)) {
426    case MMC_RSP_R1B:
427    case MMC_RSP_R1:
428        cmdat |= JZ_MMC_CMDAT_RSP_R1;
429        break;
430    case MMC_RSP_R2:
431        cmdat |= JZ_MMC_CMDAT_RSP_R2;
432        break;
433    case MMC_RSP_R3:
434        cmdat |= JZ_MMC_CMDAT_RSP_R3;
435        break;
436    default:
437        break;
438    }
439
440    if (cmd->data) {
441        cmdat |= JZ_MMC_CMDAT_DATA_EN;
442        if (cmd->data->flags & MMC_DATA_WRITE)
443            cmdat |= JZ_MMC_CMDAT_WRITE;
444        if (cmd->data->flags & MMC_DATA_STREAM)
445            cmdat |= JZ_MMC_CMDAT_STREAM;
446
447        writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
448        writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
449    }
450
451    writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
452    writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
453    writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
454
455    jz4740_mmc_clock_enable(host, 1);
456}
457
458static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
459{
460    struct mmc_command *cmd = host->req->cmd;
461    struct mmc_data *data = cmd->data;
462    int direction;
463
464    if (data->flags & MMC_DATA_READ)
465        direction = SG_MITER_TO_SG;
466    else
467        direction = SG_MITER_FROM_SG;
468
469    sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
470}
471
472
473static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
474{
475    struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
476    struct mmc_command *cmd = host->req->cmd;
477    struct mmc_request *req = host->req;
478    bool timeout = false;
479
480    if (cmd->error)
481        host->state = JZ4740_MMC_STATE_DONE;
482
483    switch (host->state) {
484    case JZ4740_MMC_STATE_READ_RESPONSE:
485        if (cmd->flags & MMC_RSP_PRESENT)
486            jz4740_mmc_read_response(host, cmd);
487
488        if (!cmd->data)
489            break;
490
491        jz_mmc_prepare_data_transfer(host);
492
493    case JZ4740_MMC_STATE_TRANSFER_DATA:
494        if (cmd->data->flags & MMC_DATA_READ)
495            timeout = jz4740_mmc_read_data(host, cmd->data);
496        else
497            timeout = jz4740_mmc_write_data(host, cmd->data);
498
499        if (unlikely(timeout)) {
500            host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
501            break;
502        }
503
504        jz4740_mmc_transfer_check_state(host, cmd->data);
505
506        timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
507        if (unlikely(timeout)) {
508            host->state = JZ4740_MMC_STATE_SEND_STOP;
509            break;
510        }
511        writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
512
513    case JZ4740_MMC_STATE_SEND_STOP:
514        if (!req->stop)
515            break;
516
517        jz4740_mmc_send_command(host, req->stop);
518
519        timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE);
520        if (timeout) {
521            host->state = JZ4740_MMC_STATE_DONE;
522            break;
523        }
524    case JZ4740_MMC_STATE_DONE:
525        break;
526    }
527
528    if (!timeout)
529        jz4740_mmc_request_done(host);
530
531    return IRQ_HANDLED;
532}
533
534static irqreturn_t jz_mmc_irq(int irq, void *devid)
535{
536    struct jz4740_mmc_host *host = devid;
537    struct mmc_command *cmd = host->cmd;
538    uint16_t irq_reg, status, tmp;
539
540    irq_reg = readw(host->base + JZ_REG_MMC_IREG);
541
542    tmp = irq_reg;
543    irq_reg &= ~host->irq_mask;
544
545    tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
546        JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
547
548    if (tmp != irq_reg)
549        writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
550
551    if (irq_reg & JZ_MMC_IRQ_SDIO) {
552        writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
553        mmc_signal_sdio_irq(host->mmc);
554        irq_reg &= ~JZ_MMC_IRQ_SDIO;
555    }
556
557    if (host->req && cmd && irq_reg) {
558        if (test_and_clear_bit(0, &host->waiting)) {
559            del_timer(&host->timeout_timer);
560
561            status = readl(host->base + JZ_REG_MMC_STATUS);
562
563            if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
564                    cmd->error = -ETIMEDOUT;
565            } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
566                    cmd->error = -EIO;
567            } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
568                    JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
569                    if (cmd->data)
570                            cmd->data->error = -EIO;
571                    cmd->error = -EIO;
572            }
573
574            jz4740_mmc_set_irq_enabled(host, irq_reg, false);
575            writew(irq_reg, host->base + JZ_REG_MMC_IREG);
576
577            return IRQ_WAKE_THREAD;
578        }
579    }
580
581    return IRQ_HANDLED;
582}
583
584static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
585{
586    int div = 0;
587    int real_rate;
588
589    jz4740_mmc_clock_disable(host);
590    clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
591
592    real_rate = clk_get_rate(host->clk);
593
594    while (real_rate > rate && div < 7) {
595        ++div;
596        real_rate >>= 1;
597    }
598
599    writew(div, host->base + JZ_REG_MMC_CLKRT);
600    return real_rate;
601}
602
603static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
604{
605    struct jz4740_mmc_host *host = mmc_priv(mmc);
606
607    host->req = req;
608
609    writew(0xffff, host->base + JZ_REG_MMC_IREG);
610
611    writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
612    jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
613
614    host->state = JZ4740_MMC_STATE_READ_RESPONSE;
615    set_bit(0, &host->waiting);
616    mod_timer(&host->timeout_timer, jiffies + 5*HZ);
617    jz4740_mmc_send_command(host, req->cmd);
618}
619
620static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
621{
622    struct jz4740_mmc_host *host = mmc_priv(mmc);
623    if (ios->clock)
624        jz4740_mmc_set_clock_rate(host, ios->clock);
625
626    switch (ios->power_mode) {
627    case MMC_POWER_UP:
628        jz4740_mmc_reset(host);
629        mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
630        host->cmdat |= JZ_MMC_CMDAT_INIT;
631        clk_prepare_enable(host->clk);
632        break;
633    case MMC_POWER_ON:
634        break;
635    default:
636        mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
637        clk_disable_unprepare(host->clk);
638        break;
639    }
640
641    switch (ios->bus_width) {
642    case MMC_BUS_WIDTH_1:
643        host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
644        break;
645    case MMC_BUS_WIDTH_4:
646        host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
647        break;
648    default:
649        break;
650    }
651}
652
653static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
654{
655    struct jz4740_mmc_host *host = mmc_priv(mmc);
656    jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
657}
658
659#ifdef CONFIG_CPU_FREQ
660
661static struct jz4740_mmc_host *cpufreq_host;
662
663static int jz4740_mmc_cpufreq_transition(struct notifier_block *nb,
664                     unsigned long val, void *data)
665{
666    /* TODO: We only have to take action when the PLL freq changes:
667             the main dividers have no influence on the MSC device clock. */
668
669    if (val == CPUFREQ_PRECHANGE) {
670        mmc_claim_host(cpufreq_host->mmc);
671        clk_disable_unprepare(cpufreq_host->clk);
672    } else if (val == CPUFREQ_POSTCHANGE) {
673        struct mmc_ios *ios = &cpufreq_host->mmc->ios;
674        if (ios->clock)
675            jz4740_mmc_set_clock_rate(cpufreq_host, ios->clock);
676        if (ios->power_mode != MMC_POWER_OFF)
677            clk_prepare_enable(cpufreq_host->clk);
678        mmc_release_host(cpufreq_host->mmc);
679    }
680    return 0;
681}
682
683static struct notifier_block jz4740_mmc_cpufreq_nb = {
684    .notifier_call = jz4740_mmc_cpufreq_transition,
685};
686
687static inline int jz4740_mmc_cpufreq_register(struct jz4740_mmc_host *host)
688{
689    cpufreq_host = host;
690    return cpufreq_register_notifier(&jz4740_mmc_cpufreq_nb,
691                     CPUFREQ_TRANSITION_NOTIFIER);
692}
693
694static inline void jz4740_mmc_cpufreq_unregister(void)
695{
696    cpufreq_unregister_notifier(&jz4740_mmc_cpufreq_nb,
697                    CPUFREQ_TRANSITION_NOTIFIER);
698}
699
700#else
701
702static inline int jz4740_mmc_cpufreq_register(struct jz4740_mmc_host *host)
703{
704    return 0;
705}
706
707static inline void jz4740_mmc_cpufreq_unregister(void)
708{
709}
710
711#endif
712
713static const struct mmc_host_ops jz4740_mmc_ops = {
714    .request = jz4740_mmc_request,
715    .set_ios = jz4740_mmc_set_ios,
716    .get_ro = mmc_gpio_get_ro,
717    .get_cd = mmc_gpio_get_cd,
718    .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
719};
720
721static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
722    JZ_GPIO_BULK_PIN(MSC_CMD),
723    JZ_GPIO_BULK_PIN(MSC_CLK),
724    JZ_GPIO_BULK_PIN(MSC_DATA0),
725    JZ_GPIO_BULK_PIN(MSC_DATA1),
726    JZ_GPIO_BULK_PIN(MSC_DATA2),
727    JZ_GPIO_BULK_PIN(MSC_DATA3),
728};
729
730static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
731    struct platform_device *pdev)
732{
733    struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
734    int ret = 0;
735
736    if (!pdata)
737        return 0;
738
739    if (!pdata->card_detect_active_low)
740        mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
741    if (!pdata->read_only_active_low)
742        mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
743
744    if (gpio_is_valid(pdata->gpio_card_detect)) {
745        ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0);
746        if (ret)
747            return ret;
748    }
749
750    if (gpio_is_valid(pdata->gpio_read_only))
751        ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only);
752
753    return ret;
754}
755
756static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
757{
758    size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
759    if (host->pdata && host->pdata->data_1bit)
760        num_pins -= 3;
761
762    return num_pins;
763}
764
765static int jz4740_mmc_probe(struct platform_device* pdev)
766{
767    int ret;
768    struct mmc_host *mmc;
769    struct jz4740_mmc_host *host;
770    struct jz4740_mmc_platform_data *pdata;
771    struct resource *res;
772
773    pdata = pdev->dev.platform_data;
774
775    mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
776    if (!mmc) {
777        dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
778        return -ENOMEM;
779    }
780
781    host = mmc_priv(mmc);
782    host->pdata = pdata;
783
784    host->irq = platform_get_irq(pdev, 0);
785    if (host->irq < 0) {
786        ret = host->irq;
787        dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
788        goto err_free_host;
789    }
790
791    host->clk = devm_clk_get(&pdev->dev, "mmc");
792    if (IS_ERR(host->clk)) {
793        ret = PTR_ERR(host->clk);
794        dev_err(&pdev->dev, "Failed to get mmc clock\n");
795        goto err_free_host;
796    }
797
798    ret = jz4740_mmc_cpufreq_register(host);
799    if (ret) {
800        dev_err(&pdev->dev,
801            "Failed to register cpufreq transition notifier\n");
802        goto err_free_host;
803    }
804
805    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
806    host->base = devm_ioremap_resource(&pdev->dev, res);
807    if (IS_ERR(host->base)) {
808        ret = PTR_ERR(host->base);
809        dev_err(&pdev->dev, "Failed to ioremap base memory\n");
810        goto err_cpufreq_unreg;
811    }
812
813    ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
814    if (ret) {
815        dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
816        goto err_cpufreq_unreg;
817    }
818
819    ret = jz4740_mmc_request_gpios(mmc, pdev);
820    if (ret)
821        goto err_gpio_bulk_free;
822
823    ret = mmc_regulator_get_supply(mmc);
824    if (ret)
825        goto err_gpio_bulk_free;
826
827    mmc->ops = &jz4740_mmc_ops;
828    mmc->f_min = JZ_MMC_CLK_RATE / 128;
829    mmc->f_max = JZ_MMC_CLK_RATE;
830    mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
831    mmc->caps |= MMC_CAP_SDIO_IRQ;
832
833    mmc->max_blk_size = (1 << 10) - 1;
834    mmc->max_blk_count = (1 << 15) - 1;
835    mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
836
837    mmc->max_segs = 128;
838    mmc->max_seg_size = mmc->max_req_size;
839
840    host->mmc = mmc;
841    host->pdev = pdev;
842    spin_lock_init(&host->lock);
843    host->irq_mask = 0xffff;
844
845    ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
846            dev_name(&pdev->dev), host);
847    if (ret) {
848        dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
849        goto err_gpio_bulk_free;
850    }
851
852    jz4740_mmc_reset(host);
853    jz4740_mmc_clock_disable(host);
854    setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
855            (unsigned long)host);
856    /* It is not important when it times out, it just needs to timeout. */
857    set_timer_slack(&host->timeout_timer, HZ);
858
859    platform_set_drvdata(pdev, host);
860    ret = mmc_add_host(mmc);
861
862    if (ret) {
863        dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
864        goto err_free_irq;
865    }
866    dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
867
868    return 0;
869
870err_free_irq:
871    free_irq(host->irq, host);
872err_gpio_bulk_free:
873    jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
874err_cpufreq_unreg:
875    jz4740_mmc_cpufreq_unregister();
876err_free_host:
877    mmc_free_host(mmc);
878
879    return ret;
880}
881
882static int jz4740_mmc_remove(struct platform_device *pdev)
883{
884    struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
885
886    del_timer_sync(&host->timeout_timer);
887    jz4740_mmc_set_irq_enabled(host, 0xff, false);
888    jz4740_mmc_reset(host);
889
890    mmc_remove_host(host->mmc);
891
892    free_irq(host->irq, host);
893
894    jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
895
896    jz4740_mmc_cpufreq_unregister();
897    mmc_free_host(host->mmc);
898
899    return 0;
900}
901
902#ifdef CONFIG_PM_SLEEP
903
904static int jz4740_mmc_suspend(struct device *dev)
905{
906    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
907
908    jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
909
910    return 0;
911}
912
913static int jz4740_mmc_resume(struct device *dev)
914{
915    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
916
917    jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
918
919    return 0;
920}
921
922static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
923    jz4740_mmc_resume);
924#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
925#else
926#define JZ4740_MMC_PM_OPS NULL
927#endif
928
929static struct platform_driver jz4740_mmc_driver = {
930    .probe = jz4740_mmc_probe,
931    .remove = jz4740_mmc_remove,
932    .driver = {
933        .name = "jz4740-mmc",
934        .owner = THIS_MODULE,
935        .pm = JZ4740_MMC_PM_OPS,
936    },
937};
938
939module_platform_driver(jz4740_mmc_driver);
940
941MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
942MODULE_LICENSE("GPL");
943MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
944

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