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Source at commit 26e6894325eab6f295ae51a468f5d866a27b2f8c created 13 years 11 months ago. By Lars-Peter Clausen, Add JZ4740 SoC core support | |
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1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 platform GPIO support |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | */ |
15 | |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> |
18 | #include <linux/init.h> |
19 | |
20 | #include <linux/spinlock.h> |
21 | #include <linux/sysdev.h> |
22 | #include <linux/io.h> |
23 | #include <linux/gpio.h> |
24 | #include <linux/delay.h> |
25 | #include <linux/interrupt.h> |
26 | #include <linux/bitops.h> |
27 | |
28 | #include <linux/debugfs.h> |
29 | #include <linux/seq_file.h> |
30 | |
31 | #include <asm/mach-jz4740/base.h> |
32 | |
33 | #define JZ4740_GPIO_BASE_A (32*0) |
34 | #define JZ4740_GPIO_BASE_B (32*1) |
35 | #define JZ4740_GPIO_BASE_C (32*2) |
36 | #define JZ4740_GPIO_BASE_D (32*3) |
37 | |
38 | #define JZ4740_GPIO_NUM_A 32 |
39 | #define JZ4740_GPIO_NUM_B 32 |
40 | #define JZ4740_GPIO_NUM_C 31 |
41 | #define JZ4740_GPIO_NUM_D 32 |
42 | |
43 | #define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A) |
44 | #define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B) |
45 | #define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C) |
46 | #define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D) |
47 | |
48 | #define JZ4740_IRQ_GPIO_A(num) (JZ4740_IRQ_GPIO_BASE_A + num) |
49 | #define JZ4740_IRQ_GPIO_B(num) (JZ4740_IRQ_GPIO_BASE_B + num) |
50 | #define JZ4740_IRQ_GPIO_C(num) (JZ4740_IRQ_GPIO_BASE_C + num) |
51 | #define JZ4740_IRQ_GPIO_D(num) (JZ4740_IRQ_GPIO_BASE_D + num) |
52 | |
53 | #define JZ_REG_GPIO_PIN 0x00 |
54 | #define JZ_REG_GPIO_DATA 0x10 |
55 | #define JZ_REG_GPIO_DATA_SET 0x14 |
56 | #define JZ_REG_GPIO_DATA_CLEAR 0x18 |
57 | #define JZ_REG_GPIO_MASK 0x20 |
58 | #define JZ_REG_GPIO_MASK_SET 0x24 |
59 | #define JZ_REG_GPIO_MASK_CLEAR 0x28 |
60 | #define JZ_REG_GPIO_PULL 0x30 |
61 | #define JZ_REG_GPIO_PULL_SET 0x34 |
62 | #define JZ_REG_GPIO_PULL_CLEAR 0x38 |
63 | #define JZ_REG_GPIO_FUNC 0x40 |
64 | #define JZ_REG_GPIO_FUNC_SET 0x44 |
65 | #define JZ_REG_GPIO_FUNC_CLEAR 0x48 |
66 | #define JZ_REG_GPIO_SELECT 0x50 |
67 | #define JZ_REG_GPIO_SELECT_SET 0x54 |
68 | #define JZ_REG_GPIO_SELECT_CLEAR 0x58 |
69 | #define JZ_REG_GPIO_DIRECTION 0x60 |
70 | #define JZ_REG_GPIO_DIRECTION_SET 0x64 |
71 | #define JZ_REG_GPIO_DIRECTION_CLEAR 0x68 |
72 | #define JZ_REG_GPIO_TRIGGER 0x70 |
73 | #define JZ_REG_GPIO_TRIGGER_SET 0x74 |
74 | #define JZ_REG_GPIO_TRIGGER_CLEAR 0x78 |
75 | #define JZ_REG_GPIO_FLAG 0x80 |
76 | #define JZ_REG_GPIO_FLAG_CLEAR 0x14 |
77 | |
78 | |
79 | #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f) |
80 | #define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg)) |
81 | #define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg)) |
82 | |
83 | struct jz_gpio_chip { |
84 | unsigned int irq; |
85 | unsigned int irq_base; |
86 | uint32_t wakeup; |
87 | uint32_t suspend_mask; |
88 | uint32_t edge_trigger_both; |
89 | |
90 | void __iomem *base; |
91 | |
92 | spinlock_t lock; |
93 | |
94 | struct gpio_chip gpio_chip; |
95 | struct irq_chip irq_chip; |
96 | struct sys_device sysdev; |
97 | }; |
98 | |
99 | |
100 | static struct jz_gpio_chip jz4740_gpio_chips[]; |
101 | |
102 | static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio) |
103 | { |
104 | return &jz4740_gpio_chips[gpio >> 5]; |
105 | } |
106 | |
107 | static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip) |
108 | { |
109 | return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip); |
110 | } |
111 | |
112 | static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq) |
113 | { |
114 | return get_irq_chip_data(irq); |
115 | } |
116 | |
117 | static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) |
118 | { |
119 | writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg)); |
120 | } |
121 | |
122 | int jz_gpio_set_function(int gpio, enum jz_gpio_function function) |
123 | { |
124 | if (function == JZ_GPIO_FUNC_NONE) { |
125 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR); |
126 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); |
127 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); |
128 | } else { |
129 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET); |
130 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); |
131 | switch (function) { |
132 | case JZ_GPIO_FUNC1: |
133 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); |
134 | break; |
135 | case JZ_GPIO_FUNC3: |
136 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET); |
137 | case JZ_GPIO_FUNC2: /* Falltrough */ |
138 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET); |
139 | break; |
140 | default: |
141 | BUG(); |
142 | break; |
143 | } |
144 | } |
145 | |
146 | return 0; |
147 | } |
148 | EXPORT_SYMBOL_GPL(jz_gpio_set_function); |
149 | |
150 | int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num) |
151 | { |
152 | size_t i; |
153 | int ret; |
154 | |
155 | for (i = 0; i < num; ++i, ++request) { |
156 | ret = gpio_request(request->gpio, request->name); |
157 | if (ret) |
158 | goto err; |
159 | jz_gpio_set_function(request->gpio, request->function); |
160 | } |
161 | |
162 | return 0; |
163 | |
164 | err: |
165 | for (--request; i > 0; --i, --request) { |
166 | gpio_free(request->gpio); |
167 | jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); |
168 | } |
169 | |
170 | return ret; |
171 | } |
172 | EXPORT_SYMBOL_GPL(jz_gpio_bulk_request); |
173 | |
174 | void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num) |
175 | { |
176 | size_t i; |
177 | |
178 | for (i = 0; i < num; ++i, ++request) { |
179 | gpio_free(request->gpio); |
180 | jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); |
181 | } |
182 | |
183 | } |
184 | EXPORT_SYMBOL_GPL(jz_gpio_bulk_free); |
185 | |
186 | void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num) |
187 | { |
188 | size_t i; |
189 | |
190 | for (i = 0; i < num; ++i, ++request) { |
191 | jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); |
192 | jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR); |
193 | jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET); |
194 | } |
195 | } |
196 | EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend); |
197 | |
198 | void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num) |
199 | { |
200 | size_t i; |
201 | |
202 | for (i = 0; i < num; ++i, ++request) |
203 | jz_gpio_set_function(request->gpio, request->function); |
204 | } |
205 | EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume); |
206 | |
207 | void jz_gpio_enable_pullup(unsigned gpio) |
208 | { |
209 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR); |
210 | } |
211 | EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup); |
212 | |
213 | void jz_gpio_disable_pullup(unsigned gpio) |
214 | { |
215 | jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET); |
216 | } |
217 | EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup); |
218 | |
219 | static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio) |
220 | { |
221 | return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio)); |
222 | } |
223 | |
224 | static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) |
225 | { |
226 | uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET); |
227 | reg += !value; |
228 | writel(BIT(gpio), reg); |
229 | } |
230 | |
231 | static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, |
232 | int value) |
233 | { |
234 | writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET)); |
235 | jz_gpio_set_value(chip, gpio, value); |
236 | |
237 | return 0; |
238 | } |
239 | |
240 | static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
241 | { |
242 | writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR)); |
243 | |
244 | return 0; |
245 | } |
246 | |
247 | int jz_gpio_port_direction_input(int port, uint32_t mask) |
248 | { |
249 | writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR)); |
250 | |
251 | return 0; |
252 | } |
253 | EXPORT_SYMBOL(jz_gpio_port_direction_input); |
254 | |
255 | int jz_gpio_port_direction_output(int port, uint32_t mask) |
256 | { |
257 | writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET)); |
258 | |
259 | return 0; |
260 | } |
261 | EXPORT_SYMBOL(jz_gpio_port_direction_output); |
262 | |
263 | void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask) |
264 | { |
265 | writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR)); |
266 | writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET)); |
267 | } |
268 | EXPORT_SYMBOL(jz_gpio_port_set_value); |
269 | |
270 | uint32_t jz_gpio_port_get_value(int port, uint32_t mask) |
271 | { |
272 | uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN)); |
273 | |
274 | return value & mask; |
275 | } |
276 | EXPORT_SYMBOL(jz_gpio_port_get_value); |
277 | |
278 | |
279 | #define IRQ_TO_GPIO(irq) (irq - JZ4740_IRQ_GPIO(0)) |
280 | #define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f) |
281 | |
282 | #define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg) |
283 | |
284 | static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc) |
285 | { |
286 | uint32_t flag; |
287 | unsigned int gpio_irq; |
288 | unsigned int gpio_bank; |
289 | struct jz_gpio_chip *chip = get_irq_desc_data(desc); |
290 | |
291 | gpio_bank = JZ4740_IRQ_GPIO0 - irq; |
292 | |
293 | flag = readl(chip->base + JZ_REG_GPIO_FLAG); |
294 | |
295 | gpio_irq = ffs(flag) - 1; |
296 | |
297 | if (chip->edge_trigger_both & BIT(gpio_irq)) { |
298 | uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); |
299 | if (value & BIT(gpio_irq)) { |
300 | writel(BIT(gpio_irq), |
301 | chip->base + JZ_REG_GPIO_DIRECTION_CLEAR); |
302 | } else { |
303 | writel(BIT(gpio_irq), |
304 | chip->base + JZ_REG_GPIO_DIRECTION_SET); |
305 | } |
306 | } |
307 | |
308 | gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0); |
309 | |
310 | generic_handle_irq(gpio_irq); |
311 | }; |
312 | |
313 | static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg) |
314 | { |
315 | writel(IRQ_TO_BIT(irq), IRQ_TO_REG(irq, reg)); |
316 | } |
317 | |
318 | static void jz_gpio_irq_mask(unsigned int irq) |
319 | { |
320 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET); |
321 | }; |
322 | |
323 | static void jz_gpio_irq_unmask(unsigned int irq) |
324 | { |
325 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR); |
326 | }; |
327 | |
328 | |
329 | /* TODO: Check if function is gpio */ |
330 | static unsigned int jz_gpio_irq_startup(unsigned int irq) |
331 | { |
332 | struct irq_desc *desc = irq_to_desc(irq); |
333 | |
334 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET); |
335 | |
336 | desc->status &= ~IRQ_MASKED; |
337 | jz_gpio_irq_unmask(irq); |
338 | |
339 | return 0; |
340 | } |
341 | |
342 | static void jz_gpio_irq_shutdown(unsigned int irq) |
343 | { |
344 | struct irq_desc *desc = irq_to_desc(irq); |
345 | |
346 | jz_gpio_irq_mask(irq); |
347 | desc->status |= IRQ_MASKED; |
348 | |
349 | /* Set direction to input */ |
350 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); |
351 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR); |
352 | } |
353 | |
354 | static void jz_gpio_irq_ack(unsigned int irq) |
355 | { |
356 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR); |
357 | }; |
358 | |
359 | static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) |
360 | { |
361 | struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); |
362 | struct irq_desc *desc = irq_to_desc(irq); |
363 | |
364 | jz_gpio_irq_mask(irq); |
365 | |
366 | if (flow_type == IRQ_TYPE_EDGE_BOTH) { |
367 | uint32_t value = readl(IRQ_TO_REG(irq, JZ_REG_GPIO_PIN)); |
368 | if (value & IRQ_TO_BIT(irq)) |
369 | flow_type = IRQ_TYPE_EDGE_FALLING; |
370 | else |
371 | flow_type = IRQ_TYPE_EDGE_RISING; |
372 | chip->edge_trigger_both |= IRQ_TO_BIT(irq); |
373 | } else { |
374 | chip->edge_trigger_both &= ~IRQ_TO_BIT(irq); |
375 | } |
376 | |
377 | switch (flow_type) { |
378 | case IRQ_TYPE_EDGE_RISING: |
379 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); |
380 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); |
381 | break; |
382 | case IRQ_TYPE_EDGE_FALLING: |
383 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); |
384 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); |
385 | break; |
386 | case IRQ_TYPE_LEVEL_HIGH: |
387 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); |
388 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); |
389 | break; |
390 | case IRQ_TYPE_LEVEL_LOW: |
391 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); |
392 | jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); |
393 | break; |
394 | default: |
395 | return -EINVAL; |
396 | } |
397 | |
398 | if (!(desc->status & IRQ_MASKED)) |
399 | jz_gpio_irq_unmask(irq); |
400 | |
401 | return 0; |
402 | } |
403 | |
404 | static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on) |
405 | { |
406 | struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); |
407 | spin_lock(&chip->lock); |
408 | if (on) |
409 | chip->wakeup |= IRQ_TO_BIT(irq); |
410 | else |
411 | chip->wakeup &= ~IRQ_TO_BIT(irq); |
412 | spin_unlock(&chip->lock); |
413 | |
414 | set_irq_wake(chip->irq, !!(chip->wakeup)); |
415 | return 0; |
416 | } |
417 | |
418 | int gpio_to_irq(unsigned gpio) |
419 | { |
420 | return JZ4740_IRQ_GPIO(0) + gpio; |
421 | } |
422 | EXPORT_SYMBOL_GPL(gpio_to_irq); |
423 | |
424 | int irq_to_gpio(unsigned gpio) |
425 | { |
426 | return IRQ_TO_GPIO(gpio); |
427 | } |
428 | EXPORT_SYMBOL_GPL(irq_to_gpio); |
429 | |
430 | #define JZ4740_GPIO_CHIP(_bank) { \ |
431 | .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \ |
432 | .gpio_chip = { \ |
433 | .label = "Bank " # _bank, \ |
434 | .owner = THIS_MODULE, \ |
435 | .set = jz_gpio_set_value, \ |
436 | .get = jz_gpio_get_value, \ |
437 | .direction_output = jz_gpio_direction_output, \ |
438 | .direction_input = jz_gpio_direction_input, \ |
439 | .base = JZ4740_GPIO_BASE_ ## _bank, \ |
440 | .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ |
441 | }, \ |
442 | .irq_chip = { \ |
443 | .name = "GPIO Bank " # _bank, \ |
444 | .mask = jz_gpio_irq_mask, \ |
445 | .unmask = jz_gpio_irq_unmask, \ |
446 | .ack = jz_gpio_irq_ack, \ |
447 | .startup = jz_gpio_irq_startup, \ |
448 | .shutdown = jz_gpio_irq_shutdown, \ |
449 | .set_type = jz_gpio_irq_set_type, \ |
450 | .set_wake = jz_gpio_irq_set_wake, \ |
451 | }, \ |
452 | } |
453 | |
454 | static struct jz_gpio_chip jz4740_gpio_chips[] = { |
455 | JZ4740_GPIO_CHIP(A), |
456 | JZ4740_GPIO_CHIP(B), |
457 | JZ4740_GPIO_CHIP(C), |
458 | JZ4740_GPIO_CHIP(D), |
459 | }; |
460 | |
461 | static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev) |
462 | { |
463 | return container_of(dev, struct jz_gpio_chip, sysdev); |
464 | } |
465 | |
466 | static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state) |
467 | { |
468 | struct jz_gpio_chip *chip = sysdev_to_chip(dev); |
469 | |
470 | chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK); |
471 | writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET); |
472 | writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR); |
473 | |
474 | return 0; |
475 | } |
476 | |
477 | static int jz4740_gpio_resume(struct sys_device *dev) |
478 | { |
479 | struct jz_gpio_chip *chip = sysdev_to_chip(dev); |
480 | uint32_t mask = chip->suspend_mask; |
481 | |
482 | writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR); |
483 | writel(mask, chip->base + JZ_REG_GPIO_MASK_SET); |
484 | |
485 | return 0; |
486 | } |
487 | |
488 | static struct sysdev_class jz4740_gpio_sysdev_class = { |
489 | .name = "gpio", |
490 | .suspend = jz4740_gpio_suspend, |
491 | .resume = jz4740_gpio_resume, |
492 | }; |
493 | |
494 | static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) |
495 | { |
496 | int ret, irq; |
497 | |
498 | chip->sysdev.id = id; |
499 | chip->sysdev.cls = &jz4740_gpio_sysdev_class; |
500 | ret = sysdev_register(&chip->sysdev); |
501 | |
502 | if (ret) |
503 | return ret; |
504 | |
505 | spin_lock_init(&chip->lock); |
506 | |
507 | chip->base = ioremap(CPHYSADDR(JZ4740_GPIO_BASE_ADDR) + (id * 0x100), 0x100); |
508 | |
509 | gpiochip_add(&chip->gpio_chip); |
510 | |
511 | chip->irq = JZ4740_IRQ_INTC_GPIO(id); |
512 | set_irq_data(chip->irq, chip); |
513 | set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); |
514 | |
515 | for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { |
516 | set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq); |
517 | set_irq_chip_data(irq, chip); |
518 | } |
519 | |
520 | return 0; |
521 | } |
522 | |
523 | int __init jz_gpiolib_init(void) |
524 | { |
525 | unsigned int i; |
526 | int ret; |
527 | |
528 | ret = sysdev_class_register(&jz4740_gpio_sysdev_class); |
529 | if (ret) |
530 | return ret; |
531 | |
532 | for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i) { |
533 | jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i); |
534 | } |
535 | |
536 | printk(KERN_INFO "JZ4740 GPIO initalized\n"); |
537 | |
538 | return 0; |
539 | } |
540 | |
541 | #ifdef CONFIG_DEBUG_FS |
542 | |
543 | static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip, |
544 | const char *name, unsigned int reg) |
545 | { |
546 | seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg)); |
547 | } |
548 | |
549 | |
550 | static int gpio_regs_show(struct seq_file *s, void *unused) |
551 | { |
552 | struct jz_gpio_chip *chip = jz4740_gpio_chips; |
553 | int i; |
554 | |
555 | for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) { |
556 | seq_printf(s, "GPIO %d: \n", i); |
557 | gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN); |
558 | gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA); |
559 | gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK); |
560 | gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL); |
561 | gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC); |
562 | gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT); |
563 | gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION); |
564 | gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER); |
565 | gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG); |
566 | } |
567 | |
568 | return 0; |
569 | } |
570 | |
571 | static int gpio_regs_open(struct inode *inode, struct file *file) |
572 | { |
573 | return single_open(file, gpio_regs_show, NULL); |
574 | } |
575 | |
576 | static const struct file_operations gpio_regs_operations = { |
577 | .open = gpio_regs_open, |
578 | .read = seq_read, |
579 | .llseek = seq_lseek, |
580 | .release = single_release, |
581 | }; |
582 | |
583 | static int __init gpio_debugfs_init(void) |
584 | { |
585 | (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO, |
586 | NULL, NULL, &gpio_regs_operations); |
587 | return 0; |
588 | } |
589 | subsys_initcall(gpio_debugfs_init); |
590 | |
591 | #endif |
592 |
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