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Source at commit 304ab16a5603dcb9d135fcba57e23a8413de54b1 created 13 years 11 months ago. By Lars-Peter Clausen, Add jz4740 serial driver | |
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1 | /* |
2 | * linux/drivers/char/8250.c |
3 | * |
4 | * Driver for 8250/16550-type serial ports |
5 | * |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
7 | * |
8 | * Copyright (C) 2001 Russell King. |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by |
12 | * the Free Software Foundation; either version 2 of the License, or |
13 | * (at your option) any later version. |
14 | * |
15 | * A note about mapbase / membase |
16 | * |
17 | * mapbase is the physical address of the IO port. |
18 | * membase is an 'ioremapped' cookie. |
19 | */ |
20 | |
21 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
22 | #define SUPPORT_SYSRQ |
23 | #endif |
24 | |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> |
27 | #include <linux/ioport.h> |
28 | #include <linux/init.h> |
29 | #include <linux/console.h> |
30 | #include <linux/sysrq.h> |
31 | #include <linux/delay.h> |
32 | #include <linux/platform_device.h> |
33 | #include <linux/tty.h> |
34 | #include <linux/tty_flip.h> |
35 | #include <linux/serial_reg.h> |
36 | #include <linux/serial_core.h> |
37 | #include <linux/serial.h> |
38 | #include <linux/serial_8250.h> |
39 | #include <linux/nmi.h> |
40 | #include <linux/mutex.h> |
41 | #include <linux/slab.h> |
42 | |
43 | #include <asm/io.h> |
44 | #include <asm/irq.h> |
45 | |
46 | #include "8250.h" |
47 | |
48 | #ifdef CONFIG_SPARC |
49 | #include "suncore.h" |
50 | #endif |
51 | |
52 | /* |
53 | * Configuration: |
54 | * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option |
55 | * is unsafe when used on edge-triggered interrupts. |
56 | */ |
57 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
58 | |
59 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; |
60 | |
61 | static struct uart_driver serial8250_reg; |
62 | |
63 | static int serial_index(struct uart_port *port) |
64 | { |
65 | return (serial8250_reg.minor - 64) + port->line; |
66 | } |
67 | |
68 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ |
69 | |
70 | /* |
71 | * Debugging. |
72 | */ |
73 | #if 0 |
74 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) |
75 | #else |
76 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) |
77 | #endif |
78 | |
79 | #if 0 |
80 | #define DEBUG_INTR(fmt...) printk(fmt) |
81 | #else |
82 | #define DEBUG_INTR(fmt...) do { } while (0) |
83 | #endif |
84 | |
85 | #define PASS_LIMIT 256 |
86 | |
87 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
88 | |
89 | |
90 | /* |
91 | * We default to IRQ0 for the "no irq" hack. Some |
92 | * machine types want others as well - they're free |
93 | * to redefine this in their header file. |
94 | */ |
95 | #define is_real_interrupt(irq) ((irq) != 0) |
96 | |
97 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
98 | #define CONFIG_SERIAL_DETECT_IRQ 1 |
99 | #endif |
100 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
101 | #define CONFIG_SERIAL_MANY_PORTS 1 |
102 | #endif |
103 | |
104 | /* |
105 | * HUB6 is always on. This will be removed once the header |
106 | * files have been cleaned. |
107 | */ |
108 | #define CONFIG_HUB6 1 |
109 | |
110 | #include <asm/serial.h> |
111 | /* |
112 | * SERIAL_PORT_DFNS tells us about built-in ports that have no |
113 | * standard enumeration mechanism. Platforms that can find all |
114 | * serial ports via mechanisms like ACPI or PCI need not supply it. |
115 | */ |
116 | #ifndef SERIAL_PORT_DFNS |
117 | #define SERIAL_PORT_DFNS |
118 | #endif |
119 | |
120 | static const struct old_serial_port old_serial_port[] = { |
121 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ |
122 | }; |
123 | |
124 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
125 | |
126 | #ifdef CONFIG_SERIAL_8250_RSA |
127 | |
128 | #define PORT_RSA_MAX 4 |
129 | static unsigned long probe_rsa[PORT_RSA_MAX]; |
130 | static unsigned int probe_rsa_count; |
131 | #endif /* CONFIG_SERIAL_8250_RSA */ |
132 | |
133 | struct uart_8250_port { |
134 | struct uart_port port; |
135 | struct timer_list timer; /* "no irq" timer */ |
136 | struct list_head list; /* ports on this IRQ */ |
137 | unsigned short capabilities; /* port capabilities */ |
138 | unsigned short bugs; /* port bugs */ |
139 | unsigned int tx_loadsz; /* transmit fifo load size */ |
140 | unsigned char acr; |
141 | unsigned char ier; |
142 | unsigned char lcr; |
143 | unsigned char mcr; |
144 | unsigned char mcr_mask; /* mask of user bits */ |
145 | unsigned char mcr_force; /* mask of forced bits */ |
146 | unsigned char cur_iotype; /* Running I/O type */ |
147 | |
148 | /* |
149 | * Some bits in registers are cleared on a read, so they must |
150 | * be saved whenever the register is read but the bits will not |
151 | * be immediately processed. |
152 | */ |
153 | #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS |
154 | unsigned char lsr_saved_flags; |
155 | #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA |
156 | unsigned char msr_saved_flags; |
157 | |
158 | /* |
159 | * We provide a per-port pm hook. |
160 | */ |
161 | void (*pm)(struct uart_port *port, |
162 | unsigned int state, unsigned int old); |
163 | }; |
164 | |
165 | struct irq_info { |
166 | struct hlist_node node; |
167 | int irq; |
168 | spinlock_t lock; /* Protects list not the hash */ |
169 | struct list_head *head; |
170 | }; |
171 | |
172 | #define NR_IRQ_HASH 32 /* Can be adjusted later */ |
173 | static struct hlist_head irq_lists[NR_IRQ_HASH]; |
174 | static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ |
175 | |
176 | /* |
177 | * Here we define the default xmit fifo size used for each type of UART. |
178 | */ |
179 | static const struct serial8250_config uart_config[] = { |
180 | [PORT_UNKNOWN] = { |
181 | .name = "unknown", |
182 | .fifo_size = 1, |
183 | .tx_loadsz = 1, |
184 | }, |
185 | [PORT_8250] = { |
186 | .name = "8250", |
187 | .fifo_size = 1, |
188 | .tx_loadsz = 1, |
189 | }, |
190 | [PORT_16450] = { |
191 | .name = "16450", |
192 | .fifo_size = 1, |
193 | .tx_loadsz = 1, |
194 | }, |
195 | [PORT_16550] = { |
196 | .name = "16550", |
197 | .fifo_size = 1, |
198 | .tx_loadsz = 1, |
199 | }, |
200 | [PORT_16550A] = { |
201 | .name = "16550A", |
202 | .fifo_size = 16, |
203 | .tx_loadsz = 8, |
204 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
205 | .flags = UART_CAP_FIFO, |
206 | }, |
207 | [PORT_CIRRUS] = { |
208 | .name = "Cirrus", |
209 | .fifo_size = 1, |
210 | .tx_loadsz = 1, |
211 | }, |
212 | [PORT_16650] = { |
213 | .name = "ST16650", |
214 | .fifo_size = 1, |
215 | .tx_loadsz = 1, |
216 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
217 | }, |
218 | [PORT_16650V2] = { |
219 | .name = "ST16650V2", |
220 | .fifo_size = 32, |
221 | .tx_loadsz = 16, |
222 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | |
223 | UART_FCR_T_TRIG_00, |
224 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
225 | }, |
226 | [PORT_16750] = { |
227 | .name = "TI16750", |
228 | .fifo_size = 64, |
229 | .tx_loadsz = 64, |
230 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | |
231 | UART_FCR7_64BYTE, |
232 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, |
233 | }, |
234 | [PORT_STARTECH] = { |
235 | .name = "Startech", |
236 | .fifo_size = 1, |
237 | .tx_loadsz = 1, |
238 | }, |
239 | [PORT_16C950] = { |
240 | .name = "16C950/954", |
241 | .fifo_size = 128, |
242 | .tx_loadsz = 128, |
243 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
244 | .flags = UART_CAP_FIFO, |
245 | }, |
246 | [PORT_16654] = { |
247 | .name = "ST16654", |
248 | .fifo_size = 64, |
249 | .tx_loadsz = 32, |
250 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | |
251 | UART_FCR_T_TRIG_10, |
252 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
253 | }, |
254 | [PORT_16850] = { |
255 | .name = "XR16850", |
256 | .fifo_size = 128, |
257 | .tx_loadsz = 128, |
258 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
259 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
260 | }, |
261 | [PORT_RSA] = { |
262 | .name = "RSA", |
263 | .fifo_size = 2048, |
264 | .tx_loadsz = 2048, |
265 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, |
266 | .flags = UART_CAP_FIFO, |
267 | }, |
268 | [PORT_NS16550A] = { |
269 | .name = "NS16550A", |
270 | .fifo_size = 16, |
271 | .tx_loadsz = 16, |
272 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
273 | .flags = UART_CAP_FIFO | UART_NATSEMI, |
274 | }, |
275 | [PORT_XSCALE] = { |
276 | .name = "XScale", |
277 | .fifo_size = 32, |
278 | .tx_loadsz = 32, |
279 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
280 | .flags = UART_CAP_FIFO | UART_CAP_UUE, |
281 | }, |
282 | [PORT_RM9000] = { |
283 | .name = "RM9000", |
284 | .fifo_size = 16, |
285 | .tx_loadsz = 16, |
286 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
287 | .flags = UART_CAP_FIFO, |
288 | }, |
289 | [PORT_OCTEON] = { |
290 | .name = "OCTEON", |
291 | .fifo_size = 64, |
292 | .tx_loadsz = 64, |
293 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, |
294 | .flags = UART_CAP_FIFO, |
295 | }, |
296 | [PORT_AR7] = { |
297 | .name = "AR7", |
298 | .fifo_size = 16, |
299 | .tx_loadsz = 16, |
300 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, |
301 | .flags = UART_CAP_FIFO | UART_CAP_AFE, |
302 | }, |
303 | }; |
304 | |
305 | #if defined (CONFIG_SERIAL_8250_AU1X00) |
306 | |
307 | /* Au1x00 UART hardware has a weird register layout */ |
308 | static const u8 au_io_in_map[] = { |
309 | [UART_RX] = 0, |
310 | [UART_IER] = 2, |
311 | [UART_IIR] = 3, |
312 | [UART_LCR] = 5, |
313 | [UART_MCR] = 6, |
314 | [UART_LSR] = 7, |
315 | [UART_MSR] = 8, |
316 | }; |
317 | |
318 | static const u8 au_io_out_map[] = { |
319 | [UART_TX] = 1, |
320 | [UART_IER] = 2, |
321 | [UART_FCR] = 4, |
322 | [UART_LCR] = 5, |
323 | [UART_MCR] = 6, |
324 | }; |
325 | |
326 | /* sane hardware needs no mapping */ |
327 | static inline int map_8250_in_reg(struct uart_port *p, int offset) |
328 | { |
329 | if (p->iotype != UPIO_AU) |
330 | return offset; |
331 | return au_io_in_map[offset]; |
332 | } |
333 | |
334 | static inline int map_8250_out_reg(struct uart_port *p, int offset) |
335 | { |
336 | if (p->iotype != UPIO_AU) |
337 | return offset; |
338 | return au_io_out_map[offset]; |
339 | } |
340 | |
341 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
342 | |
343 | static const u8 |
344 | regmap_in[8] = { |
345 | [UART_RX] = 0x00, |
346 | [UART_IER] = 0x0c, |
347 | [UART_IIR] = 0x14, |
348 | [UART_LCR] = 0x1c, |
349 | [UART_MCR] = 0x20, |
350 | [UART_LSR] = 0x24, |
351 | [UART_MSR] = 0x28, |
352 | [UART_SCR] = 0x2c |
353 | }, |
354 | regmap_out[8] = { |
355 | [UART_TX] = 0x04, |
356 | [UART_IER] = 0x0c, |
357 | [UART_FCR] = 0x18, |
358 | [UART_LCR] = 0x1c, |
359 | [UART_MCR] = 0x20, |
360 | [UART_LSR] = 0x24, |
361 | [UART_MSR] = 0x28, |
362 | [UART_SCR] = 0x2c |
363 | }; |
364 | |
365 | static inline int map_8250_in_reg(struct uart_port *p, int offset) |
366 | { |
367 | if (p->iotype != UPIO_RM9000) |
368 | return offset; |
369 | return regmap_in[offset]; |
370 | } |
371 | |
372 | static inline int map_8250_out_reg(struct uart_port *p, int offset) |
373 | { |
374 | if (p->iotype != UPIO_RM9000) |
375 | return offset; |
376 | return regmap_out[offset]; |
377 | } |
378 | |
379 | #else |
380 | |
381 | /* sane hardware needs no mapping */ |
382 | #define map_8250_in_reg(up, offset) (offset) |
383 | #define map_8250_out_reg(up, offset) (offset) |
384 | |
385 | #endif |
386 | |
387 | static unsigned int hub6_serial_in(struct uart_port *p, int offset) |
388 | { |
389 | offset = map_8250_in_reg(p, offset) << p->regshift; |
390 | outb(p->hub6 - 1 + offset, p->iobase); |
391 | return inb(p->iobase + 1); |
392 | } |
393 | |
394 | static void hub6_serial_out(struct uart_port *p, int offset, int value) |
395 | { |
396 | offset = map_8250_out_reg(p, offset) << p->regshift; |
397 | outb(p->hub6 - 1 + offset, p->iobase); |
398 | outb(value, p->iobase + 1); |
399 | } |
400 | |
401 | static unsigned int mem_serial_in(struct uart_port *p, int offset) |
402 | { |
403 | offset = map_8250_in_reg(p, offset) << p->regshift; |
404 | return readb(p->membase + offset); |
405 | } |
406 | |
407 | static void mem_serial_out(struct uart_port *p, int offset, int value) |
408 | { |
409 | offset = map_8250_out_reg(p, offset) << p->regshift; |
410 | #if defined(CONFIG_JZSOC) |
411 | if (offset == (UART_FCR << p->regshift)) |
412 | value |= 0x10; /* set FCR.UUE */ |
413 | #endif |
414 | writeb(value, p->membase + offset); |
415 | } |
416 | |
417 | static void mem32_serial_out(struct uart_port *p, int offset, int value) |
418 | { |
419 | offset = map_8250_out_reg(p, offset) << p->regshift; |
420 | writel(value, p->membase + offset); |
421 | } |
422 | |
423 | static unsigned int mem32_serial_in(struct uart_port *p, int offset) |
424 | { |
425 | offset = map_8250_in_reg(p, offset) << p->regshift; |
426 | return readl(p->membase + offset); |
427 | } |
428 | |
429 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
430 | static unsigned int au_serial_in(struct uart_port *p, int offset) |
431 | { |
432 | offset = map_8250_in_reg(p, offset) << p->regshift; |
433 | return __raw_readl(p->membase + offset); |
434 | } |
435 | |
436 | static void au_serial_out(struct uart_port *p, int offset, int value) |
437 | { |
438 | offset = map_8250_out_reg(p, offset) << p->regshift; |
439 | __raw_writel(value, p->membase + offset); |
440 | } |
441 | #endif |
442 | |
443 | static unsigned int tsi_serial_in(struct uart_port *p, int offset) |
444 | { |
445 | unsigned int tmp; |
446 | offset = map_8250_in_reg(p, offset) << p->regshift; |
447 | if (offset == UART_IIR) { |
448 | tmp = readl(p->membase + (UART_IIR & ~3)); |
449 | return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */ |
450 | } else |
451 | return readb(p->membase + offset); |
452 | } |
453 | |
454 | static void tsi_serial_out(struct uart_port *p, int offset, int value) |
455 | { |
456 | offset = map_8250_out_reg(p, offset) << p->regshift; |
457 | if (!((offset == UART_IER) && (value & UART_IER_UUE))) |
458 | writeb(value, p->membase + offset); |
459 | } |
460 | |
461 | static void dwapb_serial_out(struct uart_port *p, int offset, int value) |
462 | { |
463 | int save_offset = offset; |
464 | offset = map_8250_out_reg(p, offset) << p->regshift; |
465 | /* Save the LCR value so it can be re-written when a |
466 | * Busy Detect interrupt occurs. */ |
467 | if (save_offset == UART_LCR) { |
468 | struct uart_8250_port *up = (struct uart_8250_port *)p; |
469 | up->lcr = value; |
470 | } |
471 | writeb(value, p->membase + offset); |
472 | /* Read the IER to ensure any interrupt is cleared before |
473 | * returning from ISR. */ |
474 | if (save_offset == UART_TX || save_offset == UART_IER) |
475 | value = p->serial_in(p, UART_IER); |
476 | } |
477 | |
478 | static unsigned int io_serial_in(struct uart_port *p, int offset) |
479 | { |
480 | offset = map_8250_in_reg(p, offset) << p->regshift; |
481 | return inb(p->iobase + offset); |
482 | } |
483 | |
484 | static void io_serial_out(struct uart_port *p, int offset, int value) |
485 | { |
486 | offset = map_8250_out_reg(p, offset) << p->regshift; |
487 | outb(value, p->iobase + offset); |
488 | } |
489 | |
490 | static void set_io_from_upio(struct uart_port *p) |
491 | { |
492 | struct uart_8250_port *up = (struct uart_8250_port *)p; |
493 | switch (p->iotype) { |
494 | case UPIO_HUB6: |
495 | p->serial_in = hub6_serial_in; |
496 | p->serial_out = hub6_serial_out; |
497 | break; |
498 | |
499 | case UPIO_MEM: |
500 | p->serial_in = mem_serial_in; |
501 | p->serial_out = mem_serial_out; |
502 | break; |
503 | |
504 | case UPIO_RM9000: |
505 | case UPIO_MEM32: |
506 | p->serial_in = mem32_serial_in; |
507 | p->serial_out = mem32_serial_out; |
508 | break; |
509 | |
510 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
511 | case UPIO_AU: |
512 | p->serial_in = au_serial_in; |
513 | p->serial_out = au_serial_out; |
514 | break; |
515 | #endif |
516 | case UPIO_TSI: |
517 | p->serial_in = tsi_serial_in; |
518 | p->serial_out = tsi_serial_out; |
519 | break; |
520 | |
521 | case UPIO_DWAPB: |
522 | p->serial_in = mem_serial_in; |
523 | p->serial_out = dwapb_serial_out; |
524 | break; |
525 | |
526 | default: |
527 | p->serial_in = io_serial_in; |
528 | p->serial_out = io_serial_out; |
529 | break; |
530 | } |
531 | /* Remember loaded iotype */ |
532 | up->cur_iotype = p->iotype; |
533 | } |
534 | |
535 | static void |
536 | serial_out_sync(struct uart_8250_port *up, int offset, int value) |
537 | { |
538 | struct uart_port *p = &up->port; |
539 | switch (p->iotype) { |
540 | case UPIO_MEM: |
541 | case UPIO_MEM32: |
542 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
543 | case UPIO_AU: |
544 | #endif |
545 | case UPIO_DWAPB: |
546 | p->serial_out(p, offset, value); |
547 | p->serial_in(p, UART_LCR); /* safe, no side-effects */ |
548 | break; |
549 | default: |
550 | p->serial_out(p, offset, value); |
551 | } |
552 | } |
553 | |
554 | #define serial_in(up, offset) \ |
555 | (up->port.serial_in(&(up)->port, (offset))) |
556 | #define serial_out(up, offset, value) \ |
557 | (up->port.serial_out(&(up)->port, (offset), (value))) |
558 | /* |
559 | * We used to support using pause I/O for certain machines. We |
560 | * haven't supported this for a while, but just in case it's badly |
561 | * needed for certain old 386 machines, I've left these #define's |
562 | * in.... |
563 | */ |
564 | #define serial_inp(up, offset) serial_in(up, offset) |
565 | #define serial_outp(up, offset, value) serial_out(up, offset, value) |
566 | |
567 | /* Uart divisor latch read */ |
568 | static inline int _serial_dl_read(struct uart_8250_port *up) |
569 | { |
570 | return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; |
571 | } |
572 | |
573 | /* Uart divisor latch write */ |
574 | static inline void _serial_dl_write(struct uart_8250_port *up, int value) |
575 | { |
576 | serial_outp(up, UART_DLL, value & 0xff); |
577 | serial_outp(up, UART_DLM, value >> 8 & 0xff); |
578 | } |
579 | |
580 | #if defined(CONFIG_SERIAL_8250_AU1X00) |
581 | /* Au1x00 haven't got a standard divisor latch */ |
582 | static int serial_dl_read(struct uart_8250_port *up) |
583 | { |
584 | if (up->port.iotype == UPIO_AU) |
585 | return __raw_readl(up->port.membase + 0x28); |
586 | else |
587 | return _serial_dl_read(up); |
588 | } |
589 | |
590 | static void serial_dl_write(struct uart_8250_port *up, int value) |
591 | { |
592 | if (up->port.iotype == UPIO_AU) |
593 | __raw_writel(value, up->port.membase + 0x28); |
594 | else |
595 | _serial_dl_write(up, value); |
596 | } |
597 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
598 | static int serial_dl_read(struct uart_8250_port *up) |
599 | { |
600 | return (up->port.iotype == UPIO_RM9000) ? |
601 | (((__raw_readl(up->port.membase + 0x10) << 8) | |
602 | (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) : |
603 | _serial_dl_read(up); |
604 | } |
605 | |
606 | static void serial_dl_write(struct uart_8250_port *up, int value) |
607 | { |
608 | if (up->port.iotype == UPIO_RM9000) { |
609 | __raw_writel(value, up->port.membase + 0x08); |
610 | __raw_writel(value >> 8, up->port.membase + 0x10); |
611 | } else { |
612 | _serial_dl_write(up, value); |
613 | } |
614 | } |
615 | #else |
616 | #define serial_dl_read(up) _serial_dl_read(up) |
617 | #define serial_dl_write(up, value) _serial_dl_write(up, value) |
618 | #endif |
619 | |
620 | /* |
621 | * For the 16C950 |
622 | */ |
623 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) |
624 | { |
625 | serial_out(up, UART_SCR, offset); |
626 | serial_out(up, UART_ICR, value); |
627 | } |
628 | |
629 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) |
630 | { |
631 | unsigned int value; |
632 | |
633 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); |
634 | serial_out(up, UART_SCR, offset); |
635 | value = serial_in(up, UART_ICR); |
636 | serial_icr_write(up, UART_ACR, up->acr); |
637 | |
638 | return value; |
639 | } |
640 | |
641 | /* |
642 | * FIFO support. |
643 | */ |
644 | static void serial8250_clear_fifos(struct uart_8250_port *p) |
645 | { |
646 | if (p->capabilities & UART_CAP_FIFO) { |
647 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); |
648 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | |
649 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
650 | serial_outp(p, UART_FCR, 0); |
651 | } |
652 | } |
653 | |
654 | /* |
655 | * IER sleep support. UARTs which have EFRs need the "extended |
656 | * capability" bit enabled. Note that on XR16C850s, we need to |
657 | * reset LCR to write to IER. |
658 | */ |
659 | static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) |
660 | { |
661 | if (p->capabilities & UART_CAP_SLEEP) { |
662 | if (p->capabilities & UART_CAP_EFR) { |
663 | serial_outp(p, UART_LCR, 0xBF); |
664 | serial_outp(p, UART_EFR, UART_EFR_ECB); |
665 | serial_outp(p, UART_LCR, 0); |
666 | } |
667 | serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); |
668 | if (p->capabilities & UART_CAP_EFR) { |
669 | serial_outp(p, UART_LCR, 0xBF); |
670 | serial_outp(p, UART_EFR, 0); |
671 | serial_outp(p, UART_LCR, 0); |
672 | } |
673 | } |
674 | } |
675 | |
676 | #ifdef CONFIG_SERIAL_8250_RSA |
677 | /* |
678 | * Attempts to turn on the RSA FIFO. Returns zero on failure. |
679 | * We set the port uart clock rate if we succeed. |
680 | */ |
681 | static int __enable_rsa(struct uart_8250_port *up) |
682 | { |
683 | unsigned char mode; |
684 | int result; |
685 | |
686 | mode = serial_inp(up, UART_RSA_MSR); |
687 | result = mode & UART_RSA_MSR_FIFO; |
688 | |
689 | if (!result) { |
690 | serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); |
691 | mode = serial_inp(up, UART_RSA_MSR); |
692 | result = mode & UART_RSA_MSR_FIFO; |
693 | } |
694 | |
695 | if (result) |
696 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; |
697 | |
698 | return result; |
699 | } |
700 | |
701 | static void enable_rsa(struct uart_8250_port *up) |
702 | { |
703 | if (up->port.type == PORT_RSA) { |
704 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { |
705 | spin_lock_irq(&up->port.lock); |
706 | __enable_rsa(up); |
707 | spin_unlock_irq(&up->port.lock); |
708 | } |
709 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) |
710 | serial_outp(up, UART_RSA_FRR, 0); |
711 | } |
712 | } |
713 | |
714 | /* |
715 | * Attempts to turn off the RSA FIFO. Returns zero on failure. |
716 | * It is unknown why interrupts were disabled in here. However, |
717 | * the caller is expected to preserve this behaviour by grabbing |
718 | * the spinlock before calling this function. |
719 | */ |
720 | static void disable_rsa(struct uart_8250_port *up) |
721 | { |
722 | unsigned char mode; |
723 | int result; |
724 | |
725 | if (up->port.type == PORT_RSA && |
726 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { |
727 | spin_lock_irq(&up->port.lock); |
728 | |
729 | mode = serial_inp(up, UART_RSA_MSR); |
730 | result = !(mode & UART_RSA_MSR_FIFO); |
731 | |
732 | if (!result) { |
733 | serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); |
734 | mode = serial_inp(up, UART_RSA_MSR); |
735 | result = !(mode & UART_RSA_MSR_FIFO); |
736 | } |
737 | |
738 | if (result) |
739 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; |
740 | spin_unlock_irq(&up->port.lock); |
741 | } |
742 | } |
743 | #endif /* CONFIG_SERIAL_8250_RSA */ |
744 | |
745 | /* |
746 | * This is a quickie test to see how big the FIFO is. |
747 | * It doesn't work at all the time, more's the pity. |
748 | */ |
749 | static int size_fifo(struct uart_8250_port *up) |
750 | { |
751 | unsigned char old_fcr, old_mcr, old_lcr; |
752 | unsigned short old_dl; |
753 | int count; |
754 | |
755 | old_lcr = serial_inp(up, UART_LCR); |
756 | serial_outp(up, UART_LCR, 0); |
757 | old_fcr = serial_inp(up, UART_FCR); |
758 | old_mcr = serial_inp(up, UART_MCR); |
759 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | |
760 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
761 | serial_outp(up, UART_MCR, UART_MCR_LOOP); |
762 | serial_outp(up, UART_LCR, UART_LCR_DLAB); |
763 | old_dl = serial_dl_read(up); |
764 | serial_dl_write(up, 0x0001); |
765 | serial_outp(up, UART_LCR, 0x03); |
766 | for (count = 0; count < 256; count++) |
767 | serial_outp(up, UART_TX, count); |
768 | mdelay(20);/* FIXME - schedule_timeout */ |
769 | for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && |
770 | (count < 256); count++) |
771 | serial_inp(up, UART_RX); |
772 | serial_outp(up, UART_FCR, old_fcr); |
773 | serial_outp(up, UART_MCR, old_mcr); |
774 | serial_outp(up, UART_LCR, UART_LCR_DLAB); |
775 | serial_dl_write(up, old_dl); |
776 | serial_outp(up, UART_LCR, old_lcr); |
777 | |
778 | return count; |
779 | } |
780 | |
781 | /* |
782 | * Read UART ID using the divisor method - set DLL and DLM to zero |
783 | * and the revision will be in DLL and device type in DLM. We |
784 | * preserve the device state across this. |
785 | */ |
786 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) |
787 | { |
788 | unsigned char old_dll, old_dlm, old_lcr; |
789 | unsigned int id; |
790 | |
791 | old_lcr = serial_inp(p, UART_LCR); |
792 | serial_outp(p, UART_LCR, UART_LCR_DLAB); |
793 | |
794 | old_dll = serial_inp(p, UART_DLL); |
795 | old_dlm = serial_inp(p, UART_DLM); |
796 | |
797 | serial_outp(p, UART_DLL, 0); |
798 | serial_outp(p, UART_DLM, 0); |
799 | |
800 | id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; |
801 | |
802 | serial_outp(p, UART_DLL, old_dll); |
803 | serial_outp(p, UART_DLM, old_dlm); |
804 | serial_outp(p, UART_LCR, old_lcr); |
805 | |
806 | return id; |
807 | } |
808 | |
809 | /* |
810 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. |
811 | * When this function is called we know it is at least a StarTech |
812 | * 16650 V2, but it might be one of several StarTech UARTs, or one of |
813 | * its clones. (We treat the broken original StarTech 16650 V1 as a |
814 | * 16550, and why not? Startech doesn't seem to even acknowledge its |
815 | * existence.) |
816 | * |
817 | * What evil have men's minds wrought... |
818 | */ |
819 | static void autoconfig_has_efr(struct uart_8250_port *up) |
820 | { |
821 | unsigned int id1, id2, id3, rev; |
822 | |
823 | /* |
824 | * Everything with an EFR has SLEEP |
825 | */ |
826 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; |
827 | |
828 | /* |
829 | * First we check to see if it's an Oxford Semiconductor UART. |
830 | * |
831 | * If we have to do this here because some non-National |
832 | * Semiconductor clone chips lock up if you try writing to the |
833 | * LSR register (which serial_icr_read does) |
834 | */ |
835 | |
836 | /* |
837 | * Check for Oxford Semiconductor 16C950. |
838 | * |
839 | * EFR [4] must be set else this test fails. |
840 | * |
841 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) |
842 | * claims that it's needed for 952 dual UART's (which are not |
843 | * recommended for new designs). |
844 | */ |
845 | up->acr = 0; |
846 | serial_out(up, UART_LCR, 0xBF); |
847 | serial_out(up, UART_EFR, UART_EFR_ECB); |
848 | serial_out(up, UART_LCR, 0x00); |
849 | id1 = serial_icr_read(up, UART_ID1); |
850 | id2 = serial_icr_read(up, UART_ID2); |
851 | id3 = serial_icr_read(up, UART_ID3); |
852 | rev = serial_icr_read(up, UART_REV); |
853 | |
854 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); |
855 | |
856 | if (id1 == 0x16 && id2 == 0xC9 && |
857 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { |
858 | up->port.type = PORT_16C950; |
859 | |
860 | /* |
861 | * Enable work around for the Oxford Semiconductor 952 rev B |
862 | * chip which causes it to seriously miscalculate baud rates |
863 | * when DLL is 0. |
864 | */ |
865 | if (id3 == 0x52 && rev == 0x01) |
866 | up->bugs |= UART_BUG_QUOT; |
867 | return; |
868 | } |
869 | |
870 | /* |
871 | * We check for a XR16C850 by setting DLL and DLM to 0, and then |
872 | * reading back DLL and DLM. The chip type depends on the DLM |
873 | * value read back: |
874 | * 0x10 - XR16C850 and the DLL contains the chip revision. |
875 | * 0x12 - XR16C2850. |
876 | * 0x14 - XR16C854. |
877 | */ |
878 | id1 = autoconfig_read_divisor_id(up); |
879 | DEBUG_AUTOCONF("850id=%04x ", id1); |
880 | |
881 | id2 = id1 >> 8; |
882 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { |
883 | up->port.type = PORT_16850; |
884 | return; |
885 | } |
886 | |
887 | /* |
888 | * It wasn't an XR16C850. |
889 | * |
890 | * We distinguish between the '654 and the '650 by counting |
891 | * how many bytes are in the FIFO. I'm using this for now, |
892 | * since that's the technique that was sent to me in the |
893 | * serial driver update, but I'm not convinced this works. |
894 | * I've had problems doing this in the past. -TYT |
895 | */ |
896 | if (size_fifo(up) == 64) |
897 | up->port.type = PORT_16654; |
898 | else |
899 | up->port.type = PORT_16650V2; |
900 | } |
901 | |
902 | /* |
903 | * We detected a chip without a FIFO. Only two fall into |
904 | * this category - the original 8250 and the 16450. The |
905 | * 16450 has a scratch register (accessible with LCR=0) |
906 | */ |
907 | static void autoconfig_8250(struct uart_8250_port *up) |
908 | { |
909 | unsigned char scratch, status1, status2; |
910 | |
911 | up->port.type = PORT_8250; |
912 | |
913 | scratch = serial_in(up, UART_SCR); |
914 | serial_outp(up, UART_SCR, 0xa5); |
915 | status1 = serial_in(up, UART_SCR); |
916 | serial_outp(up, UART_SCR, 0x5a); |
917 | status2 = serial_in(up, UART_SCR); |
918 | serial_outp(up, UART_SCR, scratch); |
919 | |
920 | if (status1 == 0xa5 && status2 == 0x5a) |
921 | up->port.type = PORT_16450; |
922 | } |
923 | |
924 | static int broken_efr(struct uart_8250_port *up) |
925 | { |
926 | /* |
927 | * Exar ST16C2550 "A2" devices incorrectly detect as |
928 | * having an EFR, and report an ID of 0x0201. See |
929 | * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf |
930 | */ |
931 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) |
932 | return 1; |
933 | |
934 | return 0; |
935 | } |
936 | |
937 | /* |
938 | * We know that the chip has FIFOs. Does it have an EFR? The |
939 | * EFR is located in the same register position as the IIR and |
940 | * we know the top two bits of the IIR are currently set. The |
941 | * EFR should contain zero. Try to read the EFR. |
942 | */ |
943 | static void autoconfig_16550a(struct uart_8250_port *up) |
944 | { |
945 | unsigned char status1, status2; |
946 | unsigned int iersave; |
947 | |
948 | up->port.type = PORT_16550A; |
949 | up->capabilities |= UART_CAP_FIFO; |
950 | |
951 | /* |
952 | * Check for presence of the EFR when DLAB is set. |
953 | * Only ST16C650V1 UARTs pass this test. |
954 | */ |
955 | serial_outp(up, UART_LCR, UART_LCR_DLAB); |
956 | if (serial_in(up, UART_EFR) == 0) { |
957 | serial_outp(up, UART_EFR, 0xA8); |
958 | if (serial_in(up, UART_EFR) != 0) { |
959 | DEBUG_AUTOCONF("EFRv1 "); |
960 | up->port.type = PORT_16650; |
961 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; |
962 | } else { |
963 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); |
964 | } |
965 | serial_outp(up, UART_EFR, 0); |
966 | return; |
967 | } |
968 | |
969 | /* |
970 | * Maybe it requires 0xbf to be written to the LCR. |
971 | * (other ST16C650V2 UARTs, TI16C752A, etc) |
972 | */ |
973 | serial_outp(up, UART_LCR, 0xBF); |
974 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { |
975 | DEBUG_AUTOCONF("EFRv2 "); |
976 | autoconfig_has_efr(up); |
977 | return; |
978 | } |
979 | |
980 | /* |
981 | * Check for a National Semiconductor SuperIO chip. |
982 | * Attempt to switch to bank 2, read the value of the LOOP bit |
983 | * from EXCR1. Switch back to bank 0, change it in MCR. Then |
984 | * switch back to bank 2, read it from EXCR1 again and check |
985 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 |
986 | */ |
987 | serial_outp(up, UART_LCR, 0); |
988 | status1 = serial_in(up, UART_MCR); |
989 | serial_outp(up, UART_LCR, 0xE0); |
990 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
991 | |
992 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { |
993 | serial_outp(up, UART_LCR, 0); |
994 | serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP); |
995 | serial_outp(up, UART_LCR, 0xE0); |
996 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
997 | serial_outp(up, UART_LCR, 0); |
998 | serial_outp(up, UART_MCR, status1); |
999 | |
1000 | if ((status2 ^ status1) & UART_MCR_LOOP) { |
1001 | unsigned short quot; |
1002 | |
1003 | serial_outp(up, UART_LCR, 0xE0); |
1004 | |
1005 | quot = serial_dl_read(up); |
1006 | quot <<= 3; |
1007 | |
1008 | status1 = serial_in(up, 0x04); /* EXCR2 */ |
1009 | status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ |
1010 | status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ |
1011 | serial_outp(up, 0x04, status1); |
1012 | |
1013 | serial_dl_write(up, quot); |
1014 | |
1015 | serial_outp(up, UART_LCR, 0); |
1016 | |
1017 | up->port.uartclk = 921600*16; |
1018 | up->port.type = PORT_NS16550A; |
1019 | up->capabilities |= UART_NATSEMI; |
1020 | return; |
1021 | } |
1022 | } |
1023 | |
1024 | /* |
1025 | * No EFR. Try to detect a TI16750, which only sets bit 5 of |
1026 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. |
1027 | * Try setting it with and without DLAB set. Cheap clones |
1028 | * set bit 5 without DLAB set. |
1029 | */ |
1030 | serial_outp(up, UART_LCR, 0); |
1031 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); |
1032 | status1 = serial_in(up, UART_IIR) >> 5; |
1033 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1034 | serial_outp(up, UART_LCR, UART_LCR_DLAB); |
1035 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); |
1036 | status2 = serial_in(up, UART_IIR) >> 5; |
1037 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1038 | serial_outp(up, UART_LCR, 0); |
1039 | |
1040 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); |
1041 | |
1042 | if (status1 == 6 && status2 == 7) { |
1043 | up->port.type = PORT_16750; |
1044 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; |
1045 | return; |
1046 | } |
1047 | |
1048 | /* |
1049 | * Try writing and reading the UART_IER_UUE bit (b6). |
1050 | * If it works, this is probably one of the Xscale platform's |
1051 | * internal UARTs. |
1052 | * We're going to explicitly set the UUE bit to 0 before |
1053 | * trying to write and read a 1 just to make sure it's not |
1054 | * already a 1 and maybe locked there before we even start start. |
1055 | */ |
1056 | iersave = serial_in(up, UART_IER); |
1057 | serial_outp(up, UART_IER, iersave & ~UART_IER_UUE); |
1058 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { |
1059 | /* |
1060 | * OK it's in a known zero state, try writing and reading |
1061 | * without disturbing the current state of the other bits. |
1062 | */ |
1063 | serial_outp(up, UART_IER, iersave | UART_IER_UUE); |
1064 | if (serial_in(up, UART_IER) & UART_IER_UUE) { |
1065 | /* |
1066 | * It's an Xscale. |
1067 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). |
1068 | */ |
1069 | DEBUG_AUTOCONF("Xscale "); |
1070 | up->port.type = PORT_XSCALE; |
1071 | up->capabilities |= UART_CAP_UUE; |
1072 | return; |
1073 | } |
1074 | } else { |
1075 | /* |
1076 | * If we got here we couldn't force the IER_UUE bit to 0. |
1077 | * Log it and continue. |
1078 | */ |
1079 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); |
1080 | } |
1081 | serial_outp(up, UART_IER, iersave); |
1082 | } |
1083 | |
1084 | /* |
1085 | * This routine is called by rs_init() to initialize a specific serial |
1086 | * port. It determines what type of UART chip this serial port is |
1087 | * using: 8250, 16450, 16550, 16550A. The important question is |
1088 | * whether or not this UART is a 16550A or not, since this will |
1089 | * determine whether or not we can use its FIFO features or not. |
1090 | */ |
1091 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) |
1092 | { |
1093 | unsigned char status1, scratch, scratch2, scratch3; |
1094 | unsigned char save_lcr, save_mcr; |
1095 | unsigned long flags; |
1096 | |
1097 | if (!up->port.iobase && !up->port.mapbase && !up->port.membase) |
1098 | return; |
1099 | |
1100 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", |
1101 | serial_index(&up->port), up->port.iobase, up->port.membase); |
1102 | |
1103 | /* |
1104 | * We really do need global IRQs disabled here - we're going to |
1105 | * be frobbing the chips IRQ enable register to see if it exists. |
1106 | */ |
1107 | spin_lock_irqsave(&up->port.lock, flags); |
1108 | |
1109 | up->capabilities = 0; |
1110 | up->bugs = 0; |
1111 | |
1112 | if (!(up->port.flags & UPF_BUGGY_UART)) { |
1113 | /* |
1114 | * Do a simple existence test first; if we fail this, |
1115 | * there's no point trying anything else. |
1116 | * |
1117 | * 0x80 is used as a nonsense port to prevent against |
1118 | * false positives due to ISA bus float. The |
1119 | * assumption is that 0x80 is a non-existent port; |
1120 | * which should be safe since include/asm/io.h also |
1121 | * makes this assumption. |
1122 | * |
1123 | * Note: this is safe as long as MCR bit 4 is clear |
1124 | * and the device is in "PC" mode. |
1125 | */ |
1126 | scratch = serial_inp(up, UART_IER); |
1127 | serial_outp(up, UART_IER, 0); |
1128 | #ifdef __i386__ |
1129 | outb(0xff, 0x080); |
1130 | #endif |
1131 | /* |
1132 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL |
1133 | * 16C754B) allow only to modify them if an EFR bit is set. |
1134 | */ |
1135 | scratch2 = serial_inp(up, UART_IER) & 0x0f; |
1136 | serial_outp(up, UART_IER, 0x0F); |
1137 | #ifdef __i386__ |
1138 | outb(0, 0x080); |
1139 | #endif |
1140 | scratch3 = serial_inp(up, UART_IER) & 0x0f; |
1141 | serial_outp(up, UART_IER, scratch); |
1142 | if (scratch2 != 0 || scratch3 != 0x0F) { |
1143 | /* |
1144 | * We failed; there's nothing here |
1145 | */ |
1146 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", |
1147 | scratch2, scratch3); |
1148 | goto out; |
1149 | } |
1150 | } |
1151 | |
1152 | save_mcr = serial_in(up, UART_MCR); |
1153 | save_lcr = serial_in(up, UART_LCR); |
1154 | |
1155 | /* |
1156 | * Check to see if a UART is really there. Certain broken |
1157 | * internal modems based on the Rockwell chipset fail this |
1158 | * test, because they apparently don't implement the loopback |
1159 | * test mode. So this test is skipped on the COM 1 through |
1160 | * COM 4 ports. This *should* be safe, since no board |
1161 | * manufacturer would be stupid enough to design a board |
1162 | * that conflicts with COM 1-4 --- we hope! |
1163 | */ |
1164 | if (!(up->port.flags & UPF_SKIP_TEST)) { |
1165 | serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); |
1166 | status1 = serial_inp(up, UART_MSR) & 0xF0; |
1167 | serial_outp(up, UART_MCR, save_mcr); |
1168 | if (status1 != 0x90) { |
1169 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", |
1170 | status1); |
1171 | goto out; |
1172 | } |
1173 | } |
1174 | |
1175 | /* |
1176 | * We're pretty sure there's a port here. Lets find out what |
1177 | * type of port it is. The IIR top two bits allows us to find |
1178 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1179 | * determines what we test for next. |
1180 | * |
1181 | * We also initialise the EFR (if any) to zero for later. The |
1182 | * EFR occupies the same register location as the FCR and IIR. |
1183 | */ |
1184 | serial_outp(up, UART_LCR, 0xBF); |
1185 | serial_outp(up, UART_EFR, 0); |
1186 | serial_outp(up, UART_LCR, 0); |
1187 | |
1188 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1189 | scratch = serial_in(up, UART_IIR) >> 6; |
1190 | |
1191 | DEBUG_AUTOCONF("iir=%d ", scratch); |
1192 | |
1193 | switch (scratch) { |
1194 | case 0: |
1195 | autoconfig_8250(up); |
1196 | break; |
1197 | case 1: |
1198 | up->port.type = PORT_UNKNOWN; |
1199 | break; |
1200 | case 2: |
1201 | up->port.type = PORT_16550; |
1202 | break; |
1203 | case 3: |
1204 | autoconfig_16550a(up); |
1205 | break; |
1206 | } |
1207 | |
1208 | #ifdef CONFIG_SERIAL_8250_RSA |
1209 | /* |
1210 | * Only probe for RSA ports if we got the region. |
1211 | */ |
1212 | if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) { |
1213 | int i; |
1214 | |
1215 | for (i = 0 ; i < probe_rsa_count; ++i) { |
1216 | if (probe_rsa[i] == up->port.iobase && |
1217 | __enable_rsa(up)) { |
1218 | up->port.type = PORT_RSA; |
1219 | break; |
1220 | } |
1221 | } |
1222 | } |
1223 | #endif |
1224 | |
1225 | serial_outp(up, UART_LCR, save_lcr); |
1226 | |
1227 | if (up->capabilities != uart_config[up->port.type].flags) { |
1228 | printk(KERN_WARNING |
1229 | "ttyS%d: detected caps %08x should be %08x\n", |
1230 | serial_index(&up->port), up->capabilities, |
1231 | uart_config[up->port.type].flags); |
1232 | } |
1233 | |
1234 | up->port.fifosize = uart_config[up->port.type].fifo_size; |
1235 | up->capabilities = uart_config[up->port.type].flags; |
1236 | up->tx_loadsz = uart_config[up->port.type].tx_loadsz; |
1237 | |
1238 | if (up->port.type == PORT_UNKNOWN) |
1239 | goto out; |
1240 | |
1241 | /* |
1242 | * Reset the UART. |
1243 | */ |
1244 | #ifdef CONFIG_SERIAL_8250_RSA |
1245 | if (up->port.type == PORT_RSA) |
1246 | serial_outp(up, UART_RSA_FRR, 0); |
1247 | #endif |
1248 | serial_outp(up, UART_MCR, save_mcr); |
1249 | serial8250_clear_fifos(up); |
1250 | serial_in(up, UART_RX); |
1251 | if (up->capabilities & UART_CAP_UUE) |
1252 | serial_outp(up, UART_IER, UART_IER_UUE); |
1253 | else |
1254 | serial_outp(up, UART_IER, 0); |
1255 | |
1256 | out: |
1257 | spin_unlock_irqrestore(&up->port.lock, flags); |
1258 | DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name); |
1259 | } |
1260 | |
1261 | static void autoconfig_irq(struct uart_8250_port *up) |
1262 | { |
1263 | unsigned char save_mcr, save_ier; |
1264 | unsigned char save_ICP = 0; |
1265 | unsigned int ICP = 0; |
1266 | unsigned long irqs; |
1267 | int irq; |
1268 | |
1269 | if (up->port.flags & UPF_FOURPORT) { |
1270 | ICP = (up->port.iobase & 0xfe0) | 0x1f; |
1271 | save_ICP = inb_p(ICP); |
1272 | outb_p(0x80, ICP); |
1273 | (void) inb_p(ICP); |
1274 | } |
1275 | |
1276 | /* forget possible initially masked and pending IRQ */ |
1277 | probe_irq_off(probe_irq_on()); |
1278 | save_mcr = serial_inp(up, UART_MCR); |
1279 | save_ier = serial_inp(up, UART_IER); |
1280 | serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); |
1281 | |
1282 | irqs = probe_irq_on(); |
1283 | serial_outp(up, UART_MCR, 0); |
1284 | udelay(10); |
1285 | if (up->port.flags & UPF_FOURPORT) { |
1286 | serial_outp(up, UART_MCR, |
1287 | UART_MCR_DTR | UART_MCR_RTS); |
1288 | } else { |
1289 | serial_outp(up, UART_MCR, |
1290 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); |
1291 | } |
1292 | serial_outp(up, UART_IER, 0x0f); /* enable all intrs */ |
1293 | (void)serial_inp(up, UART_LSR); |
1294 | (void)serial_inp(up, UART_RX); |
1295 | (void)serial_inp(up, UART_IIR); |
1296 | (void)serial_inp(up, UART_MSR); |
1297 | serial_outp(up, UART_TX, 0xFF); |
1298 | udelay(20); |
1299 | irq = probe_irq_off(irqs); |
1300 | |
1301 | serial_outp(up, UART_MCR, save_mcr); |
1302 | serial_outp(up, UART_IER, save_ier); |
1303 | |
1304 | if (up->port.flags & UPF_FOURPORT) |
1305 | outb_p(save_ICP, ICP); |
1306 | |
1307 | up->port.irq = (irq > 0) ? irq : 0; |
1308 | } |
1309 | |
1310 | static inline void __stop_tx(struct uart_8250_port *p) |
1311 | { |
1312 | if (p->ier & UART_IER_THRI) { |
1313 | p->ier &= ~UART_IER_THRI; |
1314 | serial_out(p, UART_IER, p->ier); |
1315 | } |
1316 | } |
1317 | |
1318 | static void serial8250_stop_tx(struct uart_port *port) |
1319 | { |
1320 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1321 | |
1322 | __stop_tx(up); |
1323 | |
1324 | /* |
1325 | * We really want to stop the transmitter from sending. |
1326 | */ |
1327 | if (up->port.type == PORT_16C950) { |
1328 | up->acr |= UART_ACR_TXDIS; |
1329 | serial_icr_write(up, UART_ACR, up->acr); |
1330 | } |
1331 | } |
1332 | |
1333 | static void transmit_chars(struct uart_8250_port *up); |
1334 | |
1335 | static void serial8250_start_tx(struct uart_port *port) |
1336 | { |
1337 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1338 | |
1339 | if (!(up->ier & UART_IER_THRI)) { |
1340 | up->ier |= UART_IER_THRI; |
1341 | serial_out(up, UART_IER, up->ier); |
1342 | |
1343 | if (up->bugs & UART_BUG_TXEN) { |
1344 | unsigned char lsr; |
1345 | lsr = serial_in(up, UART_LSR); |
1346 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
1347 | if ((up->port.type == PORT_RM9000) ? |
1348 | (lsr & UART_LSR_THRE) : |
1349 | (lsr & UART_LSR_TEMT)) |
1350 | transmit_chars(up); |
1351 | } |
1352 | } |
1353 | |
1354 | /* |
1355 | * Re-enable the transmitter if we disabled it. |
1356 | */ |
1357 | if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1358 | up->acr &= ~UART_ACR_TXDIS; |
1359 | serial_icr_write(up, UART_ACR, up->acr); |
1360 | } |
1361 | } |
1362 | |
1363 | static void serial8250_stop_rx(struct uart_port *port) |
1364 | { |
1365 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1366 | |
1367 | up->ier &= ~UART_IER_RLSI; |
1368 | up->port.read_status_mask &= ~UART_LSR_DR; |
1369 | serial_out(up, UART_IER, up->ier); |
1370 | } |
1371 | |
1372 | static void serial8250_enable_ms(struct uart_port *port) |
1373 | { |
1374 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1375 | |
1376 | /* no MSR capabilities */ |
1377 | if (up->bugs & UART_BUG_NOMSR) |
1378 | return; |
1379 | |
1380 | up->ier |= UART_IER_MSI; |
1381 | serial_out(up, UART_IER, up->ier); |
1382 | } |
1383 | |
1384 | static void |
1385 | receive_chars(struct uart_8250_port *up, unsigned int *status) |
1386 | { |
1387 | struct tty_struct *tty = up->port.state->port.tty; |
1388 | unsigned char ch, lsr = *status; |
1389 | int max_count = 256; |
1390 | char flag; |
1391 | |
1392 | do { |
1393 | if (likely(lsr & UART_LSR_DR)) |
1394 | ch = serial_inp(up, UART_RX); |
1395 | else |
1396 | /* |
1397 | * Intel 82571 has a Serial Over Lan device that will |
1398 | * set UART_LSR_BI without setting UART_LSR_DR when |
1399 | * it receives a break. To avoid reading from the |
1400 | * receive buffer without UART_LSR_DR bit set, we |
1401 | * just force the read character to be 0 |
1402 | */ |
1403 | ch = 0; |
1404 | |
1405 | flag = TTY_NORMAL; |
1406 | up->port.icount.rx++; |
1407 | |
1408 | lsr |= up->lsr_saved_flags; |
1409 | up->lsr_saved_flags = 0; |
1410 | |
1411 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { |
1412 | /* |
1413 | * For statistics only |
1414 | */ |
1415 | if (lsr & UART_LSR_BI) { |
1416 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); |
1417 | up->port.icount.brk++; |
1418 | /* |
1419 | * We do the SysRQ and SAK checking |
1420 | * here because otherwise the break |
1421 | * may get masked by ignore_status_mask |
1422 | * or read_status_mask. |
1423 | */ |
1424 | if (uart_handle_break(&up->port)) |
1425 | goto ignore_char; |
1426 | } else if (lsr & UART_LSR_PE) |
1427 | up->port.icount.parity++; |
1428 | else if (lsr & UART_LSR_FE) |
1429 | up->port.icount.frame++; |
1430 | if (lsr & UART_LSR_OE) |
1431 | up->port.icount.overrun++; |
1432 | |
1433 | /* |
1434 | * Mask off conditions which should be ignored. |
1435 | */ |
1436 | lsr &= up->port.read_status_mask; |
1437 | |
1438 | if (lsr & UART_LSR_BI) { |
1439 | DEBUG_INTR("handling break...."); |
1440 | flag = TTY_BREAK; |
1441 | } else if (lsr & UART_LSR_PE) |
1442 | flag = TTY_PARITY; |
1443 | else if (lsr & UART_LSR_FE) |
1444 | flag = TTY_FRAME; |
1445 | } |
1446 | if (uart_handle_sysrq_char(&up->port, ch)) |
1447 | goto ignore_char; |
1448 | |
1449 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); |
1450 | |
1451 | ignore_char: |
1452 | lsr = serial_inp(up, UART_LSR); |
1453 | } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); |
1454 | spin_unlock(&up->port.lock); |
1455 | tty_flip_buffer_push(tty); |
1456 | spin_lock(&up->port.lock); |
1457 | *status = lsr; |
1458 | } |
1459 | |
1460 | static void transmit_chars(struct uart_8250_port *up) |
1461 | { |
1462 | struct circ_buf *xmit = &up->port.state->xmit; |
1463 | int count; |
1464 | |
1465 | if (up->port.x_char) { |
1466 | serial_outp(up, UART_TX, up->port.x_char); |
1467 | up->port.icount.tx++; |
1468 | up->port.x_char = 0; |
1469 | return; |
1470 | } |
1471 | if (uart_tx_stopped(&up->port)) { |
1472 | serial8250_stop_tx(&up->port); |
1473 | return; |
1474 | } |
1475 | if (uart_circ_empty(xmit)) { |
1476 | __stop_tx(up); |
1477 | return; |
1478 | } |
1479 | |
1480 | count = up->tx_loadsz; |
1481 | do { |
1482 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); |
1483 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1484 | up->port.icount.tx++; |
1485 | if (uart_circ_empty(xmit)) |
1486 | break; |
1487 | } while (--count > 0); |
1488 | |
1489 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
1490 | uart_write_wakeup(&up->port); |
1491 | |
1492 | DEBUG_INTR("THRE..."); |
1493 | |
1494 | if (uart_circ_empty(xmit)) |
1495 | __stop_tx(up); |
1496 | } |
1497 | |
1498 | static unsigned int check_modem_status(struct uart_8250_port *up) |
1499 | { |
1500 | unsigned int status = serial_in(up, UART_MSR); |
1501 | |
1502 | status |= up->msr_saved_flags; |
1503 | up->msr_saved_flags = 0; |
1504 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && |
1505 | up->port.state != NULL) { |
1506 | if (status & UART_MSR_TERI) |
1507 | up->port.icount.rng++; |
1508 | if (status & UART_MSR_DDSR) |
1509 | up->port.icount.dsr++; |
1510 | if (status & UART_MSR_DDCD) |
1511 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); |
1512 | if (status & UART_MSR_DCTS) |
1513 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); |
1514 | |
1515 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
1516 | } |
1517 | |
1518 | return status; |
1519 | } |
1520 | |
1521 | /* |
1522 | * This handles the interrupt from one port. |
1523 | */ |
1524 | static void serial8250_handle_port(struct uart_8250_port *up) |
1525 | { |
1526 | unsigned int status; |
1527 | unsigned long flags; |
1528 | |
1529 | spin_lock_irqsave(&up->port.lock, flags); |
1530 | |
1531 | status = serial_inp(up, UART_LSR); |
1532 | |
1533 | DEBUG_INTR("status = %x...", status); |
1534 | |
1535 | if (status & (UART_LSR_DR | UART_LSR_BI)) |
1536 | receive_chars(up, &status); |
1537 | check_modem_status(up); |
1538 | if (status & UART_LSR_THRE) |
1539 | transmit_chars(up); |
1540 | |
1541 | spin_unlock_irqrestore(&up->port.lock, flags); |
1542 | } |
1543 | |
1544 | /* |
1545 | * This is the serial driver's interrupt routine. |
1546 | * |
1547 | * Arjan thinks the old way was overly complex, so it got simplified. |
1548 | * Alan disagrees, saying that need the complexity to handle the weird |
1549 | * nature of ISA shared interrupts. (This is a special exception.) |
1550 | * |
1551 | * In order to handle ISA shared interrupts properly, we need to check |
1552 | * that all ports have been serviced, and therefore the ISA interrupt |
1553 | * line has been de-asserted. |
1554 | * |
1555 | * This means we need to loop through all ports. checking that they |
1556 | * don't have an interrupt pending. |
1557 | */ |
1558 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id) |
1559 | { |
1560 | struct irq_info *i = dev_id; |
1561 | struct list_head *l, *end = NULL; |
1562 | int pass_counter = 0, handled = 0; |
1563 | |
1564 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); |
1565 | |
1566 | spin_lock(&i->lock); |
1567 | |
1568 | l = i->head; |
1569 | do { |
1570 | struct uart_8250_port *up; |
1571 | unsigned int iir; |
1572 | |
1573 | up = list_entry(l, struct uart_8250_port, list); |
1574 | |
1575 | iir = serial_in(up, UART_IIR); |
1576 | if (!(iir & UART_IIR_NO_INT)) { |
1577 | serial8250_handle_port(up); |
1578 | |
1579 | handled = 1; |
1580 | |
1581 | end = NULL; |
1582 | } else if (up->port.iotype == UPIO_DWAPB && |
1583 | (iir & UART_IIR_BUSY) == UART_IIR_BUSY) { |
1584 | /* The DesignWare APB UART has an Busy Detect (0x07) |
1585 | * interrupt meaning an LCR write attempt occured while the |
1586 | * UART was busy. The interrupt must be cleared by reading |
1587 | * the UART status register (USR) and the LCR re-written. */ |
1588 | unsigned int status; |
1589 | status = *(volatile u32 *)up->port.private_data; |
1590 | serial_out(up, UART_LCR, up->lcr); |
1591 | |
1592 | handled = 1; |
1593 | |
1594 | end = NULL; |
1595 | } else if (end == NULL) |
1596 | end = l; |
1597 | |
1598 | l = l->next; |
1599 | |
1600 | if (l == i->head && pass_counter++ > PASS_LIMIT) { |
1601 | /* If we hit this, we're dead. */ |
1602 | printk(KERN_ERR "serial8250: too much work for " |
1603 | "irq%d\n", irq); |
1604 | break; |
1605 | } |
1606 | } while (l != end); |
1607 | |
1608 | spin_unlock(&i->lock); |
1609 | |
1610 | DEBUG_INTR("end.\n"); |
1611 | |
1612 | return IRQ_RETVAL(handled); |
1613 | } |
1614 | |
1615 | /* |
1616 | * To support ISA shared interrupts, we need to have one interrupt |
1617 | * handler that ensures that the IRQ line has been deasserted |
1618 | * before returning. Failing to do this will result in the IRQ |
1619 | * line being stuck active, and, since ISA irqs are edge triggered, |
1620 | * no more IRQs will be seen. |
1621 | */ |
1622 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) |
1623 | { |
1624 | spin_lock_irq(&i->lock); |
1625 | |
1626 | if (!list_empty(i->head)) { |
1627 | if (i->head == &up->list) |
1628 | i->head = i->head->next; |
1629 | list_del(&up->list); |
1630 | } else { |
1631 | BUG_ON(i->head != &up->list); |
1632 | i->head = NULL; |
1633 | } |
1634 | spin_unlock_irq(&i->lock); |
1635 | /* List empty so throw away the hash node */ |
1636 | if (i->head == NULL) { |
1637 | hlist_del(&i->node); |
1638 | kfree(i); |
1639 | } |
1640 | } |
1641 | |
1642 | static int serial_link_irq_chain(struct uart_8250_port *up) |
1643 | { |
1644 | struct hlist_head *h; |
1645 | struct hlist_node *n; |
1646 | struct irq_info *i; |
1647 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; |
1648 | |
1649 | mutex_lock(&hash_mutex); |
1650 | |
1651 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; |
1652 | |
1653 | hlist_for_each(n, h) { |
1654 | i = hlist_entry(n, struct irq_info, node); |
1655 | if (i->irq == up->port.irq) |
1656 | break; |
1657 | } |
1658 | |
1659 | if (n == NULL) { |
1660 | i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); |
1661 | if (i == NULL) { |
1662 | mutex_unlock(&hash_mutex); |
1663 | return -ENOMEM; |
1664 | } |
1665 | spin_lock_init(&i->lock); |
1666 | i->irq = up->port.irq; |
1667 | hlist_add_head(&i->node, h); |
1668 | } |
1669 | mutex_unlock(&hash_mutex); |
1670 | |
1671 | spin_lock_irq(&i->lock); |
1672 | |
1673 | if (i->head) { |
1674 | list_add(&up->list, i->head); |
1675 | spin_unlock_irq(&i->lock); |
1676 | |
1677 | ret = 0; |
1678 | } else { |
1679 | INIT_LIST_HEAD(&up->list); |
1680 | i->head = &up->list; |
1681 | spin_unlock_irq(&i->lock); |
1682 | irq_flags |= up->port.irqflags; |
1683 | ret = request_irq(up->port.irq, serial8250_interrupt, |
1684 | irq_flags, "serial", i); |
1685 | if (ret < 0) |
1686 | serial_do_unlink(i, up); |
1687 | } |
1688 | |
1689 | return ret; |
1690 | } |
1691 | |
1692 | static void serial_unlink_irq_chain(struct uart_8250_port *up) |
1693 | { |
1694 | struct irq_info *i; |
1695 | struct hlist_node *n; |
1696 | struct hlist_head *h; |
1697 | |
1698 | mutex_lock(&hash_mutex); |
1699 | |
1700 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; |
1701 | |
1702 | hlist_for_each(n, h) { |
1703 | i = hlist_entry(n, struct irq_info, node); |
1704 | if (i->irq == up->port.irq) |
1705 | break; |
1706 | } |
1707 | |
1708 | BUG_ON(n == NULL); |
1709 | BUG_ON(i->head == NULL); |
1710 | |
1711 | if (list_empty(i->head)) |
1712 | free_irq(up->port.irq, i); |
1713 | |
1714 | serial_do_unlink(i, up); |
1715 | mutex_unlock(&hash_mutex); |
1716 | } |
1717 | |
1718 | /* Base timer interval for polling */ |
1719 | static inline int poll_timeout(int timeout) |
1720 | { |
1721 | return timeout > 6 ? (timeout / 2 - 2) : 1; |
1722 | } |
1723 | |
1724 | /* |
1725 | * This function is used to handle ports that do not have an |
1726 | * interrupt. This doesn't work very well for 16450's, but gives |
1727 | * barely passable results for a 16550A. (Although at the expense |
1728 | * of much CPU overhead). |
1729 | */ |
1730 | static void serial8250_timeout(unsigned long data) |
1731 | { |
1732 | struct uart_8250_port *up = (struct uart_8250_port *)data; |
1733 | unsigned int iir; |
1734 | |
1735 | iir = serial_in(up, UART_IIR); |
1736 | if (!(iir & UART_IIR_NO_INT)) |
1737 | serial8250_handle_port(up); |
1738 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
1739 | } |
1740 | |
1741 | static void serial8250_backup_timeout(unsigned long data) |
1742 | { |
1743 | struct uart_8250_port *up = (struct uart_8250_port *)data; |
1744 | unsigned int iir, ier = 0, lsr; |
1745 | unsigned long flags; |
1746 | |
1747 | /* |
1748 | * Must disable interrupts or else we risk racing with the interrupt |
1749 | * based handler. |
1750 | */ |
1751 | if (is_real_interrupt(up->port.irq)) { |
1752 | ier = serial_in(up, UART_IER); |
1753 | serial_out(up, UART_IER, 0); |
1754 | } |
1755 | |
1756 | iir = serial_in(up, UART_IIR); |
1757 | |
1758 | /* |
1759 | * This should be a safe test for anyone who doesn't trust the |
1760 | * IIR bits on their UART, but it's specifically designed for |
1761 | * the "Diva" UART used on the management processor on many HP |
1762 | * ia64 and parisc boxes. |
1763 | */ |
1764 | spin_lock_irqsave(&up->port.lock, flags); |
1765 | lsr = serial_in(up, UART_LSR); |
1766 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
1767 | spin_unlock_irqrestore(&up->port.lock, flags); |
1768 | if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && |
1769 | (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && |
1770 | (lsr & UART_LSR_THRE)) { |
1771 | iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); |
1772 | iir |= UART_IIR_THRI; |
1773 | } |
1774 | |
1775 | if (!(iir & UART_IIR_NO_INT)) |
1776 | serial8250_handle_port(up); |
1777 | |
1778 | if (is_real_interrupt(up->port.irq)) |
1779 | serial_out(up, UART_IER, ier); |
1780 | |
1781 | /* Standard timer interval plus 0.2s to keep the port running */ |
1782 | mod_timer(&up->timer, |
1783 | jiffies + poll_timeout(up->port.timeout) + HZ / 5); |
1784 | } |
1785 | |
1786 | static unsigned int serial8250_tx_empty(struct uart_port *port) |
1787 | { |
1788 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1789 | unsigned long flags; |
1790 | unsigned int lsr; |
1791 | |
1792 | spin_lock_irqsave(&up->port.lock, flags); |
1793 | lsr = serial_in(up, UART_LSR); |
1794 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
1795 | spin_unlock_irqrestore(&up->port.lock, flags); |
1796 | |
1797 | return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; |
1798 | } |
1799 | |
1800 | static unsigned int serial8250_get_mctrl(struct uart_port *port) |
1801 | { |
1802 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1803 | unsigned int status; |
1804 | unsigned int ret; |
1805 | |
1806 | status = check_modem_status(up); |
1807 | |
1808 | ret = 0; |
1809 | if (status & UART_MSR_DCD) |
1810 | ret |= TIOCM_CAR; |
1811 | if (status & UART_MSR_RI) |
1812 | ret |= TIOCM_RNG; |
1813 | if (status & UART_MSR_DSR) |
1814 | ret |= TIOCM_DSR; |
1815 | if (status & UART_MSR_CTS) |
1816 | ret |= TIOCM_CTS; |
1817 | return ret; |
1818 | } |
1819 | |
1820 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1821 | { |
1822 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1823 | unsigned char mcr = 0; |
1824 | |
1825 | if (mctrl & TIOCM_RTS) |
1826 | mcr |= UART_MCR_RTS; |
1827 | if (mctrl & TIOCM_DTR) |
1828 | mcr |= UART_MCR_DTR; |
1829 | if (mctrl & TIOCM_OUT1) |
1830 | mcr |= UART_MCR_OUT1; |
1831 | if (mctrl & TIOCM_OUT2) |
1832 | mcr |= UART_MCR_OUT2; |
1833 | if (mctrl & TIOCM_LOOP) |
1834 | mcr |= UART_MCR_LOOP; |
1835 | |
1836 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; |
1837 | |
1838 | serial_out(up, UART_MCR, mcr); |
1839 | } |
1840 | |
1841 | static void serial8250_break_ctl(struct uart_port *port, int break_state) |
1842 | { |
1843 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1844 | unsigned long flags; |
1845 | |
1846 | spin_lock_irqsave(&up->port.lock, flags); |
1847 | if (break_state == -1) |
1848 | up->lcr |= UART_LCR_SBC; |
1849 | else |
1850 | up->lcr &= ~UART_LCR_SBC; |
1851 | serial_out(up, UART_LCR, up->lcr); |
1852 | spin_unlock_irqrestore(&up->port.lock, flags); |
1853 | } |
1854 | |
1855 | /* |
1856 | * Wait for transmitter & holding register to empty |
1857 | */ |
1858 | static void wait_for_xmitr(struct uart_8250_port *up, int bits) |
1859 | { |
1860 | unsigned int status, tmout = 10000; |
1861 | |
1862 | /* Wait up to 10ms for the character(s) to be sent. */ |
1863 | do { |
1864 | status = serial_in(up, UART_LSR); |
1865 | |
1866 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; |
1867 | |
1868 | if (--tmout == 0) |
1869 | break; |
1870 | udelay(1); |
1871 | } while ((status & bits) != bits); |
1872 | |
1873 | /* Wait up to 1s for flow control if necessary */ |
1874 | if (up->port.flags & UPF_CONS_FLOW) { |
1875 | unsigned int tmout; |
1876 | for (tmout = 1000000; tmout; tmout--) { |
1877 | unsigned int msr = serial_in(up, UART_MSR); |
1878 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; |
1879 | if (msr & UART_MSR_CTS) |
1880 | break; |
1881 | udelay(1); |
1882 | touch_nmi_watchdog(); |
1883 | } |
1884 | } |
1885 | } |
1886 | |
1887 | #ifdef CONFIG_CONSOLE_POLL |
1888 | /* |
1889 | * Console polling routines for writing and reading from the uart while |
1890 | * in an interrupt or debug context. |
1891 | */ |
1892 | |
1893 | static int serial8250_get_poll_char(struct uart_port *port) |
1894 | { |
1895 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1896 | unsigned char lsr = serial_inp(up, UART_LSR); |
1897 | |
1898 | while (!(lsr & UART_LSR_DR)) |
1899 | lsr = serial_inp(up, UART_LSR); |
1900 | |
1901 | return serial_inp(up, UART_RX); |
1902 | } |
1903 | |
1904 | |
1905 | static void serial8250_put_poll_char(struct uart_port *port, |
1906 | unsigned char c) |
1907 | { |
1908 | unsigned int ier; |
1909 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1910 | |
1911 | /* |
1912 | * First save the IER then disable the interrupts |
1913 | */ |
1914 | ier = serial_in(up, UART_IER); |
1915 | if (up->capabilities & UART_CAP_UUE) |
1916 | serial_out(up, UART_IER, UART_IER_UUE); |
1917 | else |
1918 | serial_out(up, UART_IER, 0); |
1919 | |
1920 | wait_for_xmitr(up, BOTH_EMPTY); |
1921 | /* |
1922 | * Send the character out. |
1923 | * If a LF, also do CR... |
1924 | */ |
1925 | serial_out(up, UART_TX, c); |
1926 | if (c == 10) { |
1927 | wait_for_xmitr(up, BOTH_EMPTY); |
1928 | serial_out(up, UART_TX, 13); |
1929 | } |
1930 | |
1931 | /* |
1932 | * Finally, wait for transmitter to become empty |
1933 | * and restore the IER |
1934 | */ |
1935 | wait_for_xmitr(up, BOTH_EMPTY); |
1936 | serial_out(up, UART_IER, ier); |
1937 | } |
1938 | |
1939 | #endif /* CONFIG_CONSOLE_POLL */ |
1940 | |
1941 | static int serial8250_startup(struct uart_port *port) |
1942 | { |
1943 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
1944 | unsigned long flags; |
1945 | unsigned char lsr, iir; |
1946 | int retval; |
1947 | |
1948 | up->capabilities = uart_config[up->port.type].flags; |
1949 | up->mcr = 0; |
1950 | |
1951 | if (up->port.iotype != up->cur_iotype) |
1952 | set_io_from_upio(port); |
1953 | |
1954 | if (up->port.type == PORT_16C950) { |
1955 | /* Wake up and initialize UART */ |
1956 | up->acr = 0; |
1957 | serial_outp(up, UART_LCR, 0xBF); |
1958 | serial_outp(up, UART_EFR, UART_EFR_ECB); |
1959 | serial_outp(up, UART_IER, 0); |
1960 | serial_outp(up, UART_LCR, 0); |
1961 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ |
1962 | serial_outp(up, UART_LCR, 0xBF); |
1963 | serial_outp(up, UART_EFR, UART_EFR_ECB); |
1964 | serial_outp(up, UART_LCR, 0); |
1965 | } |
1966 | |
1967 | #ifdef CONFIG_SERIAL_8250_RSA |
1968 | /* |
1969 | * If this is an RSA port, see if we can kick it up to the |
1970 | * higher speed clock. |
1971 | */ |
1972 | enable_rsa(up); |
1973 | #endif |
1974 | |
1975 | /* |
1976 | * Clear the FIFO buffers and disable them. |
1977 | * (they will be reenabled in set_termios()) |
1978 | */ |
1979 | serial8250_clear_fifos(up); |
1980 | |
1981 | /* |
1982 | * Clear the interrupt registers. |
1983 | */ |
1984 | (void) serial_inp(up, UART_LSR); |
1985 | (void) serial_inp(up, UART_RX); |
1986 | (void) serial_inp(up, UART_IIR); |
1987 | (void) serial_inp(up, UART_MSR); |
1988 | |
1989 | /* |
1990 | * At this point, there's no way the LSR could still be 0xff; |
1991 | * if it is, then bail out, because there's likely no UART |
1992 | * here. |
1993 | */ |
1994 | if (!(up->port.flags & UPF_BUGGY_UART) && |
1995 | (serial_inp(up, UART_LSR) == 0xff)) { |
1996 | printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n", |
1997 | serial_index(&up->port)); |
1998 | return -ENODEV; |
1999 | } |
2000 | |
2001 | /* |
2002 | * For a XR16C850, we need to set the trigger levels |
2003 | */ |
2004 | if (up->port.type == PORT_16850) { |
2005 | unsigned char fctr; |
2006 | |
2007 | serial_outp(up, UART_LCR, 0xbf); |
2008 | |
2009 | fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); |
2010 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); |
2011 | serial_outp(up, UART_TRG, UART_TRG_96); |
2012 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX); |
2013 | serial_outp(up, UART_TRG, UART_TRG_96); |
2014 | |
2015 | serial_outp(up, UART_LCR, 0); |
2016 | } |
2017 | |
2018 | if (is_real_interrupt(up->port.irq)) { |
2019 | unsigned char iir1; |
2020 | /* |
2021 | * Test for UARTs that do not reassert THRE when the |
2022 | * transmitter is idle and the interrupt has already |
2023 | * been cleared. Real 16550s should always reassert |
2024 | * this interrupt whenever the transmitter is idle and |
2025 | * the interrupt is enabled. Delays are necessary to |
2026 | * allow register changes to become visible. |
2027 | */ |
2028 | spin_lock_irqsave(&up->port.lock, flags); |
2029 | if (up->port.irqflags & IRQF_SHARED) |
2030 | disable_irq_nosync(up->port.irq); |
2031 | |
2032 | wait_for_xmitr(up, UART_LSR_THRE); |
2033 | serial_out_sync(up, UART_IER, UART_IER_THRI); |
2034 | udelay(1); /* allow THRE to set */ |
2035 | iir1 = serial_in(up, UART_IIR); |
2036 | serial_out(up, UART_IER, 0); |
2037 | serial_out_sync(up, UART_IER, UART_IER_THRI); |
2038 | udelay(1); /* allow a working UART time to re-assert THRE */ |
2039 | iir = serial_in(up, UART_IIR); |
2040 | serial_out(up, UART_IER, 0); |
2041 | |
2042 | if (up->port.irqflags & IRQF_SHARED) |
2043 | enable_irq(up->port.irq); |
2044 | spin_unlock_irqrestore(&up->port.lock, flags); |
2045 | |
2046 | /* |
2047 | * If the interrupt is not reasserted, setup a timer to |
2048 | * kick the UART on a regular basis. |
2049 | */ |
2050 | if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) { |
2051 | up->bugs |= UART_BUG_THRE; |
2052 | pr_debug("ttyS%d - using backup timer\n", |
2053 | serial_index(port)); |
2054 | } |
2055 | } |
2056 | |
2057 | /* |
2058 | * The above check will only give an accurate result the first time |
2059 | * the port is opened so this value needs to be preserved. |
2060 | */ |
2061 | if (up->bugs & UART_BUG_THRE) { |
2062 | up->timer.function = serial8250_backup_timeout; |
2063 | up->timer.data = (unsigned long)up; |
2064 | mod_timer(&up->timer, jiffies + |
2065 | poll_timeout(up->port.timeout) + HZ / 5); |
2066 | } |
2067 | |
2068 | /* |
2069 | * If the "interrupt" for this port doesn't correspond with any |
2070 | * hardware interrupt, we use a timer-based system. The original |
2071 | * driver used to do this with IRQ0. |
2072 | */ |
2073 | if (!is_real_interrupt(up->port.irq)) { |
2074 | up->timer.data = (unsigned long)up; |
2075 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
2076 | } else { |
2077 | retval = serial_link_irq_chain(up); |
2078 | if (retval) |
2079 | return retval; |
2080 | } |
2081 | |
2082 | /* |
2083 | * Now, initialize the UART |
2084 | */ |
2085 | serial_outp(up, UART_LCR, UART_LCR_WLEN8); |
2086 | |
2087 | spin_lock_irqsave(&up->port.lock, flags); |
2088 | if (up->port.flags & UPF_FOURPORT) { |
2089 | if (!is_real_interrupt(up->port.irq)) |
2090 | up->port.mctrl |= TIOCM_OUT1; |
2091 | } else |
2092 | /* |
2093 | * Most PC uarts need OUT2 raised to enable interrupts. |
2094 | */ |
2095 | if (is_real_interrupt(up->port.irq)) |
2096 | up->port.mctrl |= TIOCM_OUT2; |
2097 | |
2098 | serial8250_set_mctrl(&up->port, up->port.mctrl); |
2099 | |
2100 | /* Serial over Lan (SoL) hack: |
2101 | Intel 8257x Gigabit ethernet chips have a |
2102 | 16550 emulation, to be used for Serial Over Lan. |
2103 | Those chips take a longer time than a normal |
2104 | serial device to signalize that a transmission |
2105 | data was queued. Due to that, the above test generally |
2106 | fails. One solution would be to delay the reading of |
2107 | iir. However, this is not reliable, since the timeout |
2108 | is variable. So, let's just don't test if we receive |
2109 | TX irq. This way, we'll never enable UART_BUG_TXEN. |
2110 | */ |
2111 | if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) |
2112 | goto dont_test_tx_en; |
2113 | |
2114 | /* |
2115 | * Do a quick test to see if we receive an |
2116 | * interrupt when we enable the TX irq. |
2117 | */ |
2118 | serial_outp(up, UART_IER, UART_IER_THRI); |
2119 | lsr = serial_in(up, UART_LSR); |
2120 | iir = serial_in(up, UART_IIR); |
2121 | serial_outp(up, UART_IER, 0); |
2122 | |
2123 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { |
2124 | if (!(up->bugs & UART_BUG_TXEN)) { |
2125 | up->bugs |= UART_BUG_TXEN; |
2126 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
2127 | serial_index(port)); |
2128 | } |
2129 | } else { |
2130 | up->bugs &= ~UART_BUG_TXEN; |
2131 | } |
2132 | |
2133 | dont_test_tx_en: |
2134 | spin_unlock_irqrestore(&up->port.lock, flags); |
2135 | |
2136 | /* |
2137 | * Clear the interrupt registers again for luck, and clear the |
2138 | * saved flags to avoid getting false values from polling |
2139 | * routines or the previous session. |
2140 | */ |
2141 | serial_inp(up, UART_LSR); |
2142 | serial_inp(up, UART_RX); |
2143 | serial_inp(up, UART_IIR); |
2144 | serial_inp(up, UART_MSR); |
2145 | up->lsr_saved_flags = 0; |
2146 | up->msr_saved_flags = 0; |
2147 | |
2148 | /* |
2149 | * Finally, enable interrupts. Note: Modem status interrupts |
2150 | * are set via set_termios(), which will be occurring imminently |
2151 | * anyway, so we don't enable them here. |
2152 | */ |
2153 | up->ier = UART_IER_RLSI | UART_IER_RDI; |
2154 | serial_outp(up, UART_IER, up->ier); |
2155 | |
2156 | if (up->port.flags & UPF_FOURPORT) { |
2157 | unsigned int icp; |
2158 | /* |
2159 | * Enable interrupts on the AST Fourport board |
2160 | */ |
2161 | icp = (up->port.iobase & 0xfe0) | 0x01f; |
2162 | outb_p(0x80, icp); |
2163 | (void) inb_p(icp); |
2164 | } |
2165 | |
2166 | return 0; |
2167 | } |
2168 | |
2169 | static void serial8250_shutdown(struct uart_port *port) |
2170 | { |
2171 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2172 | unsigned long flags; |
2173 | |
2174 | /* |
2175 | * Disable interrupts from this port |
2176 | */ |
2177 | up->ier = 0; |
2178 | serial_outp(up, UART_IER, 0); |
2179 | |
2180 | spin_lock_irqsave(&up->port.lock, flags); |
2181 | if (up->port.flags & UPF_FOURPORT) { |
2182 | /* reset interrupts on the AST Fourport board */ |
2183 | inb((up->port.iobase & 0xfe0) | 0x1f); |
2184 | up->port.mctrl |= TIOCM_OUT1; |
2185 | } else |
2186 | up->port.mctrl &= ~TIOCM_OUT2; |
2187 | |
2188 | serial8250_set_mctrl(&up->port, up->port.mctrl); |
2189 | spin_unlock_irqrestore(&up->port.lock, flags); |
2190 | |
2191 | /* |
2192 | * Disable break condition and FIFOs |
2193 | */ |
2194 | serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); |
2195 | serial8250_clear_fifos(up); |
2196 | |
2197 | #ifdef CONFIG_SERIAL_8250_RSA |
2198 | /* |
2199 | * Reset the RSA board back to 115kbps compat mode. |
2200 | */ |
2201 | disable_rsa(up); |
2202 | #endif |
2203 | |
2204 | /* |
2205 | * Read data port to reset things, and then unlink from |
2206 | * the IRQ chain. |
2207 | */ |
2208 | (void) serial_in(up, UART_RX); |
2209 | |
2210 | del_timer_sync(&up->timer); |
2211 | up->timer.function = serial8250_timeout; |
2212 | if (is_real_interrupt(up->port.irq)) |
2213 | serial_unlink_irq_chain(up); |
2214 | } |
2215 | |
2216 | #if defined(CONFIG_JZSOC) && !defined(CONFIG_SOC_JZ4730) |
2217 | static unsigned short quot1[3] = {0}; /* quot[0]:baud_div, quot[1]:umr, quot[2]:uacr */ |
2218 | static unsigned short * serial8250_get_divisor(struct uart_port *port, unsigned int baud) |
2219 | { |
2220 | int err, sum, i, j; |
2221 | int a[12], b[12]; |
2222 | unsigned short div, umr, uacr; |
2223 | unsigned short umr_best, div_best, uacr_best; |
2224 | long long t0, t1, t2, t3; |
2225 | |
2226 | sum = 0; |
2227 | umr_best = div_best = uacr_best = 0; |
2228 | div = 1; |
2229 | |
2230 | if ((port->uartclk % (16 * baud)) == 0) { |
2231 | quot1[0] = port->uartclk / (16 * baud); |
2232 | quot1[1] = 16; |
2233 | quot1[2] = 0; |
2234 | return quot1; |
2235 | } |
2236 | |
2237 | while (1) { |
2238 | umr = port->uartclk / (baud * div); |
2239 | if (umr > 32) { |
2240 | div++; |
2241 | continue; |
2242 | } |
2243 | if (umr < 4) { |
2244 | break; |
2245 | } |
2246 | for (i = 0; i < 12; i++) { |
2247 | a[i] = umr; |
2248 | b[i] = 0; |
2249 | sum = 0; |
2250 | for (j = 0; j <= i; j++) { |
2251 | sum += a[j]; |
2252 | } |
2253 | |
2254 | /* the precision could be 1/2^(36) due to the value of t0 */ |
2255 | t0 = 0x1000000000LL; |
2256 | t1 = (i + 1) * t0; |
2257 | t2 = (sum * div) * t0; |
2258 | t3 = div * t0; |
2259 | do_div(t1, baud); |
2260 | do_div(t2, port->uartclk); |
2261 | do_div(t3, (2 * port->uartclk)); |
2262 | err = t1 - t2 - t3; |
2263 | |
2264 | if (err > 0) { |
2265 | a[i] += 1; |
2266 | b[i] = 1; |
2267 | } |
2268 | } |
2269 | |
2270 | uacr = 0; |
2271 | for (i = 0; i < 12; i++) { |
2272 | if (b[i] == 1) { |
2273 | uacr |= 1 << i; |
2274 | } |
2275 | } |
2276 | |
2277 | /* the best value of umr should be near 16, and the value of uacr should better be smaller */ |
2278 | if (abs(umr - 16) < abs(umr_best - 16) || (abs(umr - 16) == abs(umr_best - 16) && uacr_best > uacr)) { |
2279 | div_best = div; |
2280 | umr_best = umr; |
2281 | uacr_best = uacr; |
2282 | } |
2283 | div++; |
2284 | } |
2285 | |
2286 | quot1[0] = div_best; |
2287 | quot1[1] = umr_best; |
2288 | quot1[2] = uacr_best; |
2289 | |
2290 | return quot1; |
2291 | } |
2292 | #else |
2293 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) |
2294 | { |
2295 | unsigned int quot; |
2296 | |
2297 | /* |
2298 | * Handle magic divisors for baud rates above baud_base on |
2299 | * SMSC SuperIO chips. |
2300 | */ |
2301 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && |
2302 | baud == (port->uartclk/4)) |
2303 | quot = 0x8001; |
2304 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && |
2305 | baud == (port->uartclk/8)) |
2306 | quot = 0x8002; |
2307 | else |
2308 | quot = uart_get_divisor(port, baud); |
2309 | |
2310 | return quot; |
2311 | } |
2312 | #endif |
2313 | |
2314 | static void |
2315 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, |
2316 | struct ktermios *old) |
2317 | { |
2318 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2319 | unsigned char cval, fcr = 0; |
2320 | unsigned long flags; |
2321 | unsigned int baud, quot; |
2322 | #if defined(CONFIG_JZSOC) && !defined(CONFIG_SOC_JZ4730) |
2323 | unsigned short *quot1; |
2324 | #endif |
2325 | |
2326 | switch (termios->c_cflag & CSIZE) { |
2327 | case CS5: |
2328 | cval = UART_LCR_WLEN5; |
2329 | break; |
2330 | case CS6: |
2331 | cval = UART_LCR_WLEN6; |
2332 | break; |
2333 | case CS7: |
2334 | cval = UART_LCR_WLEN7; |
2335 | break; |
2336 | default: |
2337 | case CS8: |
2338 | cval = UART_LCR_WLEN8; |
2339 | break; |
2340 | } |
2341 | |
2342 | if (termios->c_cflag & CSTOPB) |
2343 | cval |= UART_LCR_STOP; |
2344 | if (termios->c_cflag & PARENB) |
2345 | cval |= UART_LCR_PARITY; |
2346 | if (!(termios->c_cflag & PARODD)) |
2347 | cval |= UART_LCR_EPAR; |
2348 | #ifdef CMSPAR |
2349 | if (termios->c_cflag & CMSPAR) |
2350 | cval |= UART_LCR_SPAR; |
2351 | #endif |
2352 | |
2353 | /* |
2354 | * Ask the core to calculate the divisor for us. |
2355 | */ |
2356 | baud = uart_get_baud_rate(port, termios, old, |
2357 | port->uartclk / 16 / 0xffff, |
2358 | port->uartclk / 16); |
2359 | #if defined(CONFIG_JZSOC) && !defined(CONFIG_SOC_JZ4730) |
2360 | quot1 = serial8250_get_divisor(port, baud); |
2361 | quot = quot1[0]; /* not usefull, just let gcc happy */ |
2362 | #else |
2363 | quot = serial8250_get_divisor(port, baud); |
2364 | #endif |
2365 | |
2366 | /* |
2367 | * Oxford Semi 952 rev B workaround |
2368 | */ |
2369 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
2370 | quot++; |
2371 | |
2372 | if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) { |
2373 | if (baud < 2400) |
2374 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; |
2375 | else |
2376 | fcr = uart_config[up->port.type].fcr; |
2377 | } |
2378 | |
2379 | /* |
2380 | * MCR-based auto flow control. When AFE is enabled, RTS will be |
2381 | * deasserted when the receive FIFO contains more characters than |
2382 | * the trigger, or the MCR RTS bit is cleared. In the case where |
2383 | * the remote UART is not using CTS auto flow control, we must |
2384 | * have sufficient FIFO entries for the latency of the remote |
2385 | * UART to respond. IOW, at least 32 bytes of FIFO. |
2386 | */ |
2387 | if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { |
2388 | up->mcr &= ~UART_MCR_AFE; |
2389 | if (termios->c_cflag & CRTSCTS) |
2390 | up->mcr |= UART_MCR_AFE; |
2391 | } |
2392 | |
2393 | /* |
2394 | * Ok, we're now changing the port state. Do it with |
2395 | * interrupts disabled. |
2396 | */ |
2397 | spin_lock_irqsave(&up->port.lock, flags); |
2398 | |
2399 | /* |
2400 | * Update the per-port timeout. |
2401 | */ |
2402 | uart_update_timeout(port, termios->c_cflag, baud); |
2403 | |
2404 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
2405 | if (termios->c_iflag & INPCK) |
2406 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
2407 | if (termios->c_iflag & (BRKINT | PARMRK)) |
2408 | up->port.read_status_mask |= UART_LSR_BI; |
2409 | |
2410 | /* |
2411 | * Characteres to ignore |
2412 | */ |
2413 | up->port.ignore_status_mask = 0; |
2414 | if (termios->c_iflag & IGNPAR) |
2415 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; |
2416 | if (termios->c_iflag & IGNBRK) { |
2417 | up->port.ignore_status_mask |= UART_LSR_BI; |
2418 | /* |
2419 | * If we're ignoring parity and break indicators, |
2420 | * ignore overruns too (for real raw support). |
2421 | */ |
2422 | if (termios->c_iflag & IGNPAR) |
2423 | up->port.ignore_status_mask |= UART_LSR_OE; |
2424 | } |
2425 | |
2426 | /* |
2427 | * ignore all characters if CREAD is not set |
2428 | */ |
2429 | if ((termios->c_cflag & CREAD) == 0) |
2430 | up->port.ignore_status_mask |= UART_LSR_DR; |
2431 | |
2432 | /* |
2433 | * CTS flow control flag and modem status interrupts |
2434 | */ |
2435 | up->ier &= ~UART_IER_MSI; |
2436 | if (!(up->bugs & UART_BUG_NOMSR) && |
2437 | UART_ENABLE_MS(&up->port, termios->c_cflag)) |
2438 | up->ier |= UART_IER_MSI; |
2439 | if (up->capabilities & UART_CAP_UUE) |
2440 | up->ier |= UART_IER_UUE | UART_IER_RTOIE; |
2441 | |
2442 | #ifdef CONFIG_JZSOC |
2443 | up->ier |= UART_IER_RTOIE; /* Set this flag, or very slow */ |
2444 | #endif |
2445 | |
2446 | serial_out(up, UART_IER, up->ier); |
2447 | |
2448 | if (up->capabilities & UART_CAP_EFR) { |
2449 | unsigned char efr = 0; |
2450 | /* |
2451 | * TI16C752/Startech hardware flow control. FIXME: |
2452 | * - TI16C752 requires control thresholds to be set. |
2453 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. |
2454 | */ |
2455 | if (termios->c_cflag & CRTSCTS) |
2456 | efr |= UART_EFR_CTS; |
2457 | |
2458 | serial_outp(up, UART_LCR, 0xBF); |
2459 | serial_outp(up, UART_EFR, efr); |
2460 | } |
2461 | |
2462 | #ifdef CONFIG_ARCH_OMAP |
2463 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ |
2464 | if (cpu_is_omap1510() && is_omap_port(up)) { |
2465 | if (baud == 115200) { |
2466 | quot = 1; |
2467 | serial_out(up, UART_OMAP_OSC_12M_SEL, 1); |
2468 | } else |
2469 | serial_out(up, UART_OMAP_OSC_12M_SEL, 0); |
2470 | } |
2471 | #endif |
2472 | |
2473 | if (up->capabilities & UART_NATSEMI) { |
2474 | /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ |
2475 | serial_outp(up, UART_LCR, 0xe0); |
2476 | } else { |
2477 | serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ |
2478 | } |
2479 | |
2480 | #if defined(CONFIG_JZSOC) && !defined(CONFIG_SOC_JZ4730) |
2481 | #define UART_UMR 9 |
2482 | #define UART_UACR 10 |
2483 | serial_dl_write(up, quot1[0]); |
2484 | serial_outp(up, UART_UMR, quot1[1]); |
2485 | serial_outp(up, UART_UACR, quot1[2]); |
2486 | #else |
2487 | serial_dl_write(up, quot); |
2488 | #endif |
2489 | |
2490 | /* |
2491 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR |
2492 | * is written without DLAB set, this mode will be disabled. |
2493 | */ |
2494 | if (up->port.type == PORT_16750) |
2495 | serial_outp(up, UART_FCR, fcr); |
2496 | |
2497 | serial_outp(up, UART_LCR, cval); /* reset DLAB */ |
2498 | up->lcr = cval; /* Save LCR */ |
2499 | if (up->port.type != PORT_16750) { |
2500 | if (fcr & UART_FCR_ENABLE_FIFO) { |
2501 | /* emulated UARTs (Lucent Venus 167x) need two steps */ |
2502 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
2503 | } |
2504 | serial_outp(up, UART_FCR, fcr); /* set fcr */ |
2505 | } |
2506 | serial8250_set_mctrl(&up->port, up->port.mctrl); |
2507 | spin_unlock_irqrestore(&up->port.lock, flags); |
2508 | /* Don't rewrite B0 */ |
2509 | if (tty_termios_baud_rate(termios)) |
2510 | tty_termios_encode_baud_rate(termios, baud, baud); |
2511 | } |
2512 | |
2513 | static void |
2514 | serial8250_set_ldisc(struct uart_port *port) |
2515 | { |
2516 | int line = port->line; |
2517 | |
2518 | if (line >= port->state->port.tty->driver->num) |
2519 | return; |
2520 | |
2521 | if (port->state->port.tty->ldisc->ops->num == N_PPS) { |
2522 | port->flags |= UPF_HARDPPS_CD; |
2523 | serial8250_enable_ms(port); |
2524 | } else |
2525 | port->flags &= ~UPF_HARDPPS_CD; |
2526 | } |
2527 | |
2528 | static void |
2529 | serial8250_pm(struct uart_port *port, unsigned int state, |
2530 | unsigned int oldstate) |
2531 | { |
2532 | struct uart_8250_port *p = (struct uart_8250_port *)port; |
2533 | |
2534 | serial8250_set_sleep(p, state != 0); |
2535 | |
2536 | if (p->pm) |
2537 | p->pm(port, state, oldstate); |
2538 | } |
2539 | |
2540 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) |
2541 | { |
2542 | if (pt->port.iotype == UPIO_AU) |
2543 | return 0x1000; |
2544 | #ifdef CONFIG_ARCH_OMAP |
2545 | if (is_omap_port(pt)) |
2546 | return 0x16 << pt->port.regshift; |
2547 | #endif |
2548 | return 8 << pt->port.regshift; |
2549 | } |
2550 | |
2551 | /* |
2552 | * Resource handling. |
2553 | */ |
2554 | static int serial8250_request_std_resource(struct uart_8250_port *up) |
2555 | { |
2556 | unsigned int size = serial8250_port_size(up); |
2557 | int ret = 0; |
2558 | |
2559 | switch (up->port.iotype) { |
2560 | case UPIO_AU: |
2561 | case UPIO_TSI: |
2562 | case UPIO_MEM32: |
2563 | case UPIO_MEM: |
2564 | case UPIO_DWAPB: |
2565 | if (!up->port.mapbase) |
2566 | break; |
2567 | |
2568 | if (!request_mem_region(up->port.mapbase, size, "serial")) { |
2569 | ret = -EBUSY; |
2570 | break; |
2571 | } |
2572 | |
2573 | if (up->port.flags & UPF_IOREMAP) { |
2574 | up->port.membase = ioremap_nocache(up->port.mapbase, |
2575 | size); |
2576 | if (!up->port.membase) { |
2577 | release_mem_region(up->port.mapbase, size); |
2578 | ret = -ENOMEM; |
2579 | } |
2580 | } |
2581 | break; |
2582 | |
2583 | case UPIO_HUB6: |
2584 | case UPIO_PORT: |
2585 | if (!request_region(up->port.iobase, size, "serial")) |
2586 | ret = -EBUSY; |
2587 | break; |
2588 | } |
2589 | return ret; |
2590 | } |
2591 | |
2592 | static void serial8250_release_std_resource(struct uart_8250_port *up) |
2593 | { |
2594 | unsigned int size = serial8250_port_size(up); |
2595 | |
2596 | switch (up->port.iotype) { |
2597 | case UPIO_AU: |
2598 | case UPIO_TSI: |
2599 | case UPIO_MEM32: |
2600 | case UPIO_MEM: |
2601 | case UPIO_DWAPB: |
2602 | if (!up->port.mapbase) |
2603 | break; |
2604 | |
2605 | if (up->port.flags & UPF_IOREMAP) { |
2606 | iounmap(up->port.membase); |
2607 | up->port.membase = NULL; |
2608 | } |
2609 | |
2610 | release_mem_region(up->port.mapbase, size); |
2611 | break; |
2612 | |
2613 | case UPIO_HUB6: |
2614 | case UPIO_PORT: |
2615 | release_region(up->port.iobase, size); |
2616 | break; |
2617 | } |
2618 | } |
2619 | |
2620 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) |
2621 | { |
2622 | unsigned long start = UART_RSA_BASE << up->port.regshift; |
2623 | unsigned int size = 8 << up->port.regshift; |
2624 | int ret = -EINVAL; |
2625 | |
2626 | switch (up->port.iotype) { |
2627 | case UPIO_HUB6: |
2628 | case UPIO_PORT: |
2629 | start += up->port.iobase; |
2630 | if (request_region(start, size, "serial-rsa")) |
2631 | ret = 0; |
2632 | else |
2633 | ret = -EBUSY; |
2634 | break; |
2635 | } |
2636 | |
2637 | return ret; |
2638 | } |
2639 | |
2640 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) |
2641 | { |
2642 | unsigned long offset = UART_RSA_BASE << up->port.regshift; |
2643 | unsigned int size = 8 << up->port.regshift; |
2644 | |
2645 | switch (up->port.iotype) { |
2646 | case UPIO_HUB6: |
2647 | case UPIO_PORT: |
2648 | release_region(up->port.iobase + offset, size); |
2649 | break; |
2650 | } |
2651 | } |
2652 | |
2653 | static void serial8250_release_port(struct uart_port *port) |
2654 | { |
2655 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2656 | |
2657 | serial8250_release_std_resource(up); |
2658 | if (up->port.type == PORT_RSA) |
2659 | serial8250_release_rsa_resource(up); |
2660 | } |
2661 | |
2662 | static int serial8250_request_port(struct uart_port *port) |
2663 | { |
2664 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2665 | int ret = 0; |
2666 | |
2667 | ret = serial8250_request_std_resource(up); |
2668 | if (ret == 0 && up->port.type == PORT_RSA) { |
2669 | ret = serial8250_request_rsa_resource(up); |
2670 | if (ret < 0) |
2671 | serial8250_release_std_resource(up); |
2672 | } |
2673 | |
2674 | return ret; |
2675 | } |
2676 | |
2677 | static void serial8250_config_port(struct uart_port *port, int flags) |
2678 | { |
2679 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2680 | int probeflags = PROBE_ANY; |
2681 | int ret; |
2682 | |
2683 | /* |
2684 | * Find the region that we can probe for. This in turn |
2685 | * tells us whether we can probe for the type of port. |
2686 | */ |
2687 | ret = serial8250_request_std_resource(up); |
2688 | if (ret < 0) |
2689 | return; |
2690 | |
2691 | ret = serial8250_request_rsa_resource(up); |
2692 | if (ret < 0) |
2693 | probeflags &= ~PROBE_RSA; |
2694 | |
2695 | if (up->port.iotype != up->cur_iotype) |
2696 | set_io_from_upio(port); |
2697 | |
2698 | if (flags & UART_CONFIG_TYPE) |
2699 | autoconfig(up, probeflags); |
2700 | |
2701 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
2702 | /* if access method is AU, it is a 16550 with a quirk */ |
2703 | if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU) |
2704 | up->bugs |= UART_BUG_NOMSR; |
2705 | #endif |
2706 | |
2707 | if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) |
2708 | autoconfig_irq(up); |
2709 | |
2710 | if (up->port.type != PORT_RSA && probeflags & PROBE_RSA) |
2711 | serial8250_release_rsa_resource(up); |
2712 | if (up->port.type == PORT_UNKNOWN) |
2713 | serial8250_release_std_resource(up); |
2714 | } |
2715 | |
2716 | static int |
2717 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) |
2718 | { |
2719 | if (ser->irq >= nr_irqs || ser->irq < 0 || |
2720 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || |
2721 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || |
2722 | ser->type == PORT_STARTECH) |
2723 | return -EINVAL; |
2724 | return 0; |
2725 | } |
2726 | |
2727 | static const char * |
2728 | serial8250_type(struct uart_port *port) |
2729 | { |
2730 | int type = port->type; |
2731 | |
2732 | if (type >= ARRAY_SIZE(uart_config)) |
2733 | type = 0; |
2734 | return uart_config[type].name; |
2735 | } |
2736 | |
2737 | static struct uart_ops serial8250_pops = { |
2738 | .tx_empty = serial8250_tx_empty, |
2739 | .set_mctrl = serial8250_set_mctrl, |
2740 | .get_mctrl = serial8250_get_mctrl, |
2741 | .stop_tx = serial8250_stop_tx, |
2742 | .start_tx = serial8250_start_tx, |
2743 | .stop_rx = serial8250_stop_rx, |
2744 | .enable_ms = serial8250_enable_ms, |
2745 | .break_ctl = serial8250_break_ctl, |
2746 | .startup = serial8250_startup, |
2747 | .shutdown = serial8250_shutdown, |
2748 | .set_termios = serial8250_set_termios, |
2749 | .set_ldisc = serial8250_set_ldisc, |
2750 | .pm = serial8250_pm, |
2751 | .type = serial8250_type, |
2752 | .release_port = serial8250_release_port, |
2753 | .request_port = serial8250_request_port, |
2754 | .config_port = serial8250_config_port, |
2755 | .verify_port = serial8250_verify_port, |
2756 | #ifdef CONFIG_CONSOLE_POLL |
2757 | .poll_get_char = serial8250_get_poll_char, |
2758 | .poll_put_char = serial8250_put_poll_char, |
2759 | #endif |
2760 | }; |
2761 | |
2762 | static struct uart_8250_port serial8250_ports[UART_NR]; |
2763 | |
2764 | static void __init serial8250_isa_init_ports(void) |
2765 | { |
2766 | struct uart_8250_port *up; |
2767 | static int first = 1; |
2768 | int i, irqflag = 0; |
2769 | |
2770 | if (!first) |
2771 | return; |
2772 | first = 0; |
2773 | |
2774 | for (i = 0; i < nr_uarts; i++) { |
2775 | struct uart_8250_port *up = &serial8250_ports[i]; |
2776 | |
2777 | up->port.line = i; |
2778 | spin_lock_init(&up->port.lock); |
2779 | |
2780 | init_timer(&up->timer); |
2781 | up->timer.function = serial8250_timeout; |
2782 | |
2783 | /* |
2784 | * ALPHA_KLUDGE_MCR needs to be killed. |
2785 | */ |
2786 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; |
2787 | up->mcr_force = ALPHA_KLUDGE_MCR; |
2788 | |
2789 | up->port.ops = &serial8250_pops; |
2790 | } |
2791 | |
2792 | if (share_irqs) |
2793 | irqflag = IRQF_SHARED; |
2794 | |
2795 | for (i = 0, up = serial8250_ports; |
2796 | i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; |
2797 | i++, up++) { |
2798 | up->port.iobase = old_serial_port[i].port; |
2799 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); |
2800 | up->port.irqflags = old_serial_port[i].irqflags; |
2801 | up->port.uartclk = old_serial_port[i].baud_base * 16; |
2802 | up->port.flags = old_serial_port[i].flags; |
2803 | up->port.hub6 = old_serial_port[i].hub6; |
2804 | up->port.membase = old_serial_port[i].iomem_base; |
2805 | up->port.iotype = old_serial_port[i].io_type; |
2806 | up->port.regshift = old_serial_port[i].iomem_reg_shift; |
2807 | set_io_from_upio(&up->port); |
2808 | up->port.irqflags |= irqflag; |
2809 | } |
2810 | } |
2811 | |
2812 | static void |
2813 | serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) |
2814 | { |
2815 | up->port.type = type; |
2816 | up->port.fifosize = uart_config[type].fifo_size; |
2817 | up->capabilities = uart_config[type].flags; |
2818 | up->tx_loadsz = uart_config[type].tx_loadsz; |
2819 | } |
2820 | |
2821 | static void __init |
2822 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) |
2823 | { |
2824 | int i; |
2825 | |
2826 | for (i = 0; i < nr_uarts; i++) { |
2827 | struct uart_8250_port *up = &serial8250_ports[i]; |
2828 | up->cur_iotype = 0xFF; |
2829 | } |
2830 | |
2831 | serial8250_isa_init_ports(); |
2832 | |
2833 | for (i = 0; i < nr_uarts; i++) { |
2834 | struct uart_8250_port *up = &serial8250_ports[i]; |
2835 | |
2836 | up->port.dev = dev; |
2837 | |
2838 | if (up->port.flags & UPF_FIXED_TYPE) |
2839 | serial8250_init_fixed_type_port(up, up->port.type); |
2840 | |
2841 | uart_add_one_port(drv, &up->port); |
2842 | } |
2843 | } |
2844 | |
2845 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
2846 | |
2847 | static void serial8250_console_putchar(struct uart_port *port, int ch) |
2848 | { |
2849 | struct uart_8250_port *up = (struct uart_8250_port *)port; |
2850 | |
2851 | wait_for_xmitr(up, UART_LSR_THRE); |
2852 | serial_out(up, UART_TX, ch); |
2853 | } |
2854 | |
2855 | /* |
2856 | * Print a string to the serial port trying not to disturb |
2857 | * any possible real use of the port... |
2858 | * |
2859 | * The console_lock must be held when we get here. |
2860 | */ |
2861 | static void |
2862 | serial8250_console_write(struct console *co, const char *s, unsigned int count) |
2863 | { |
2864 | struct uart_8250_port *up = &serial8250_ports[co->index]; |
2865 | unsigned long flags; |
2866 | unsigned int ier; |
2867 | int locked = 1; |
2868 | |
2869 | touch_nmi_watchdog(); |
2870 | |
2871 | local_irq_save(flags); |
2872 | if (up->port.sysrq) { |
2873 | /* serial8250_handle_port() already took the lock */ |
2874 | locked = 0; |
2875 | } else if (oops_in_progress) { |
2876 | locked = spin_trylock(&up->port.lock); |
2877 | } else |
2878 | spin_lock(&up->port.lock); |
2879 | |
2880 | /* |
2881 | * First save the IER then disable the interrupts |
2882 | */ |
2883 | ier = serial_in(up, UART_IER); |
2884 | |
2885 | if (up->capabilities & UART_CAP_UUE) |
2886 | serial_out(up, UART_IER, UART_IER_UUE); |
2887 | else |
2888 | serial_out(up, UART_IER, 0); |
2889 | |
2890 | uart_console_write(&up->port, s, count, serial8250_console_putchar); |
2891 | |
2892 | /* |
2893 | * Finally, wait for transmitter to become empty |
2894 | * and restore the IER |
2895 | */ |
2896 | wait_for_xmitr(up, BOTH_EMPTY); |
2897 | serial_out(up, UART_IER, ier); |
2898 | |
2899 | /* |
2900 | * The receive handling will happen properly because the |
2901 | * receive ready bit will still be set; it is not cleared |
2902 | * on read. However, modem control will not, we must |
2903 | * call it if we have saved something in the saved flags |
2904 | * while processing with interrupts off. |
2905 | */ |
2906 | if (up->msr_saved_flags) |
2907 | check_modem_status(up); |
2908 | |
2909 | if (locked) |
2910 | spin_unlock(&up->port.lock); |
2911 | local_irq_restore(flags); |
2912 | } |
2913 | |
2914 | static int __init serial8250_console_setup(struct console *co, char *options) |
2915 | { |
2916 | struct uart_port *port; |
2917 | int baud = 9600; |
2918 | int bits = 8; |
2919 | int parity = 'n'; |
2920 | int flow = 'n'; |
2921 | |
2922 | /* |
2923 | * Check whether an invalid uart number has been specified, and |
2924 | * if so, search for the first available port that does have |
2925 | * console support. |
2926 | */ |
2927 | if (co->index >= nr_uarts) |
2928 | co->index = 0; |
2929 | port = &serial8250_ports[co->index].port; |
2930 | if (!port->iobase && !port->membase) |
2931 | return -ENODEV; |
2932 | |
2933 | if (options) |
2934 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
2935 | |
2936 | return uart_set_options(port, co, baud, parity, bits, flow); |
2937 | } |
2938 | |
2939 | static int serial8250_console_early_setup(void) |
2940 | { |
2941 | return serial8250_find_port_for_earlycon(); |
2942 | } |
2943 | |
2944 | static struct console serial8250_console = { |
2945 | .name = "ttyS", |
2946 | .write = serial8250_console_write, |
2947 | .device = uart_console_device, |
2948 | .setup = serial8250_console_setup, |
2949 | .early_setup = serial8250_console_early_setup, |
2950 | .flags = CON_PRINTBUFFER, |
2951 | .index = -1, |
2952 | .data = &serial8250_reg, |
2953 | }; |
2954 | |
2955 | static int __init serial8250_console_init(void) |
2956 | { |
2957 | if (nr_uarts > UART_NR) |
2958 | nr_uarts = UART_NR; |
2959 | |
2960 | serial8250_isa_init_ports(); |
2961 | register_console(&serial8250_console); |
2962 | return 0; |
2963 | } |
2964 | console_initcall(serial8250_console_init); |
2965 | |
2966 | int serial8250_find_port(struct uart_port *p) |
2967 | { |
2968 | int line; |
2969 | struct uart_port *port; |
2970 | |
2971 | for (line = 0; line < nr_uarts; line++) { |
2972 | port = &serial8250_ports[line].port; |
2973 | if (uart_match_port(p, port)) |
2974 | return line; |
2975 | } |
2976 | return -ENODEV; |
2977 | } |
2978 | |
2979 | #define SERIAL8250_CONSOLE &serial8250_console |
2980 | #else |
2981 | #define SERIAL8250_CONSOLE NULL |
2982 | #endif |
2983 | |
2984 | static struct uart_driver serial8250_reg = { |
2985 | .owner = THIS_MODULE, |
2986 | .driver_name = "serial", |
2987 | .dev_name = "ttyS", |
2988 | .major = TTY_MAJOR, |
2989 | .minor = 64, |
2990 | .cons = SERIAL8250_CONSOLE, |
2991 | }; |
2992 | |
2993 | /* |
2994 | * early_serial_setup - early registration for 8250 ports |
2995 | * |
2996 | * Setup an 8250 port structure prior to console initialisation. Use |
2997 | * after console initialisation will cause undefined behaviour. |
2998 | */ |
2999 | int __init early_serial_setup(struct uart_port *port) |
3000 | { |
3001 | struct uart_port *p; |
3002 | |
3003 | if (port->line >= ARRAY_SIZE(serial8250_ports)) |
3004 | return -ENODEV; |
3005 | |
3006 | serial8250_isa_init_ports(); |
3007 | p = &serial8250_ports[port->line].port; |
3008 | p->iobase = port->iobase; |
3009 | p->membase = port->membase; |
3010 | p->irq = port->irq; |
3011 | p->irqflags = port->irqflags; |
3012 | p->uartclk = port->uartclk; |
3013 | p->fifosize = port->fifosize; |
3014 | p->regshift = port->regshift; |
3015 | p->iotype = port->iotype; |
3016 | p->flags = port->flags; |
3017 | p->mapbase = port->mapbase; |
3018 | p->private_data = port->private_data; |
3019 | p->type = port->type; |
3020 | p->line = port->line; |
3021 | |
3022 | set_io_from_upio(p); |
3023 | if (port->serial_in) |
3024 | p->serial_in = port->serial_in; |
3025 | if (port->serial_out) |
3026 | p->serial_out = port->serial_out; |
3027 | |
3028 | return 0; |
3029 | } |
3030 | |
3031 | /** |
3032 | * serial8250_suspend_port - suspend one serial port |
3033 | * @line: serial line number |
3034 | * |
3035 | * Suspend one serial port. |
3036 | */ |
3037 | void serial8250_suspend_port(int line) |
3038 | { |
3039 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); |
3040 | } |
3041 | |
3042 | /** |
3043 | * serial8250_resume_port - resume one serial port |
3044 | * @line: serial line number |
3045 | * |
3046 | * Resume one serial port. |
3047 | */ |
3048 | void serial8250_resume_port(int line) |
3049 | { |
3050 | struct uart_8250_port *up = &serial8250_ports[line]; |
3051 | |
3052 | if (up->capabilities & UART_NATSEMI) { |
3053 | unsigned char tmp; |
3054 | |
3055 | /* Ensure it's still in high speed mode */ |
3056 | serial_outp(up, UART_LCR, 0xE0); |
3057 | |
3058 | tmp = serial_in(up, 0x04); /* EXCR2 */ |
3059 | tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ |
3060 | tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ |
3061 | serial_outp(up, 0x04, tmp); |
3062 | |
3063 | serial_outp(up, UART_LCR, 0); |
3064 | } |
3065 | uart_resume_port(&serial8250_reg, &up->port); |
3066 | } |
3067 | |
3068 | /* |
3069 | * Register a set of serial devices attached to a platform device. The |
3070 | * list is terminated with a zero flags entry, which means we expect |
3071 | * all entries to have at least UPF_BOOT_AUTOCONF set. |
3072 | */ |
3073 | static int __devinit serial8250_probe(struct platform_device *dev) |
3074 | { |
3075 | struct plat_serial8250_port *p = dev->dev.platform_data; |
3076 | struct uart_port port; |
3077 | int ret, i, irqflag = 0; |
3078 | |
3079 | memset(&port, 0, sizeof(struct uart_port)); |
3080 | |
3081 | if (share_irqs) |
3082 | irqflag = IRQF_SHARED; |
3083 | |
3084 | for (i = 0; p && p->flags != 0; p++, i++) { |
3085 | port.iobase = p->iobase; |
3086 | port.membase = p->membase; |
3087 | port.irq = p->irq; |
3088 | port.irqflags = p->irqflags; |
3089 | port.uartclk = p->uartclk; |
3090 | port.regshift = p->regshift; |
3091 | port.iotype = p->iotype; |
3092 | port.flags = p->flags; |
3093 | port.mapbase = p->mapbase; |
3094 | port.hub6 = p->hub6; |
3095 | port.private_data = p->private_data; |
3096 | port.type = p->type; |
3097 | port.serial_in = p->serial_in; |
3098 | port.serial_out = p->serial_out; |
3099 | port.dev = &dev->dev; |
3100 | port.irqflags |= irqflag; |
3101 | ret = serial8250_register_port(&port); |
3102 | if (ret < 0) { |
3103 | dev_err(&dev->dev, "unable to register port at index %d " |
3104 | "(IO%lx MEM%llx IRQ%d): %d\n", i, |
3105 | p->iobase, (unsigned long long)p->mapbase, |
3106 | p->irq, ret); |
3107 | } |
3108 | } |
3109 | return 0; |
3110 | } |
3111 | |
3112 | /* |
3113 | * Remove serial ports registered against a platform device. |
3114 | */ |
3115 | static int __devexit serial8250_remove(struct platform_device *dev) |
3116 | { |
3117 | int i; |
3118 | |
3119 | for (i = 0; i < nr_uarts; i++) { |
3120 | struct uart_8250_port *up = &serial8250_ports[i]; |
3121 | |
3122 | if (up->port.dev == &dev->dev) |
3123 | serial8250_unregister_port(i); |
3124 | } |
3125 | return 0; |
3126 | } |
3127 | |
3128 | static int serial8250_suspend(struct platform_device *dev, pm_message_t state) |
3129 | { |
3130 | int i; |
3131 | |
3132 | for (i = 0; i < UART_NR; i++) { |
3133 | struct uart_8250_port *up = &serial8250_ports[i]; |
3134 | |
3135 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
3136 | uart_suspend_port(&serial8250_reg, &up->port); |
3137 | } |
3138 | |
3139 | return 0; |
3140 | } |
3141 | |
3142 | static int serial8250_resume(struct platform_device *dev) |
3143 | { |
3144 | int i; |
3145 | |
3146 | for (i = 0; i < UART_NR; i++) { |
3147 | struct uart_8250_port *up = &serial8250_ports[i]; |
3148 | |
3149 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
3150 | serial8250_resume_port(i); |
3151 | } |
3152 | |
3153 | return 0; |
3154 | } |
3155 | |
3156 | static struct platform_driver serial8250_isa_driver = { |
3157 | .probe = serial8250_probe, |
3158 | .remove = __devexit_p(serial8250_remove), |
3159 | .suspend = serial8250_suspend, |
3160 | .resume = serial8250_resume, |
3161 | .driver = { |
3162 | .name = "serial8250", |
3163 | .owner = THIS_MODULE, |
3164 | }, |
3165 | }; |
3166 | |
3167 | /* |
3168 | * This "device" covers _all_ ISA 8250-compatible serial devices listed |
3169 | * in the table in include/asm/serial.h |
3170 | */ |
3171 | static struct platform_device *serial8250_isa_devs; |
3172 | |
3173 | /* |
3174 | * serial8250_register_port and serial8250_unregister_port allows for |
3175 | * 16x50 serial ports to be configured at run-time, to support PCMCIA |
3176 | * modems and PCI multiport cards. |
3177 | */ |
3178 | static DEFINE_MUTEX(serial_mutex); |
3179 | |
3180 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) |
3181 | { |
3182 | int i; |
3183 | |
3184 | /* |
3185 | * First, find a port entry which matches. |
3186 | */ |
3187 | for (i = 0; i < nr_uarts; i++) |
3188 | if (uart_match_port(&serial8250_ports[i].port, port)) |
3189 | return &serial8250_ports[i]; |
3190 | |
3191 | /* |
3192 | * We didn't find a matching entry, so look for the first |
3193 | * free entry. We look for one which hasn't been previously |
3194 | * used (indicated by zero iobase). |
3195 | */ |
3196 | for (i = 0; i < nr_uarts; i++) |
3197 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && |
3198 | serial8250_ports[i].port.iobase == 0) |
3199 | return &serial8250_ports[i]; |
3200 | |
3201 | /* |
3202 | * That also failed. Last resort is to find any entry which |
3203 | * doesn't have a real port associated with it. |
3204 | */ |
3205 | for (i = 0; i < nr_uarts; i++) |
3206 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) |
3207 | return &serial8250_ports[i]; |
3208 | |
3209 | return NULL; |
3210 | } |
3211 | |
3212 | /** |
3213 | * serial8250_register_port - register a serial port |
3214 | * @port: serial port template |
3215 | * |
3216 | * Configure the serial port specified by the request. If the |
3217 | * port exists and is in use, it is hung up and unregistered |
3218 | * first. |
3219 | * |
3220 | * The port is then probed and if necessary the IRQ is autodetected |
3221 | * If this fails an error is returned. |
3222 | * |
3223 | * On success the port is ready to use and the line number is returned. |
3224 | */ |
3225 | int serial8250_register_port(struct uart_port *port) |
3226 | { |
3227 | struct uart_8250_port *uart; |
3228 | int ret = -ENOSPC; |
3229 | |
3230 | if (port->uartclk == 0) |
3231 | return -EINVAL; |
3232 | |
3233 | mutex_lock(&serial_mutex); |
3234 | |
3235 | uart = serial8250_find_match_or_unused(port); |
3236 | if (uart) { |
3237 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3238 | |
3239 | uart->port.iobase = port->iobase; |
3240 | uart->port.membase = port->membase; |
3241 | uart->port.irq = port->irq; |
3242 | uart->port.irqflags = port->irqflags; |
3243 | uart->port.uartclk = port->uartclk; |
3244 | uart->port.fifosize = port->fifosize; |
3245 | uart->port.regshift = port->regshift; |
3246 | uart->port.iotype = port->iotype; |
3247 | uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; |
3248 | uart->port.mapbase = port->mapbase; |
3249 | uart->port.private_data = port->private_data; |
3250 | if (port->dev) |
3251 | uart->port.dev = port->dev; |
3252 | |
3253 | if (port->flags & UPF_FIXED_TYPE) |
3254 | serial8250_init_fixed_type_port(uart, port->type); |
3255 | |
3256 | set_io_from_upio(&uart->port); |
3257 | /* Possibly override default I/O functions. */ |
3258 | if (port->serial_in) |
3259 | uart->port.serial_in = port->serial_in; |
3260 | if (port->serial_out) |
3261 | uart->port.serial_out = port->serial_out; |
3262 | |
3263 | ret = uart_add_one_port(&serial8250_reg, &uart->port); |
3264 | if (ret == 0) |
3265 | ret = uart->port.line; |
3266 | } |
3267 | mutex_unlock(&serial_mutex); |
3268 | |
3269 | return ret; |
3270 | } |
3271 | EXPORT_SYMBOL(serial8250_register_port); |
3272 | |
3273 | /** |
3274 | * serial8250_unregister_port - remove a 16x50 serial port at runtime |
3275 | * @line: serial line number |
3276 | * |
3277 | * Remove one serial port. This may not be called from interrupt |
3278 | * context. We hand the port back to the our control. |
3279 | */ |
3280 | void serial8250_unregister_port(int line) |
3281 | { |
3282 | struct uart_8250_port *uart = &serial8250_ports[line]; |
3283 | |
3284 | mutex_lock(&serial_mutex); |
3285 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3286 | if (serial8250_isa_devs) { |
3287 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; |
3288 | uart->port.type = PORT_UNKNOWN; |
3289 | uart->port.dev = &serial8250_isa_devs->dev; |
3290 | uart_add_one_port(&serial8250_reg, &uart->port); |
3291 | } else { |
3292 | uart->port.dev = NULL; |
3293 | } |
3294 | mutex_unlock(&serial_mutex); |
3295 | } |
3296 | EXPORT_SYMBOL(serial8250_unregister_port); |
3297 | |
3298 | static int __init serial8250_init(void) |
3299 | { |
3300 | int ret; |
3301 | |
3302 | if (nr_uarts > UART_NR) |
3303 | nr_uarts = UART_NR; |
3304 | |
3305 | printk(KERN_INFO "Serial: 8250/16550 driver, " |
3306 | "%d ports, IRQ sharing %sabled\n", nr_uarts, |
3307 | share_irqs ? "en" : "dis"); |
3308 | |
3309 | #ifdef CONFIG_SPARC |
3310 | ret = sunserial_register_minors(&serial8250_reg, UART_NR); |
3311 | #else |
3312 | serial8250_reg.nr = UART_NR; |
3313 | ret = uart_register_driver(&serial8250_reg); |
3314 | #endif |
3315 | if (ret) |
3316 | goto out; |
3317 | |
3318 | serial8250_isa_devs = platform_device_alloc("serial8250", |
3319 | PLAT8250_DEV_LEGACY); |
3320 | if (!serial8250_isa_devs) { |
3321 | ret = -ENOMEM; |
3322 | goto unreg_uart_drv; |
3323 | } |
3324 | |
3325 | ret = platform_device_add(serial8250_isa_devs); |
3326 | if (ret) |
3327 | goto put_dev; |
3328 | |
3329 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); |
3330 | |
3331 | ret = platform_driver_register(&serial8250_isa_driver); |
3332 | if (ret == 0) |
3333 | goto out; |
3334 | |
3335 | platform_device_del(serial8250_isa_devs); |
3336 | put_dev: |
3337 | platform_device_put(serial8250_isa_devs); |
3338 | unreg_uart_drv: |
3339 | #ifdef CONFIG_SPARC |
3340 | sunserial_unregister_minors(&serial8250_reg, UART_NR); |
3341 | #else |
3342 | uart_unregister_driver(&serial8250_reg); |
3343 | #endif |
3344 | out: |
3345 | return ret; |
3346 | } |
3347 | |
3348 | static void __exit serial8250_exit(void) |
3349 | { |
3350 | struct platform_device *isa_dev = serial8250_isa_devs; |
3351 | |
3352 | /* |
3353 | * This tells serial8250_unregister_port() not to re-register |
3354 | * the ports (thereby making serial8250_isa_driver permanently |
3355 | * in use.) |
3356 | */ |
3357 | serial8250_isa_devs = NULL; |
3358 | |
3359 | platform_driver_unregister(&serial8250_isa_driver); |
3360 | platform_device_unregister(isa_dev); |
3361 | |
3362 | #ifdef CONFIG_SPARC |
3363 | sunserial_unregister_minors(&serial8250_reg, UART_NR); |
3364 | #else |
3365 | uart_unregister_driver(&serial8250_reg); |
3366 | #endif |
3367 | } |
3368 | |
3369 | module_init(serial8250_init); |
3370 | module_exit(serial8250_exit); |
3371 | |
3372 | EXPORT_SYMBOL(serial8250_suspend_port); |
3373 | EXPORT_SYMBOL(serial8250_resume_port); |
3374 | |
3375 | MODULE_LICENSE("GPL"); |
3376 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); |
3377 | |
3378 | module_param(share_irqs, uint, 0644); |
3379 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" |
3380 | " (unsafe)"); |
3381 | |
3382 | module_param(nr_uarts, uint, 0644); |
3383 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); |
3384 | |
3385 | module_param(skip_txen_test, uint, 0644); |
3386 | MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); |
3387 | |
3388 | #ifdef CONFIG_SERIAL_8250_RSA |
3389 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); |
3390 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); |
3391 | #endif |
3392 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); |
3393 |
Branches:
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javiroman/ks7010
jz-2.6.34
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9