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Source at commit 308eb78115de485aca7ffd594cd9b373f1b87ce3 created 10 years 10 months ago. By Lars-Peter Clausen, devicetree stuff | |
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1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 SoC ADC driver |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | * This driver synchronizes access to the JZ4740 ADC core between the |
15 | * JZ4740 battery and hwmon drivers. |
16 | */ |
17 | |
18 | #include <linux/err.h> |
19 | #include <linux/io.h> |
20 | #include <linux/irq.h> |
21 | #include <linux/interrupt.h> |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> |
24 | #include <linux/platform_device.h> |
25 | #include <linux/slab.h> |
26 | #include <linux/spinlock.h> |
27 | |
28 | #include <linux/clk.h> |
29 | #include <linux/mfd/core.h> |
30 | |
31 | #include <linux/jz4740-adc.h> |
32 | |
33 | |
34 | #define JZ_REG_ADC_ENABLE 0x00 |
35 | #define JZ_REG_ADC_CFG 0x04 |
36 | #define JZ_REG_ADC_CTRL 0x08 |
37 | #define JZ_REG_ADC_STATUS 0x0c |
38 | |
39 | #define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10 |
40 | #define JZ_REG_ADC_BATTERY_BASE 0x1c |
41 | #define JZ_REG_ADC_HWMON_BASE 0x20 |
42 | |
43 | #define JZ_ADC_ENABLE_TOUCH BIT(2) |
44 | #define JZ_ADC_ENABLE_BATTERY BIT(1) |
45 | #define JZ_ADC_ENABLE_ADCIN BIT(0) |
46 | |
47 | enum { |
48 | JZ_ADC_IRQ_ADCIN = 0, |
49 | JZ_ADC_IRQ_BATTERY, |
50 | JZ_ADC_IRQ_TOUCH, |
51 | JZ_ADC_IRQ_PENUP, |
52 | JZ_ADC_IRQ_PENDOWN, |
53 | }; |
54 | |
55 | struct jz4740_adc { |
56 | struct resource *mem; |
57 | void __iomem *base; |
58 | |
59 | int irq; |
60 | struct irq_chip_generic *gc; |
61 | |
62 | struct clk *clk; |
63 | atomic_t clk_ref; |
64 | |
65 | spinlock_t lock; |
66 | }; |
67 | |
68 | static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc) |
69 | { |
70 | struct irq_chip_generic *gc = irq_desc_get_handler_data(desc); |
71 | uint8_t status; |
72 | unsigned int i; |
73 | |
74 | status = readb(gc->reg_base + JZ_REG_ADC_STATUS); |
75 | |
76 | for (i = 0; i < 5; ++i) { |
77 | if (status & BIT(i)) |
78 | generic_handle_irq(gc->irq_base + i); |
79 | } |
80 | } |
81 | |
82 | |
83 | /* Refcounting for the ADC clock is done in here instead of in the clock |
84 | * framework, because it is the only clock which is shared between multiple |
85 | * devices and thus is the only clock which needs refcounting */ |
86 | static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc) |
87 | { |
88 | if (atomic_inc_return(&adc->clk_ref) == 1) |
89 | clk_prepare_enable(adc->clk); |
90 | } |
91 | |
92 | static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc) |
93 | { |
94 | if (atomic_dec_return(&adc->clk_ref) == 0) |
95 | clk_disable_unprepare(adc->clk); |
96 | } |
97 | |
98 | static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine, |
99 | bool enabled) |
100 | { |
101 | unsigned long flags; |
102 | uint8_t val; |
103 | |
104 | spin_lock_irqsave(&adc->lock, flags); |
105 | |
106 | val = readb(adc->base + JZ_REG_ADC_ENABLE); |
107 | if (enabled) |
108 | val |= BIT(engine); |
109 | else |
110 | val &= ~BIT(engine); |
111 | writeb(val, adc->base + JZ_REG_ADC_ENABLE); |
112 | |
113 | spin_unlock_irqrestore(&adc->lock, flags); |
114 | } |
115 | |
116 | static int jz4740_adc_cell_enable(struct platform_device *pdev) |
117 | { |
118 | struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); |
119 | |
120 | jz4740_adc_clk_enable(adc); |
121 | jz4740_adc_set_enabled(adc, pdev->id, true); |
122 | |
123 | return 0; |
124 | } |
125 | |
126 | static int jz4740_adc_cell_disable(struct platform_device *pdev) |
127 | { |
128 | struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent); |
129 | |
130 | jz4740_adc_set_enabled(adc, pdev->id, false); |
131 | jz4740_adc_clk_disable(adc); |
132 | |
133 | return 0; |
134 | } |
135 | |
136 | int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val) |
137 | { |
138 | struct jz4740_adc *adc = dev_get_drvdata(dev); |
139 | unsigned long flags; |
140 | uint32_t cfg; |
141 | |
142 | if (!adc) |
143 | return -ENODEV; |
144 | |
145 | spin_lock_irqsave(&adc->lock, flags); |
146 | |
147 | cfg = readl(adc->base + JZ_REG_ADC_CFG); |
148 | |
149 | cfg &= ~mask; |
150 | cfg |= val; |
151 | |
152 | writel(cfg, adc->base + JZ_REG_ADC_CFG); |
153 | |
154 | spin_unlock_irqrestore(&adc->lock, flags); |
155 | |
156 | return 0; |
157 | } |
158 | EXPORT_SYMBOL_GPL(jz4740_adc_set_config); |
159 | |
160 | static struct resource jz4740_iio_resources[] = { |
161 | { |
162 | .start = JZ_ADC_IRQ_ADCIN, |
163 | .flags = IORESOURCE_IRQ, |
164 | }, |
165 | { |
166 | .start = JZ_ADC_IRQ_BATTERY, |
167 | .flags = IORESOURCE_IRQ, |
168 | }, |
169 | { |
170 | .start = JZ_REG_ADC_BATTERY_BASE, |
171 | .end = JZ_REG_ADC_BATTERY_BASE + 7, |
172 | .flags = IORESOURCE_MEM, |
173 | }, |
174 | }; |
175 | |
176 | static const struct mfd_cell jz4740_adc_cells[] = { |
177 | { |
178 | .id = 0, |
179 | .name = "jz4740-iio", |
180 | .num_resources = ARRAY_SIZE(jz4740_iio_resources), |
181 | .resources = jz4740_iio_resources, |
182 | |
183 | .enable = jz4740_adc_cell_enable, |
184 | .disable = jz4740_adc_cell_disable, |
185 | }, |
186 | }; |
187 | |
188 | static int jz4740_adc_probe(struct platform_device *pdev) |
189 | { |
190 | struct irq_chip_generic *gc; |
191 | struct irq_chip_type *ct; |
192 | struct jz4740_adc *adc; |
193 | struct resource *mem_base; |
194 | int ret; |
195 | int irq_base; |
196 | |
197 | adc = devm_kzalloc(&pdev->dev, sizeof(*adc), GFP_KERNEL); |
198 | if (!adc) { |
199 | dev_err(&pdev->dev, "Failed to allocate driver structure\n"); |
200 | return -ENOMEM; |
201 | } |
202 | |
203 | adc->irq = platform_get_irq(pdev, 0); |
204 | if (adc->irq < 0) { |
205 | ret = adc->irq; |
206 | dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); |
207 | return ret; |
208 | } |
209 | |
210 | irq_base = platform_get_irq(pdev, 1); |
211 | if (irq_base < 0) { |
212 | dev_err(&pdev->dev, "Failed to get irq base: %d\n", irq_base); |
213 | return irq_base; |
214 | } |
215 | |
216 | mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
217 | if (!mem_base) { |
218 | dev_err(&pdev->dev, "Failed to get platform mmio resource\n"); |
219 | return -ENOENT; |
220 | } |
221 | |
222 | /* Only request the shared registers for the MFD driver */ |
223 | adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS, |
224 | pdev->name); |
225 | if (!adc->mem) { |
226 | dev_err(&pdev->dev, "Failed to request mmio memory region\n"); |
227 | return -EBUSY; |
228 | } |
229 | |
230 | adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem)); |
231 | if (!adc->base) { |
232 | ret = -EBUSY; |
233 | dev_err(&pdev->dev, "Failed to ioremap mmio memory\n"); |
234 | goto err_release_mem_region; |
235 | } |
236 | |
237 | adc->clk = clk_get(&pdev->dev, "adc"); |
238 | if (IS_ERR(adc->clk)) { |
239 | ret = PTR_ERR(adc->clk); |
240 | dev_err(&pdev->dev, "Failed to get clock: %d\n", ret); |
241 | goto err_iounmap; |
242 | } |
243 | |
244 | spin_lock_init(&adc->lock); |
245 | atomic_set(&adc->clk_ref, 0); |
246 | |
247 | platform_set_drvdata(pdev, adc); |
248 | |
249 | gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base, |
250 | handle_level_irq); |
251 | |
252 | ct = gc->chip_types; |
253 | ct->regs.mask = JZ_REG_ADC_CTRL; |
254 | ct->regs.ack = JZ_REG_ADC_STATUS; |
255 | ct->chip.irq_mask = irq_gc_mask_set_bit; |
256 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; |
257 | ct->chip.irq_ack = irq_gc_ack_set_bit; |
258 | |
259 | irq_setup_generic_chip(gc, IRQ_MSK(5), 0, 0, IRQ_NOPROBE | IRQ_LEVEL); |
260 | |
261 | adc->gc = gc; |
262 | |
263 | irq_set_handler_data(adc->irq, gc); |
264 | irq_set_chained_handler(adc->irq, jz4740_adc_irq_demux); |
265 | |
266 | writeb(0x00, adc->base + JZ_REG_ADC_ENABLE); |
267 | writeb(0xff, adc->base + JZ_REG_ADC_CTRL); |
268 | |
269 | ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells, |
270 | ARRAY_SIZE(jz4740_adc_cells), mem_base, |
271 | irq_base, NULL); |
272 | if (ret < 0) |
273 | goto err_clk_put; |
274 | |
275 | return 0; |
276 | |
277 | err_clk_put: |
278 | clk_put(adc->clk); |
279 | err_iounmap: |
280 | iounmap(adc->base); |
281 | err_release_mem_region: |
282 | release_mem_region(adc->mem->start, resource_size(adc->mem)); |
283 | return ret; |
284 | } |
285 | |
286 | static int jz4740_adc_remove(struct platform_device *pdev) |
287 | { |
288 | struct jz4740_adc *adc = platform_get_drvdata(pdev); |
289 | |
290 | mfd_remove_devices(&pdev->dev); |
291 | |
292 | irq_remove_generic_chip(adc->gc, IRQ_MSK(5), IRQ_NOPROBE | IRQ_LEVEL, 0); |
293 | kfree(adc->gc); |
294 | irq_set_handler_data(adc->irq, NULL); |
295 | irq_set_chained_handler(adc->irq, NULL); |
296 | |
297 | iounmap(adc->base); |
298 | release_mem_region(adc->mem->start, resource_size(adc->mem)); |
299 | |
300 | clk_put(adc->clk); |
301 | |
302 | return 0; |
303 | } |
304 | |
305 | static struct platform_driver jz4740_adc_driver = { |
306 | .probe = jz4740_adc_probe, |
307 | .remove = jz4740_adc_remove, |
308 | .driver = { |
309 | .name = "jz4740-adc", |
310 | .owner = THIS_MODULE, |
311 | }, |
312 | }; |
313 | |
314 | module_platform_driver(jz4740_adc_driver); |
315 | |
316 | MODULE_DESCRIPTION("JZ4740 SoC ADC driver"); |
317 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |
318 | MODULE_LICENSE("GPL"); |
319 | MODULE_ALIAS("platform:jz4740-adc"); |
320 |
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Tags:
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