Root/
Source at commit 30f69f3fb20bd719b5e1bf879339914063d38f47 created 13 years 11 months ago. By Jerome Glisse, drm/radeon/kms: fix rs600 tlb flush | |
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1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
26 | * Jerome Glisse |
27 | */ |
28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
29 | * |
30 | * This file gather function specific to RS600 which is the IGP of |
31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
33 | * the avivo one, bios is an atombios, 3D block are the one of the |
34 | * R4XX family. The GART is different from the RS400 one and is very |
35 | * close to the one of the R600 family (R600 likely being an evolution |
36 | * of the RS600 GART block). |
37 | */ |
38 | #include "drmP.h" |
39 | #include "radeon.h" |
40 | #include "radeon_asic.h" |
41 | #include "atom.h" |
42 | #include "rs600d.h" |
43 | |
44 | #include "rs600_reg_safe.h" |
45 | |
46 | void rs600_gpu_init(struct radeon_device *rdev); |
47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
48 | |
49 | /* hpd for digital panel detect/disconnect */ |
50 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
51 | { |
52 | u32 tmp; |
53 | bool connected = false; |
54 | |
55 | switch (hpd) { |
56 | case RADEON_HPD_1: |
57 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
58 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
59 | connected = true; |
60 | break; |
61 | case RADEON_HPD_2: |
62 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
63 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
64 | connected = true; |
65 | break; |
66 | default: |
67 | break; |
68 | } |
69 | return connected; |
70 | } |
71 | |
72 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
73 | enum radeon_hpd_id hpd) |
74 | { |
75 | u32 tmp; |
76 | bool connected = rs600_hpd_sense(rdev, hpd); |
77 | |
78 | switch (hpd) { |
79 | case RADEON_HPD_1: |
80 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
81 | if (connected) |
82 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
83 | else |
84 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
85 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
86 | break; |
87 | case RADEON_HPD_2: |
88 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
89 | if (connected) |
90 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
91 | else |
92 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
93 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
94 | break; |
95 | default: |
96 | break; |
97 | } |
98 | } |
99 | |
100 | void rs600_hpd_init(struct radeon_device *rdev) |
101 | { |
102 | struct drm_device *dev = rdev->ddev; |
103 | struct drm_connector *connector; |
104 | |
105 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
106 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
107 | switch (radeon_connector->hpd.hpd) { |
108 | case RADEON_HPD_1: |
109 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
110 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
111 | rdev->irq.hpd[0] = true; |
112 | break; |
113 | case RADEON_HPD_2: |
114 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
115 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
116 | rdev->irq.hpd[1] = true; |
117 | break; |
118 | default: |
119 | break; |
120 | } |
121 | } |
122 | if (rdev->irq.installed) |
123 | rs600_irq_set(rdev); |
124 | } |
125 | |
126 | void rs600_hpd_fini(struct radeon_device *rdev) |
127 | { |
128 | struct drm_device *dev = rdev->ddev; |
129 | struct drm_connector *connector; |
130 | |
131 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
132 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
133 | switch (radeon_connector->hpd.hpd) { |
134 | case RADEON_HPD_1: |
135 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
136 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
137 | rdev->irq.hpd[0] = false; |
138 | break; |
139 | case RADEON_HPD_2: |
140 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
141 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
142 | rdev->irq.hpd[1] = false; |
143 | break; |
144 | default: |
145 | break; |
146 | } |
147 | } |
148 | } |
149 | |
150 | /* |
151 | * GART. |
152 | */ |
153 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
154 | { |
155 | uint32_t tmp; |
156 | |
157 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
158 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
159 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
160 | |
161 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
162 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
163 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
164 | |
165 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
166 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
167 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
168 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
169 | } |
170 | |
171 | int rs600_gart_init(struct radeon_device *rdev) |
172 | { |
173 | int r; |
174 | |
175 | if (rdev->gart.table.vram.robj) { |
176 | WARN(1, "RS600 GART already initialized.\n"); |
177 | return 0; |
178 | } |
179 | /* Initialize common gart structure */ |
180 | r = radeon_gart_init(rdev); |
181 | if (r) { |
182 | return r; |
183 | } |
184 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
185 | return radeon_gart_table_vram_alloc(rdev); |
186 | } |
187 | |
188 | int rs600_gart_enable(struct radeon_device *rdev) |
189 | { |
190 | u32 tmp; |
191 | int r, i; |
192 | |
193 | if (rdev->gart.table.vram.robj == NULL) { |
194 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
195 | return -EINVAL; |
196 | } |
197 | r = radeon_gart_table_vram_pin(rdev); |
198 | if (r) |
199 | return r; |
200 | radeon_gart_restore(rdev); |
201 | /* Enable bus master */ |
202 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
203 | WREG32(R_00004C_BUS_CNTL, tmp); |
204 | /* FIXME: setup default page */ |
205 | WREG32_MC(R_000100_MC_PT0_CNTL, |
206 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
207 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
208 | |
209 | for (i = 0; i < 19; i++) { |
210 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
211 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
212 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
213 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
214 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
215 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
216 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
217 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
218 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
219 | } |
220 | /* enable first context */ |
221 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
222 | S_000102_ENABLE_PAGE_TABLE(1) | |
223 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
224 | |
225 | /* disable all other contexts */ |
226 | for (i = 1; i < 8; i++) |
227 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
228 | |
229 | /* setup the page table */ |
230 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
231 | rdev->gart.table_addr); |
232 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
233 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
234 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
235 | |
236 | /* System context maps to VRAM space */ |
237 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
238 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
239 | |
240 | /* enable page tables */ |
241 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
242 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
243 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
244 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
245 | rs600_gart_tlb_flush(rdev); |
246 | rdev->gart.ready = true; |
247 | return 0; |
248 | } |
249 | |
250 | void rs600_gart_disable(struct radeon_device *rdev) |
251 | { |
252 | u32 tmp; |
253 | int r; |
254 | |
255 | /* FIXME: disable out of gart access */ |
256 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
257 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
258 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
259 | if (rdev->gart.table.vram.robj) { |
260 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
261 | if (r == 0) { |
262 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
263 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
264 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
265 | } |
266 | } |
267 | } |
268 | |
269 | void rs600_gart_fini(struct radeon_device *rdev) |
270 | { |
271 | radeon_gart_fini(rdev); |
272 | rs600_gart_disable(rdev); |
273 | radeon_gart_table_vram_free(rdev); |
274 | } |
275 | |
276 | #define R600_PTE_VALID (1 << 0) |
277 | #define R600_PTE_SYSTEM (1 << 1) |
278 | #define R600_PTE_SNOOPED (1 << 2) |
279 | #define R600_PTE_READABLE (1 << 5) |
280 | #define R600_PTE_WRITEABLE (1 << 6) |
281 | |
282 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
283 | { |
284 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
285 | |
286 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
287 | return -EINVAL; |
288 | } |
289 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
290 | addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; |
291 | addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; |
292 | writeq(addr, ((void __iomem *)ptr) + (i * 8)); |
293 | return 0; |
294 | } |
295 | |
296 | int rs600_irq_set(struct radeon_device *rdev) |
297 | { |
298 | uint32_t tmp = 0; |
299 | uint32_t mode_int = 0; |
300 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
301 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
302 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
303 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
304 | |
305 | if (!rdev->irq.installed) { |
306 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); |
307 | WREG32(R_000040_GEN_INT_CNTL, 0); |
308 | return -EINVAL; |
309 | } |
310 | if (rdev->irq.sw_int) { |
311 | tmp |= S_000040_SW_INT_EN(1); |
312 | } |
313 | if (rdev->irq.crtc_vblank_int[0]) { |
314 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
315 | } |
316 | if (rdev->irq.crtc_vblank_int[1]) { |
317 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
318 | } |
319 | if (rdev->irq.hpd[0]) { |
320 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
321 | } |
322 | if (rdev->irq.hpd[1]) { |
323 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
324 | } |
325 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
326 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
327 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
328 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
329 | return 0; |
330 | } |
331 | |
332 | static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) |
333 | { |
334 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
335 | uint32_t irq_mask = ~C_000044_SW_INT; |
336 | u32 tmp; |
337 | |
338 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
339 | *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
340 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { |
341 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
342 | S_006534_D1MODE_VBLANK_ACK(1)); |
343 | } |
344 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
345 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
346 | S_006D34_D2MODE_VBLANK_ACK(1)); |
347 | } |
348 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) { |
349 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
350 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
351 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
352 | } |
353 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) { |
354 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
355 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
356 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
357 | } |
358 | } else { |
359 | *r500_disp_int = 0; |
360 | } |
361 | |
362 | if (irqs) { |
363 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
364 | } |
365 | return irqs & irq_mask; |
366 | } |
367 | |
368 | void rs600_irq_disable(struct radeon_device *rdev) |
369 | { |
370 | u32 tmp; |
371 | |
372 | WREG32(R_000040_GEN_INT_CNTL, 0); |
373 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
374 | /* Wait and acknowledge irq */ |
375 | mdelay(1); |
376 | rs600_irq_ack(rdev, &tmp); |
377 | } |
378 | |
379 | int rs600_irq_process(struct radeon_device *rdev) |
380 | { |
381 | uint32_t status, msi_rearm; |
382 | uint32_t r500_disp_int; |
383 | bool queue_hotplug = false; |
384 | |
385 | status = rs600_irq_ack(rdev, &r500_disp_int); |
386 | if (!status && !r500_disp_int) { |
387 | return IRQ_NONE; |
388 | } |
389 | while (status || r500_disp_int) { |
390 | /* SW interrupt */ |
391 | if (G_000044_SW_INT(status)) |
392 | radeon_fence_process(rdev); |
393 | /* Vertical blank interrupts */ |
394 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) { |
395 | drm_handle_vblank(rdev->ddev, 0); |
396 | rdev->pm.vblank_sync = true; |
397 | wake_up(&rdev->irq.vblank_queue); |
398 | } |
399 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) { |
400 | drm_handle_vblank(rdev->ddev, 1); |
401 | rdev->pm.vblank_sync = true; |
402 | wake_up(&rdev->irq.vblank_queue); |
403 | } |
404 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { |
405 | queue_hotplug = true; |
406 | DRM_DEBUG("HPD1\n"); |
407 | } |
408 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) { |
409 | queue_hotplug = true; |
410 | DRM_DEBUG("HPD2\n"); |
411 | } |
412 | status = rs600_irq_ack(rdev, &r500_disp_int); |
413 | } |
414 | if (queue_hotplug) |
415 | queue_work(rdev->wq, &rdev->hotplug_work); |
416 | if (rdev->msi_enabled) { |
417 | switch (rdev->family) { |
418 | case CHIP_RS600: |
419 | case CHIP_RS690: |
420 | case CHIP_RS740: |
421 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
422 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
423 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
424 | break; |
425 | default: |
426 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; |
427 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); |
428 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); |
429 | break; |
430 | } |
431 | } |
432 | return IRQ_HANDLED; |
433 | } |
434 | |
435 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
436 | { |
437 | if (crtc == 0) |
438 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
439 | else |
440 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
441 | } |
442 | |
443 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
444 | { |
445 | unsigned i; |
446 | |
447 | for (i = 0; i < rdev->usec_timeout; i++) { |
448 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
449 | return 0; |
450 | udelay(1); |
451 | } |
452 | return -1; |
453 | } |
454 | |
455 | void rs600_gpu_init(struct radeon_device *rdev) |
456 | { |
457 | r100_hdp_reset(rdev); |
458 | r420_pipes_init(rdev); |
459 | /* Wait for mc idle */ |
460 | if (rs600_mc_wait_for_idle(rdev)) |
461 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
462 | } |
463 | |
464 | void rs600_mc_init(struct radeon_device *rdev) |
465 | { |
466 | u64 base; |
467 | |
468 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
469 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
470 | rdev->mc.vram_is_ddr = true; |
471 | rdev->mc.vram_width = 128; |
472 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
473 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
474 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
475 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
476 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
477 | base = G_000004_MC_FB_START(base) << 16; |
478 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
479 | radeon_vram_location(rdev, &rdev->mc, base); |
480 | radeon_gtt_location(rdev, &rdev->mc); |
481 | radeon_update_bandwidth_info(rdev); |
482 | } |
483 | |
484 | void rs600_bandwidth_update(struct radeon_device *rdev) |
485 | { |
486 | struct drm_display_mode *mode0 = NULL; |
487 | struct drm_display_mode *mode1 = NULL; |
488 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
489 | /* FIXME: implement full support */ |
490 | |
491 | radeon_update_display_priority(rdev); |
492 | |
493 | if (rdev->mode_info.crtcs[0]->base.enabled) |
494 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
495 | if (rdev->mode_info.crtcs[1]->base.enabled) |
496 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
497 | |
498 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
499 | |
500 | if (rdev->disp_priority == 2) { |
501 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
502 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
503 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
504 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
505 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
506 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
507 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
508 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
509 | } |
510 | } |
511 | |
512 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
513 | { |
514 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
515 | S_000070_MC_IND_CITF_ARB0(1)); |
516 | return RREG32(R_000074_MC_IND_DATA); |
517 | } |
518 | |
519 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
520 | { |
521 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
522 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
523 | WREG32(R_000074_MC_IND_DATA, v); |
524 | } |
525 | |
526 | void rs600_debugfs(struct radeon_device *rdev) |
527 | { |
528 | if (r100_debugfs_rbbm_init(rdev)) |
529 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
530 | } |
531 | |
532 | void rs600_set_safe_registers(struct radeon_device *rdev) |
533 | { |
534 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
535 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
536 | } |
537 | |
538 | static void rs600_mc_program(struct radeon_device *rdev) |
539 | { |
540 | struct rv515_mc_save save; |
541 | |
542 | /* Stops all mc clients */ |
543 | rv515_mc_stop(rdev, &save); |
544 | |
545 | /* Wait for mc idle */ |
546 | if (rs600_mc_wait_for_idle(rdev)) |
547 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
548 | |
549 | /* FIXME: What does AGP means for such chipset ? */ |
550 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
551 | WREG32_MC(R_000006_AGP_BASE, 0); |
552 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
553 | /* Program MC */ |
554 | WREG32_MC(R_000004_MC_FB_LOCATION, |
555 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
556 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
557 | WREG32(R_000134_HDP_FB_LOCATION, |
558 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
559 | |
560 | rv515_mc_resume(rdev, &save); |
561 | } |
562 | |
563 | static int rs600_startup(struct radeon_device *rdev) |
564 | { |
565 | int r; |
566 | |
567 | rs600_mc_program(rdev); |
568 | /* Resume clock */ |
569 | rv515_clock_startup(rdev); |
570 | /* Initialize GPU configuration (# pipes, ...) */ |
571 | rs600_gpu_init(rdev); |
572 | /* Initialize GART (initialize after TTM so we can allocate |
573 | * memory through TTM but finalize after TTM) */ |
574 | r = rs600_gart_enable(rdev); |
575 | if (r) |
576 | return r; |
577 | /* Enable IRQ */ |
578 | rs600_irq_set(rdev); |
579 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
580 | /* 1M ring buffer */ |
581 | r = r100_cp_init(rdev, 1024 * 1024); |
582 | if (r) { |
583 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
584 | return r; |
585 | } |
586 | r = r100_wb_init(rdev); |
587 | if (r) |
588 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
589 | r = r100_ib_init(rdev); |
590 | if (r) { |
591 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
592 | return r; |
593 | } |
594 | return 0; |
595 | } |
596 | |
597 | int rs600_resume(struct radeon_device *rdev) |
598 | { |
599 | /* Make sur GART are not working */ |
600 | rs600_gart_disable(rdev); |
601 | /* Resume clock before doing reset */ |
602 | rv515_clock_startup(rdev); |
603 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
604 | if (radeon_gpu_reset(rdev)) { |
605 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
606 | RREG32(R_000E40_RBBM_STATUS), |
607 | RREG32(R_0007C0_CP_STAT)); |
608 | } |
609 | /* post */ |
610 | atom_asic_init(rdev->mode_info.atom_context); |
611 | /* Resume clock after posting */ |
612 | rv515_clock_startup(rdev); |
613 | /* Initialize surface registers */ |
614 | radeon_surface_init(rdev); |
615 | return rs600_startup(rdev); |
616 | } |
617 | |
618 | int rs600_suspend(struct radeon_device *rdev) |
619 | { |
620 | r100_cp_disable(rdev); |
621 | r100_wb_disable(rdev); |
622 | rs600_irq_disable(rdev); |
623 | rs600_gart_disable(rdev); |
624 | return 0; |
625 | } |
626 | |
627 | void rs600_fini(struct radeon_device *rdev) |
628 | { |
629 | radeon_pm_fini(rdev); |
630 | r100_cp_fini(rdev); |
631 | r100_wb_fini(rdev); |
632 | r100_ib_fini(rdev); |
633 | radeon_gem_fini(rdev); |
634 | rs600_gart_fini(rdev); |
635 | radeon_irq_kms_fini(rdev); |
636 | radeon_fence_driver_fini(rdev); |
637 | radeon_bo_fini(rdev); |
638 | radeon_atombios_fini(rdev); |
639 | kfree(rdev->bios); |
640 | rdev->bios = NULL; |
641 | } |
642 | |
643 | int rs600_init(struct radeon_device *rdev) |
644 | { |
645 | int r; |
646 | |
647 | /* Disable VGA */ |
648 | rv515_vga_render_disable(rdev); |
649 | /* Initialize scratch registers */ |
650 | radeon_scratch_init(rdev); |
651 | /* Initialize surface registers */ |
652 | radeon_surface_init(rdev); |
653 | /* BIOS */ |
654 | if (!radeon_get_bios(rdev)) { |
655 | if (ASIC_IS_AVIVO(rdev)) |
656 | return -EINVAL; |
657 | } |
658 | if (rdev->is_atom_bios) { |
659 | r = radeon_atombios_init(rdev); |
660 | if (r) |
661 | return r; |
662 | } else { |
663 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
664 | return -EINVAL; |
665 | } |
666 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
667 | if (radeon_gpu_reset(rdev)) { |
668 | dev_warn(rdev->dev, |
669 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
670 | RREG32(R_000E40_RBBM_STATUS), |
671 | RREG32(R_0007C0_CP_STAT)); |
672 | } |
673 | /* check if cards are posted or not */ |
674 | if (radeon_boot_test_post_card(rdev) == false) |
675 | return -EINVAL; |
676 | |
677 | /* Initialize clocks */ |
678 | radeon_get_clock_info(rdev->ddev); |
679 | /* Initialize power management */ |
680 | radeon_pm_init(rdev); |
681 | /* initialize memory controller */ |
682 | rs600_mc_init(rdev); |
683 | rs600_debugfs(rdev); |
684 | /* Fence driver */ |
685 | r = radeon_fence_driver_init(rdev); |
686 | if (r) |
687 | return r; |
688 | r = radeon_irq_kms_init(rdev); |
689 | if (r) |
690 | return r; |
691 | /* Memory manager */ |
692 | r = radeon_bo_init(rdev); |
693 | if (r) |
694 | return r; |
695 | r = rs600_gart_init(rdev); |
696 | if (r) |
697 | return r; |
698 | rs600_set_safe_registers(rdev); |
699 | rdev->accel_working = true; |
700 | r = rs600_startup(rdev); |
701 | if (r) { |
702 | /* Somethings want wront with the accel init stop accel */ |
703 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
704 | r100_cp_fini(rdev); |
705 | r100_wb_fini(rdev); |
706 | r100_ib_fini(rdev); |
707 | rs600_gart_fini(rdev); |
708 | radeon_irq_kms_fini(rdev); |
709 | rdev->accel_working = false; |
710 | } |
711 | return 0; |
712 | } |
713 |
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v2.6.34-rc5
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