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Source at commit 33b7f489d8e3742f85c0ff76fbf6ed5863a01e0e created 11 years 10 months ago. By Maarten ter Huurne, MIPS: JZ4740: Acquire and enable DMA controller clock | |
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1 | /* |
2 | * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> |
3 | * JZ4740 SoC DMA support |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. |
9 | * |
10 | * You should have received a copy of the GNU General Public License along |
11 | * with this program; if not, write to the Free Software Foundation, Inc., |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
13 | * |
14 | */ |
15 | |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> |
18 | #include <linux/spinlock.h> |
19 | #include <linux/clk.h> |
20 | #include <linux/interrupt.h> |
21 | |
22 | #include <linux/dma-mapping.h> |
23 | #include <asm/mach-jz4740/dma.h> |
24 | #include <asm/mach-jz4740/base.h> |
25 | |
26 | #define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20) |
27 | #define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20) |
28 | #define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20) |
29 | #define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20) |
30 | #define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20) |
31 | #define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20) |
32 | #define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20) |
33 | |
34 | #define JZ_REG_DMA_CTRL 0x300 |
35 | #define JZ_REG_DMA_IRQ 0x304 |
36 | #define JZ_REG_DMA_DOORBELL 0x308 |
37 | #define JZ_REG_DMA_DOORBELL_SET 0x30C |
38 | |
39 | #define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31) |
40 | #define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6) |
41 | #define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4) |
42 | #define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3) |
43 | #define JZ_DMA_STATUS_CTRL_HALT BIT(2) |
44 | #define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1) |
45 | #define JZ_DMA_STATUS_CTRL_ENABLE BIT(0) |
46 | |
47 | #define JZ_DMA_CMD_SRC_INC BIT(23) |
48 | #define JZ_DMA_CMD_DST_INC BIT(22) |
49 | #define JZ_DMA_CMD_RDIL_MASK (0xf << 16) |
50 | #define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14) |
51 | #define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12) |
52 | #define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8) |
53 | #define JZ_DMA_CMD_BLOCK_MODE BIT(7) |
54 | #define JZ_DMA_CMD_DESC_VALID BIT(4) |
55 | #define JZ_DMA_CMD_DESC_VALID_MODE BIT(3) |
56 | #define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2) |
57 | #define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1) |
58 | #define JZ_DMA_CMD_LINK_ENABLE BIT(0) |
59 | |
60 | #define JZ_DMA_CMD_FLAGS_OFFSET 22 |
61 | #define JZ_DMA_CMD_RDIL_OFFSET 16 |
62 | #define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14 |
63 | #define JZ_DMA_CMD_DST_WIDTH_OFFSET 12 |
64 | #define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8 |
65 | #define JZ_DMA_CMD_MODE_OFFSET 7 |
66 | |
67 | #define JZ_DMA_CTRL_PRIORITY_012345 (0x0 << 8) |
68 | #define JZ_DMA_CTRL_PRIORITY_023145 (0x1 << 8) |
69 | #define JZ_DMA_CTRL_PRIORITY_201345 (0x2 << 8) |
70 | #define JZ_DMA_CTRL_PRIORITY_ROUND_ROBIN (0x3 << 8) |
71 | #define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8) |
72 | #define JZ_DMA_CTRL_HALT BIT(3) |
73 | #define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2) |
74 | #define JZ_DMA_CTRL_ENABLE BIT(0) |
75 | |
76 | |
77 | static void __iomem *jz4740_dma_base; |
78 | static spinlock_t jz4740_dma_lock; |
79 | |
80 | static inline uint32_t jz4740_dma_read(size_t reg) |
81 | { |
82 | return readl(jz4740_dma_base + reg); |
83 | } |
84 | |
85 | static inline void jz4740_dma_write(size_t reg, uint32_t val) |
86 | { |
87 | writel(val, jz4740_dma_base + reg); |
88 | } |
89 | |
90 | static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask) |
91 | { |
92 | uint32_t val2; |
93 | val2 = jz4740_dma_read(reg); |
94 | val2 &= ~mask; |
95 | val2 |= val; |
96 | jz4740_dma_write(reg, val2); |
97 | } |
98 | |
99 | struct jz4740_dma_chan { |
100 | unsigned int id; |
101 | void *dev; |
102 | const char *name; |
103 | |
104 | enum jz4740_dma_flags flags; |
105 | uint32_t transfer_shift; |
106 | |
107 | jz4740_dma_complete_callback_t complete_cb; |
108 | |
109 | unsigned used:1; |
110 | }; |
111 | |
112 | #define JZ4740_DMA_CHANNEL(_id) { .id = _id } |
113 | |
114 | struct jz4740_dma_chan jz4740_dma_channels[] = { |
115 | JZ4740_DMA_CHANNEL(0), |
116 | JZ4740_DMA_CHANNEL(1), |
117 | JZ4740_DMA_CHANNEL(2), |
118 | JZ4740_DMA_CHANNEL(3), |
119 | JZ4740_DMA_CHANNEL(4), |
120 | JZ4740_DMA_CHANNEL(5), |
121 | }; |
122 | |
123 | struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name, |
124 | int prio) |
125 | { |
126 | unsigned int i; |
127 | struct jz4740_dma_chan *dma = NULL; |
128 | |
129 | if (prio < 0 || prio > 1) |
130 | return NULL; |
131 | |
132 | spin_lock(&jz4740_dma_lock); |
133 | |
134 | for (i = prio * 3; i < prio * 3 + 3; ++i) { |
135 | if (!jz4740_dma_channels[i].used) { |
136 | dma = &jz4740_dma_channels[i]; |
137 | dma->used = 1; |
138 | break; |
139 | } |
140 | } |
141 | |
142 | spin_unlock(&jz4740_dma_lock); |
143 | |
144 | if (!dma) |
145 | return NULL; |
146 | |
147 | dma->dev = dev; |
148 | dma->name = name; |
149 | |
150 | return dma; |
151 | } |
152 | EXPORT_SYMBOL_GPL(jz4740_dma_request); |
153 | |
154 | void jz4740_dma_configure(struct jz4740_dma_chan *dma, |
155 | const struct jz4740_dma_config *config) |
156 | { |
157 | uint32_t cmd; |
158 | |
159 | switch (config->transfer_size) { |
160 | case JZ4740_DMA_TRANSFER_SIZE_2BYTE: |
161 | dma->transfer_shift = 1; |
162 | break; |
163 | case JZ4740_DMA_TRANSFER_SIZE_4BYTE: |
164 | dma->transfer_shift = 2; |
165 | break; |
166 | case JZ4740_DMA_TRANSFER_SIZE_16BYTE: |
167 | dma->transfer_shift = 4; |
168 | break; |
169 | case JZ4740_DMA_TRANSFER_SIZE_32BYTE: |
170 | dma->transfer_shift = 5; |
171 | break; |
172 | default: |
173 | dma->transfer_shift = 0; |
174 | break; |
175 | } |
176 | |
177 | cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET; |
178 | cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET; |
179 | cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET; |
180 | cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET; |
181 | cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET; |
182 | cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE; |
183 | |
184 | jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd); |
185 | jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0); |
186 | jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type); |
187 | } |
188 | EXPORT_SYMBOL_GPL(jz4740_dma_configure); |
189 | |
190 | void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src) |
191 | { |
192 | jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src); |
193 | } |
194 | EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr); |
195 | |
196 | void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst) |
197 | { |
198 | jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst); |
199 | } |
200 | EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr); |
201 | |
202 | void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count) |
203 | { |
204 | count >>= dma->transfer_shift; |
205 | jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count); |
206 | } |
207 | EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count); |
208 | |
209 | void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma, |
210 | jz4740_dma_complete_callback_t cb) |
211 | { |
212 | dma->complete_cb = cb; |
213 | } |
214 | EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb); |
215 | |
216 | void jz4740_dma_free(struct jz4740_dma_chan *dma) |
217 | { |
218 | dma->dev = NULL; |
219 | dma->complete_cb = NULL; |
220 | dma->used = 0; |
221 | } |
222 | EXPORT_SYMBOL_GPL(jz4740_dma_free); |
223 | |
224 | void jz4740_dma_enable(struct jz4740_dma_chan *dma) |
225 | { |
226 | jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), |
227 | JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE, |
228 | JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC | |
229 | JZ_DMA_STATUS_CTRL_ENABLE); |
230 | |
231 | jz4740_dma_write_mask(JZ_REG_DMA_CTRL, |
232 | JZ_DMA_CTRL_ENABLE, |
233 | JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE); |
234 | } |
235 | EXPORT_SYMBOL_GPL(jz4740_dma_enable); |
236 | |
237 | void jz4740_dma_disable(struct jz4740_dma_chan *dma) |
238 | { |
239 | jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0, |
240 | JZ_DMA_STATUS_CTRL_ENABLE); |
241 | } |
242 | EXPORT_SYMBOL_GPL(jz4740_dma_disable); |
243 | |
244 | uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma) |
245 | { |
246 | uint32_t residue; |
247 | residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id)); |
248 | return residue << dma->transfer_shift; |
249 | } |
250 | EXPORT_SYMBOL_GPL(jz4740_dma_get_residue); |
251 | |
252 | static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma) |
253 | { |
254 | (void) jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id)); |
255 | |
256 | jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0, |
257 | JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE); |
258 | |
259 | if (dma->complete_cb) |
260 | dma->complete_cb(dma, 0, dma->dev); |
261 | } |
262 | |
263 | static irqreturn_t jz4740_dma_irq(int irq, void *dev_id) |
264 | { |
265 | uint32_t irq_status; |
266 | unsigned int i; |
267 | |
268 | irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ); |
269 | |
270 | for (i = 0; i < 6; ++i) { |
271 | if (irq_status & (1 << i)) |
272 | jz4740_dma_chan_irq(&jz4740_dma_channels[i]); |
273 | } |
274 | |
275 | return IRQ_HANDLED; |
276 | } |
277 | |
278 | static int jz4740_dma_init(void) |
279 | { |
280 | struct clk *clk; |
281 | unsigned int ret; |
282 | |
283 | jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400); |
284 | if (!jz4740_dma_base) |
285 | return -EBUSY; |
286 | |
287 | spin_lock_init(&jz4740_dma_lock); |
288 | |
289 | clk = clk_get(NULL, "dma"); |
290 | if (IS_ERR(clk)) { |
291 | ret = PTR_ERR(clk); |
292 | printk(KERN_ERR "JZ4740 DMA: Failed to request clock: %d\n", |
293 | ret); |
294 | goto err_iounmap; |
295 | } |
296 | |
297 | ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL); |
298 | if (ret) { |
299 | printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret); |
300 | goto err_clkput; |
301 | } |
302 | |
303 | clk_enable(clk); |
304 | jz4740_dma_write_mask(JZ_REG_DMA_CTRL, |
305 | JZ_DMA_CTRL_PRIORITY_ROUND_ROBIN, |
306 | JZ_DMA_CTRL_PRIORITY_MASK); |
307 | |
308 | return 0; |
309 | |
310 | err_clkput: |
311 | clk_put(clk); |
312 | |
313 | err_iounmap: |
314 | iounmap(jz4740_dma_base); |
315 | return ret; |
316 | } |
317 | arch_initcall(jz4740_dma_init); |
318 |
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