Root/drivers/net/au1000_eth.h

1/*
2 *
3 * Alchemy Au1x00 ethernet driver include file
4 *
5 * Author: Pete Popov <ppopov@mvista.com>
6 *
7 * Copyright 2001 MontaVista Software Inc.
8 *
9 * ########################################################################
10 *
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 *
24 * ########################################################################
25 *
26 *
27 */
28
29
30#define MAC_IOSIZE 0x10000
31#define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
32#define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
33
34#define NUM_RX_BUFFS 4
35#define NUM_TX_BUFFS 4
36#define MAX_BUF_SIZE 2048
37
38#define ETH_TX_TIMEOUT HZ/4
39#define MAC_MIN_PKT_SIZE 64
40
41#define MULTICAST_FILTER_LIMIT 64
42
43/*
44 * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
45 * boundary for both, receive and transmit.
46 */
47typedef struct db_dest {
48    struct db_dest *pnext;
49    volatile u32 *vaddr;
50    dma_addr_t dma_addr;
51} db_dest_t;
52
53/*
54 * The transmit and receive descriptors are memory
55 * mapped registers.
56 */
57typedef struct tx_dma {
58    u32 status;
59    u32 buff_stat;
60    u32 len;
61    u32 pad;
62} tx_dma_t;
63
64typedef struct rx_dma {
65    u32 status;
66    u32 buff_stat;
67    u32 pad[2];
68} rx_dma_t;
69
70
71/*
72 * MAC control registers, memory mapped.
73 */
74typedef struct mac_reg {
75    u32 control;
76    u32 mac_addr_high;
77    u32 mac_addr_low;
78    u32 multi_hash_high;
79    u32 multi_hash_low;
80    u32 mii_control;
81    u32 mii_data;
82    u32 flow_control;
83    u32 vlan1_tag;
84    u32 vlan2_tag;
85} mac_reg_t;
86
87
88struct au1000_private {
89    db_dest_t *pDBfree;
90    db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS];
91    volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA];
92    volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA];
93    db_dest_t *rx_db_inuse[NUM_RX_DMA];
94    db_dest_t *tx_db_inuse[NUM_TX_DMA];
95    u32 rx_head;
96    u32 tx_head;
97    u32 tx_tail;
98    u32 tx_full;
99
100    int mac_id;
101
102    int mac_enabled; /* whether MAC is currently enabled and running (req. for mdio) */
103
104    int old_link; /* used by au1000_adjust_link */
105    int old_speed;
106    int old_duplex;
107
108    struct phy_device *phy_dev;
109    struct mii_bus *mii_bus;
110
111    /* These variables are just for quick access to certain regs addresses. */
112    volatile mac_reg_t *mac; /* mac registers */
113    volatile u32 *enable; /* address of MAC Enable Register */
114
115    u32 vaddr; /* virtual address of rx/tx buffers */
116    dma_addr_t dma_addr; /* dma address of rx/tx buffers */
117
118    spinlock_t lock; /* Serialise access to device */
119};
120

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