Root/drivers/net/bnx2x_fw_defs.h

1/* bnx2x_fw_defs.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10
11#define CSTORM_ASSERT_LIST_INDEX_OFFSET \
12    (IS_E1H_OFFSET ? 0x7000 : 0x1000)
13#define CSTORM_ASSERT_LIST_OFFSET(idx) \
14    (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
15#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
16    (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
17    ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
18    0x40) + (index * 0x4)))
19#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
20    (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
21    ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
22#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
23    (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
24    ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
25#define CSTORM_FUNCTION_MODE_OFFSET \
26    (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
27#define CSTORM_HC_BTR_OFFSET(port) \
28    (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
29#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
30    (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
31    (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
32    (index * 0x4)))
33#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
34    (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
35    (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
36    (index * 0x4)))
37#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
38    (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
39    (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
40#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
41    (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
42    (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
43#define CSTORM_STATS_FLAGS_OFFSET(function) \
44    (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
45    (function * 0x8)))
46#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
47    (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
48#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
49    (IS_E1H_OFFSET ? 0xa000 : 0x1000)
50#define TSTORM_ASSERT_LIST_OFFSET(idx) \
51    (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53    (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \
54    : (0x9c0 + (port * 0x130) + (client_id * 0x10)))
55#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
56    (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)
57#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
58    (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
59    ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
60    0x28) + (index * 0x4)))
61#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
62    (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
63    ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
64#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
65    (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
66    ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
67#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
68    (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
69    (function * 0x8)))
70#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
71    (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
72    (function * 0x38)))
73#define TSTORM_FUNCTION_MODE_OFFSET \
74    (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
75#define TSTORM_HC_BTR_OFFSET(port) \
76    (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
77#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
78    (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
79    (function * 0x80)))
80#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
81#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
82    (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
83    (function * 0x38)))
84#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
85    (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
86    0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))
87#define TSTORM_STATS_FLAGS_OFFSET(function) \
88    (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
89    (function * 0x8)))
90#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)
91#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
92#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
93#define USTORM_ASSERT_LIST_INDEX_OFFSET \
94    (IS_E1H_OFFSET ? 0x8960 : 0x1000)
95#define USTORM_ASSERT_LIST_OFFSET(idx) \
96    (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
97#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
98    (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \
99    (0x5330 + (port * 0x260) + (clientId * 0x20)))
100#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
101    (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \
102    ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
103    0x40) + (index * 0x4)))
104#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
105    (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
106    ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
107#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
108    (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
109    ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
110#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
111    (IS_E1H_OFFSET ? (0x8020 + (port * 0x4b0) + (clientId * 0x30)) : \
112    0xffffffff)
113#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
114    (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1d98 + \
115    (function * 0x8)))
116#define USTORM_FUNCTION_MODE_OFFSET \
117    (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
118#define USTORM_HC_BTR_OFFSET(port) \
119    (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
120#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
121    (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \
122    (0x5328 + (port * 0x260) + (clientId * 0x20)))
123#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
124    (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \
125    (function * 0x8)))
126#define USTORM_PAUSE_ENABLED_OFFSET(port) \
127    (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
128#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
129    (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
130    0x28)) : (0x4740 + (port * 0x2d0) + (stats_counter_id * 0x28)))
131#define USTORM_RX_PRODS_OFFSET(port, client_id) \
132    (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \
133    : (0x5318 + (port * 0x260) + (client_id * 0x20)))
134#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
135    (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
136    (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
137    (index * 0x4)))
138#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
139    (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
140    (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
141    (index * 0x4)))
142#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
143    (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
144    (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
145#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
146    (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
147    (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
148#define USTORM_STATS_FLAGS_OFFSET(function) \
149    (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1d80 + \
150    (function * 0x8)))
151#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
152    (IS_E1H_OFFSET ? 0x9000 : 0x1000)
153#define XSTORM_ASSERT_LIST_OFFSET(idx) \
154    (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
155#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
156    (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))
157#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
158    (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
159    ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
160    0x28) + (index * 0x4)))
161#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
162    (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
163    ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
164#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
165    (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
166    ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
167#define XSTORM_E1HOV_OFFSET(function) \
168    (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)
169#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
170    (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
171    (function * 0x8)))
172#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
173    (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \
174    (function * 0x90)))
175#define XSTORM_FUNCTION_MODE_OFFSET \
176    (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)
177#define XSTORM_HC_BTR_OFFSET(port) \
178    (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
179#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
180    (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
181    0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
182#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
183    (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \
184    (function * 0x90)))
185#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
186    (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
187    (function * 0x10)))
188#define XSTORM_SPQ_PROD_OFFSET(function) \
189    (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
190    (function * 0x10)))
191#define XSTORM_STATS_FLAGS_OFFSET(function) \
192    (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
193    (function * 0x8)))
194#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
195
196/**
197* This file defines HSI constants for the ETH flow
198*/
199#ifdef _EVEREST_MICROCODE
200#include "microcode_constants.h"
201#include "eth_rx_bd.h"
202#include "eth_tx_bd.h"
203#include "eth_rx_cqe.h"
204#include "eth_rx_sge.h"
205#include "eth_rx_cqe_next_page.h"
206#endif
207
208/* RSS hash types */
209#define DEFAULT_HASH_TYPE 0
210#define IPV4_HASH_TYPE 1
211#define TCP_IPV4_HASH_TYPE 2
212#define IPV6_HASH_TYPE 3
213#define TCP_IPV6_HASH_TYPE 4
214
215
216/* Ethernet Ring parameters */
217#define X_ETH_LOCAL_RING_SIZE 13
218#define FIRST_BD_IN_PKT 0
219#define PARSE_BD_INDEX 1
220#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
221
222
223/* Rx ring params */
224#define U_ETH_LOCAL_BD_RING_SIZE 16
225#define U_ETH_LOCAL_SGE_RING_SIZE 12
226#define U_ETH_SGL_SIZE 8
227
228
229#define U_ETH_BDS_PER_PAGE_MASK \
230    ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
231#define U_ETH_CQE_PER_PAGE_MASK \
232    ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
233#define U_ETH_SGES_PER_PAGE_MASK \
234    ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
235
236#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
237    (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
238
239
240#define TU_ETH_CQES_PER_PAGE \
241    (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
242#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
243#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
244
245#define U_ETH_UNDEFINED_Q 0xFF
246
247/* values of command IDs in the ramrod message */
248#define RAMROD_CMD_ID_ETH_PORT_SETUP 80
249#define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85
250#define RAMROD_CMD_ID_ETH_STAT_QUERY 90
251#define RAMROD_CMD_ID_ETH_UPDATE 100
252#define RAMROD_CMD_ID_ETH_HALT 105
253#define RAMROD_CMD_ID_ETH_SET_MAC 110
254#define RAMROD_CMD_ID_ETH_CFC_DEL 115
255#define RAMROD_CMD_ID_ETH_PORT_DEL 120
256#define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125
257
258
259/* command values for set mac command */
260#define T_ETH_MAC_COMMAND_SET 0
261#define T_ETH_MAC_COMMAND_INVALIDATE 1
262
263#define T_ETH_INDIRECTION_TABLE_SIZE 128
264
265/*The CRC32 seed, that is used for the hash(reduction) multicast address */
266#define T_ETH_CRC32_HASH_SEED 0x00000000
267
268/* Maximal L2 clients supported */
269#define ETH_MAX_RX_CLIENTS_E1 19
270#define ETH_MAX_RX_CLIENTS_E1H 25
271
272/* Maximal aggregation queues supported */
273#define ETH_MAX_AGGREGATION_QUEUES_E1 32
274#define ETH_MAX_AGGREGATION_QUEUES_E1H 64
275
276/* ETH RSS modes */
277#define ETH_RSS_MODE_DISABLED 0
278#define ETH_RSS_MODE_REGULAR 1
279
280
281/**
282* This file defines HSI constants common to all microcode flows
283*/
284
285/* Connection types */
286#define ETH_CONNECTION_TYPE 0
287#define TOE_CONNECTION_TYPE 1
288#define RDMA_CONNECTION_TYPE 2
289#define ISCSI_CONNECTION_TYPE 3
290#define FCOE_CONNECTION_TYPE 4
291#define RESERVED_CONNECTION_TYPE_0 5
292#define RESERVED_CONNECTION_TYPE_1 6
293#define RESERVED_CONNECTION_TYPE_2 7
294
295
296#define PROTOCOL_STATE_BIT_OFFSET 6
297
298#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
299#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
300#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
301
302/* microcode fixed page page size 4K (chains and ring segments) */
303#define MC_PAGE_SIZE 4096
304
305
306/* Host coalescing constants */
307
308/* index numbers */
309#define HC_USTORM_DEF_SB_NUM_INDICES 8
310#define HC_CSTORM_DEF_SB_NUM_INDICES 8
311#define HC_XSTORM_DEF_SB_NUM_INDICES 4
312#define HC_TSTORM_DEF_SB_NUM_INDICES 4
313#define HC_USTORM_SB_NUM_INDICES 4
314#define HC_CSTORM_SB_NUM_INDICES 4
315
316/* index values - which counter to update */
317
318#define HC_INDEX_U_TOE_RX_CQ_CONS 0
319#define HC_INDEX_U_ETH_RX_CQ_CONS 1
320#define HC_INDEX_U_ETH_RX_BD_CONS 2
321#define HC_INDEX_U_FCOE_EQ_CONS 3
322
323#define HC_INDEX_C_TOE_TX_CQ_CONS 0
324#define HC_INDEX_C_ETH_TX_CQ_CONS 1
325#define HC_INDEX_C_ISCSI_EQ_CONS 2
326
327#define HC_INDEX_DEF_X_SPQ_CONS 0
328
329#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
330#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
331#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
332#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
333#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
334#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
335
336#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
337#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
338#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
339#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
340
341
342/* used by the driver to get the SB offset */
343#define USTORM_ID 0
344#define CSTORM_ID 1
345#define XSTORM_ID 2
346#define TSTORM_ID 3
347#define ATTENTION_ID 4
348
349/* max number of slow path commands per port */
350#define MAX_RAMRODS_PER_PORT 8
351
352/* values for RX ETH CQE type field */
353#define RX_ETH_CQE_TYPE_ETH_FASTPATH 0
354#define RX_ETH_CQE_TYPE_ETH_RAMROD 1
355
356
357/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
358#define EMULATION_FREQUENCY_FACTOR 1600
359#define FPGA_FREQUENCY_FACTOR 100
360
361#define TIMERS_TICK_SIZE_CHIP (1e-3)
362#define TIMERS_TICK_SIZE_EMUL \
363 ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
364#define TIMERS_TICK_SIZE_FPGA \
365 ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
366
367#define TSEMI_CLK1_RESUL_CHIP (1e-3)
368#define TSEMI_CLK1_RESUL_EMUL \
369 ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
370#define TSEMI_CLK1_RESUL_FPGA \
371 ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
372
373#define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP)
374#define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL)
375#define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA)
376
377#define XSEMI_CLK1_RESUL_CHIP (1e-3)
378#define XSEMI_CLK1_RESUL_EMUL \
379 ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
380#define XSEMI_CLK1_RESUL_FPGA \
381 ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
382
383#define XSEMI_CLK2_RESUL_CHIP (1e-6)
384#define XSEMI_CLK2_RESUL_EMUL \
385 ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
386#define XSEMI_CLK2_RESUL_FPGA \
387 ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
388
389#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
390#define SDM_TIMER_TICK_RESUL_EMUL \
391 ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
392#define SDM_TIMER_TICK_RESUL_FPGA \
393 ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
394
395
396/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
397#define XSTORM_IP_ID_ROLL_HALF 0x8000
398#define XSTORM_IP_ID_ROLL_ALL 0
399
400#define FW_LOG_LIST_SIZE 50
401
402#define NUM_OF_PROTOCOLS 4
403#define NUM_OF_SAFC_BITS 16
404#define MAX_COS_NUMBER 4
405#define MAX_T_STAT_COUNTER_ID 18
406#define MAX_X_STAT_COUNTER_ID 18
407#define MAX_U_STAT_COUNTER_ID 18
408
409
410#define UNKNOWN_ADDRESS 0
411#define UNICAST_ADDRESS 1
412#define MULTICAST_ADDRESS 2
413#define BROADCAST_ADDRESS 3
414
415#define SINGLE_FUNCTION 0
416#define MULTI_FUNCTION 1
417
418#define IP_V4 0
419#define IP_V6 1
420
421

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od-2011-09-18
v2.6.34-rc5
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