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Root/drivers/net/davinci_emac.c

1	/*
2	* DaVinci Ethernet Medium Access Controller
3	*
4	* DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
5	*
6	* Copyright (C) 2009 Texas Instruments.
7	*
8	* ---------------------------------------------------------------------------
9	*
10	* This program is free software; you can redistribute it and/or modify
11	* it under the terms of the GNU General Public License as published by
12	* the Free Software Foundation; either version 2 of the License, or
13	* (at your option) any later version.
14	*
15	* This program is distributed in the hope that it will be useful,
16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18	* GNU General Public License for more details.
19	*
20	* You should have received a copy of the GNU General Public License
21	* along with this program; if not, write to the Free Software
22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23	* ---------------------------------------------------------------------------
24	* History:
25	* 0-5 A number of folks worked on this driver in bits and pieces but the major
26	* contribution came from Suraj Iyer and Anant Gole
27	* 6.0 Anant Gole - rewrote the driver as per Linux conventions
28	* 6.1 Chaithrika U S - added support for Gigabit and RMII features,
29	* PHY layer usage
30	*/
31
32	/** Pending Items in this driver:
33	* 1. Use Linux cache infrastcture for DMA'ed memory (dma_xxx functions)
34	*/
35
36	#include <linux/module.h>
37	#include <linux/kernel.h>
38	#include <linux/sched.h>
39	#include <linux/string.h>
40	#include <linux/timer.h>
41	#include <linux/errno.h>
42	#include <linux/in.h>
43	#include <linux/ioport.h>
44	#include <linux/slab.h>
45	#include <linux/mm.h>
46	#include <linux/interrupt.h>
47	#include <linux/init.h>
48	#include <linux/netdevice.h>
49	#include <linux/etherdevice.h>
50	#include <linux/skbuff.h>
51	#include <linux/ethtool.h>
52	#include <linux/highmem.h>
53	#include <linux/proc_fs.h>
54	#include <linux/ctype.h>
55	#include <linux/version.h>
56	#include <linux/spinlock.h>
57	#include <linux/dma-mapping.h>
58	#include <linux/clk.h>
59	#include <linux/platform_device.h>
60	#include <linux/semaphore.h>
61	#include <linux/phy.h>
62	#include <linux/bitops.h>
63	#include <linux/io.h>
64	#include <linux/uaccess.h>
65
66	#include <asm/irq.h>
67	#include <asm/page.h>
68
69	#include <mach/emac.h>
70
71	static int debug_level;
72	module_param(debug_level, int, 0);
73	MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
74
75	/* Netif debug messages possible */
76	#define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV \| \
77	NETIF_MSG_PROBE \| \
78	NETIF_MSG_LINK \| \
79	NETIF_MSG_TIMER \| \
80	NETIF_MSG_IFDOWN \| \
81	NETIF_MSG_IFUP \| \
82	NETIF_MSG_RX_ERR \| \
83	NETIF_MSG_TX_ERR \| \
84	NETIF_MSG_TX_QUEUED \| \
85	NETIF_MSG_INTR \| \
86	NETIF_MSG_TX_DONE \| \
87	NETIF_MSG_RX_STATUS \| \
88	NETIF_MSG_PKTDATA \| \
89	NETIF_MSG_HW \| \
90	NETIF_MSG_WOL)
91
92	/* version info */
93	#define EMAC_MAJOR_VERSION 6
94	#define EMAC_MINOR_VERSION 1
95	#define EMAC_MODULE_VERSION "6.1"
96	MODULE_VERSION(EMAC_MODULE_VERSION);
97	static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
98
99	/* Configuration items */
100	#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
101	#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
102	#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
103	#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
104	#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
105	#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
106	#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
107	#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
108	#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
109	#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
110	#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
111	#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
112
113	#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
114	#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
115
116	#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
117	#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
118	#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
119	#define EMAC_DEF_TX_CH (0) /* Default 0th channel */
120	#define EMAC_DEF_RX_CH (0) /* Default 0th channel */
121	#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
122	#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
123	#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
124	#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
125
126	/* Buffer descriptor parameters */
127	#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
128	#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
129
130	/* EMAC register related defines */
131	#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
132	#define EMAC_NUM_MULTICAST_BITS (64)
133	#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
134	#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
135	#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
136	#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
137	#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
138	#define EMAC_INT_MASK_CLEAR (0xFF)
139
140	/* RX MBP register bit positions */
141	#define EMAC_RXMBP_PASSCRC_MASK BIT(30)
142	#define EMAC_RXMBP_QOSEN_MASK BIT(29)
143	#define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
144	#define EMAC_RXMBP_CMFEN_MASK BIT(24)
145	#define EMAC_RXMBP_CSFEN_MASK BIT(23)
146	#define EMAC_RXMBP_CEFEN_MASK BIT(22)
147	#define EMAC_RXMBP_CAFEN_MASK BIT(21)
148	#define EMAC_RXMBP_PROMCH_SHIFT (16)
149	#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
150	#define EMAC_RXMBP_BROADEN_MASK BIT(13)
151	#define EMAC_RXMBP_BROADCH_SHIFT (8)
152	#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
153	#define EMAC_RXMBP_MULTIEN_MASK BIT(5)
154	#define EMAC_RXMBP_MULTICH_SHIFT (0)
155	#define EMAC_RXMBP_MULTICH_MASK (0x7)
156	#define EMAC_RXMBP_CHMASK (0x7)
157
158	/* EMAC register definitions/bit maps used */
159	# define EMAC_MBP_RXPROMISC (0x00200000)
160	# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
161	# define EMAC_MBP_RXBCAST (0x00002000)
162	# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
163	# define EMAC_MBP_RXMCAST (0x00000020)
164	# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
165
166	/* EMAC mac_control register */
167	#define EMAC_MACCONTROL_TXPTYPE (0x200)
168	#define EMAC_MACCONTROL_TXPACEEN (0x40)
169	#define EMAC_MACCONTROL_MIIEN (0x20)
170	#define EMAC_MACCONTROL_GIGABITEN (0x80)
171	#define EMAC_MACCONTROL_GIGABITEN_SHIFT (7)
172	#define EMAC_MACCONTROL_FULLDUPLEXEN (0x1)
173	#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
174
175	/* GIGABIT MODE related bits */
176	#define EMAC_DM646X_MACCONTORL_GMIIEN BIT(5)
177	#define EMAC_DM646X_MACCONTORL_GIG BIT(7)
178	#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
179
180	/* EMAC mac_status register */
181	#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
182	#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
183	#define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
184	#define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
185	#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
186	#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
187	#define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
188	#define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
189
190	/* EMAC RX register masks */
191	#define EMAC_RX_MAX_LEN_MASK (0xFFFF)
192	#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
193
194	/* MAC_IN_VECTOR (0x180) register bit fields */
195	#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT (0x20000)
196	#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT (0x10000)
197	#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC (0x0100)
198	#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC (0x01)
199
200	/** NOTE:: For DM646x the IN_VECTOR has changed */
201	#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
202	#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
203
204	/* CPPI bit positions */
205	#define EMAC_CPPI_SOP_BIT BIT(31)
206	#define EMAC_CPPI_EOP_BIT BIT(30)
207	#define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
208	#define EMAC_CPPI_EOQ_BIT BIT(28)
209	#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
210	#define EMAC_CPPI_PASS_CRC_BIT BIT(26)
211	#define EMAC_RX_BD_BUF_SIZE (0xFFFF)
212	#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
213	#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
214
215	/* Max hardware defines */
216	#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
217	#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
218
219	/* EMAC Peripheral Device Register Memory Layout structure */
220	#define EMAC_TXIDVER 0x0
221	#define EMAC_TXCONTROL 0x4
222	#define EMAC_TXTEARDOWN 0x8
223	#define EMAC_RXIDVER 0x10
224	#define EMAC_RXCONTROL 0x14
225	#define EMAC_RXTEARDOWN 0x18
226	#define EMAC_TXINTSTATRAW 0x80
227	#define EMAC_TXINTSTATMASKED 0x84
228	#define EMAC_TXINTMASKSET 0x88
229	#define EMAC_TXINTMASKCLEAR 0x8C
230	#define EMAC_MACINVECTOR 0x90
231
232	#define EMAC_DM646X_MACEOIVECTOR 0x94
233
234	#define EMAC_RXINTSTATRAW 0xA0
235	#define EMAC_RXINTSTATMASKED 0xA4
236	#define EMAC_RXINTMASKSET 0xA8
237	#define EMAC_RXINTMASKCLEAR 0xAC
238	#define EMAC_MACINTSTATRAW 0xB0
239	#define EMAC_MACINTSTATMASKED 0xB4
240	#define EMAC_MACINTMASKSET 0xB8
241	#define EMAC_MACINTMASKCLEAR 0xBC
242
243	#define EMAC_RXMBPENABLE 0x100
244	#define EMAC_RXUNICASTSET 0x104
245	#define EMAC_RXUNICASTCLEAR 0x108
246	#define EMAC_RXMAXLEN 0x10C
247	#define EMAC_RXBUFFEROFFSET 0x110
248	#define EMAC_RXFILTERLOWTHRESH 0x114
249
250	#define EMAC_MACCONTROL 0x160
251	#define EMAC_MACSTATUS 0x164
252	#define EMAC_EMCONTROL 0x168
253	#define EMAC_FIFOCONTROL 0x16C
254	#define EMAC_MACCONFIG 0x170
255	#define EMAC_SOFTRESET 0x174
256	#define EMAC_MACSRCADDRLO 0x1D0
257	#define EMAC_MACSRCADDRHI 0x1D4
258	#define EMAC_MACHASH1 0x1D8
259	#define EMAC_MACHASH2 0x1DC
260	#define EMAC_MACADDRLO 0x500
261	#define EMAC_MACADDRHI 0x504
262	#define EMAC_MACINDEX 0x508
263
264	/* EMAC HDP and Completion registors */
265	#define EMAC_TXHDP(ch) (0x600 + (ch * 4))
266	#define EMAC_RXHDP(ch) (0x620 + (ch * 4))
267	#define EMAC_TXCP(ch) (0x640 + (ch * 4))
268	#define EMAC_RXCP(ch) (0x660 + (ch * 4))
269
270	/* EMAC statistics registers */
271	#define EMAC_RXGOODFRAMES 0x200
272	#define EMAC_RXBCASTFRAMES 0x204
273	#define EMAC_RXMCASTFRAMES 0x208
274	#define EMAC_RXPAUSEFRAMES 0x20C
275	#define EMAC_RXCRCERRORS 0x210
276	#define EMAC_RXALIGNCODEERRORS 0x214
277	#define EMAC_RXOVERSIZED 0x218
278	#define EMAC_RXJABBER 0x21C
279	#define EMAC_RXUNDERSIZED 0x220
280	#define EMAC_RXFRAGMENTS 0x224
281	#define EMAC_RXFILTERED 0x228
282	#define EMAC_RXQOSFILTERED 0x22C
283	#define EMAC_RXOCTETS 0x230
284	#define EMAC_TXGOODFRAMES 0x234
285	#define EMAC_TXBCASTFRAMES 0x238
286	#define EMAC_TXMCASTFRAMES 0x23C
287	#define EMAC_TXPAUSEFRAMES 0x240
288	#define EMAC_TXDEFERRED 0x244
289	#define EMAC_TXCOLLISION 0x248
290	#define EMAC_TXSINGLECOLL 0x24C
291	#define EMAC_TXMULTICOLL 0x250
292	#define EMAC_TXEXCESSIVECOLL 0x254
293	#define EMAC_TXLATECOLL 0x258
294	#define EMAC_TXUNDERRUN 0x25C
295	#define EMAC_TXCARRIERSENSE 0x260
296	#define EMAC_TXOCTETS 0x264
297	#define EMAC_NETOCTETS 0x280
298	#define EMAC_RXSOFOVERRUNS 0x284
299	#define EMAC_RXMOFOVERRUNS 0x288
300	#define EMAC_RXDMAOVERRUNS 0x28C
301
302	/* EMAC DM644x control registers */
303	#define EMAC_CTRL_EWCTL (0x4)
304	#define EMAC_CTRL_EWINTTCNT (0x8)
305
306	/* EMAC MDIO related */
307	/* Mask & Control defines */
308	#define MDIO_CONTROL_CLKDIV (0xFF)
309	#define MDIO_CONTROL_ENABLE BIT(30)
310	#define MDIO_USERACCESS_GO BIT(31)
311	#define MDIO_USERACCESS_WRITE BIT(30)
312	#define MDIO_USERACCESS_READ (0)
313	#define MDIO_USERACCESS_REGADR (0x1F << 21)
314	#define MDIO_USERACCESS_PHYADR (0x1F << 16)
315	#define MDIO_USERACCESS_DATA (0xFFFF)
316	#define MDIO_USERPHYSEL_LINKSEL BIT(7)
317	#define MDIO_VER_MODID (0xFFFF << 16)
318	#define MDIO_VER_REVMAJ (0xFF << 8)
319	#define MDIO_VER_REVMIN (0xFF)
320
321	#define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
322	#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
323	#define MDIO_CONTROL (0x04)
324
325	/* EMAC DM646X control module registers */
326	#define EMAC_DM646X_CMRXINTEN (0x14)
327	#define EMAC_DM646X_CMTXINTEN (0x18)
328
329	/* EMAC EOI codes for C0 */
330	#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
331	#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
332
333	/** net_buf_obj: EMAC network bufferdata structure
334	*
335	* EMAC network buffer data structure
336	*/
337	struct emac_netbufobj {
338	void *buf_token;
339	char *data_ptr;
340	int length;
341	};
342
343	/** net_pkt_obj: EMAC network packet data structure
344	*
345	* EMAC network packet data structure - supports buffer list (for future)
346	*/
347	struct emac_netpktobj {
348	void pkt_token; / data token may hold tx/rx chan id */
349	struct emac_netbufobj buf_list; / array of network buffer objects */
350	int num_bufs;
351	int pkt_length;
352	};
353
354	/** emac_tx_bd: EMAC TX Buffer descriptor data structure
355	*
356	* EMAC TX Buffer descriptor data structure
357	*/
358	struct emac_tx_bd {
359	int h_next;
360	int buff_ptr;
361	int off_b_len;
362	int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
363	struct emac_tx_bd __iomem *next;
364	void *buf_token;
365	};
366
367	/** emac_txch: EMAC TX Channel data structure
368	*
369	* EMAC TX Channel data structure
370	*/
371	struct emac_txch {
372	/* Config related */
373	u32 num_bd;
374	u32 service_max;
375
376	/* CPPI specific */
377	u32 alloc_size;
378	void __iomem *bd_mem;
379	struct emac_tx_bd __iomem *bd_pool_head;
380	struct emac_tx_bd __iomem *active_queue_head;
381	struct emac_tx_bd __iomem *active_queue_tail;
382	struct emac_tx_bd __iomem *last_hw_bdprocessed;
383	u32 queue_active;
384	u32 teardown_pending;
385	u32 *tx_complete;
386
387	/** statistics */
388	u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
389	u32 mis_queued_packets;
390	u32 queue_reinit;
391	u32 end_of_queue_add;
392	u32 out_of_tx_bd;
393	u32 no_active_pkts; /* IRQ when there were no packets to process */
394	u32 active_queue_count;
395	};
396
397	/** emac_rx_bd: EMAC RX Buffer descriptor data structure
398	*
399	* EMAC RX Buffer descriptor data structure
400	*/
401	struct emac_rx_bd {
402	int h_next;
403	int buff_ptr;
404	int off_b_len;
405	int mode;
406	struct emac_rx_bd __iomem *next;
407	void *data_ptr;
408	void *buf_token;
409	};
410
411	/** emac_rxch: EMAC RX Channel data structure
412	*
413	* EMAC RX Channel data structure
414	*/
415	struct emac_rxch {
416	/* configuration info */
417	u32 num_bd;
418	u32 service_max;
419	u32 buf_size;
420	char mac_addr[6];
421
422	/** CPPI specific */
423	u32 alloc_size;
424	void __iomem *bd_mem;
425	struct emac_rx_bd __iomem *bd_pool_head;
426	struct emac_rx_bd __iomem *active_queue_head;
427	struct emac_rx_bd __iomem *active_queue_tail;
428	u32 queue_active;
429	u32 teardown_pending;
430
431	/* packet and buffer objects */
432	struct emac_netpktobj pkt_queue;
433	struct emac_netbufobj buf_queue;
434
435	/** statistics */
436	u32 proc_count; /* number of times emac_rx_bdproc is called */
437	u32 processed_bd;
438	u32 recycled_bd;
439	u32 out_of_rx_bd;
440	u32 out_of_rx_buffers;
441	u32 queue_reinit;
442	u32 end_of_queue_add;
443	u32 end_of_queue;
444	u32 mis_queued_packets;
445	};
446
447	/* emac_priv: EMAC private data structure
448	*
449	* EMAC adapter private data structure
450	*/
451	struct emac_priv {
452	u32 msg_enable;
453	struct net_device *ndev;
454	struct platform_device *pdev;
455	struct napi_struct napi;
456	char mac_addr[6];
457	spinlock_t tx_lock;
458	spinlock_t rx_lock;
459	void __iomem *remap_addr;
460	u32 emac_base_phys;
461	void __iomem *emac_base;
462	void __iomem *ctrl_base;
463	void __iomem *emac_ctrl_ram;
464	u32 ctrl_ram_size;
465	struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
466	struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
467	u32 link; /* 1=link on, 0=link off */
468	u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
469	u32 duplex; /* Link duplex: 0=Half, 1=Full */
470	u32 rx_buf_size;
471	u32 isr_count;
472	u8 rmii_en;
473	u8 version;
474	struct net_device_stats net_dev_stats;
475	u32 mac_hash1;
476	u32 mac_hash2;
477	u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
478	u32 rx_addr_type;
479	/* periodic timer required for MDIO polling */
480	struct timer_list periodic_timer;
481	u32 periodic_ticks;
482	u32 timer_active;
483	u32 phy_mask;
484	/* mii_bus,phy members */
485	struct mii_bus *mii_bus;
486	struct phy_device *phydev;
487	spinlock_t lock;
488	};
489
490	/* clock frequency for EMAC */
491	static struct clk *emac_clk;
492	static unsigned long emac_bus_frequency;
493	static unsigned long mdio_max_freq;
494
495	/* EMAC internal utility function */
496	static inline u32 emac_virt_to_phys(void __iomem *addr)
497	{
498	return (u32 __force) io_v2p(addr);
499	}
500
501	/* Cache macros - Packet buffers would be from skb pool which is cached */
502	#define EMAC_VIRT_NOCACHE(addr) (addr)
503	#define EMAC_CACHE_INVALIDATE(addr, size) \
504	dma_cache_maint((void *)addr, size, DMA_FROM_DEVICE)
505	#define EMAC_CACHE_WRITEBACK(addr, size) \
506	dma_cache_maint((void *)addr, size, DMA_TO_DEVICE)
507	#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
508	dma_cache_maint((void *)addr, size, DMA_BIDIRECTIONAL)
509
510	/* DM644x does not have BD's in cached memory - so no cache functions */
511	#define BD_CACHE_INVALIDATE(addr, size)
512	#define BD_CACHE_WRITEBACK(addr, size)
513	#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
514
515	/* EMAC TX Host Error description strings */
516	static char *emac_txhost_errcodes[16] = {
517	"No error", "SOP error", "Ownership bit not set in SOP buffer",
518	"Zero Next Buffer Descriptor Pointer Without EOP",
519	"Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
520	"Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
521	"Reserved", "Reserved", "Reserved", "Reserved"
522	};
523
524	/* EMAC RX Host Error description strings */
525	static char *emac_rxhost_errcodes[16] = {
526	"No error", "Reserved", "Ownership bit not set in input buffer",
527	"Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
528	"Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
529	"Reserved", "Reserved", "Reserved", "Reserved"
530	};
531
532	/* Helper macros */
533	#define emac_read(reg) ioread32(priv->emac_base + (reg))
534	#define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
535
536	#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
537	#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
538
539	#define emac_mdio_read(reg) ioread32(bus->priv + (reg))
540	#define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
541
542	/**
543	* emac_dump_regs: Dump important EMAC registers to debug terminal
544	* @priv: The DaVinci EMAC private adapter structure
545	*
546	* Executes ethtool set cmd & sets phy mode
547	*
548	*/
549	static void emac_dump_regs(struct emac_priv *priv)
550	{
551	struct device *emac_dev = &priv->ndev->dev;
552
553	/* Print important registers in EMAC */
554	dev_info(emac_dev, "EMAC Basic registers\n");
555	dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
556	emac_ctrl_read(EMAC_CTRL_EWCTL),
557	emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
558	dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
559	emac_read(EMAC_TXIDVER),
560	((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
561	emac_read(EMAC_RXIDVER),
562	((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
563	dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
564	"TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
565	emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
566	dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
567	"RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
568	emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
569	dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
570	"MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
571	emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
572	dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
573	emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
574	dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
575	"RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
576	emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
577	dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
578	"MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
579	emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
580	dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
581	emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
582	dev_info(emac_dev, "EMAC Statistics\n");
583	dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
584	emac_read(EMAC_RXGOODFRAMES));
585	dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
586	emac_read(EMAC_RXBCASTFRAMES));
587	dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
588	emac_read(EMAC_RXMCASTFRAMES));
589	dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
590	emac_read(EMAC_RXPAUSEFRAMES));
591	dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
592	emac_read(EMAC_RXCRCERRORS));
593	dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
594	emac_read(EMAC_RXALIGNCODEERRORS));
595	dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
596	emac_read(EMAC_RXOVERSIZED));
597	dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
598	emac_read(EMAC_RXJABBER));
599	dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
600	emac_read(EMAC_RXUNDERSIZED));
601	dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
602	emac_read(EMAC_RXFRAGMENTS));
603	dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
604	emac_read(EMAC_RXFILTERED));
605	dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
606	emac_read(EMAC_RXQOSFILTERED));
607	dev_info(emac_dev, "EMAC: rx_octets:%d\n",
608	emac_read(EMAC_RXOCTETS));
609	dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
610	emac_read(EMAC_TXGOODFRAMES));
611	dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
612	emac_read(EMAC_TXBCASTFRAMES));
613	dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
614	emac_read(EMAC_TXMCASTFRAMES));
615	dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
616	emac_read(EMAC_TXPAUSEFRAMES));
617	dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
618	emac_read(EMAC_TXDEFERRED));
619	dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
620	emac_read(EMAC_TXCOLLISION));
621	dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
622	emac_read(EMAC_TXSINGLECOLL));
623	dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
624	emac_read(EMAC_TXMULTICOLL));
625	dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
626	emac_read(EMAC_TXEXCESSIVECOLL));
627	dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
628	emac_read(EMAC_TXLATECOLL));
629	dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
630	emac_read(EMAC_TXUNDERRUN));
631	dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
632	emac_read(EMAC_TXCARRIERSENSE));
633	dev_info(emac_dev, "EMAC: tx_octets:%d\n",
634	emac_read(EMAC_TXOCTETS));
635	dev_info(emac_dev, "EMAC: net_octets:%d\n",
636	emac_read(EMAC_NETOCTETS));
637	dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
638	emac_read(EMAC_RXSOFOVERRUNS));
639	dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
640	emac_read(EMAC_RXMOFOVERRUNS));
641	dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
642	emac_read(EMAC_RXDMAOVERRUNS));
643	}
644
645	/*************************************************************************
646	* EMAC MDIO/Phy Functionality
647	*************************************************************************/
648	/**
649	* emac_get_drvinfo: Get EMAC driver information
650	* @ndev: The DaVinci EMAC network adapter
651	* @info: ethtool info structure containing name and version
652	*
653	* Returns EMAC driver information (name and version)
654	*
655	*/
656	static void emac_get_drvinfo(struct net_device *ndev,
657	struct ethtool_drvinfo *info)
658	{
659	strcpy(info->driver, emac_version_string);
660	strcpy(info->version, EMAC_MODULE_VERSION);
661	}
662
663	/**
664	* emac_get_settings: Get EMAC settings
665	* @ndev: The DaVinci EMAC network adapter
666	* @ecmd: ethtool command
667	*
668	* Executes ethool get command
669	*
670	*/
671	static int emac_get_settings(struct net_device *ndev,
672	struct ethtool_cmd *ecmd)
673	{
674	struct emac_priv *priv = netdev_priv(ndev);
675	if (priv->phy_mask)
676	return phy_ethtool_gset(priv->phydev, ecmd);
677	else
678	return -EOPNOTSUPP;
679
680	}
681
682	/**
683	* emac_set_settings: Set EMAC settings
684	* @ndev: The DaVinci EMAC network adapter
685	* @ecmd: ethtool command
686	*
687	* Executes ethool set command
688	*
689	*/
690	static int emac_set_settings(struct net_device ndev, struct ethtool_cmd ecmd)
691	{
692	struct emac_priv *priv = netdev_priv(ndev);
693	if (priv->phy_mask)
694	return phy_ethtool_sset(priv->phydev, ecmd);
695	else
696	return -EOPNOTSUPP;
697
698	}
699
700	/**
701	* ethtool_ops: DaVinci EMAC Ethtool structure
702	*
703	* Ethtool support for EMAC adapter
704	*
705	*/
706	static const struct ethtool_ops ethtool_ops = {
707	.get_drvinfo = emac_get_drvinfo,
708	.get_settings = emac_get_settings,
709	.set_settings = emac_set_settings,
710	.get_link = ethtool_op_get_link,
711	};
712
713	/**
714	* emac_update_phystatus: Update Phy status
715	* @priv: The DaVinci EMAC private adapter structure
716	*
717	* Updates phy status and takes action for network queue if required
718	* based upon link status
719	*
720	*/
721	static void emac_update_phystatus(struct emac_priv *priv)
722	{
723	u32 mac_control;
724	u32 new_duplex;
725	u32 cur_duplex;
726	struct net_device *ndev = priv->ndev;
727
728	mac_control = emac_read(EMAC_MACCONTROL);
729	cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
730	DUPLEX_FULL : DUPLEX_HALF;
731	if (priv->phy_mask)
732	new_duplex = priv->phydev->duplex;
733	else
734	new_duplex = DUPLEX_FULL;
735
736	/* We get called only if link has changed (speed/duplex/status) */
737	if ((priv->link) && (new_duplex != cur_duplex)) {
738	priv->duplex = new_duplex;
739	if (DUPLEX_FULL == priv->duplex)
740	mac_control \|= (EMAC_MACCONTROL_FULLDUPLEXEN);
741	else
742	mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
743	}
744
745	if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
746	mac_control = emac_read(EMAC_MACCONTROL);
747	mac_control \|= (EMAC_DM646X_MACCONTORL_GMIIEN \|
748	EMAC_DM646X_MACCONTORL_GIG \|
749	EMAC_DM646X_MACCONTORL_GIGFORCE);
750	} else {
751	/* Clear the GIG bit and GIGFORCE bit */
752	mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE \|
753	EMAC_DM646X_MACCONTORL_GIG);
754
755	if (priv->rmii_en && (priv->speed == SPEED_100))
756	mac_control \|= EMAC_MACCONTROL_RMIISPEED_MASK;
757	else
758	mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
759	}
760
761	/* Update mac_control if changed */
762	emac_write(EMAC_MACCONTROL, mac_control);
763
764	if (priv->link) {
765	/* link ON */
766	if (!netif_carrier_ok(ndev))
767	netif_carrier_on(ndev);
768	/* reactivate the transmit queue if it is stopped */
769	if (netif_running(ndev) && netif_queue_stopped(ndev))
770	netif_wake_queue(ndev);
771	} else {
772	/* link OFF */
773	if (netif_carrier_ok(ndev))
774	netif_carrier_off(ndev);
775	if (!netif_queue_stopped(ndev))
776	netif_stop_queue(ndev);
777	}
778	}
779
780	/**
781	* hash_get: Calculate hash value from mac address
782	* @addr: mac address to delete from hash table
783	*
784	* Calculates hash value from mac address
785	*
786	*/
787	static u32 hash_get(u8 *addr)
788	{
789	u32 hash;
790	u8 tmpval;
791	int cnt;
792	hash = 0;
793
794	for (cnt = 0; cnt < 2; cnt++) {
795	tmpval = *addr++;
796	hash ^= (tmpval >> 2) ^ (tmpval << 4);
797	tmpval = *addr++;
798	hash ^= (tmpval >> 4) ^ (tmpval << 2);
799	tmpval = *addr++;
800	hash ^= (tmpval >> 6) ^ (tmpval);
801	}
802
803	return hash & 0x3F;
804	}
805
806	/**
807	* hash_add: Hash function to add mac addr from hash table
808	* @priv: The DaVinci EMAC private adapter structure
809	* mac_addr: mac address to delete from hash table
810	*
811	* Adds mac address to the internal hash table
812	*
813	*/
814	static int hash_add(struct emac_priv priv, u8 mac_addr)
815	{
816	struct device *emac_dev = &priv->ndev->dev;
817	u32 rc = 0;
818	u32 hash_bit;
819	u32 hash_value = hash_get(mac_addr);
820
821	if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
822	if (netif_msg_drv(priv)) {
823	dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
824	"Hash %08x, should not be greater than %08x",
825	hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
826	}
827	return -1;
828	}
829
830	/* set the hash bit only if not previously set */
831	if (priv->multicast_hash_cnt[hash_value] == 0) {
832	rc = 1; /* hash value changed */
833	if (hash_value < 32) {
834	hash_bit = BIT(hash_value);
835	priv->mac_hash1 \|= hash_bit;
836	} else {
837	hash_bit = BIT((hash_value - 32));
838	priv->mac_hash2 \|= hash_bit;
839	}
840	}
841
842	/* incr counter for num of mcast addr's mapped to "this" hash bit */
843	++priv->multicast_hash_cnt[hash_value];
844
845	return rc;
846	}
847
848	/**
849	* hash_del: Hash function to delete mac addr from hash table
850	* @priv: The DaVinci EMAC private adapter structure
851	* mac_addr: mac address to delete from hash table
852	*
853	* Removes mac address from the internal hash table
854	*
855	*/
856	static int hash_del(struct emac_priv priv, u8 mac_addr)
857	{
858	u32 hash_value;
859	u32 hash_bit;
860
861	hash_value = hash_get(mac_addr);
862	if (priv->multicast_hash_cnt[hash_value] > 0) {
863	/* dec cntr for num of mcast addr's mapped to this hash bit */
864	--priv->multicast_hash_cnt[hash_value];
865	}
866
867	/* if counter still > 0, at least one multicast address refers
868	* to this hash bit. so return 0 */
869	if (priv->multicast_hash_cnt[hash_value] > 0)
870	return 0;
871
872	if (hash_value < 32) {
873	hash_bit = BIT(hash_value);
874	priv->mac_hash1 &= ~hash_bit;
875	} else {
876	hash_bit = BIT((hash_value - 32));
877	priv->mac_hash2 &= ~hash_bit;
878	}
879
880	/* return 1 to indicate change in mac_hash registers reqd */
881	return 1;
882	}
883
884	/* EMAC multicast operation */
885	#define EMAC_MULTICAST_ADD 0
886	#define EMAC_MULTICAST_DEL 1
887	#define EMAC_ALL_MULTI_SET 2
888	#define EMAC_ALL_MULTI_CLR 3
889
890	/**
891	* emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
892	* @priv: The DaVinci EMAC private adapter structure
893	* @action: multicast operation to perform
894	* mac_addr: mac address to set
895	*
896	* Set multicast addresses in EMAC adapter - internal function
897	*
898	*/
899	static void emac_add_mcast(struct emac_priv priv, u32 action, u8 mac_addr)
900	{
901	struct device *emac_dev = &priv->ndev->dev;
902	int update = -1;
903
904	switch (action) {
905	case EMAC_MULTICAST_ADD:
906	update = hash_add(priv, mac_addr);
907	break;
908	case EMAC_MULTICAST_DEL:
909	update = hash_del(priv, mac_addr);
910	break;
911	case EMAC_ALL_MULTI_SET:
912	update = 1;
913	priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
914	priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
915	break;
916	case EMAC_ALL_MULTI_CLR:
917	update = 1;
918	priv->mac_hash1 = 0;
919	priv->mac_hash2 = 0;
920	memset(&(priv->multicast_hash_cnt[0]), 0,
921	sizeof(priv->multicast_hash_cnt[0]) *
922	EMAC_NUM_MULTICAST_BITS);
923	break;
924	default:
925	if (netif_msg_drv(priv))
926	dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
927	": bad operation %d", action);
928	break;
929	}
930
931	/* write to the hardware only if the register status chances */
932	if (update > 0) {
933	emac_write(EMAC_MACHASH1, priv->mac_hash1);
934	emac_write(EMAC_MACHASH2, priv->mac_hash2);
935	}
936	}
937
938	/**
939	* emac_dev_mcast_set: Set multicast address in the EMAC adapter
940	* @ndev: The DaVinci EMAC network adapter
941	*
942	* Set multicast addresses in EMAC adapter
943	*
944	*/
945	static void emac_dev_mcast_set(struct net_device *ndev)
946	{
947	u32 mbp_enable;
948	struct emac_priv *priv = netdev_priv(ndev);
949
950	mbp_enable = emac_read(EMAC_RXMBPENABLE);
951	if (ndev->flags & IFF_PROMISC) {
952	mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
953	mbp_enable \|= (EMAC_MBP_RXPROMISC);
954	} else {
955	mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
956	if ((ndev->flags & IFF_ALLMULTI) \|\|
957	(ndev->mc_count > EMAC_DEF_MAX_MULTICAST_ADDRESSES)) {
958	mbp_enable = (mbp_enable \| EMAC_MBP_RXMCAST);
959	emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
960	}
961	if (ndev->mc_count > 0) {
962	struct dev_mc_list *mc_ptr;
963	mbp_enable = (mbp_enable \| EMAC_MBP_RXMCAST);
964	emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
965	/* program multicast address list into EMAC hardware */
966	for (mc_ptr = ndev->mc_list; mc_ptr;
967	mc_ptr = mc_ptr->next) {
968	emac_add_mcast(priv, EMAC_MULTICAST_ADD,
969	(u8 *)mc_ptr->dmi_addr);
970	}
971	} else {
972	mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
973	emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
974	}
975	}
976	/* Set mbp config register */
977	emac_write(EMAC_RXMBPENABLE, mbp_enable);
978	}
979
980	/*************************************************************************
981	* EMAC Hardware manipulation
982	*************************************************************************/
983
984	/**
985	* emac_int_disable: Disable EMAC module interrupt (from adapter)
986	* @priv: The DaVinci EMAC private adapter structure
987	*
988	* Disable EMAC interrupt on the adapter
989	*
990	*/
991	static void emac_int_disable(struct emac_priv *priv)
992	{
993	if (priv->version == EMAC_VERSION_2) {
994	unsigned long flags;
995
996	local_irq_save(flags);
997
998	/* Program C0_Int_En to zero to turn off
999	* interrupts to the CPU */
1000	emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1001	emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1002	/* NOTE: Rx Threshold and Misc interrupts are not disabled */
1003
1004	local_irq_restore(flags);
1005
1006	} else {
1007	/* Set DM644x control registers for interrupt control */
1008	emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1009	}
1010	}
1011
1012	/**
1013	* emac_int_enable: Enable EMAC module interrupt (from adapter)
1014	* @priv: The DaVinci EMAC private adapter structure
1015	*
1016	* Enable EMAC interrupt on the adapter
1017	*
1018	*/
1019	static void emac_int_enable(struct emac_priv *priv)
1020	{
1021	if (priv->version == EMAC_VERSION_2) {
1022	emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1023	emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1024
1025	/* In addition to turning on interrupt Enable, we need
1026	* ack by writing appropriate values to the EOI
1027	* register */
1028
1029	/* NOTE: Rx Threshold and Misc interrupts are not enabled */
1030
1031	/* ack rxen only then a new pulse will be generated */
1032	emac_write(EMAC_DM646X_MACEOIVECTOR,
1033	EMAC_DM646X_MAC_EOI_C0_RXEN);
1034
1035	/* ack txen- only then a new pulse will be generated */
1036	emac_write(EMAC_DM646X_MACEOIVECTOR,
1037	EMAC_DM646X_MAC_EOI_C0_TXEN);
1038
1039	} else {
1040	/* Set DM644x control registers for interrupt control */
1041	emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1042	}
1043	}
1044
1045	/**
1046	* emac_irq: EMAC interrupt handler
1047	* @irq: interrupt number
1048	* @dev_id: EMAC network adapter data structure ptr
1049	*
1050	* EMAC Interrupt handler - we only schedule NAPI and not process any packets
1051	* here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1052	*
1053	* Returns interrupt handled condition
1054	*/
1055	static irqreturn_t emac_irq(int irq, void *dev_id)
1056	{
1057	struct net_device ndev = (struct net_device )dev_id;
1058	struct emac_priv *priv = netdev_priv(ndev);
1059
1060	++priv->isr_count;
1061	if (likely(netif_running(priv->ndev))) {
1062	emac_int_disable(priv);
1063	napi_schedule(&priv->napi);
1064	} else {
1065	/* we are closing down, so dont process anything */
1066	}
1067	return IRQ_HANDLED;
1068	}
1069
1070	/** EMAC on-chip buffer descriptor memory
1071	*
1072	* WARNING: Please note that the on chip memory is used for both TX and RX
1073	* buffer descriptor queues and is equally divided between TX and RX desc's
1074	* If the number of TX or RX descriptors change this memory pointers need
1075	* to be adjusted. If external memory is allocated then these pointers can
1076	* pointer to the memory
1077	*
1078	*/
1079	#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1080	#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1081	(((priv)->ctrl_ram_size) >> 1))
1082
1083	/**
1084	* emac_init_txch: TX channel initialization
1085	* @priv: The DaVinci EMAC private adapter structure
1086	* @ch: RX channel number
1087	*
1088	* Called during device init to setup a TX channel (allocate buffer desc
1089	* create free pool and keep ready for transmission
1090	*
1091	* Returns success(0) or mem alloc failures error code
1092	*/
1093	static int emac_init_txch(struct emac_priv *priv, u32 ch)
1094	{
1095	struct device *emac_dev = &priv->ndev->dev;
1096	u32 cnt, bd_size;
1097	void __iomem *mem;
1098	struct emac_tx_bd __iomem *curr_bd;
1099	struct emac_txch *txch = NULL;
1100
1101	txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1102	if (NULL == txch) {
1103	dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1104	return -ENOMEM;
1105	}
1106	priv->txch[ch] = txch;
1107	txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1108	txch->active_queue_head = NULL;
1109	txch->active_queue_tail = NULL;
1110	txch->queue_active = 0;
1111	txch->teardown_pending = 0;
1112
1113	/* allocate memory for TX CPPI channel on a 4 byte boundry */
1114	txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1115	GFP_KERNEL);
1116	if (NULL == txch->tx_complete) {
1117	dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1118	kfree(txch);
1119	return -ENOMEM;
1120	}
1121
1122	/* allocate buffer descriptor pool align every BD on four word
1123	* boundry for future requirements */
1124	bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1125	txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1126	txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1127
1128	/* alloc TX BD memory */
1129	txch->bd_mem = EMAC_TX_BD_MEM(priv);
1130	__memzero((void __force *)txch->bd_mem, txch->alloc_size);
1131
1132	/* initialize the BD linked list */
1133	mem = (void __force __iomem *)
1134	(((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1135	txch->bd_pool_head = NULL;
1136	for (cnt = 0; cnt < txch->num_bd; cnt++) {
1137	curr_bd = mem + (cnt * bd_size);
1138	curr_bd->next = txch->bd_pool_head;
1139	txch->bd_pool_head = curr_bd;
1140	}
1141
1142	/* reset statistics counters */
1143	txch->out_of_tx_bd = 0;
1144	txch->no_active_pkts = 0;
1145	txch->active_queue_count = 0;
1146
1147	return 0;
1148	}
1149
1150	/**
1151	* emac_cleanup_txch: Book-keep function to clean TX channel resources
1152	* @priv: The DaVinci EMAC private adapter structure
1153	* @ch: TX channel number
1154	*
1155	* Called to clean up TX channel resources
1156	*
1157	*/
1158	static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1159	{
1160	struct emac_txch *txch = priv->txch[ch];
1161
1162	if (txch) {
1163	if (txch->bd_mem)
1164	txch->bd_mem = NULL;
1165	kfree(txch->tx_complete);
1166	kfree(txch);
1167	priv->txch[ch] = NULL;
1168	}
1169	}
1170
1171	/**
1172	* emac_net_tx_complete: TX packet completion function
1173	* @priv: The DaVinci EMAC private adapter structure
1174	* @net_data_tokens: packet token - skb pointer
1175	* @num_tokens: number of skb's to free
1176	* @ch: TX channel number
1177	*
1178	* Frees the skb once packet is transmitted
1179	*
1180	*/
1181	static int emac_net_tx_complete(struct emac_priv *priv,
1182	void **net_data_tokens,
1183	int num_tokens, u32 ch)
1184	{
1185	u32 cnt;
1186
1187	if (unlikely(num_tokens && netif_queue_stopped(priv->ndev)))
1188	netif_start_queue(priv->ndev);
1189	for (cnt = 0; cnt < num_tokens; cnt++) {
1190	struct sk_buff skb = (struct sk_buff )net_data_tokens[cnt];
1191	if (skb == NULL)
1192	continue;
1193	priv->net_dev_stats.tx_packets++;
1194	priv->net_dev_stats.tx_bytes += skb->len;
1195	dev_kfree_skb_any(skb);
1196	}
1197	return 0;
1198	}
1199
1200	/**
1201	* emac_txch_teardown: TX channel teardown
1202	* @priv: The DaVinci EMAC private adapter structure
1203	* @ch: TX channel number
1204	*
1205	* Called to teardown TX channel
1206	*
1207	*/
1208	static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1209	{
1210	struct device *emac_dev = &priv->ndev->dev;
1211	u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1212	struct emac_txch *txch = priv->txch[ch];
1213	struct emac_tx_bd __iomem *curr_bd;
1214
1215	while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1216	EMAC_TEARDOWN_VALUE) {
1217	/* wait till tx teardown complete */
1218	cpu_relax(); /* TODO: check if this helps ... */
1219	--teardown_cnt;
1220	if (0 == teardown_cnt) {
1221	dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1222	break;
1223	}
1224	}
1225	emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1226
1227	/* process sent packets and return skb's to upper layer */
1228	if (1 == txch->queue_active) {
1229	curr_bd = txch->active_queue_head;
1230	while (curr_bd != NULL) {
1231	emac_net_tx_complete(priv, (void __force *)
1232	&curr_bd->buf_token, 1, ch);
1233	if (curr_bd != txch->active_queue_tail)
1234	curr_bd = curr_bd->next;
1235	else
1236	break;
1237	}
1238	txch->bd_pool_head = txch->active_queue_head;
1239	txch->active_queue_head =
1240	txch->active_queue_tail = NULL;
1241	}
1242	}
1243
1244	/**
1245	* emac_stop_txch: Stop TX channel operation
1246	* @priv: The DaVinci EMAC private adapter structure
1247	* @ch: TX channel number
1248	*
1249	* Called to stop TX channel operation
1250	*
1251	*/
1252	static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1253	{
1254	struct emac_txch *txch = priv->txch[ch];
1255
1256	if (txch) {
1257	txch->teardown_pending = 1;
1258	emac_write(EMAC_TXTEARDOWN, 0);
1259	emac_txch_teardown(priv, ch);
1260	txch->teardown_pending = 0;
1261	emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1262	}
1263	}
1264
1265	/**
1266	* emac_tx_bdproc: TX buffer descriptor (packet) processing
1267	* @priv: The DaVinci EMAC private adapter structure
1268	* @ch: TX channel number to process buffer descriptors for
1269	* @budget: number of packets allowed to process
1270	* @pending: indication to caller that packets are pending to process
1271	*
1272	* Processes TX buffer descriptors after packets are transmitted - checks
1273	* ownership bit on the TX * descriptor and requeues it to free pool & frees
1274	* the SKB buffer. Only "budget" number of packets are processed and
1275	* indication of pending packets provided to the caller
1276	*
1277	* Returns number of packets processed
1278	*/
1279	static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1280	{
1281	struct device *emac_dev = &priv->ndev->dev;
1282	unsigned long flags;
1283	u32 frame_status;
1284	u32 pkts_processed = 0;
1285	u32 tx_complete_cnt = 0;
1286	struct emac_tx_bd __iomem *curr_bd;
1287	struct emac_txch *txch = priv->txch[ch];
1288	u32 *tx_complete_ptr = txch->tx_complete;
1289
1290	if (unlikely(1 == txch->teardown_pending)) {
1291	if (netif_msg_tx_err(priv) && net_ratelimit()) {
1292	dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1293	"teardown pending\n");
1294	}
1295	return 0; /* dont handle any pkt completions */
1296	}
1297
1298	++txch->proc_count;
1299	spin_lock_irqsave(&priv->tx_lock, flags);
1300	curr_bd = txch->active_queue_head;
1301	if (NULL == curr_bd) {
1302	emac_write(EMAC_TXCP(ch),
1303	emac_virt_to_phys(txch->last_hw_bdprocessed));
1304	txch->no_active_pkts++;
1305	spin_unlock_irqrestore(&priv->tx_lock, flags);
1306	return 0;
1307	}
1308	BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1309	frame_status = curr_bd->mode;
1310	while ((curr_bd) &&
1311	((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1312	(pkts_processed < budget)) {
1313	emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd));
1314	txch->active_queue_head = curr_bd->next;
1315	if (frame_status & EMAC_CPPI_EOQ_BIT) {
1316	if (curr_bd->next) { /* misqueued packet */
1317	emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1318	++txch->mis_queued_packets;
1319	} else {
1320	txch->queue_active = 0; /* end of queue */
1321	}
1322	}
1323	*tx_complete_ptr = (u32) curr_bd->buf_token;
1324	++tx_complete_ptr;
1325	++tx_complete_cnt;
1326	curr_bd->next = txch->bd_pool_head;
1327	txch->bd_pool_head = curr_bd;
1328	--txch->active_queue_count;
1329	pkts_processed++;
1330	txch->last_hw_bdprocessed = curr_bd;
1331	curr_bd = txch->active_queue_head;
1332	if (curr_bd) {
1333	BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1334	frame_status = curr_bd->mode;
1335	}
1336	} /* end of pkt processing loop */
1337
1338	emac_net_tx_complete(priv,
1339	(void *)&txch->tx_complete[0],
1340	tx_complete_cnt, ch);
1341	spin_unlock_irqrestore(&priv->tx_lock, flags);
1342	return pkts_processed;
1343	}
1344
1345	#define EMAC_ERR_TX_OUT_OF_BD -1
1346
1347	/**
1348	* emac_send: EMAC Transmit function (internal)
1349	* @priv: The DaVinci EMAC private adapter structure
1350	* @pkt: packet pointer (contains skb ptr)
1351	* @ch: TX channel number
1352	*
1353	* Called by the transmit function to queue the packet in EMAC hardware queue
1354	*
1355	* Returns success(0) or error code (typically out of desc's)
1356	*/
1357	static int emac_send(struct emac_priv priv, struct emac_netpktobj pkt, u32 ch)
1358	{
1359	unsigned long flags;
1360	struct emac_tx_bd __iomem *curr_bd;
1361	struct emac_txch *txch;
1362	struct emac_netbufobj *buf_list;
1363
1364	txch = priv->txch[ch];
1365	buf_list = pkt->buf_list; /* get handle to the buffer array */
1366
1367	/* check packet size and pad if short */
1368	if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1369	buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1370	pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1371	}
1372
1373	spin_lock_irqsave(&priv->tx_lock, flags);
1374	curr_bd = txch->bd_pool_head;
1375	if (curr_bd == NULL) {
1376	txch->out_of_tx_bd++;
1377	spin_unlock_irqrestore(&priv->tx_lock, flags);
1378	return EMAC_ERR_TX_OUT_OF_BD;
1379	}
1380
1381	txch->bd_pool_head = curr_bd->next;
1382	curr_bd->buf_token = buf_list->buf_token;
1383	/* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1384	curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
1385	curr_bd->off_b_len = buf_list->length;
1386	curr_bd->h_next = 0;
1387	curr_bd->next = NULL;
1388	curr_bd->mode = (EMAC_CPPI_SOP_BIT \| EMAC_CPPI_OWNERSHIP_BIT \|
1389	EMAC_CPPI_EOP_BIT \| pkt->pkt_length);
1390
1391	/* flush the packet from cache if write back cache is present */
1392	BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1393
1394	/* send the packet */
1395	if (txch->active_queue_head == NULL) {
1396	txch->active_queue_head = curr_bd;
1397	txch->active_queue_tail = curr_bd;
1398	if (1 != txch->queue_active) {
1399	emac_write(EMAC_TXHDP(ch),
1400	emac_virt_to_phys(curr_bd));
1401	txch->queue_active = 1;
1402	}
1403	++txch->queue_reinit;
1404	} else {
1405	register struct emac_tx_bd __iomem *tail_bd;
1406	register u32 frame_status;
1407
1408	tail_bd = txch->active_queue_tail;
1409	tail_bd->next = curr_bd;
1410	txch->active_queue_tail = curr_bd;
1411	tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1412	tail_bd->h_next = (int)emac_virt_to_phys(curr_bd);
1413	frame_status = tail_bd->mode;
1414	if (frame_status & EMAC_CPPI_EOQ_BIT) {
1415	emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd));
1416	frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1417	tail_bd->mode = frame_status;
1418	++txch->end_of_queue_add;
1419	}
1420	}
1421	txch->active_queue_count++;
1422	spin_unlock_irqrestore(&priv->tx_lock, flags);
1423	return 0;
1424	}
1425
1426	/**
1427	* emac_dev_xmit: EMAC Transmit function
1428	* @skb: SKB pointer
1429	* @ndev: The DaVinci EMAC network adapter
1430	*
1431	* Called by the system to transmit a packet - we queue the packet in
1432	* EMAC hardware transmit queue
1433	*
1434	* Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1435	*/
1436	static int emac_dev_xmit(struct sk_buff skb, struct net_device ndev)
1437	{
1438	struct device *emac_dev = &ndev->dev;
1439	int ret_code;
1440	struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1441	struct emac_netpktobj tx_packet; /* packet object */
1442	struct emac_priv *priv = netdev_priv(ndev);
1443
1444	/* If no link, return */
1445	if (unlikely(!priv->link)) {
1446	if (netif_msg_tx_err(priv) && net_ratelimit())
1447	dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1448	return NETDEV_TX_BUSY;
1449	}
1450
1451	/* Build the buffer and packet objects - Since only single fragment is
1452	* supported, need not set length and token in both packet & object.
1453	* Doing so for completeness sake & to show that this needs to be done
1454	* in multifragment case
1455	*/
1456	tx_packet.buf_list = &tx_buf;
1457	tx_packet.num_bufs = 1; /* only single fragment supported */
1458	tx_packet.pkt_length = skb->len;
1459	tx_packet.pkt_token = (void *)skb;
1460	tx_buf.length = skb->len;
1461	tx_buf.buf_token = (void *)skb;
1462	tx_buf.data_ptr = skb->data;
1463	EMAC_CACHE_WRITEBACK((unsigned long)skb->data, skb->len);
1464	ndev->trans_start = jiffies;
1465	ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1466	if (unlikely(ret_code != 0)) {
1467	if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1468	if (netif_msg_tx_err(priv) && net_ratelimit())
1469	dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1470	" err. Out of TX BD's");
1471	netif_stop_queue(priv->ndev);
1472	}
1473	priv->net_dev_stats.tx_dropped++;
1474	return NETDEV_TX_BUSY;
1475	}
1476
1477	return NETDEV_TX_OK;
1478	}
1479
1480	/**
1481	* emac_dev_tx_timeout: EMAC Transmit timeout function
1482	* @ndev: The DaVinci EMAC network adapter
1483	*
1484	* Called when system detects that a skb timeout period has expired
1485	* potentially due to a fault in the adapter in not being able to send
1486	* it out on the wire. We teardown the TX channel assuming a hardware
1487	* error and re-initialize the TX channel for hardware operation
1488	*
1489	*/
1490	static void emac_dev_tx_timeout(struct net_device *ndev)
1491	{
1492	struct emac_priv *priv = netdev_priv(ndev);
1493	struct device *emac_dev = &ndev->dev;
1494
1495	if (netif_msg_tx_err(priv))
1496	dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1497
1498	priv->net_dev_stats.tx_errors++;
1499	emac_int_disable(priv);
1500	emac_stop_txch(priv, EMAC_DEF_TX_CH);
1501	emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1502	emac_init_txch(priv, EMAC_DEF_TX_CH);
1503	emac_write(EMAC_TXHDP(0), 0);
1504	emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1505	emac_int_enable(priv);
1506	}
1507
1508	/**
1509	* emac_net_alloc_rx_buf: Allocate a skb for RX
1510	* @priv: The DaVinci EMAC private adapter structure
1511	* @buf_size: size of SKB data buffer to allocate
1512	* @data_token: data token returned (skb handle for storing in buffer desc)
1513	* @ch: RX channel number
1514	*
1515	* Called during RX channel setup - allocates skb buffer of required size
1516	* and provides the skb handle and allocated buffer data pointer to caller
1517	*
1518	* Returns skb data pointer or 0 on failure to alloc skb
1519	*/
1520	static void emac_net_alloc_rx_buf(struct emac_priv priv, int buf_size,
1521	void **data_token, u32 ch)
1522	{
1523	struct net_device *ndev = priv->ndev;
1524	struct device *emac_dev = &ndev->dev;
1525	struct sk_buff *p_skb;
1526
1527	p_skb = dev_alloc_skb(buf_size);
1528	if (unlikely(NULL == p_skb)) {
1529	if (netif_msg_rx_err(priv) && net_ratelimit())
1530	dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1531	return NULL;
1532	}
1533
1534	/* set device pointer in skb and reserve space for extra bytes */
1535	p_skb->dev = ndev;
1536	skb_reserve(p_skb, NET_IP_ALIGN);
1537	data_token = (void ) p_skb;
1538	EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p_skb->data, buf_size);
1539	return p_skb->data;
1540	}
1541
1542	/**
1543	* emac_init_rxch: RX channel initialization
1544	* @priv: The DaVinci EMAC private adapter structure
1545	* @ch: RX channel number
1546	* @param: mac address for RX channel
1547	*
1548	* Called during device init to setup a RX channel (allocate buffers and
1549	* buffer descriptors, create queue and keep ready for reception
1550	*
1551	* Returns success(0) or mem alloc failures error code
1552	*/
1553	static int emac_init_rxch(struct emac_priv priv, u32 ch, char param)
1554	{
1555	struct device *emac_dev = &priv->ndev->dev;
1556	u32 cnt, bd_size;
1557	void __iomem *mem;
1558	struct emac_rx_bd __iomem *curr_bd;
1559	struct emac_rxch *rxch = NULL;
1560
1561	rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1562	if (NULL == rxch) {
1563	dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1564	return -ENOMEM;
1565	}
1566	priv->rxch[ch] = rxch;
1567	rxch->buf_size = priv->rx_buf_size;
1568	rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1569	rxch->queue_active = 0;
1570	rxch->teardown_pending = 0;
1571
1572	/* save mac address */
1573	for (cnt = 0; cnt < 6; cnt++)
1574	rxch->mac_addr[cnt] = param[cnt];
1575
1576	/* allocate buffer descriptor pool align every BD on four word
1577	* boundry for future requirements */
1578	bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1579	rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1580	rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1581	rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1582	__memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1583	rxch->pkt_queue.buf_list = &rxch->buf_queue;
1584
1585	/* allocate RX buffer and initialize the BD linked list */
1586	mem = (void __force __iomem *)
1587	(((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1588	rxch->active_queue_head = NULL;
1589	rxch->active_queue_tail = mem;
1590	for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1591	curr_bd = mem + (cnt * bd_size);
1592	/* for future use the last parameter contains the BD ptr */
1593	curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1594	rxch->buf_size,
1595	(void __force **)&curr_bd->buf_token,
1596	EMAC_DEF_RX_CH);
1597	if (curr_bd->data_ptr == NULL) {
1598	dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1599	"failed for ch %d\n", ch);
1600	kfree(rxch);
1601	return -ENOMEM;
1602	}
1603
1604	/* populate the hardware descriptor */
1605	curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head);
1606	/* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1607	curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
1608	curr_bd->off_b_len = rxch->buf_size;
1609	curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1610
1611	/* write back to hardware memory */
1612	BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1613	EMAC_BD_LENGTH_FOR_CACHE);
1614	curr_bd->next = rxch->active_queue_head;
1615	rxch->active_queue_head = curr_bd;
1616	}
1617
1618	/* At this point rxCppi->activeQueueHead points to the first
1619	RX BD ready to be given to RX HDP and rxch->active_queue_tail
1620	points to the last RX BD
1621	*/
1622	return 0;
1623	}
1624
1625	/**
1626	* emac_rxch_teardown: RX channel teardown
1627	* @priv: The DaVinci EMAC private adapter structure
1628	* @ch: RX channel number
1629	*
1630	* Called during device stop to teardown RX channel
1631	*
1632	*/
1633	static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1634	{
1635	struct device *emac_dev = &priv->ndev->dev;
1636	u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1637
1638	while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1639	EMAC_TEARDOWN_VALUE) {
1640	/* wait till tx teardown complete */
1641	cpu_relax(); /* TODO: check if this helps ... */
1642	--teardown_cnt;
1643	if (0 == teardown_cnt) {
1644	dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1645	break;
1646	}
1647	}
1648	emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1649	}
1650
1651	/**
1652	* emac_stop_rxch: Stop RX channel operation
1653	* @priv: The DaVinci EMAC private adapter structure
1654	* @ch: RX channel number
1655	*
1656	* Called during device stop to stop RX channel operation
1657	*
1658	*/
1659	static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1660	{
1661	struct emac_rxch *rxch = priv->rxch[ch];
1662
1663	if (rxch) {
1664	rxch->teardown_pending = 1;
1665	emac_write(EMAC_RXTEARDOWN, ch);
1666	/* wait for teardown complete */
1667	emac_rxch_teardown(priv, ch);
1668	rxch->teardown_pending = 0;
1669	emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1670	}
1671	}
1672
1673	/**
1674	* emac_cleanup_rxch: Book-keep function to clean RX channel resources
1675	* @priv: The DaVinci EMAC private adapter structure
1676	* @ch: RX channel number
1677	*
1678	* Called during device stop to clean up RX channel resources
1679	*
1680	*/
1681	static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1682	{
1683	struct emac_rxch *rxch = priv->rxch[ch];
1684	struct emac_rx_bd __iomem *curr_bd;
1685
1686	if (rxch) {
1687	/* free the receive buffers previously allocated */
1688	curr_bd = rxch->active_queue_head;
1689	while (curr_bd) {
1690	if (curr_bd->buf_token) {
1691	dev_kfree_skb_any((struct sk_buff *)\
1692	curr_bd->buf_token);
1693	}
1694	curr_bd = curr_bd->next;
1695	}
1696	if (rxch->bd_mem)
1697	rxch->bd_mem = NULL;
1698	kfree(rxch);
1699	priv->rxch[ch] = NULL;
1700	}
1701	}
1702
1703	/**
1704	* emac_set_type0addr: Set EMAC Type0 mac address
1705	* @priv: The DaVinci EMAC private adapter structure
1706	* @ch: RX channel number
1707	* @mac_addr: MAC address to set in device
1708	*
1709	* Called internally to set Type0 mac address of the adapter (Device)
1710	*
1711	* Returns success (0) or appropriate error code (none as of now)
1712	*/
1713	static void emac_set_type0addr(struct emac_priv priv, u32 ch, char mac_addr)
1714	{
1715	u32 val;
1716	val = ((mac_addr[5] << 8) \| (mac_addr[4]));
1717	emac_write(EMAC_MACSRCADDRLO, val);
1718
1719	val = ((mac_addr[3] << 24) \| (mac_addr[2] << 16) \| \
1720	(mac_addr[1] << 8) \| (mac_addr[0]));
1721	emac_write(EMAC_MACSRCADDRHI, val);
1722	val = emac_read(EMAC_RXUNICASTSET);
1723	val \|= BIT(ch);
1724	emac_write(EMAC_RXUNICASTSET, val);
1725	val = emac_read(EMAC_RXUNICASTCLEAR);
1726	val &= ~BIT(ch);
1727	emac_write(EMAC_RXUNICASTCLEAR, val);
1728	}
1729
1730	/**
1731	* emac_set_type1addr: Set EMAC Type1 mac address
1732	* @priv: The DaVinci EMAC private adapter structure
1733	* @ch: RX channel number
1734	* @mac_addr: MAC address to set in device
1735	*
1736	* Called internally to set Type1 mac address of the adapter (Device)
1737	*
1738	* Returns success (0) or appropriate error code (none as of now)
1739	*/
1740	static void emac_set_type1addr(struct emac_priv priv, u32 ch, char mac_addr)
1741	{
1742	u32 val;
1743	emac_write(EMAC_MACINDEX, ch);
1744	val = ((mac_addr[5] << 8) \| mac_addr[4]);
1745	emac_write(EMAC_MACADDRLO, val);
1746	val = ((mac_addr[3] << 24) \| (mac_addr[2] << 16) \| \
1747	(mac_addr[1] << 8) \| (mac_addr[0]));
1748	emac_write(EMAC_MACADDRHI, val);
1749	emac_set_type0addr(priv, ch, mac_addr);
1750	}
1751
1752	/**
1753	* emac_set_type2addr: Set EMAC Type2 mac address
1754	* @priv: The DaVinci EMAC private adapter structure
1755	* @ch: RX channel number
1756	* @mac_addr: MAC address to set in device
1757	* @index: index into RX address entries
1758	* @match: match parameter for RX address matching logic
1759	*
1760	* Called internally to set Type2 mac address of the adapter (Device)
1761	*
1762	* Returns success (0) or appropriate error code (none as of now)
1763	*/
1764	static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1765	char *mac_addr, int index, int match)
1766	{
1767	u32 val;
1768	emac_write(EMAC_MACINDEX, index);
1769	val = ((mac_addr[3] << 24) \| (mac_addr[2] << 16) \| \
1770	(mac_addr[1] << 8) \| (mac_addr[0]));
1771	emac_write(EMAC_MACADDRHI, val);
1772	val = ((mac_addr[5] << 8) \| mac_addr[4] \| ((ch & 0x7) << 16) \| \
1773	(match << 19) \| BIT(20));
1774	emac_write(EMAC_MACADDRLO, val);
1775	emac_set_type0addr(priv, ch, mac_addr);
1776	}
1777
1778	/**
1779	* emac_setmac: Set mac address in the adapter (internal function)
1780	* @priv: The DaVinci EMAC private adapter structure
1781	* @ch: RX channel number
1782	* @mac_addr: MAC address to set in device
1783	*
1784	* Called internally to set the mac address of the adapter (Device)
1785	*
1786	* Returns success (0) or appropriate error code (none as of now)
1787	*/
1788	static void emac_setmac(struct emac_priv priv, u32 ch, char mac_addr)
1789	{
1790	struct device *emac_dev = &priv->ndev->dev;
1791
1792	if (priv->rx_addr_type == 0) {
1793	emac_set_type0addr(priv, ch, mac_addr);
1794	} else if (priv->rx_addr_type == 1) {
1795	u32 cnt;
1796	for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1797	emac_set_type1addr(priv, ch, mac_addr);
1798	} else if (priv->rx_addr_type == 2) {
1799	emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1800	emac_set_type0addr(priv, ch, mac_addr);
1801	} else {
1802	if (netif_msg_drv(priv))
1803	dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1804	}
1805	}
1806
1807	/**
1808	* emac_dev_setmac_addr: Set mac address in the adapter
1809	* @ndev: The DaVinci EMAC network adapter
1810	* @addr: MAC address to set in device
1811	*
1812	* Called by the system to set the mac address of the adapter (Device)
1813	*
1814	* Returns success (0) or appropriate error code (none as of now)
1815	*/
1816	static int emac_dev_setmac_addr(struct net_device ndev, void addr)
1817	{
1818	struct emac_priv *priv = netdev_priv(ndev);
1819	struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1820	struct device *emac_dev = &priv->ndev->dev;
1821	struct sockaddr *sa = addr;
1822
1823	if (!is_valid_ether_addr(sa->sa_data))
1824	return -EINVAL;
1825
1826	/* Store mac addr in priv and rx channel and set it in EMAC hw */
1827	memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1828	memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1829
1830	/* If the interface is down - rxch is NULL. */
1831	/* MAC address is configured only after the interface is enabled. */
1832	if (netif_running(ndev)) {
1833	memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1834	emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1835	}
1836
1837	if (netif_msg_drv(priv))
1838	dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1839	priv->mac_addr);
1840
1841	return 0;
1842	}
1843
1844	/**
1845	* emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1846	* @priv: The DaVinci EMAC private adapter structure
1847	* @ch: RX channel number to process buffer descriptors for
1848	* @curr_bd: current buffer descriptor
1849	* @buffer: buffer pointer for descriptor
1850	* @buf_token: buffer token (stores skb information)
1851	*
1852	* Prepares the recycled buffer descriptor and addes it to hardware
1853	* receive queue - if queue empty this descriptor becomes the head
1854	* else addes the descriptor to end of queue
1855	*
1856	*/
1857	static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1858	struct emac_rx_bd __iomem *curr_bd,
1859	char buffer, void buf_token)
1860	{
1861	struct emac_rxch *rxch = priv->rxch[ch];
1862
1863	/* populate the hardware descriptor */
1864	curr_bd->h_next = 0;
1865	/* FIXME buff_ptr = dma_map_single(... buffer ...) */
1866	curr_bd->buff_ptr = virt_to_phys(buffer);
1867	curr_bd->off_b_len = rxch->buf_size;
1868	curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1869	curr_bd->next = NULL;
1870	curr_bd->data_ptr = buffer;
1871	curr_bd->buf_token = buf_token;
1872
1873	/* write back */
1874	BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1875	if (rxch->active_queue_head == NULL) {
1876	rxch->active_queue_head = curr_bd;
1877	rxch->active_queue_tail = curr_bd;
1878	if (0 != rxch->queue_active) {
1879	emac_write(EMAC_RXHDP(ch),
1880	emac_virt_to_phys(rxch->active_queue_head));
1881	rxch->queue_active = 1;
1882	}
1883	} else {
1884	struct emac_rx_bd __iomem *tail_bd;
1885	u32 frame_status;
1886
1887	tail_bd = rxch->active_queue_tail;
1888	rxch->active_queue_tail = curr_bd;
1889	tail_bd->next = curr_bd;
1890	tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1891	tail_bd->h_next = emac_virt_to_phys(curr_bd);
1892	frame_status = tail_bd->mode;
1893	if (frame_status & EMAC_CPPI_EOQ_BIT) {
1894	emac_write(EMAC_RXHDP(ch),
1895	emac_virt_to_phys(curr_bd));
1896	frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1897	tail_bd->mode = frame_status;
1898	++rxch->end_of_queue_add;
1899	}
1900	}
1901	++rxch->recycled_bd;
1902	}
1903
1904	/**
1905	* emac_net_rx_cb: Prepares packet and sends to upper layer
1906	* @priv: The DaVinci EMAC private adapter structure
1907	* @net_pkt_list: Network packet list (received packets)
1908	*
1909	* Invalidates packet buffer memory and sends the received packet to upper
1910	* layer
1911	*
1912	* Returns success or appropriate error code (none as of now)
1913	*/
1914	static int emac_net_rx_cb(struct emac_priv *priv,
1915	struct emac_netpktobj *net_pkt_list)
1916	{
1917	struct sk_buff *p_skb;
1918	p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
1919	/* set length of packet */
1920	skb_put(p_skb, net_pkt_list->pkt_length);
1921	EMAC_CACHE_INVALIDATE((unsigned long)p_skb->data, p_skb->len);
1922	p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
1923	p_skb->dev->last_rx = jiffies;
1924	netif_receive_skb(p_skb);
1925	priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
1926	priv->net_dev_stats.rx_packets++;
1927	return 0;
1928	}
1929
1930	/**
1931	* emac_rx_bdproc: RX buffer descriptor (packet) processing
1932	* @priv: The DaVinci EMAC private adapter structure
1933	* @ch: RX channel number to process buffer descriptors for
1934	* @budget: number of packets allowed to process
1935	* @pending: indication to caller that packets are pending to process
1936	*
1937	* Processes RX buffer descriptors - checks ownership bit on the RX buffer
1938	* descriptor, sends the receive packet to upper layer, allocates a new SKB
1939	* and recycles the buffer descriptor (requeues it in hardware RX queue).
1940	* Only "budget" number of packets are processed and indication of pending
1941	* packets provided to the caller.
1942	*
1943	* Returns number of packets processed (and indication of pending packets)
1944	*/
1945	static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1946	{
1947	unsigned long flags;
1948	u32 frame_status;
1949	u32 pkts_processed = 0;
1950	char *new_buffer;
1951	struct emac_rx_bd __iomem *curr_bd;
1952	struct emac_rx_bd __iomem *last_bd;
1953	struct emac_netpktobj *curr_pkt, pkt_obj;
1954	struct emac_netbufobj buf_obj;
1955	struct emac_netbufobj *rx_buf_obj;
1956	void *new_buf_token;
1957	struct emac_rxch *rxch = priv->rxch[ch];
1958
1959	if (unlikely(1 == rxch->teardown_pending))
1960	return 0;
1961	++rxch->proc_count;
1962	spin_lock_irqsave(&priv->rx_lock, flags);
1963	pkt_obj.buf_list = &buf_obj;
1964	curr_pkt = &pkt_obj;
1965	curr_bd = rxch->active_queue_head;
1966	BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1967	frame_status = curr_bd->mode;
1968
1969	while ((curr_bd) &&
1970	((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1971	(pkts_processed < budget)) {
1972
1973	new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
1974	&new_buf_token, EMAC_DEF_RX_CH);
1975	if (unlikely(NULL == new_buffer)) {
1976	++rxch->out_of_rx_buffers;
1977	goto end_emac_rx_bdproc;
1978	}
1979
1980	/* populate received packet data structure */
1981	rx_buf_obj = &curr_pkt->buf_list[0];
1982	rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
1983	rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
1984	rx_buf_obj->buf_token = curr_bd->buf_token;
1985	curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
1986	curr_pkt->num_bufs = 1;
1987	curr_pkt->pkt_length =
1988	(frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1989	emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd));
1990	++rxch->processed_bd;
1991	last_bd = curr_bd;
1992	curr_bd = last_bd->next;
1993	rxch->active_queue_head = curr_bd;
1994
1995	/* check if end of RX queue ? */
1996	if (frame_status & EMAC_CPPI_EOQ_BIT) {
1997	if (curr_bd) {
1998	++rxch->mis_queued_packets;
1999	emac_write(EMAC_RXHDP(ch),
2000	emac_virt_to_phys(curr_bd));
2001	} else {
2002	++rxch->end_of_queue;
2003	rxch->queue_active = 0;
2004	}
2005	}
2006
2007	/* recycle BD */
2008	emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2009	new_buf_token);
2010
2011	/* return the packet to the user - BD ptr passed in
2012	* last parameter for potential future use */
2013	spin_unlock_irqrestore(&priv->rx_lock, flags);
2014	emac_net_rx_cb(priv, curr_pkt);
2015	spin_lock_irqsave(&priv->rx_lock, flags);
2016	curr_bd = rxch->active_queue_head;
2017	if (curr_bd) {
2018	BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2019	frame_status = curr_bd->mode;
2020	}
2021	++pkts_processed;
2022	}
2023
2024	end_emac_rx_bdproc:
2025	spin_unlock_irqrestore(&priv->rx_lock, flags);
2026	return pkts_processed;
2027	}
2028
2029	/**
2030	* emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2031	* @priv: The DaVinci EMAC private adapter structure
2032	*
2033	* Enables EMAC hardware for packet processing - enables PHY, enables RX
2034	* for packet reception and enables device interrupts and then NAPI
2035	*
2036	* Returns success (0) or appropriate error code (none right now)
2037	*/
2038	static int emac_hw_enable(struct emac_priv *priv)
2039	{
2040	u32 ch, val, mbp_enable, mac_control;
2041
2042	/* Soft reset */
2043	emac_write(EMAC_SOFTRESET, 1);
2044	while (emac_read(EMAC_SOFTRESET))
2045	cpu_relax();
2046
2047	/* Disable interrupt & Set pacing for more interrupts initially */
2048	emac_int_disable(priv);
2049
2050	/* Full duplex enable bit set when auto negotiation happens */
2051	mac_control =
2052	(((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) \|
2053	((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) \|
2054	((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) \|
2055	((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2056	emac_write(EMAC_MACCONTROL, mac_control);
2057
2058	mbp_enable =
2059	(((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) \|
2060	((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) \|
2061	((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) \|
2062	((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) \|
2063	((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) \|
2064	((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) \|
2065	((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) \|
2066	((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2067	EMAC_RXMBP_PROMCH_SHIFT) \|
2068	((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) \|
2069	((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2070	EMAC_RXMBP_BROADCH_SHIFT) \|
2071	((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) \|
2072	((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2073	EMAC_RXMBP_MULTICH_SHIFT));
2074	emac_write(EMAC_RXMBPENABLE, mbp_enable);
2075	emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2076	EMAC_RX_MAX_LEN_MASK));
2077	emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2078	EMAC_RX_BUFFER_OFFSET_MASK));
2079	emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2080	emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2081	priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2082
2083	val = emac_read(EMAC_TXCONTROL);
2084	val \|= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2085	emac_write(EMAC_TXCONTROL, val);
2086	val = emac_read(EMAC_RXCONTROL);
2087	val \|= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2088	emac_write(EMAC_RXCONTROL, val);
2089	emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2090
2091	for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2092	emac_write(EMAC_TXHDP(ch), 0);
2093	emac_write(EMAC_TXINTMASKSET, BIT(ch));
2094	}
2095	for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2096	struct emac_rxch *rxch = priv->rxch[ch];
2097	emac_setmac(priv, ch, rxch->mac_addr);
2098	emac_write(EMAC_RXINTMASKSET, BIT(ch));
2099	rxch->queue_active = 1;
2100	emac_write(EMAC_RXHDP(ch),
2101	emac_virt_to_phys(rxch->active_queue_head));
2102	}
2103
2104	/* Enable MII */
2105	val = emac_read(EMAC_MACCONTROL);
2106	val \|= (EMAC_MACCONTROL_MIIEN);
2107	emac_write(EMAC_MACCONTROL, val);
2108
2109	/* Enable NAPI and interrupts */
2110	napi_enable(&priv->napi);
2111	emac_int_enable(priv);
2112	return 0;
2113
2114	}
2115
2116	/**
2117	* emac_poll: EMAC NAPI Poll function
2118	* @ndev: The DaVinci EMAC network adapter
2119	* @budget: Number of receive packets to process (as told by NAPI layer)
2120	*
2121	* NAPI Poll function implemented to process packets as per budget. We check
2122	* the type of interrupt on the device and accordingly call the TX or RX
2123	* packet processing functions. We follow the budget for RX processing and
2124	* also put a cap on number of TX pkts processed through config param. The
2125	* NAPI schedule function is called if more packets pending.
2126	*
2127	* Returns number of packets received (in most cases; else TX pkts - rarely)
2128	*/
2129	static int emac_poll(struct napi_struct *napi, int budget)
2130	{
2131	unsigned int mask;
2132	struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2133	struct net_device *ndev = priv->ndev;
2134	struct device *emac_dev = &ndev->dev;
2135	u32 status = 0;
2136	u32 num_pkts = 0;
2137
2138	if (!netif_running(ndev))
2139	return 0;
2140
2141	/* Check interrupt vectors and call packet processing */
2142	status = emac_read(EMAC_MACINVECTOR);
2143
2144	mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2145
2146	if (priv->version == EMAC_VERSION_2)
2147	mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2148
2149	if (status & mask) {
2150	num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2151	EMAC_DEF_TX_MAX_SERVICE);
2152	} /* TX processing */
2153
2154	if (num_pkts)
2155	return budget;
2156
2157	mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2158
2159	if (priv->version == EMAC_VERSION_2)
2160	mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2161
2162	if (status & mask) {
2163	num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2164	} /* RX processing */
2165
2166	if (num_pkts < budget) {
2167	napi_complete(napi);
2168	emac_int_enable(priv);
2169	}
2170
2171	if (unlikely(status & EMAC_DM644X_MAC_IN_VECTOR_HOST_INT)) {
2172	u32 ch, cause;
2173	dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2174	netif_stop_queue(ndev);
2175	napi_disable(&priv->napi);
2176
2177	status = emac_read(EMAC_MACSTATUS);
2178	cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2179	EMAC_MACSTATUS_TXERRCODE_SHIFT);
2180	if (cause) {
2181	ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2182	EMAC_MACSTATUS_TXERRCH_SHIFT);
2183	if (net_ratelimit()) {
2184	dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2185	&emac_txhost_errcodes[cause][0], ch);
2186	}
2187	}
2188	cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2189	EMAC_MACSTATUS_RXERRCODE_SHIFT);
2190	if (cause) {
2191	ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2192	EMAC_MACSTATUS_RXERRCH_SHIFT);
2193	if (netif_msg_hw(priv) && net_ratelimit())
2194	dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2195	&emac_rxhost_errcodes[cause][0], ch);
2196	}
2197	} /* Host error processing */
2198
2199	return num_pkts;
2200	}
2201
2202	#ifdef CONFIG_NET_POLL_CONTROLLER
2203	/**
2204	* emac_poll_controller: EMAC Poll controller function
2205	* @ndev: The DaVinci EMAC network adapter
2206	*
2207	* Polled functionality used by netconsole and others in non interrupt mode
2208	*
2209	*/
2210	void emac_poll_controller(struct net_device *ndev)
2211	{
2212	struct emac_priv *priv = netdev_priv(ndev);
2213
2214	emac_int_disable(priv);
2215	emac_irq(ndev->irq, priv);
2216	emac_int_enable(priv);
2217	}
2218	#endif
2219
2220	/* PHY/MII bus related */
2221
2222	/* Wait until mdio is ready for next command */
2223	#define MDIO_WAIT_FOR_USER_ACCESS\
2224	while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2225	MDIO_USERACCESS_GO) != 0)
2226
2227	static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2228	{
2229	unsigned int phy_data = 0;
2230	unsigned int phy_control;
2231
2232	/* Wait until mdio is ready for next command */
2233	MDIO_WAIT_FOR_USER_ACCESS;
2234
2235	phy_control = (MDIO_USERACCESS_GO \|
2236	MDIO_USERACCESS_READ \|
2237	((phy_reg << 21) & MDIO_USERACCESS_REGADR) \|
2238	((phy_id << 16) & MDIO_USERACCESS_PHYADR) \|
2239	(phy_data & MDIO_USERACCESS_DATA));
2240	emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2241
2242	/* Wait until mdio is ready for next command */
2243	MDIO_WAIT_FOR_USER_ACCESS;
2244
2245	return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2246
2247	}
2248
2249	static int emac_mii_write(struct mii_bus *bus, int phy_id,
2250	int phy_reg, u16 phy_data)
2251	{
2252
2253	unsigned int control;
2254
2255	/* until mdio is ready for next command */
2256	MDIO_WAIT_FOR_USER_ACCESS;
2257
2258	control = (MDIO_USERACCESS_GO \|
2259	MDIO_USERACCESS_WRITE \|
2260	((phy_reg << 21) & MDIO_USERACCESS_REGADR) \|
2261	((phy_id << 16) & MDIO_USERACCESS_PHYADR) \|
2262	(phy_data & MDIO_USERACCESS_DATA));
2263	emac_mdio_write(MDIO_USERACCESS(0), control);
2264
2265	return 0;
2266	}
2267
2268	static int emac_mii_reset(struct mii_bus *bus)
2269	{
2270	unsigned int clk_div;
2271	int mdio_bus_freq = emac_bus_frequency;
2272
2273	if (mdio_max_freq & mdio_bus_freq)
2274	clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2275	else
2276	clk_div = 0xFF;
2277
2278	clk_div &= MDIO_CONTROL_CLKDIV;
2279
2280	/* Set enable and clock divider in MDIOControl */
2281	emac_mdio_write(MDIO_CONTROL, (clk_div \| MDIO_CONTROL_ENABLE));
2282
2283	return 0;
2284
2285	}
2286
2287	static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2288
2289	/* emac_driver: EMAC MII bus structure */
2290
2291	static struct mii_bus *emac_mii;
2292
2293	static void emac_adjust_link(struct net_device *ndev)
2294	{
2295	struct emac_priv *priv = netdev_priv(ndev);
2296	struct phy_device *phydev = priv->phydev;
2297	unsigned long flags;
2298	int new_state = 0;
2299
2300	spin_lock_irqsave(&priv->lock, flags);
2301
2302	if (phydev->link) {
2303	/* check the mode of operation - full/half duplex */
2304	if (phydev->duplex != priv->duplex) {
2305	new_state = 1;
2306	priv->duplex = phydev->duplex;
2307	}
2308	if (phydev->speed != priv->speed) {
2309	new_state = 1;
2310	priv->speed = phydev->speed;
2311	}
2312	if (!priv->link) {
2313	new_state = 1;
2314	priv->link = 1;
2315	}
2316
2317	} else if (priv->link) {
2318	new_state = 1;
2319	priv->link = 0;
2320	priv->speed = 0;
2321	priv->duplex = ~0;
2322	}
2323	if (new_state) {
2324	emac_update_phystatus(priv);
2325	phy_print_status(priv->phydev);
2326	}
2327
2328	spin_unlock_irqrestore(&priv->lock, flags);
2329	}
2330
2331	/*************************************************************************
2332	* Linux Driver Model
2333	*************************************************************************/
2334
2335	/**
2336	* emac_devioctl: EMAC adapter ioctl
2337	* @ndev: The DaVinci EMAC network adapter
2338	* @ifrq: request parameter
2339	* @cmd: command parameter
2340	*
2341	* EMAC driver ioctl function
2342	*
2343	* Returns success(0) or appropriate error code
2344	*/
2345	static int emac_devioctl(struct net_device ndev, struct ifreq ifrq, int cmd)
2346	{
2347	dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2348
2349	if (!(netif_running(ndev)))
2350	return -EINVAL;
2351
2352	/* TODO: Add phy read and write and private statistics get feature */
2353
2354	return -EOPNOTSUPP;
2355	}
2356
2357	/**
2358	* emac_dev_open: EMAC device open
2359	* @ndev: The DaVinci EMAC network adapter
2360	*
2361	* Called when system wants to start the interface. We init TX/RX channels
2362	* and enable the hardware for packet reception/transmission and start the
2363	* network queue.
2364	*
2365	* Returns 0 for a successful open, or appropriate error code
2366	*/
2367	static int emac_dev_open(struct net_device *ndev)
2368	{
2369	struct device *emac_dev = &ndev->dev;
2370	u32 rc, cnt, ch;
2371	int phy_addr;
2372	struct resource *res;
2373	int q, m;
2374	int i = 0;
2375	int k = 0;
2376	struct emac_priv *priv = netdev_priv(ndev);
2377
2378	netif_carrier_off(ndev);
2379	for (cnt = 0; cnt <= ETH_ALEN; cnt++)
2380	ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2381
2382	/* Configuration items */
2383	priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2384
2385	/* Clear basic hardware */
2386	for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2387	emac_write(EMAC_TXHDP(ch), 0);
2388	emac_write(EMAC_RXHDP(ch), 0);
2389	emac_write(EMAC_RXHDP(ch), 0);
2390	emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2391	emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2392	}
2393	priv->mac_hash1 = 0;
2394	priv->mac_hash2 = 0;
2395	emac_write(EMAC_MACHASH1, 0);
2396	emac_write(EMAC_MACHASH2, 0);
2397
2398	/* multi ch not supported - open 1 TX, 1RX ch by default */
2399	rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2400	if (0 != rc) {
2401	dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2402	return rc;
2403	}
2404	rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2405	if (0 != rc) {
2406	dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2407	return rc;
2408	}
2409
2410	/* Request IRQ */
2411
2412	while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2413	for (i = res->start; i <= res->end; i++) {
2414	if (request_irq(i, emac_irq, IRQF_DISABLED,
2415	ndev->name, ndev))
2416	goto rollback;
2417	}
2418	k++;
2419	}
2420
2421	/* Start/Enable EMAC hardware */
2422	emac_hw_enable(priv);
2423
2424	/* find the first phy */
2425	priv->phydev = NULL;
2426	if (priv->phy_mask) {
2427	emac_mii_reset(priv->mii_bus);
2428	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2429	if (priv->mii_bus->phy_map[phy_addr]) {
2430	priv->phydev = priv->mii_bus->phy_map[phy_addr];
2431	break;
2432	}
2433	}
2434
2435	if (!priv->phydev) {
2436	printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2437	return -1;
2438	}
2439
2440	priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2441	&emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2442
2443	if (IS_ERR(priv->phydev)) {
2444	printk(KERN_ERR "%s: Could not attach to PHY\n",
2445	ndev->name);
2446	return PTR_ERR(priv->phydev);
2447	}
2448
2449	priv->link = 0;
2450	priv->speed = 0;
2451	priv->duplex = ~0;
2452
2453	printk(KERN_INFO "%s: attached PHY driver [%s] "
2454	"(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2455	priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2456	priv->phydev->phy_id);
2457	} else{
2458	/* No PHY , fix the link, speed and duplex settings */
2459	priv->link = 1;
2460	priv->speed = SPEED_100;
2461	priv->duplex = DUPLEX_FULL;
2462	emac_update_phystatus(priv);
2463	}
2464
2465	if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2466	emac_dump_regs(priv);
2467
2468	if (netif_msg_drv(priv))
2469	dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2470
2471	if (priv->phy_mask)
2472	phy_start(priv->phydev);
2473
2474	return 0;
2475
2476	rollback:
2477
2478	dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2479
2480	for (q = k; k >= 0; k--) {
2481	for (m = i; m >= res->start; m--)
2482	free_irq(m, ndev);
2483	res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2484	m = res->end;
2485	}
2486	return -EBUSY;
2487	}
2488
2489	/**
2490	* emac_dev_stop: EMAC device stop
2491	* @ndev: The DaVinci EMAC network adapter
2492	*
2493	* Called when system wants to stop or down the interface. We stop the network
2494	* queue, disable interrupts and cleanup TX/RX channels.
2495	*
2496	* We return the statistics in net_device_stats structure pulled from emac
2497	*/
2498	static int emac_dev_stop(struct net_device *ndev)
2499	{
2500	struct resource *res;
2501	int i = 0;
2502	int irq_num;
2503	struct emac_priv *priv = netdev_priv(ndev);
2504	struct device *emac_dev = &ndev->dev;
2505
2506	/* inform the upper layers. */
2507	netif_stop_queue(ndev);
2508	napi_disable(&priv->napi);
2509
2510	netif_carrier_off(ndev);
2511	emac_int_disable(priv);
2512	emac_stop_txch(priv, EMAC_DEF_TX_CH);
2513	emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2514	emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2515	emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2516	emac_write(EMAC_SOFTRESET, 1);
2517
2518	if (priv->phydev)
2519	phy_disconnect(priv->phydev);
2520
2521	/* Free IRQ */
2522	while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2523	for (irq_num = res->start; irq_num <= res->end; irq_num++)
2524	free_irq(irq_num, priv->ndev);
2525	i++;
2526	}
2527
2528	if (netif_msg_drv(priv))
2529	dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2530
2531	return 0;
2532	}
2533
2534	/**
2535	* emac_dev_getnetstats: EMAC get statistics function
2536	* @ndev: The DaVinci EMAC network adapter
2537	*
2538	* Called when system wants to get statistics from the device.
2539	*
2540	* We return the statistics in net_device_stats structure pulled from emac
2541	*/
2542	static struct net_device_stats emac_dev_getnetstats(struct net_device ndev)
2543	{
2544	struct emac_priv *priv = netdev_priv(ndev);
2545
2546	/* update emac hardware stats and reset the registers*/
2547
2548	priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2549	emac_write(EMAC_RXMCASTFRAMES, EMAC_ALL_MULTI_REG_VALUE);
2550
2551	priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2552	emac_read(EMAC_TXSINGLECOLL) +
2553	emac_read(EMAC_TXMULTICOLL));
2554	emac_write(EMAC_TXCOLLISION, EMAC_ALL_MULTI_REG_VALUE);
2555	emac_write(EMAC_TXSINGLECOLL, EMAC_ALL_MULTI_REG_VALUE);
2556	emac_write(EMAC_TXMULTICOLL, EMAC_ALL_MULTI_REG_VALUE);
2557
2558	priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2559	emac_read(EMAC_RXJABBER) +
2560	emac_read(EMAC_RXUNDERSIZED));
2561	emac_write(EMAC_RXOVERSIZED, EMAC_ALL_MULTI_REG_VALUE);
2562	emac_write(EMAC_RXJABBER, EMAC_ALL_MULTI_REG_VALUE);
2563	emac_write(EMAC_RXUNDERSIZED, EMAC_ALL_MULTI_REG_VALUE);
2564
2565	priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2566	emac_read(EMAC_RXMOFOVERRUNS));
2567	emac_write(EMAC_RXSOFOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
2568	emac_write(EMAC_RXMOFOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
2569
2570	priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2571	emac_write(EMAC_RXDMAOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
2572
2573	priv->net_dev_stats.tx_carrier_errors +=
2574	emac_read(EMAC_TXCARRIERSENSE);
2575	emac_write(EMAC_TXCARRIERSENSE, EMAC_ALL_MULTI_REG_VALUE);
2576
2577	priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2578	emac_write(EMAC_TXUNDERRUN, EMAC_ALL_MULTI_REG_VALUE);
2579
2580	return &priv->net_dev_stats;
2581	}
2582
2583	static const struct net_device_ops emac_netdev_ops = {
2584	.ndo_open = emac_dev_open,
2585	.ndo_stop = emac_dev_stop,
2586	.ndo_start_xmit = emac_dev_xmit,
2587	.ndo_set_multicast_list = emac_dev_mcast_set,
2588	.ndo_set_mac_address = emac_dev_setmac_addr,
2589	.ndo_do_ioctl = emac_devioctl,
2590	.ndo_tx_timeout = emac_dev_tx_timeout,
2591	.ndo_get_stats = emac_dev_getnetstats,
2592	#ifdef CONFIG_NET_POLL_CONTROLLER
2593	.ndo_poll_controller = emac_poll_controller,
2594	#endif
2595	};
2596
2597	/**
2598	* davinci_emac_probe: EMAC device probe
2599	* @pdev: The DaVinci EMAC device that we are removing
2600	*
2601	* Called when probing for emac devicesr. We get details of instances and
2602	* resource information from platform init and register a network device
2603	* and allocate resources necessary for driver to perform
2604	*/
2605	static int __devinit davinci_emac_probe(struct platform_device *pdev)
2606	{
2607	int rc = 0;
2608	struct resource *res;
2609	struct net_device *ndev;
2610	struct emac_priv *priv;
2611	unsigned long size;
2612	struct emac_platform_data *pdata;
2613	struct device *emac_dev;
2614
2615	/* obtain emac clock from kernel */
2616	emac_clk = clk_get(&pdev->dev, NULL);
2617	if (IS_ERR(emac_clk)) {
2618	printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2619	return -EBUSY;
2620	}
2621	emac_bus_frequency = clk_get_rate(emac_clk);
2622	/* TODO: Probe PHY here if possible */
2623
2624	ndev = alloc_etherdev(sizeof(struct emac_priv));
2625	if (!ndev) {
2626	printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2627	clk_put(emac_clk);
2628	return -ENOMEM;
2629	}
2630
2631	platform_set_drvdata(pdev, ndev);
2632	priv = netdev_priv(ndev);
2633	priv->pdev = pdev;
2634	priv->ndev = ndev;
2635	priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2636
2637	spin_lock_init(&priv->tx_lock);
2638	spin_lock_init(&priv->rx_lock);
2639	spin_lock_init(&priv->lock);
2640
2641	pdata = pdev->dev.platform_data;
2642	if (!pdata) {
2643	printk(KERN_ERR "DaVinci EMAC: No platfrom data\n");
2644	return -ENODEV;
2645	}
2646
2647	/* MAC addr and PHY mask , RMII enable info from platform_data */
2648	memcpy(priv->mac_addr, pdata->mac_addr, 6);
2649	priv->phy_mask = pdata->phy_mask;
2650	priv->rmii_en = pdata->rmii_en;
2651	priv->version = pdata->version;
2652	emac_dev = &ndev->dev;
2653	/* Get EMAC platform data */
2654	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2655	if (!res) {
2656	dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2657	rc = -ENOENT;
2658	goto probe_quit;
2659	}
2660
2661	priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2662	size = res->end - res->start + 1;
2663	if (!request_mem_region(res->start, size, ndev->name)) {
2664	dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() \
2665	for regs\n");
2666	rc = -ENXIO;
2667	goto probe_quit;
2668	}
2669
2670	priv->remap_addr = ioremap(res->start, size);
2671	if (!priv->remap_addr) {
2672	dev_err(emac_dev, "Unable to map IO\n");
2673	rc = -ENOMEM;
2674	release_mem_region(res->start, size);
2675	goto probe_quit;
2676	}
2677	priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2678	ndev->base_addr = (unsigned long)priv->remap_addr;
2679
2680	priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2681	priv->ctrl_ram_size = pdata->ctrl_ram_size;
2682	priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2683
2684	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2685	if (!res) {
2686	dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2687	rc = -ENOENT;
2688	goto no_irq_res;
2689	}
2690	ndev->irq = res->start;
2691
2692	if (!is_valid_ether_addr(priv->mac_addr)) {
2693	/* Use random MAC if none passed */
2694	random_ether_addr(priv->mac_addr);
2695	printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2696	__func__, priv->mac_addr);
2697	}
2698
2699	ndev->netdev_ops = &emac_netdev_ops;
2700	SET_ETHTOOL_OPS(ndev, &ethtool_ops);
2701	netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2702
2703	/* register the network device */
2704	SET_NETDEV_DEV(ndev, &pdev->dev);
2705	rc = register_netdev(ndev);
2706	if (rc) {
2707	dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2708	rc = -ENODEV;
2709	goto netdev_reg_err;
2710	}
2711
2712	clk_enable(emac_clk);
2713
2714	/* MII/Phy intialisation, mdio bus registration */
2715	emac_mii = mdiobus_alloc();
2716	if (emac_mii == NULL) {
2717	dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2718	rc = -ENOMEM;
2719	goto mdio_alloc_err;
2720	}
2721
2722	priv->mii_bus = emac_mii;
2723	emac_mii->name = "emac-mii",
2724	emac_mii->read = emac_mii_read,
2725	emac_mii->write = emac_mii_write,
2726	emac_mii->reset = emac_mii_reset,
2727	emac_mii->irq = mii_irqs,
2728	emac_mii->phy_mask = ~(priv->phy_mask);
2729	emac_mii->parent = &pdev->dev;
2730	emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2731	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2732	mdio_max_freq = pdata->mdio_max_freq;
2733	emac_mii->reset(emac_mii);
2734
2735	/* Register the MII bus */
2736	rc = mdiobus_register(emac_mii);
2737	if (rc)
2738	goto mdiobus_quit;
2739
2740	if (netif_msg_probe(priv)) {
2741	dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2742	"(regs: %p, irq: %d)\n",
2743	(void *)priv->emac_base_phys, ndev->irq);
2744	}
2745	return 0;
2746
2747	mdiobus_quit:
2748	mdiobus_free(emac_mii);
2749
2750	netdev_reg_err:
2751	mdio_alloc_err:
2752	no_irq_res:
2753	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2754	release_mem_region(res->start, res->end - res->start + 1);
2755	iounmap(priv->remap_addr);
2756
2757	probe_quit:
2758	clk_put(emac_clk);
2759	free_netdev(ndev);
2760	return rc;
2761	}
2762
2763	/**
2764	* davinci_emac_remove: EMAC device remove
2765	* @pdev: The DaVinci EMAC device that we are removing
2766	*
2767	* Called when removing the device driver. We disable clock usage and release
2768	* the resources taken up by the driver and unregister network device
2769	*/
2770	static int __devexit davinci_emac_remove(struct platform_device *pdev)
2771	{
2772	struct resource *res;
2773	struct net_device *ndev = platform_get_drvdata(pdev);
2774	struct emac_priv *priv = netdev_priv(ndev);
2775
2776	dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2777
2778	platform_set_drvdata(pdev, NULL);
2779	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2780	mdiobus_unregister(priv->mii_bus);
2781	mdiobus_free(priv->mii_bus);
2782
2783	release_mem_region(res->start, res->end - res->start + 1);
2784
2785	unregister_netdev(ndev);
2786	free_netdev(ndev);
2787	iounmap(priv->remap_addr);
2788
2789	clk_disable(emac_clk);
2790	clk_put(emac_clk);
2791
2792	return 0;
2793	}
2794
2795	/**
2796	* davinci_emac_driver: EMAC platform driver structure
2797	*
2798	* We implement only probe and remove functions - suspend/resume and
2799	* others not supported by this module
2800	*/
2801	static struct platform_driver davinci_emac_driver = {
2802	.driver = {
2803	.name = "davinci_emac",
2804	.owner = THIS_MODULE,
2805	},
2806	.probe = davinci_emac_probe,
2807	.remove = __devexit_p(davinci_emac_remove),
2808	};
2809
2810	/**
2811	* davinci_emac_init: EMAC driver module init
2812	*
2813	* Called when initializing the driver. We register the driver with
2814	* the platform.
2815	*/
2816	static int __init davinci_emac_init(void)
2817	{
2818	return platform_driver_register(&davinci_emac_driver);
2819	}
2820	module_init(davinci_emac_init);
2821
2822	/**
2823	* davinci_emac_exit: EMAC driver module exit
2824	*
2825	* Called when exiting the driver completely. We unregister the driver with
2826	* the platform and exit
2827	*/
2828	static void __exit davinci_emac_exit(void)
2829	{
2830	platform_driver_unregister(&davinci_emac_driver);
2831	}
2832	module_exit(davinci_emac_exit);
2833
2834	MODULE_LICENSE("GPL");
2835	MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2836	MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2837	MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
2838

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