Root/drivers/net/epic100.c

1/* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2/*
3    Written/copyright 1997-2001 by Donald Becker.
4
5    This software may be used and distributed according to the terms of
6    the GNU General Public License (GPL), incorporated herein by reference.
7    Drivers based on or derived from this code fall under the GPL and must
8    retain the authorship, copyright and license notice. This file is not
9    a complete program and may only be used when the entire operating
10    system is licensed under the GPL.
11
12    This driver is for the SMC83c170/175 "EPIC" series, as used on the
13    SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15    The author may be reached as becker@scyld.com, or C/O
16    Scyld Computing Corporation
17    410 Severn Ave., Suite 210
18    Annapolis MD 21403
19
20    Information and updates available at
21    http://www.scyld.com/network/epic100.html
22    [this link no longer provides anything useful -jgarzik]
23
24    ---------------------------------------------------------------------
25
26*/
27
28#define DRV_NAME "epic100"
29#define DRV_VERSION "2.1"
30#define DRV_RELDATE "Sept 11, 2006"
31
32/* The user-configurable values.
33   These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36
37/* Used to pass the full-duplex flag, etc. */
38#define MAX_UNITS 8 /* More are supported, limit only on options */
39static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
41
42/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43   Setting to > 1518 effectively disables this feature. */
44static int rx_copybreak;
45
46/* Operational parameters that are set at compile time. */
47
48/* Keep the ring sizes a power of two for operational efficiency.
49   The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50   Making the Tx ring too large decreases the effectiveness of channel
51   bonding and packet priority.
52   There are no ill effects from too-large receive rings. */
53#define TX_RING_SIZE 256
54#define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55#define RX_RING_SIZE 256
56#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
58
59/* Operational parameters that usually are not changed. */
60/* Time in jiffies before concluding the transmitter is hung. */
61#define TX_TIMEOUT (2*HZ)
62
63#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
64
65/* Bytes transferred to chip before transmission starts. */
66/* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67#define TX_FIFO_THRESH 256
68#define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
69
70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/string.h>
73#include <linux/timer.h>
74#include <linux/errno.h>
75#include <linux/ioport.h>
76#include <linux/slab.h>
77#include <linux/interrupt.h>
78#include <linux/pci.h>
79#include <linux/delay.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/init.h>
84#include <linux/spinlock.h>
85#include <linux/ethtool.h>
86#include <linux/mii.h>
87#include <linux/crc32.h>
88#include <linux/bitops.h>
89#include <asm/io.h>
90#include <asm/uaccess.h>
91
92/* These identify the driver base version and may not be removed. */
93static char version[] __devinitdata =
94DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
95static char version2[] __devinitdata =
96" (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
97
98MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
99MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
100MODULE_LICENSE("GPL");
101
102module_param(debug, int, 0);
103module_param(rx_copybreak, int, 0);
104module_param_array(options, int, NULL, 0);
105module_param_array(full_duplex, int, NULL, 0);
106MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
107MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
108MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
109MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
110
111/*
112                Theory of Operation
113
114I. Board Compatibility
115
116This device driver is designed for the SMC "EPIC/100", the SMC
117single-chip Ethernet controllers for PCI. This chip is used on
118the SMC EtherPower II boards.
119
120II. Board-specific settings
121
122PCI bus devices are configured by the system at boot time, so no jumpers
123need to be set on the board. The system BIOS will assign the
124PCI INTA signal to a (preferably otherwise unused) system IRQ line.
125Note: Kernel versions earlier than 1.3.73 do not support shared PCI
126interrupt lines.
127
128III. Driver operation
129
130IIIa. Ring buffers
131
132IVb. References
133
134http://www.smsc.com/main/tools/discontinued/83c171.pdf
135http://www.smsc.com/main/tools/discontinued/83c175.pdf
136http://scyld.com/expert/NWay.html
137http://www.national.com/pf/DP/DP83840A.html
138
139IVc. Errata
140
141*/
142
143
144enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
145
146#define EPIC_TOTAL_SIZE 0x100
147#define USE_IO_OPS 1
148
149typedef enum {
150    SMSC_83C170_0,
151    SMSC_83C170,
152    SMSC_83C175,
153} chip_t;
154
155
156struct epic_chip_info {
157    const char *name;
158        int drv_flags; /* Driver use, intended as capability flags. */
159};
160
161
162/* indexed by chip_t */
163static const struct epic_chip_info pci_id_tbl[] = {
164    { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
165    { "SMSC EPIC/100 83c170", TYPE2_INTR },
166    { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
167};
168
169
170static struct pci_device_id epic_pci_tbl[] = {
171    { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
172    { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
173    { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
174      PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
175    { 0,}
176};
177MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
178
179
180#ifndef USE_IO_OPS
181#undef inb
182#undef inw
183#undef inl
184#undef outb
185#undef outw
186#undef outl
187#define inb readb
188#define inw readw
189#define inl readl
190#define outb writeb
191#define outw writew
192#define outl writel
193#endif
194
195/* Offsets to registers, using the (ugh) SMC names. */
196enum epic_registers {
197  COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
198  PCIBurstCnt=0x18,
199  TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
200  MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
201  LAN0=64, /* MAC address. */
202  MC0=80, /* Multicast filter table. */
203  RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
204  PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
205};
206
207/* Interrupt register bits, using my own meaningful names. */
208enum IntrStatus {
209    TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
210    PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
211    RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
212    TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
213    RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
214};
215enum CommandBits {
216    StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
217    StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
218};
219
220#define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
221
222#define EpicNapiEvent (TxEmpty | TxDone | \
223             RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
224#define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
225
226static const u16 media2miictl[16] = {
227    0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
228    0, 0, 0, 0, 0, 0, 0, 0 };
229
230/*
231 * The EPIC100 Rx and Tx buffer descriptors. Note that these
232 * really ARE host-endian; it's not a misannotation. We tell
233 * the card to byteswap them internally on big-endian hosts -
234 * look for #ifdef CONFIG_BIG_ENDIAN in epic_open().
235 */
236
237struct epic_tx_desc {
238    u32 txstatus;
239    u32 bufaddr;
240    u32 buflength;
241    u32 next;
242};
243
244struct epic_rx_desc {
245    u32 rxstatus;
246    u32 bufaddr;
247    u32 buflength;
248    u32 next;
249};
250
251enum desc_status_bits {
252    DescOwn=0x8000,
253};
254
255#define PRIV_ALIGN 15 /* Required alignment mask */
256struct epic_private {
257    struct epic_rx_desc *rx_ring;
258    struct epic_tx_desc *tx_ring;
259    /* The saved address of a sent-in-place packet/buffer, for skfree(). */
260    struct sk_buff* tx_skbuff[TX_RING_SIZE];
261    /* The addresses of receive-in-place skbuffs. */
262    struct sk_buff* rx_skbuff[RX_RING_SIZE];
263
264    dma_addr_t tx_ring_dma;
265    dma_addr_t rx_ring_dma;
266
267    /* Ring pointers. */
268    spinlock_t lock; /* Group with Tx control cache line. */
269    spinlock_t napi_lock;
270    struct napi_struct napi;
271    unsigned int reschedule_in_poll;
272    unsigned int cur_tx, dirty_tx;
273
274    unsigned int cur_rx, dirty_rx;
275    u32 irq_mask;
276    unsigned int rx_buf_sz; /* Based on MTU+slack. */
277
278    struct pci_dev *pci_dev; /* PCI bus location. */
279    int chip_id, chip_flags;
280
281    struct net_device_stats stats;
282    struct timer_list timer; /* Media selection timer. */
283    int tx_threshold;
284    unsigned char mc_filter[8];
285    signed char phys[4]; /* MII device addresses. */
286    u16 advertising; /* NWay media advertisement */
287    int mii_phy_cnt;
288    struct mii_if_info mii;
289    unsigned int tx_full:1; /* The Tx queue is full. */
290    unsigned int default_port:4; /* Last dev->if_port value. */
291};
292
293static int epic_open(struct net_device *dev);
294static int read_eeprom(long ioaddr, int location);
295static int mdio_read(struct net_device *dev, int phy_id, int location);
296static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
297static void epic_restart(struct net_device *dev);
298static void epic_timer(unsigned long data);
299static void epic_tx_timeout(struct net_device *dev);
300static void epic_init_ring(struct net_device *dev);
301static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
302static int epic_rx(struct net_device *dev, int budget);
303static int epic_poll(struct napi_struct *napi, int budget);
304static irqreturn_t epic_interrupt(int irq, void *dev_instance);
305static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
306static const struct ethtool_ops netdev_ethtool_ops;
307static int epic_close(struct net_device *dev);
308static struct net_device_stats *epic_get_stats(struct net_device *dev);
309static void set_rx_mode(struct net_device *dev);
310
311static const struct net_device_ops epic_netdev_ops = {
312    .ndo_open = epic_open,
313    .ndo_stop = epic_close,
314    .ndo_start_xmit = epic_start_xmit,
315    .ndo_tx_timeout = epic_tx_timeout,
316    .ndo_get_stats = epic_get_stats,
317    .ndo_set_multicast_list = set_rx_mode,
318    .ndo_do_ioctl = netdev_ioctl,
319    .ndo_change_mtu = eth_change_mtu,
320    .ndo_set_mac_address = eth_mac_addr,
321    .ndo_validate_addr = eth_validate_addr,
322};
323
324static int __devinit epic_init_one (struct pci_dev *pdev,
325                    const struct pci_device_id *ent)
326{
327    static int card_idx = -1;
328    long ioaddr;
329    int chip_idx = (int) ent->driver_data;
330    int irq;
331    struct net_device *dev;
332    struct epic_private *ep;
333    int i, ret, option = 0, duplex = 0;
334    void *ring_space;
335    dma_addr_t ring_dma;
336
337/* when built into the kernel, we only print version if device is found */
338#ifndef MODULE
339    static int printed_version;
340    if (!printed_version++)
341        printk(KERN_INFO "%s%s", version, version2);
342#endif
343
344    card_idx++;
345
346    ret = pci_enable_device(pdev);
347    if (ret)
348        goto out;
349    irq = pdev->irq;
350
351    if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
352        dev_err(&pdev->dev, "no PCI region space\n");
353        ret = -ENODEV;
354        goto err_out_disable;
355    }
356
357    pci_set_master(pdev);
358
359    ret = pci_request_regions(pdev, DRV_NAME);
360    if (ret < 0)
361        goto err_out_disable;
362
363    ret = -ENOMEM;
364
365    dev = alloc_etherdev(sizeof (*ep));
366    if (!dev) {
367        dev_err(&pdev->dev, "no memory for eth device\n");
368        goto err_out_free_res;
369    }
370    SET_NETDEV_DEV(dev, &pdev->dev);
371
372#ifdef USE_IO_OPS
373    ioaddr = pci_resource_start (pdev, 0);
374#else
375    ioaddr = pci_resource_start (pdev, 1);
376    ioaddr = (long) pci_ioremap_bar(pdev, 1);
377    if (!ioaddr) {
378        dev_err(&pdev->dev, "ioremap failed\n");
379        goto err_out_free_netdev;
380    }
381#endif
382
383    pci_set_drvdata(pdev, dev);
384    ep = netdev_priv(dev);
385    ep->mii.dev = dev;
386    ep->mii.mdio_read = mdio_read;
387    ep->mii.mdio_write = mdio_write;
388    ep->mii.phy_id_mask = 0x1f;
389    ep->mii.reg_num_mask = 0x1f;
390
391    ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
392    if (!ring_space)
393        goto err_out_iounmap;
394    ep->tx_ring = (struct epic_tx_desc *)ring_space;
395    ep->tx_ring_dma = ring_dma;
396
397    ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
398    if (!ring_space)
399        goto err_out_unmap_tx;
400    ep->rx_ring = (struct epic_rx_desc *)ring_space;
401    ep->rx_ring_dma = ring_dma;
402
403    if (dev->mem_start) {
404        option = dev->mem_start;
405        duplex = (dev->mem_start & 16) ? 1 : 0;
406    } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
407        if (options[card_idx] >= 0)
408            option = options[card_idx];
409        if (full_duplex[card_idx] >= 0)
410            duplex = full_duplex[card_idx];
411    }
412
413    dev->base_addr = ioaddr;
414    dev->irq = irq;
415
416    spin_lock_init(&ep->lock);
417    spin_lock_init(&ep->napi_lock);
418    ep->reschedule_in_poll = 0;
419
420    /* Bring the chip out of low-power mode. */
421    outl(0x4200, ioaddr + GENCTL);
422    /* Magic?! If we don't set this bit the MII interface won't work. */
423    /* This magic is documented in SMSC app note 7.15 */
424    for (i = 16; i > 0; i--)
425        outl(0x0008, ioaddr + TEST1);
426
427    /* Turn on the MII transceiver. */
428    outl(0x12, ioaddr + MIICfg);
429    if (chip_idx == 1)
430        outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
431    outl(0x0200, ioaddr + GENCTL);
432
433    /* Note: the '175 does not have a serial EEPROM. */
434    for (i = 0; i < 3; i++)
435        ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(inw(ioaddr + LAN0 + i*4));
436
437    if (debug > 2) {
438        dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
439        for (i = 0; i < 64; i++)
440            printk(" %4.4x%s", read_eeprom(ioaddr, i),
441                   i % 16 == 15 ? "\n" : "");
442    }
443
444    ep->pci_dev = pdev;
445    ep->chip_id = chip_idx;
446    ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
447    ep->irq_mask =
448        (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
449         | CntFull | TxUnderrun | EpicNapiEvent;
450
451    /* Find the connected MII xcvrs.
452       Doing this in open() would allow detecting external xcvrs later, but
453       takes much time and no cards have external MII. */
454    {
455        int phy, phy_idx = 0;
456        for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
457            int mii_status = mdio_read(dev, phy, MII_BMSR);
458            if (mii_status != 0xffff && mii_status != 0x0000) {
459                ep->phys[phy_idx++] = phy;
460                dev_info(&pdev->dev,
461                    "MII transceiver #%d control "
462                    "%4.4x status %4.4x.\n",
463                    phy, mdio_read(dev, phy, 0), mii_status);
464            }
465        }
466        ep->mii_phy_cnt = phy_idx;
467        if (phy_idx != 0) {
468            phy = ep->phys[0];
469            ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
470            dev_info(&pdev->dev,
471                "Autonegotiation advertising %4.4x link "
472                   "partner %4.4x.\n",
473                   ep->mii.advertising, mdio_read(dev, phy, 5));
474        } else if ( ! (ep->chip_flags & NO_MII)) {
475            dev_warn(&pdev->dev,
476                "***WARNING***: No MII transceiver found!\n");
477            /* Use the known PHY address of the EPII. */
478            ep->phys[0] = 3;
479        }
480        ep->mii.phy_id = ep->phys[0];
481    }
482
483    /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
484    if (ep->chip_flags & MII_PWRDWN)
485        outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
486    outl(0x0008, ioaddr + GENCTL);
487
488    /* The lower four bits are the media type. */
489    if (duplex) {
490        ep->mii.force_media = ep->mii.full_duplex = 1;
491        dev_info(&pdev->dev, "Forced full duplex requested.\n");
492    }
493    dev->if_port = ep->default_port = option;
494
495    /* The Epic-specific entries in the device structure. */
496    dev->netdev_ops = &epic_netdev_ops;
497    dev->ethtool_ops = &netdev_ethtool_ops;
498    dev->watchdog_timeo = TX_TIMEOUT;
499    netif_napi_add(dev, &ep->napi, epic_poll, 64);
500
501    ret = register_netdev(dev);
502    if (ret < 0)
503        goto err_out_unmap_rx;
504
505    printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %pM\n",
506           dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq,
507           dev->dev_addr);
508
509out:
510    return ret;
511
512err_out_unmap_rx:
513    pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
514err_out_unmap_tx:
515    pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
516err_out_iounmap:
517#ifndef USE_IO_OPS
518    iounmap(ioaddr);
519err_out_free_netdev:
520#endif
521    free_netdev(dev);
522err_out_free_res:
523    pci_release_regions(pdev);
524err_out_disable:
525    pci_disable_device(pdev);
526    goto out;
527}
528
529/* Serial EEPROM section. */
530
531/* EEPROM_Ctrl bits. */
532#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
533#define EE_CS 0x02 /* EEPROM chip select. */
534#define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
535#define EE_WRITE_0 0x01
536#define EE_WRITE_1 0x09
537#define EE_DATA_READ 0x10 /* EEPROM chip data out. */
538#define EE_ENB (0x0001 | EE_CS)
539
540/* Delay between EEPROM clock transitions.
541   This serves to flush the operation to the PCI bus.
542 */
543
544#define eeprom_delay() inl(ee_addr)
545
546/* The EEPROM commands include the alway-set leading bit. */
547#define EE_WRITE_CMD (5 << 6)
548#define EE_READ64_CMD (6 << 6)
549#define EE_READ256_CMD (6 << 8)
550#define EE_ERASE_CMD (7 << 6)
551
552static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
553{
554    long ioaddr = dev->base_addr;
555
556    outl(0x00000000, ioaddr + INTMASK);
557}
558
559static inline void __epic_pci_commit(long ioaddr)
560{
561#ifndef USE_IO_OPS
562    inl(ioaddr + INTMASK);
563#endif
564}
565
566static inline void epic_napi_irq_off(struct net_device *dev,
567                     struct epic_private *ep)
568{
569    long ioaddr = dev->base_addr;
570
571    outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
572    __epic_pci_commit(ioaddr);
573}
574
575static inline void epic_napi_irq_on(struct net_device *dev,
576                    struct epic_private *ep)
577{
578    long ioaddr = dev->base_addr;
579
580    /* No need to commit possible posted write */
581    outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
582}
583
584static int __devinit read_eeprom(long ioaddr, int location)
585{
586    int i;
587    int retval = 0;
588    long ee_addr = ioaddr + EECTL;
589    int read_cmd = location |
590        (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
591
592    outl(EE_ENB & ~EE_CS, ee_addr);
593    outl(EE_ENB, ee_addr);
594
595    /* Shift the read command bits out. */
596    for (i = 12; i >= 0; i--) {
597        short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
598        outl(EE_ENB | dataval, ee_addr);
599        eeprom_delay();
600        outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
601        eeprom_delay();
602    }
603    outl(EE_ENB, ee_addr);
604
605    for (i = 16; i > 0; i--) {
606        outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
607        eeprom_delay();
608        retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
609        outl(EE_ENB, ee_addr);
610        eeprom_delay();
611    }
612
613    /* Terminate the EEPROM access. */
614    outl(EE_ENB & ~EE_CS, ee_addr);
615    return retval;
616}
617
618#define MII_READOP 1
619#define MII_WRITEOP 2
620static int mdio_read(struct net_device *dev, int phy_id, int location)
621{
622    long ioaddr = dev->base_addr;
623    int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
624    int i;
625
626    outl(read_cmd, ioaddr + MIICtrl);
627    /* Typical operation takes 25 loops. */
628    for (i = 400; i > 0; i--) {
629        barrier();
630        if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
631            /* Work around read failure bug. */
632            if (phy_id == 1 && location < 6
633                && inw(ioaddr + MIIData) == 0xffff) {
634                outl(read_cmd, ioaddr + MIICtrl);
635                continue;
636            }
637            return inw(ioaddr + MIIData);
638        }
639    }
640    return 0xffff;
641}
642
643static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
644{
645    long ioaddr = dev->base_addr;
646    int i;
647
648    outw(value, ioaddr + MIIData);
649    outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
650    for (i = 10000; i > 0; i--) {
651        barrier();
652        if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
653            break;
654    }
655    return;
656}
657
658
659static int epic_open(struct net_device *dev)
660{
661    struct epic_private *ep = netdev_priv(dev);
662    long ioaddr = dev->base_addr;
663    int i;
664    int retval;
665
666    /* Soft reset the chip. */
667    outl(0x4001, ioaddr + GENCTL);
668
669    napi_enable(&ep->napi);
670    if ((retval = request_irq(dev->irq, &epic_interrupt, IRQF_SHARED, dev->name, dev))) {
671        napi_disable(&ep->napi);
672        return retval;
673    }
674
675    epic_init_ring(dev);
676
677    outl(0x4000, ioaddr + GENCTL);
678    /* This magic is documented in SMSC app note 7.15 */
679    for (i = 16; i > 0; i--)
680        outl(0x0008, ioaddr + TEST1);
681
682    /* Pull the chip out of low-power mode, enable interrupts, and set for
683       PCI read multiple. The MIIcfg setting and strange write order are
684       required by the details of which bits are reset and the transceiver
685       wiring on the Ositech CardBus card.
686    */
687#if 0
688    outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
689#endif
690    if (ep->chip_flags & MII_PWRDWN)
691        outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
692
693    /* Tell the chip to byteswap descriptors on big-endian hosts */
694#ifdef CONFIG_BIG_ENDIAN
695    outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
696    inl(ioaddr + GENCTL);
697    outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
698#else
699    outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
700    inl(ioaddr + GENCTL);
701    outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
702#endif
703
704    udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
705
706    for (i = 0; i < 3; i++)
707        outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
708
709    ep->tx_threshold = TX_FIFO_THRESH;
710    outl(ep->tx_threshold, ioaddr + TxThresh);
711
712    if (media2miictl[dev->if_port & 15]) {
713        if (ep->mii_phy_cnt)
714            mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
715        if (dev->if_port == 1) {
716            if (debug > 1)
717                printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
718                       "status %4.4x.\n",
719                       dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
720        }
721    } else {
722        int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
723        if (mii_lpa != 0xffff) {
724            if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
725                ep->mii.full_duplex = 1;
726            else if (! (mii_lpa & LPA_LPACK))
727                mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
728            if (debug > 1)
729                printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
730                       " register read of %4.4x.\n", dev->name,
731                       ep->mii.full_duplex ? "full" : "half",
732                       ep->phys[0], mii_lpa);
733        }
734    }
735
736    outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
737    outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
738    outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
739
740    /* Start the chip's Rx process. */
741    set_rx_mode(dev);
742    outl(StartRx | RxQueued, ioaddr + COMMAND);
743
744    netif_start_queue(dev);
745
746    /* Enable interrupts by setting the interrupt mask. */
747    outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
748         | CntFull | TxUnderrun
749         | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
750
751    if (debug > 1)
752        printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
753               "%s-duplex.\n",
754               dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
755               ep->mii.full_duplex ? "full" : "half");
756
757    /* Set the timer to switch to check for link beat and perhaps switch
758       to an alternate media type. */
759    init_timer(&ep->timer);
760    ep->timer.expires = jiffies + 3*HZ;
761    ep->timer.data = (unsigned long)dev;
762    ep->timer.function = &epic_timer; /* timer handler */
763    add_timer(&ep->timer);
764
765    return 0;
766}
767
768/* Reset the chip to recover from a PCI transaction error.
769   This may occur at interrupt time. */
770static void epic_pause(struct net_device *dev)
771{
772    long ioaddr = dev->base_addr;
773    struct epic_private *ep = netdev_priv(dev);
774
775    netif_stop_queue (dev);
776
777    /* Disable interrupts by clearing the interrupt mask. */
778    outl(0x00000000, ioaddr + INTMASK);
779    /* Stop the chip's Tx and Rx DMA processes. */
780    outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
781
782    /* Update the error counts. */
783    if (inw(ioaddr + COMMAND) != 0xffff) {
784        ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
785        ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
786        ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
787    }
788
789    /* Remove the packets on the Rx queue. */
790    epic_rx(dev, RX_RING_SIZE);
791}
792
793static void epic_restart(struct net_device *dev)
794{
795    long ioaddr = dev->base_addr;
796    struct epic_private *ep = netdev_priv(dev);
797    int i;
798
799    /* Soft reset the chip. */
800    outl(0x4001, ioaddr + GENCTL);
801
802    printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
803           dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
804    udelay(1);
805
806    /* This magic is documented in SMSC app note 7.15 */
807    for (i = 16; i > 0; i--)
808        outl(0x0008, ioaddr + TEST1);
809
810#ifdef CONFIG_BIG_ENDIAN
811    outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
812#else
813    outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
814#endif
815    outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
816    if (ep->chip_flags & MII_PWRDWN)
817        outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
818
819    for (i = 0; i < 3; i++)
820        outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
821
822    ep->tx_threshold = TX_FIFO_THRESH;
823    outl(ep->tx_threshold, ioaddr + TxThresh);
824    outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
825    outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
826        sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
827    outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
828         sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
829
830    /* Start the chip's Rx process. */
831    set_rx_mode(dev);
832    outl(StartRx | RxQueued, ioaddr + COMMAND);
833
834    /* Enable interrupts by setting the interrupt mask. */
835    outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
836         | CntFull | TxUnderrun
837         | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
838
839    printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
840           " interrupt %4.4x.\n",
841           dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
842           (int)inl(ioaddr + INTSTAT));
843    return;
844}
845
846static void check_media(struct net_device *dev)
847{
848    struct epic_private *ep = netdev_priv(dev);
849    long ioaddr = dev->base_addr;
850    int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
851    int negotiated = mii_lpa & ep->mii.advertising;
852    int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
853
854    if (ep->mii.force_media)
855        return;
856    if (mii_lpa == 0xffff) /* Bogus read */
857        return;
858    if (ep->mii.full_duplex != duplex) {
859        ep->mii.full_duplex = duplex;
860        printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
861               " partner capability of %4.4x.\n", dev->name,
862               ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
863        outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
864    }
865}
866
867static void epic_timer(unsigned long data)
868{
869    struct net_device *dev = (struct net_device *)data;
870    struct epic_private *ep = netdev_priv(dev);
871    long ioaddr = dev->base_addr;
872    int next_tick = 5*HZ;
873
874    if (debug > 3) {
875        printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
876               dev->name, (int)inl(ioaddr + TxSTAT));
877        printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
878               "IntStatus %4.4x RxStatus %4.4x.\n",
879               dev->name, (int)inl(ioaddr + INTMASK),
880               (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
881    }
882
883    check_media(dev);
884
885    ep->timer.expires = jiffies + next_tick;
886    add_timer(&ep->timer);
887}
888
889static void epic_tx_timeout(struct net_device *dev)
890{
891    struct epic_private *ep = netdev_priv(dev);
892    long ioaddr = dev->base_addr;
893
894    if (debug > 0) {
895        printk(KERN_WARNING "%s: Transmit timeout using MII device, "
896               "Tx status %4.4x.\n",
897               dev->name, (int)inw(ioaddr + TxSTAT));
898        if (debug > 1) {
899            printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
900                   dev->name, ep->dirty_tx, ep->cur_tx);
901        }
902    }
903    if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
904        ep->stats.tx_fifo_errors++;
905        outl(RestartTx, ioaddr + COMMAND);
906    } else {
907        epic_restart(dev);
908        outl(TxQueued, dev->base_addr + COMMAND);
909    }
910
911    dev->trans_start = jiffies;
912    ep->stats.tx_errors++;
913    if (!ep->tx_full)
914        netif_wake_queue(dev);
915}
916
917/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
918static void epic_init_ring(struct net_device *dev)
919{
920    struct epic_private *ep = netdev_priv(dev);
921    int i;
922
923    ep->tx_full = 0;
924    ep->dirty_tx = ep->cur_tx = 0;
925    ep->cur_rx = ep->dirty_rx = 0;
926    ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
927
928    /* Initialize all Rx descriptors. */
929    for (i = 0; i < RX_RING_SIZE; i++) {
930        ep->rx_ring[i].rxstatus = 0;
931        ep->rx_ring[i].buflength = ep->rx_buf_sz;
932        ep->rx_ring[i].next = ep->rx_ring_dma +
933                      (i+1)*sizeof(struct epic_rx_desc);
934        ep->rx_skbuff[i] = NULL;
935    }
936    /* Mark the last entry as wrapping the ring. */
937    ep->rx_ring[i-1].next = ep->rx_ring_dma;
938
939    /* Fill in the Rx buffers. Handle allocation failure gracefully. */
940    for (i = 0; i < RX_RING_SIZE; i++) {
941        struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
942        ep->rx_skbuff[i] = skb;
943        if (skb == NULL)
944            break;
945        skb_reserve(skb, 2); /* 16 byte align the IP header. */
946        ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
947            skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
948        ep->rx_ring[i].rxstatus = DescOwn;
949    }
950    ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
951
952    /* The Tx buffer descriptor is filled in as needed, but we
953       do need to clear the ownership bit. */
954    for (i = 0; i < TX_RING_SIZE; i++) {
955        ep->tx_skbuff[i] = NULL;
956        ep->tx_ring[i].txstatus = 0x0000;
957        ep->tx_ring[i].next = ep->tx_ring_dma +
958            (i+1)*sizeof(struct epic_tx_desc);
959    }
960    ep->tx_ring[i-1].next = ep->tx_ring_dma;
961    return;
962}
963
964static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
965{
966    struct epic_private *ep = netdev_priv(dev);
967    int entry, free_count;
968    u32 ctrl_word;
969    unsigned long flags;
970
971    if (skb_padto(skb, ETH_ZLEN))
972        return 0;
973
974    /* Caution: the write order is important here, set the field with the
975       "ownership" bit last. */
976
977    /* Calculate the next Tx descriptor entry. */
978    spin_lock_irqsave(&ep->lock, flags);
979    free_count = ep->cur_tx - ep->dirty_tx;
980    entry = ep->cur_tx % TX_RING_SIZE;
981
982    ep->tx_skbuff[entry] = skb;
983    ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
984                                 skb->len, PCI_DMA_TODEVICE);
985    if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
986        ctrl_word = 0x100000; /* No interrupt */
987    } else if (free_count == TX_QUEUE_LEN/2) {
988        ctrl_word = 0x140000; /* Tx-done intr. */
989    } else if (free_count < TX_QUEUE_LEN - 1) {
990        ctrl_word = 0x100000; /* No Tx-done intr. */
991    } else {
992        /* Leave room for an additional entry. */
993        ctrl_word = 0x140000; /* Tx-done intr. */
994        ep->tx_full = 1;
995    }
996    ep->tx_ring[entry].buflength = ctrl_word | skb->len;
997    ep->tx_ring[entry].txstatus =
998        ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
999                | DescOwn;
1000
1001    ep->cur_tx++;
1002    if (ep->tx_full)
1003        netif_stop_queue(dev);
1004
1005    spin_unlock_irqrestore(&ep->lock, flags);
1006    /* Trigger an immediate transmit demand. */
1007    outl(TxQueued, dev->base_addr + COMMAND);
1008
1009    dev->trans_start = jiffies;
1010    if (debug > 4)
1011        printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1012               "flag %2.2x Tx status %8.8x.\n",
1013               dev->name, (int)skb->len, entry, ctrl_word,
1014               (int)inl(dev->base_addr + TxSTAT));
1015
1016    return 0;
1017}
1018
1019static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1020              int status)
1021{
1022    struct net_device_stats *stats = &ep->stats;
1023
1024#ifndef final_version
1025    /* There was an major error, log it. */
1026    if (debug > 1)
1027        printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1028               dev->name, status);
1029#endif
1030    stats->tx_errors++;
1031    if (status & 0x1050)
1032        stats->tx_aborted_errors++;
1033    if (status & 0x0008)
1034        stats->tx_carrier_errors++;
1035    if (status & 0x0040)
1036        stats->tx_window_errors++;
1037    if (status & 0x0010)
1038        stats->tx_fifo_errors++;
1039}
1040
1041static void epic_tx(struct net_device *dev, struct epic_private *ep)
1042{
1043    unsigned int dirty_tx, cur_tx;
1044
1045    /*
1046     * Note: if this lock becomes a problem we can narrow the locked
1047     * region at the cost of occasionally grabbing the lock more times.
1048     */
1049    cur_tx = ep->cur_tx;
1050    for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1051        struct sk_buff *skb;
1052        int entry = dirty_tx % TX_RING_SIZE;
1053        int txstatus = ep->tx_ring[entry].txstatus;
1054
1055        if (txstatus & DescOwn)
1056            break; /* It still hasn't been Txed */
1057
1058        if (likely(txstatus & 0x0001)) {
1059            ep->stats.collisions += (txstatus >> 8) & 15;
1060            ep->stats.tx_packets++;
1061            ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1062        } else
1063            epic_tx_error(dev, ep, txstatus);
1064
1065        /* Free the original skb. */
1066        skb = ep->tx_skbuff[entry];
1067        pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1068                 skb->len, PCI_DMA_TODEVICE);
1069        dev_kfree_skb_irq(skb);
1070        ep->tx_skbuff[entry] = NULL;
1071    }
1072
1073#ifndef final_version
1074    if (cur_tx - dirty_tx > TX_RING_SIZE) {
1075        printk(KERN_WARNING
1076               "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1077               dev->name, dirty_tx, cur_tx, ep->tx_full);
1078        dirty_tx += TX_RING_SIZE;
1079    }
1080#endif
1081    ep->dirty_tx = dirty_tx;
1082    if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1083        /* The ring is no longer full, allow new TX entries. */
1084        ep->tx_full = 0;
1085        netif_wake_queue(dev);
1086    }
1087}
1088
1089/* The interrupt handler does all of the Rx thread work and cleans up
1090   after the Tx thread. */
1091static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1092{
1093    struct net_device *dev = dev_instance;
1094    struct epic_private *ep = netdev_priv(dev);
1095    long ioaddr = dev->base_addr;
1096    unsigned int handled = 0;
1097    int status;
1098
1099    status = inl(ioaddr + INTSTAT);
1100    /* Acknowledge all of the current interrupt sources ASAP. */
1101    outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1102
1103    if (debug > 4) {
1104        printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1105                   "intstat=%#8.8x.\n", dev->name, status,
1106                   (int)inl(ioaddr + INTSTAT));
1107    }
1108
1109    if ((status & IntrSummary) == 0)
1110        goto out;
1111
1112    handled = 1;
1113
1114    if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1115        spin_lock(&ep->napi_lock);
1116        if (napi_schedule_prep(&ep->napi)) {
1117            epic_napi_irq_off(dev, ep);
1118            __napi_schedule(&ep->napi);
1119        } else
1120            ep->reschedule_in_poll++;
1121        spin_unlock(&ep->napi_lock);
1122    }
1123    status &= ~EpicNapiEvent;
1124
1125    /* Check uncommon events all at once. */
1126    if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1127        if (status == EpicRemoved)
1128            goto out;
1129
1130        /* Always update the error counts to avoid overhead later. */
1131        ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1132        ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1133        ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1134
1135        if (status & TxUnderrun) { /* Tx FIFO underflow. */
1136            ep->stats.tx_fifo_errors++;
1137            outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1138            /* Restart the transmit process. */
1139            outl(RestartTx, ioaddr + COMMAND);
1140        }
1141        if (status & PCIBusErr170) {
1142            printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1143                     dev->name, status);
1144            epic_pause(dev);
1145            epic_restart(dev);
1146        }
1147        /* Clear all error sources. */
1148        outl(status & 0x7f18, ioaddr + INTSTAT);
1149    }
1150
1151out:
1152    if (debug > 3) {
1153        printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1154                   dev->name, status);
1155    }
1156
1157    return IRQ_RETVAL(handled);
1158}
1159
1160static int epic_rx(struct net_device *dev, int budget)
1161{
1162    struct epic_private *ep = netdev_priv(dev);
1163    int entry = ep->cur_rx % RX_RING_SIZE;
1164    int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1165    int work_done = 0;
1166
1167    if (debug > 4)
1168        printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1169               ep->rx_ring[entry].rxstatus);
1170
1171    if (rx_work_limit > budget)
1172        rx_work_limit = budget;
1173
1174    /* If we own the next entry, it's a new packet. Send it up. */
1175    while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) {
1176        int status = ep->rx_ring[entry].rxstatus;
1177
1178        if (debug > 4)
1179            printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1180        if (--rx_work_limit < 0)
1181            break;
1182        if (status & 0x2006) {
1183            if (debug > 2)
1184                printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1185                       dev->name, status);
1186            if (status & 0x2000) {
1187                printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1188                       "multiple buffers, status %4.4x!\n", dev->name, status);
1189                ep->stats.rx_length_errors++;
1190            } else if (status & 0x0006)
1191                /* Rx Frame errors are counted in hardware. */
1192                ep->stats.rx_errors++;
1193        } else {
1194            /* Malloc up new buffer, compatible with net-2e. */
1195            /* Omit the four octet CRC from the length. */
1196            short pkt_len = (status >> 16) - 4;
1197            struct sk_buff *skb;
1198
1199            if (pkt_len > PKT_BUF_SZ - 4) {
1200                printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1201                       "%d bytes.\n",
1202                       dev->name, status, pkt_len);
1203                pkt_len = 1514;
1204            }
1205            /* Check if the packet is long enough to accept without copying
1206               to a minimally-sized skbuff. */
1207            if (pkt_len < rx_copybreak
1208                && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1209                skb_reserve(skb, 2); /* 16 byte align the IP header */
1210                pci_dma_sync_single_for_cpu(ep->pci_dev,
1211                                ep->rx_ring[entry].bufaddr,
1212                                ep->rx_buf_sz,
1213                                PCI_DMA_FROMDEVICE);
1214                skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len);
1215                skb_put(skb, pkt_len);
1216                pci_dma_sync_single_for_device(ep->pci_dev,
1217                                   ep->rx_ring[entry].bufaddr,
1218                                   ep->rx_buf_sz,
1219                                   PCI_DMA_FROMDEVICE);
1220            } else {
1221                pci_unmap_single(ep->pci_dev,
1222                    ep->rx_ring[entry].bufaddr,
1223                    ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1224                skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1225                ep->rx_skbuff[entry] = NULL;
1226            }
1227            skb->protocol = eth_type_trans(skb, dev);
1228            netif_receive_skb(skb);
1229            ep->stats.rx_packets++;
1230            ep->stats.rx_bytes += pkt_len;
1231        }
1232        work_done++;
1233        entry = (++ep->cur_rx) % RX_RING_SIZE;
1234    }
1235
1236    /* Refill the Rx ring buffers. */
1237    for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1238        entry = ep->dirty_rx % RX_RING_SIZE;
1239        if (ep->rx_skbuff[entry] == NULL) {
1240            struct sk_buff *skb;
1241            skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1242            if (skb == NULL)
1243                break;
1244            skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1245            ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1246                skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1247            work_done++;
1248        }
1249        /* AV: shouldn't we add a barrier here? */
1250        ep->rx_ring[entry].rxstatus = DescOwn;
1251    }
1252    return work_done;
1253}
1254
1255static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1256{
1257    long ioaddr = dev->base_addr;
1258    int status;
1259
1260    status = inl(ioaddr + INTSTAT);
1261
1262    if (status == EpicRemoved)
1263        return;
1264    if (status & RxOverflow) /* Missed a Rx frame. */
1265        ep->stats.rx_errors++;
1266    if (status & (RxOverflow | RxFull))
1267        outw(RxQueued, ioaddr + COMMAND);
1268}
1269
1270static int epic_poll(struct napi_struct *napi, int budget)
1271{
1272    struct epic_private *ep = container_of(napi, struct epic_private, napi);
1273    struct net_device *dev = ep->mii.dev;
1274    int work_done = 0;
1275    long ioaddr = dev->base_addr;
1276
1277rx_action:
1278
1279    epic_tx(dev, ep);
1280
1281    work_done += epic_rx(dev, budget);
1282
1283    epic_rx_err(dev, ep);
1284
1285    if (work_done < budget) {
1286        unsigned long flags;
1287        int more;
1288
1289        /* A bit baroque but it avoids a (space hungry) spin_unlock */
1290
1291        spin_lock_irqsave(&ep->napi_lock, flags);
1292
1293        more = ep->reschedule_in_poll;
1294        if (!more) {
1295            __napi_complete(napi);
1296            outl(EpicNapiEvent, ioaddr + INTSTAT);
1297            epic_napi_irq_on(dev, ep);
1298        } else
1299            ep->reschedule_in_poll--;
1300
1301        spin_unlock_irqrestore(&ep->napi_lock, flags);
1302
1303        if (more)
1304            goto rx_action;
1305    }
1306
1307    return work_done;
1308}
1309
1310static int epic_close(struct net_device *dev)
1311{
1312    long ioaddr = dev->base_addr;
1313    struct epic_private *ep = netdev_priv(dev);
1314    struct sk_buff *skb;
1315    int i;
1316
1317    netif_stop_queue(dev);
1318    napi_disable(&ep->napi);
1319
1320    if (debug > 1)
1321        printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1322               dev->name, (int)inl(ioaddr + INTSTAT));
1323
1324    del_timer_sync(&ep->timer);
1325
1326    epic_disable_int(dev, ep);
1327
1328    free_irq(dev->irq, dev);
1329
1330    epic_pause(dev);
1331
1332    /* Free all the skbuffs in the Rx queue. */
1333    for (i = 0; i < RX_RING_SIZE; i++) {
1334        skb = ep->rx_skbuff[i];
1335        ep->rx_skbuff[i] = NULL;
1336        ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1337        ep->rx_ring[i].buflength = 0;
1338        if (skb) {
1339            pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1340                      ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1341            dev_kfree_skb(skb);
1342        }
1343        ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1344    }
1345    for (i = 0; i < TX_RING_SIZE; i++) {
1346        skb = ep->tx_skbuff[i];
1347        ep->tx_skbuff[i] = NULL;
1348        if (!skb)
1349            continue;
1350        pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1351                 skb->len, PCI_DMA_TODEVICE);
1352        dev_kfree_skb(skb);
1353    }
1354
1355    /* Green! Leave the chip in low-power mode. */
1356    outl(0x0008, ioaddr + GENCTL);
1357
1358    return 0;
1359}
1360
1361static struct net_device_stats *epic_get_stats(struct net_device *dev)
1362{
1363    struct epic_private *ep = netdev_priv(dev);
1364    long ioaddr = dev->base_addr;
1365
1366    if (netif_running(dev)) {
1367        /* Update the error counts. */
1368        ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1369        ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1370        ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1371    }
1372
1373    return &ep->stats;
1374}
1375
1376/* Set or clear the multicast filter for this adaptor.
1377   Note that we only use exclusion around actually queueing the
1378   new frame, not around filling ep->setup_frame. This is non-deterministic
1379   when re-entered but still correct. */
1380
1381static void set_rx_mode(struct net_device *dev)
1382{
1383    long ioaddr = dev->base_addr;
1384    struct epic_private *ep = netdev_priv(dev);
1385    unsigned char mc_filter[8]; /* Multicast hash filter */
1386    int i;
1387
1388    if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1389        outl(0x002C, ioaddr + RxCtrl);
1390        /* Unconditionally log net taps. */
1391        memset(mc_filter, 0xff, sizeof(mc_filter));
1392    } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1393        /* There is apparently a chip bug, so the multicast filter
1394           is never enabled. */
1395        /* Too many to filter perfectly -- accept all multicasts. */
1396        memset(mc_filter, 0xff, sizeof(mc_filter));
1397        outl(0x000C, ioaddr + RxCtrl);
1398    } else if (dev->mc_count == 0) {
1399        outl(0x0004, ioaddr + RxCtrl);
1400        return;
1401    } else { /* Never executed, for now. */
1402        struct dev_mc_list *mclist;
1403
1404        memset(mc_filter, 0, sizeof(mc_filter));
1405        for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1406             i++, mclist = mclist->next) {
1407            unsigned int bit_nr =
1408                ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f;
1409            mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1410        }
1411    }
1412    /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1413    if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1414        for (i = 0; i < 4; i++)
1415            outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1416        memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1417    }
1418    return;
1419}
1420
1421static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1422{
1423    struct epic_private *np = netdev_priv(dev);
1424
1425    strcpy (info->driver, DRV_NAME);
1426    strcpy (info->version, DRV_VERSION);
1427    strcpy (info->bus_info, pci_name(np->pci_dev));
1428}
1429
1430static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1431{
1432    struct epic_private *np = netdev_priv(dev);
1433    int rc;
1434
1435    spin_lock_irq(&np->lock);
1436    rc = mii_ethtool_gset(&np->mii, cmd);
1437    spin_unlock_irq(&np->lock);
1438
1439    return rc;
1440}
1441
1442static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1443{
1444    struct epic_private *np = netdev_priv(dev);
1445    int rc;
1446
1447    spin_lock_irq(&np->lock);
1448    rc = mii_ethtool_sset(&np->mii, cmd);
1449    spin_unlock_irq(&np->lock);
1450
1451    return rc;
1452}
1453
1454static int netdev_nway_reset(struct net_device *dev)
1455{
1456    struct epic_private *np = netdev_priv(dev);
1457    return mii_nway_restart(&np->mii);
1458}
1459
1460static u32 netdev_get_link(struct net_device *dev)
1461{
1462    struct epic_private *np = netdev_priv(dev);
1463    return mii_link_ok(&np->mii);
1464}
1465
1466static u32 netdev_get_msglevel(struct net_device *dev)
1467{
1468    return debug;
1469}
1470
1471static void netdev_set_msglevel(struct net_device *dev, u32 value)
1472{
1473    debug = value;
1474}
1475
1476static int ethtool_begin(struct net_device *dev)
1477{
1478    unsigned long ioaddr = dev->base_addr;
1479    /* power-up, if interface is down */
1480    if (! netif_running(dev)) {
1481        outl(0x0200, ioaddr + GENCTL);
1482        outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1483    }
1484    return 0;
1485}
1486
1487static void ethtool_complete(struct net_device *dev)
1488{
1489    unsigned long ioaddr = dev->base_addr;
1490    /* power-down, if interface is down */
1491    if (! netif_running(dev)) {
1492        outl(0x0008, ioaddr + GENCTL);
1493        outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1494    }
1495}
1496
1497static const struct ethtool_ops netdev_ethtool_ops = {
1498    .get_drvinfo = netdev_get_drvinfo,
1499    .get_settings = netdev_get_settings,
1500    .set_settings = netdev_set_settings,
1501    .nway_reset = netdev_nway_reset,
1502    .get_link = netdev_get_link,
1503    .get_msglevel = netdev_get_msglevel,
1504    .set_msglevel = netdev_set_msglevel,
1505    .begin = ethtool_begin,
1506    .complete = ethtool_complete
1507};
1508
1509static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1510{
1511    struct epic_private *np = netdev_priv(dev);
1512    long ioaddr = dev->base_addr;
1513    struct mii_ioctl_data *data = if_mii(rq);
1514    int rc;
1515
1516    /* power-up, if interface is down */
1517    if (! netif_running(dev)) {
1518        outl(0x0200, ioaddr + GENCTL);
1519        outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1520    }
1521
1522    /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1523    spin_lock_irq(&np->lock);
1524    rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1525    spin_unlock_irq(&np->lock);
1526
1527    /* power-down, if interface is down */
1528    if (! netif_running(dev)) {
1529        outl(0x0008, ioaddr + GENCTL);
1530        outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1531    }
1532    return rc;
1533}
1534
1535
1536static void __devexit epic_remove_one (struct pci_dev *pdev)
1537{
1538    struct net_device *dev = pci_get_drvdata(pdev);
1539    struct epic_private *ep = netdev_priv(dev);
1540
1541    pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1542    pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1543    unregister_netdev(dev);
1544#ifndef USE_IO_OPS
1545    iounmap((void*) dev->base_addr);
1546#endif
1547    pci_release_regions(pdev);
1548    free_netdev(dev);
1549    pci_disable_device(pdev);
1550    pci_set_drvdata(pdev, NULL);
1551    /* pci_power_off(pdev, -1); */
1552}
1553
1554
1555#ifdef CONFIG_PM
1556
1557static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1558{
1559    struct net_device *dev = pci_get_drvdata(pdev);
1560    long ioaddr = dev->base_addr;
1561
1562    if (!netif_running(dev))
1563        return 0;
1564    epic_pause(dev);
1565    /* Put the chip into low-power mode. */
1566    outl(0x0008, ioaddr + GENCTL);
1567    /* pci_power_off(pdev, -1); */
1568    return 0;
1569}
1570
1571
1572static int epic_resume (struct pci_dev *pdev)
1573{
1574    struct net_device *dev = pci_get_drvdata(pdev);
1575
1576    if (!netif_running(dev))
1577        return 0;
1578    epic_restart(dev);
1579    /* pci_power_on(pdev); */
1580    return 0;
1581}
1582
1583#endif /* CONFIG_PM */
1584
1585
1586static struct pci_driver epic_driver = {
1587    .name = DRV_NAME,
1588    .id_table = epic_pci_tbl,
1589    .probe = epic_init_one,
1590    .remove = __devexit_p(epic_remove_one),
1591#ifdef CONFIG_PM
1592    .suspend = epic_suspend,
1593    .resume = epic_resume,
1594#endif /* CONFIG_PM */
1595};
1596
1597
1598static int __init epic_init (void)
1599{
1600/* when a module, this is printed whether or not devices are found in probe */
1601#ifdef MODULE
1602    printk (KERN_INFO "%s%s",
1603        version, version2);
1604#endif
1605
1606    return pci_register_driver(&epic_driver);
1607}
1608
1609
1610static void __exit epic_cleanup (void)
1611{
1612    pci_unregister_driver (&epic_driver);
1613}
1614
1615
1616module_init(epic_init);
1617module_exit(epic_cleanup);
1618

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