Root/drivers/net/ns83820.c

1#define VERSION "0.23"
2/* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96//#define dprintk printk
97#define dprintk(x...) do { } while (0)
98
99#include <linux/module.h>
100#include <linux/moduleparam.h>
101#include <linux/types.h>
102#include <linux/pci.h>
103#include <linux/dma-mapping.h>
104#include <linux/netdevice.h>
105#include <linux/etherdevice.h>
106#include <linux/delay.h>
107#include <linux/workqueue.h>
108#include <linux/init.h>
109#include <linux/ip.h> /* for iph */
110#include <linux/in.h> /* for IPPROTO_... */
111#include <linux/compiler.h>
112#include <linux/prefetch.h>
113#include <linux/ethtool.h>
114#include <linux/timer.h>
115#include <linux/if_vlan.h>
116#include <linux/rtnetlink.h>
117#include <linux/jiffies.h>
118
119#include <asm/io.h>
120#include <asm/uaccess.h>
121#include <asm/system.h>
122
123#define DRV_NAME "ns83820"
124
125/* Global parameters. See module_param near the bottom. */
126static int ihr = 2;
127static int reset_phy = 0;
128static int lnksts = 0; /* CFG_LNKSTS bit polarity */
129
130/* Dprintk is used for more interesting debug events */
131#undef Dprintk
132#define Dprintk dprintk
133
134/* tunables */
135#define RX_BUF_SIZE 1500 /* 8192 */
136#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
137#define NS83820_VLAN_ACCEL_SUPPORT
138#endif
139
140/* Must not exceed ~65000. */
141#define NR_RX_DESC 64
142#define NR_TX_DESC 128
143
144/* not tunable */
145#define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
146
147#define MIN_TX_DESC_FREE 8
148
149/* register defines */
150#define CFGCS 0x04
151
152#define CR_TXE 0x00000001
153#define CR_TXD 0x00000002
154/* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
155 * The Receive engine skips one descriptor and moves
156 * onto the next one!! */
157#define CR_RXE 0x00000004
158#define CR_RXD 0x00000008
159#define CR_TXR 0x00000010
160#define CR_RXR 0x00000020
161#define CR_SWI 0x00000080
162#define CR_RST 0x00000100
163
164#define PTSCR_EEBIST_FAIL 0x00000001
165#define PTSCR_EEBIST_EN 0x00000002
166#define PTSCR_EELOAD_EN 0x00000004
167#define PTSCR_RBIST_FAIL 0x000001b8
168#define PTSCR_RBIST_DONE 0x00000200
169#define PTSCR_RBIST_EN 0x00000400
170#define PTSCR_RBIST_RST 0x00002000
171
172#define MEAR_EEDI 0x00000001
173#define MEAR_EEDO 0x00000002
174#define MEAR_EECLK 0x00000004
175#define MEAR_EESEL 0x00000008
176#define MEAR_MDIO 0x00000010
177#define MEAR_MDDIR 0x00000020
178#define MEAR_MDC 0x00000040
179
180#define ISR_TXDESC3 0x40000000
181#define ISR_TXDESC2 0x20000000
182#define ISR_TXDESC1 0x10000000
183#define ISR_TXDESC0 0x08000000
184#define ISR_RXDESC3 0x04000000
185#define ISR_RXDESC2 0x02000000
186#define ISR_RXDESC1 0x01000000
187#define ISR_RXDESC0 0x00800000
188#define ISR_TXRCMP 0x00400000
189#define ISR_RXRCMP 0x00200000
190#define ISR_DPERR 0x00100000
191#define ISR_SSERR 0x00080000
192#define ISR_RMABT 0x00040000
193#define ISR_RTABT 0x00020000
194#define ISR_RXSOVR 0x00010000
195#define ISR_HIBINT 0x00008000
196#define ISR_PHY 0x00004000
197#define ISR_PME 0x00002000
198#define ISR_SWI 0x00001000
199#define ISR_MIB 0x00000800
200#define ISR_TXURN 0x00000400
201#define ISR_TXIDLE 0x00000200
202#define ISR_TXERR 0x00000100
203#define ISR_TXDESC 0x00000080
204#define ISR_TXOK 0x00000040
205#define ISR_RXORN 0x00000020
206#define ISR_RXIDLE 0x00000010
207#define ISR_RXEARLY 0x00000008
208#define ISR_RXERR 0x00000004
209#define ISR_RXDESC 0x00000002
210#define ISR_RXOK 0x00000001
211
212#define TXCFG_CSI 0x80000000
213#define TXCFG_HBI 0x40000000
214#define TXCFG_MLB 0x20000000
215#define TXCFG_ATP 0x10000000
216#define TXCFG_ECRETRY 0x00800000
217#define TXCFG_BRST_DIS 0x00080000
218#define TXCFG_MXDMA1024 0x00000000
219#define TXCFG_MXDMA512 0x00700000
220#define TXCFG_MXDMA256 0x00600000
221#define TXCFG_MXDMA128 0x00500000
222#define TXCFG_MXDMA64 0x00400000
223#define TXCFG_MXDMA32 0x00300000
224#define TXCFG_MXDMA16 0x00200000
225#define TXCFG_MXDMA8 0x00100000
226
227#define CFG_LNKSTS 0x80000000
228#define CFG_SPDSTS 0x60000000
229#define CFG_SPDSTS1 0x40000000
230#define CFG_SPDSTS0 0x20000000
231#define CFG_DUPSTS 0x10000000
232#define CFG_TBI_EN 0x01000000
233#define CFG_MODE_1000 0x00400000
234/* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
235 * Read the Phy response and then configure the MAC accordingly */
236#define CFG_AUTO_1000 0x00200000
237#define CFG_PINT_CTL 0x001c0000
238#define CFG_PINT_DUPSTS 0x00100000
239#define CFG_PINT_LNKSTS 0x00080000
240#define CFG_PINT_SPDSTS 0x00040000
241#define CFG_TMRTEST 0x00020000
242#define CFG_MRM_DIS 0x00010000
243#define CFG_MWI_DIS 0x00008000
244#define CFG_T64ADDR 0x00004000
245#define CFG_PCI64_DET 0x00002000
246#define CFG_DATA64_EN 0x00001000
247#define CFG_M64ADDR 0x00000800
248#define CFG_PHY_RST 0x00000400
249#define CFG_PHY_DIS 0x00000200
250#define CFG_EXTSTS_EN 0x00000100
251#define CFG_REQALG 0x00000080
252#define CFG_SB 0x00000040
253#define CFG_POW 0x00000020
254#define CFG_EXD 0x00000010
255#define CFG_PESEL 0x00000008
256#define CFG_BROM_DIS 0x00000004
257#define CFG_EXT_125 0x00000002
258#define CFG_BEM 0x00000001
259
260#define EXTSTS_UDPPKT 0x00200000
261#define EXTSTS_TCPPKT 0x00080000
262#define EXTSTS_IPPKT 0x00020000
263#define EXTSTS_VPKT 0x00010000
264#define EXTSTS_VTG_MASK 0x0000ffff
265
266#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
267
268#define MIBC_MIBS 0x00000008
269#define MIBC_ACLR 0x00000004
270#define MIBC_FRZ 0x00000002
271#define MIBC_WRN 0x00000001
272
273#define PCR_PSEN (1 << 31)
274#define PCR_PS_MCAST (1 << 30)
275#define PCR_PS_DA (1 << 29)
276#define PCR_STHI_8 (3 << 23)
277#define PCR_STLO_4 (1 << 23)
278#define PCR_FFHI_8K (3 << 21)
279#define PCR_FFLO_4K (1 << 21)
280#define PCR_PAUSE_CNT 0xFFFE
281
282#define RXCFG_AEP 0x80000000
283#define RXCFG_ARP 0x40000000
284#define RXCFG_STRIPCRC 0x20000000
285#define RXCFG_RX_FD 0x10000000
286#define RXCFG_ALP 0x08000000
287#define RXCFG_AIRL 0x04000000
288#define RXCFG_MXDMA512 0x00700000
289#define RXCFG_DRTH 0x0000003e
290#define RXCFG_DRTH0 0x00000002
291
292#define RFCR_RFEN 0x80000000
293#define RFCR_AAB 0x40000000
294#define RFCR_AAM 0x20000000
295#define RFCR_AAU 0x10000000
296#define RFCR_APM 0x08000000
297#define RFCR_APAT 0x07800000
298#define RFCR_APAT3 0x04000000
299#define RFCR_APAT2 0x02000000
300#define RFCR_APAT1 0x01000000
301#define RFCR_APAT0 0x00800000
302#define RFCR_AARP 0x00400000
303#define RFCR_MHEN 0x00200000
304#define RFCR_UHEN 0x00100000
305#define RFCR_ULM 0x00080000
306
307#define VRCR_RUDPE 0x00000080
308#define VRCR_RTCPE 0x00000040
309#define VRCR_RIPE 0x00000020
310#define VRCR_IPEN 0x00000010
311#define VRCR_DUTF 0x00000008
312#define VRCR_DVTF 0x00000004
313#define VRCR_VTREN 0x00000002
314#define VRCR_VTDEN 0x00000001
315
316#define VTCR_PPCHK 0x00000008
317#define VTCR_GCHK 0x00000004
318#define VTCR_VPPTI 0x00000002
319#define VTCR_VGTI 0x00000001
320
321#define CR 0x00
322#define CFG 0x04
323#define MEAR 0x08
324#define PTSCR 0x0c
325#define ISR 0x10
326#define IMR 0x14
327#define IER 0x18
328#define IHR 0x1c
329#define TXDP 0x20
330#define TXDP_HI 0x24
331#define TXCFG 0x28
332#define GPIOR 0x2c
333#define RXDP 0x30
334#define RXDP_HI 0x34
335#define RXCFG 0x38
336#define PQCR 0x3c
337#define WCSR 0x40
338#define PCR 0x44
339#define RFCR 0x48
340#define RFDR 0x4c
341
342#define SRR 0x58
343
344#define VRCR 0xbc
345#define VTCR 0xc0
346#define VDR 0xc4
347#define CCSR 0xcc
348
349#define TBICR 0xe0
350#define TBISR 0xe4
351#define TANAR 0xe8
352#define TANLPAR 0xec
353#define TANER 0xf0
354#define TESR 0xf4
355
356#define TBICR_MR_AN_ENABLE 0x00001000
357#define TBICR_MR_RESTART_AN 0x00000200
358
359#define TBISR_MR_LINK_STATUS 0x00000020
360#define TBISR_MR_AN_COMPLETE 0x00000004
361
362#define TANAR_PS2 0x00000100
363#define TANAR_PS1 0x00000080
364#define TANAR_HALF_DUP 0x00000040
365#define TANAR_FULL_DUP 0x00000020
366
367#define GPIOR_GP5_OE 0x00000200
368#define GPIOR_GP4_OE 0x00000100
369#define GPIOR_GP3_OE 0x00000080
370#define GPIOR_GP2_OE 0x00000040
371#define GPIOR_GP1_OE 0x00000020
372#define GPIOR_GP3_OUT 0x00000004
373#define GPIOR_GP1_OUT 0x00000001
374
375#define LINK_AUTONEGOTIATE 0x01
376#define LINK_DOWN 0x02
377#define LINK_UP 0x04
378
379#define HW_ADDR_LEN sizeof(dma_addr_t)
380#define desc_addr_set(desc, addr) \
381    do { \
382        ((desc)[0] = cpu_to_le32(addr)); \
383        if (HW_ADDR_LEN == 8) \
384            (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
385    } while(0)
386#define desc_addr_get(desc) \
387    (le32_to_cpu((desc)[0]) | \
388    (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
389
390#define DESC_LINK 0
391#define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
392#define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
393#define DESC_EXTSTS (DESC_CMDSTS + 4/4)
394
395#define CMDSTS_OWN 0x80000000
396#define CMDSTS_MORE 0x40000000
397#define CMDSTS_INTR 0x20000000
398#define CMDSTS_ERR 0x10000000
399#define CMDSTS_OK 0x08000000
400#define CMDSTS_RUNT 0x00200000
401#define CMDSTS_LEN_MASK 0x0000ffff
402
403#define CMDSTS_DEST_MASK 0x01800000
404#define CMDSTS_DEST_SELF 0x00800000
405#define CMDSTS_DEST_MULTI 0x01000000
406
407#define DESC_SIZE 8 /* Should be cache line sized */
408
409struct rx_info {
410    spinlock_t lock;
411    int up;
412    unsigned long idle;
413
414    struct sk_buff *skbs[NR_RX_DESC];
415
416    __le32 *next_rx_desc;
417    u16 next_rx, next_empty;
418
419    __le32 *descs;
420    dma_addr_t phy_descs;
421};
422
423
424struct ns83820 {
425    struct net_device_stats stats;
426    u8 __iomem *base;
427
428    struct pci_dev *pci_dev;
429    struct net_device *ndev;
430
431#ifdef NS83820_VLAN_ACCEL_SUPPORT
432    struct vlan_group *vlgrp;
433#endif
434
435    struct rx_info rx_info;
436    struct tasklet_struct rx_tasklet;
437
438    unsigned ihr;
439    struct work_struct tq_refill;
440
441    /* protects everything below. irqsave when using. */
442    spinlock_t misc_lock;
443
444    u32 CFG_cache;
445
446    u32 MEAR_cache;
447    u32 IMR_cache;
448
449    unsigned linkstate;
450
451    spinlock_t tx_lock;
452
453    u16 tx_done_idx;
454    u16 tx_idx;
455    volatile u16 tx_free_idx; /* idx of free desc chain */
456    u16 tx_intr_idx;
457
458    atomic_t nr_tx_skbs;
459    struct sk_buff *tx_skbs[NR_TX_DESC];
460
461    char pad[16] __attribute__((aligned(16)));
462    __le32 *tx_descs;
463    dma_addr_t tx_phy_descs;
464
465    struct timer_list tx_watchdog;
466};
467
468static inline struct ns83820 *PRIV(struct net_device *dev)
469{
470    return netdev_priv(dev);
471}
472
473#define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
474
475static inline void kick_rx(struct net_device *ndev)
476{
477    struct ns83820 *dev = PRIV(ndev);
478    dprintk("kick_rx: maybe kicking\n");
479    if (test_and_clear_bit(0, &dev->rx_info.idle)) {
480        dprintk("actually kicking\n");
481        writel(dev->rx_info.phy_descs +
482            (4 * DESC_SIZE * dev->rx_info.next_rx),
483               dev->base + RXDP);
484        if (dev->rx_info.next_rx == dev->rx_info.next_empty)
485            printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
486                ndev->name);
487        __kick_rx(dev);
488    }
489}
490
491//free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
492#define start_tx_okay(dev) \
493    (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
494
495
496#ifdef NS83820_VLAN_ACCEL_SUPPORT
497static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
498{
499    struct ns83820 *dev = PRIV(ndev);
500
501    spin_lock_irq(&dev->misc_lock);
502    spin_lock(&dev->tx_lock);
503
504    dev->vlgrp = grp;
505
506    spin_unlock(&dev->tx_lock);
507    spin_unlock_irq(&dev->misc_lock);
508}
509#endif
510
511/* Packet Receiver
512 *
513 * The hardware supports linked lists of receive descriptors for
514 * which ownership is transfered back and forth by means of an
515 * ownership bit. While the hardware does support the use of a
516 * ring for receive descriptors, we only make use of a chain in
517 * an attempt to reduce bus traffic under heavy load scenarios.
518 * This will also make bugs a bit more obvious. The current code
519 * only makes use of a single rx chain; I hope to implement
520 * priority based rx for version 1.0. Goal: even under overload
521 * conditions, still route realtime traffic with as low jitter as
522 * possible.
523 */
524static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
525{
526    desc_addr_set(desc + DESC_LINK, link);
527    desc_addr_set(desc + DESC_BUFPTR, buf);
528    desc[DESC_EXTSTS] = cpu_to_le32(extsts);
529    mb();
530    desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
531}
532
533#define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
534static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
535{
536    unsigned next_empty;
537    u32 cmdsts;
538    __le32 *sg;
539    dma_addr_t buf;
540
541    next_empty = dev->rx_info.next_empty;
542
543    /* don't overrun last rx marker */
544    if (unlikely(nr_rx_empty(dev) <= 2)) {
545        kfree_skb(skb);
546        return 1;
547    }
548
549#if 0
550    dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
551        dev->rx_info.next_empty,
552        dev->rx_info.nr_used,
553        dev->rx_info.next_rx
554        );
555#endif
556
557    sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
558    BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
559    dev->rx_info.skbs[next_empty] = skb;
560
561    dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
562    cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
563    buf = pci_map_single(dev->pci_dev, skb->data,
564                 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
565    build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
566    /* update link of previous rx */
567    if (likely(next_empty != dev->rx_info.next_rx))
568        dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
569
570    return 0;
571}
572
573static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
574{
575    struct ns83820 *dev = PRIV(ndev);
576    unsigned i;
577    unsigned long flags = 0;
578
579    if (unlikely(nr_rx_empty(dev) <= 2))
580        return 0;
581
582    dprintk("rx_refill(%p)\n", ndev);
583    if (gfp == GFP_ATOMIC)
584        spin_lock_irqsave(&dev->rx_info.lock, flags);
585    for (i=0; i<NR_RX_DESC; i++) {
586        struct sk_buff *skb;
587        long res;
588
589        /* extra 16 bytes for alignment */
590        skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
591        if (unlikely(!skb))
592            break;
593
594        skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
595        if (gfp != GFP_ATOMIC)
596            spin_lock_irqsave(&dev->rx_info.lock, flags);
597        res = ns83820_add_rx_skb(dev, skb);
598        if (gfp != GFP_ATOMIC)
599            spin_unlock_irqrestore(&dev->rx_info.lock, flags);
600        if (res) {
601            i = 1;
602            break;
603        }
604    }
605    if (gfp == GFP_ATOMIC)
606        spin_unlock_irqrestore(&dev->rx_info.lock, flags);
607
608    return i ? 0 : -ENOMEM;
609}
610
611static void rx_refill_atomic(struct net_device *ndev)
612{
613    rx_refill(ndev, GFP_ATOMIC);
614}
615
616/* REFILL */
617static inline void queue_refill(struct work_struct *work)
618{
619    struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
620    struct net_device *ndev = dev->ndev;
621
622    rx_refill(ndev, GFP_KERNEL);
623    if (dev->rx_info.up)
624        kick_rx(ndev);
625}
626
627static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
628{
629    build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
630}
631
632static void phy_intr(struct net_device *ndev)
633{
634    struct ns83820 *dev = PRIV(ndev);
635    static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
636    u32 cfg, new_cfg;
637    u32 tbisr, tanar, tanlpar;
638    int speed, fullduplex, newlinkstate;
639
640    cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
641
642    if (dev->CFG_cache & CFG_TBI_EN) {
643        /* we have an optical transceiver */
644        tbisr = readl(dev->base + TBISR);
645        tanar = readl(dev->base + TANAR);
646        tanlpar = readl(dev->base + TANLPAR);
647        dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
648            tbisr, tanar, tanlpar);
649
650        if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
651              && (tanar & TANAR_FULL_DUP)) ) {
652
653            /* both of us are full duplex */
654            writel(readl(dev->base + TXCFG)
655                   | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
656                   dev->base + TXCFG);
657            writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
658                   dev->base + RXCFG);
659            /* Light up full duplex LED */
660            writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
661                   dev->base + GPIOR);
662
663        } else if(((tanlpar & TANAR_HALF_DUP)
664               && (tanar & TANAR_HALF_DUP))
665            || ((tanlpar & TANAR_FULL_DUP)
666                && (tanar & TANAR_HALF_DUP))
667            || ((tanlpar & TANAR_HALF_DUP)
668                && (tanar & TANAR_FULL_DUP))) {
669
670            /* one or both of us are half duplex */
671            writel((readl(dev->base + TXCFG)
672                & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
673                   dev->base + TXCFG);
674            writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
675                   dev->base + RXCFG);
676            /* Turn off full duplex LED */
677            writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
678                   dev->base + GPIOR);
679        }
680
681        speed = 4; /* 1000F */
682
683    } else {
684        /* we have a copper transceiver */
685        new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
686
687        if (cfg & CFG_SPDSTS1)
688            new_cfg |= CFG_MODE_1000;
689        else
690            new_cfg &= ~CFG_MODE_1000;
691
692        speed = ((cfg / CFG_SPDSTS0) & 3);
693        fullduplex = (cfg & CFG_DUPSTS);
694
695        if (fullduplex) {
696            new_cfg |= CFG_SB;
697            writel(readl(dev->base + TXCFG)
698                    | TXCFG_CSI | TXCFG_HBI,
699                   dev->base + TXCFG);
700            writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
701                   dev->base + RXCFG);
702        } else {
703            writel(readl(dev->base + TXCFG)
704                    & ~(TXCFG_CSI | TXCFG_HBI),
705                   dev->base + TXCFG);
706            writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
707                   dev->base + RXCFG);
708        }
709
710        if ((cfg & CFG_LNKSTS) &&
711            ((new_cfg ^ dev->CFG_cache) != 0)) {
712            writel(new_cfg, dev->base + CFG);
713            dev->CFG_cache = new_cfg;
714        }
715
716        dev->CFG_cache &= ~CFG_SPDSTS;
717        dev->CFG_cache |= cfg & CFG_SPDSTS;
718    }
719
720    newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
721
722    if (newlinkstate & LINK_UP
723        && dev->linkstate != newlinkstate) {
724        netif_start_queue(ndev);
725        netif_wake_queue(ndev);
726        printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
727            ndev->name,
728            speeds[speed],
729            fullduplex ? "full" : "half");
730    } else if (newlinkstate & LINK_DOWN
731           && dev->linkstate != newlinkstate) {
732        netif_stop_queue(ndev);
733        printk(KERN_INFO "%s: link now down.\n", ndev->name);
734    }
735
736    dev->linkstate = newlinkstate;
737}
738
739static int ns83820_setup_rx(struct net_device *ndev)
740{
741    struct ns83820 *dev = PRIV(ndev);
742    unsigned i;
743    int ret;
744
745    dprintk("ns83820_setup_rx(%p)\n", ndev);
746
747    dev->rx_info.idle = 1;
748    dev->rx_info.next_rx = 0;
749    dev->rx_info.next_rx_desc = dev->rx_info.descs;
750    dev->rx_info.next_empty = 0;
751
752    for (i=0; i<NR_RX_DESC; i++)
753        clear_rx_desc(dev, i);
754
755    writel(0, dev->base + RXDP_HI);
756    writel(dev->rx_info.phy_descs, dev->base + RXDP);
757
758    ret = rx_refill(ndev, GFP_KERNEL);
759    if (!ret) {
760        dprintk("starting receiver\n");
761        /* prevent the interrupt handler from stomping on us */
762        spin_lock_irq(&dev->rx_info.lock);
763
764        writel(0x0001, dev->base + CCSR);
765        writel(0, dev->base + RFCR);
766        writel(0x7fc00000, dev->base + RFCR);
767        writel(0xffc00000, dev->base + RFCR);
768
769        dev->rx_info.up = 1;
770
771        phy_intr(ndev);
772
773        /* Okay, let it rip */
774        spin_lock_irq(&dev->misc_lock);
775        dev->IMR_cache |= ISR_PHY;
776        dev->IMR_cache |= ISR_RXRCMP;
777        //dev->IMR_cache |= ISR_RXERR;
778        //dev->IMR_cache |= ISR_RXOK;
779        dev->IMR_cache |= ISR_RXORN;
780        dev->IMR_cache |= ISR_RXSOVR;
781        dev->IMR_cache |= ISR_RXDESC;
782        dev->IMR_cache |= ISR_RXIDLE;
783        dev->IMR_cache |= ISR_TXDESC;
784        dev->IMR_cache |= ISR_TXIDLE;
785
786        writel(dev->IMR_cache, dev->base + IMR);
787        writel(1, dev->base + IER);
788        spin_unlock(&dev->misc_lock);
789
790        kick_rx(ndev);
791
792        spin_unlock_irq(&dev->rx_info.lock);
793    }
794    return ret;
795}
796
797static void ns83820_cleanup_rx(struct ns83820 *dev)
798{
799    unsigned i;
800    unsigned long flags;
801
802    dprintk("ns83820_cleanup_rx(%p)\n", dev);
803
804    /* disable receive interrupts */
805    spin_lock_irqsave(&dev->misc_lock, flags);
806    dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
807    writel(dev->IMR_cache, dev->base + IMR);
808    spin_unlock_irqrestore(&dev->misc_lock, flags);
809
810    /* synchronize with the interrupt handler and kill it */
811    dev->rx_info.up = 0;
812    synchronize_irq(dev->pci_dev->irq);
813
814    /* touch the pci bus... */
815    readl(dev->base + IMR);
816
817    /* assumes the transmitter is already disabled and reset */
818    writel(0, dev->base + RXDP_HI);
819    writel(0, dev->base + RXDP);
820
821    for (i=0; i<NR_RX_DESC; i++) {
822        struct sk_buff *skb = dev->rx_info.skbs[i];
823        dev->rx_info.skbs[i] = NULL;
824        clear_rx_desc(dev, i);
825        kfree_skb(skb);
826    }
827}
828
829static void ns83820_rx_kick(struct net_device *ndev)
830{
831    struct ns83820 *dev = PRIV(ndev);
832    /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
833        if (dev->rx_info.up) {
834            rx_refill_atomic(ndev);
835            kick_rx(ndev);
836        }
837    }
838
839    if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
840        schedule_work(&dev->tq_refill);
841    else
842        kick_rx(ndev);
843    if (dev->rx_info.idle)
844        printk(KERN_DEBUG "%s: BAD\n", ndev->name);
845}
846
847/* rx_irq
848 *
849 */
850static void rx_irq(struct net_device *ndev)
851{
852    struct ns83820 *dev = PRIV(ndev);
853    struct rx_info *info = &dev->rx_info;
854    unsigned next_rx;
855    int rx_rc, len;
856    u32 cmdsts;
857    __le32 *desc;
858    unsigned long flags;
859    int nr = 0;
860
861    dprintk("rx_irq(%p)\n", ndev);
862    dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
863        readl(dev->base + RXDP),
864        (long)(dev->rx_info.phy_descs),
865        (int)dev->rx_info.next_rx,
866        (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
867        (int)dev->rx_info.next_empty,
868        (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
869        );
870
871    spin_lock_irqsave(&info->lock, flags);
872    if (!info->up)
873        goto out;
874
875    dprintk("walking descs\n");
876    next_rx = info->next_rx;
877    desc = info->next_rx_desc;
878    while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
879           (cmdsts != CMDSTS_OWN)) {
880        struct sk_buff *skb;
881        u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
882        dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
883
884        dprintk("cmdsts: %08x\n", cmdsts);
885        dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
886        dprintk("extsts: %08x\n", extsts);
887
888        skb = info->skbs[next_rx];
889        info->skbs[next_rx] = NULL;
890        info->next_rx = (next_rx + 1) % NR_RX_DESC;
891
892        mb();
893        clear_rx_desc(dev, next_rx);
894
895        pci_unmap_single(dev->pci_dev, bufptr,
896                 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
897        len = cmdsts & CMDSTS_LEN_MASK;
898#ifdef NS83820_VLAN_ACCEL_SUPPORT
899        /* NH: As was mentioned below, this chip is kinda
900         * brain dead about vlan tag stripping. Frames
901         * that are 64 bytes with a vlan header appended
902         * like arp frames, or pings, are flagged as Runts
903         * when the tag is stripped and hardware. This
904         * also means that the OK bit in the descriptor
905         * is cleared when the frame comes in so we have
906         * to do a specific length check here to make sure
907         * the frame would have been ok, had we not stripped
908         * the tag.
909         */
910        if (likely((CMDSTS_OK & cmdsts) ||
911            ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
912#else
913        if (likely(CMDSTS_OK & cmdsts)) {
914#endif
915            skb_put(skb, len);
916            if (unlikely(!skb))
917                goto netdev_mangle_me_harder_failed;
918            if (cmdsts & CMDSTS_DEST_MULTI)
919                dev->stats.multicast ++;
920            dev->stats.rx_packets ++;
921            dev->stats.rx_bytes += len;
922            if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
923                skb->ip_summed = CHECKSUM_UNNECESSARY;
924            } else {
925                skb->ip_summed = CHECKSUM_NONE;
926            }
927            skb->protocol = eth_type_trans(skb, ndev);
928#ifdef NS83820_VLAN_ACCEL_SUPPORT
929            if(extsts & EXTSTS_VPKT) {
930                unsigned short tag;
931                tag = ntohs(extsts & EXTSTS_VTG_MASK);
932                rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
933            } else {
934                rx_rc = netif_rx(skb);
935            }
936#else
937            rx_rc = netif_rx(skb);
938#endif
939            if (NET_RX_DROP == rx_rc) {
940netdev_mangle_me_harder_failed:
941                dev->stats.rx_dropped ++;
942            }
943        } else {
944            kfree_skb(skb);
945        }
946
947        nr++;
948        next_rx = info->next_rx;
949        desc = info->descs + (DESC_SIZE * next_rx);
950    }
951    info->next_rx = next_rx;
952    info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
953
954out:
955    if (0 && !nr) {
956        Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
957    }
958
959    spin_unlock_irqrestore(&info->lock, flags);
960}
961
962static void rx_action(unsigned long _dev)
963{
964    struct net_device *ndev = (void *)_dev;
965    struct ns83820 *dev = PRIV(ndev);
966    rx_irq(ndev);
967    writel(ihr, dev->base + IHR);
968
969    spin_lock_irq(&dev->misc_lock);
970    dev->IMR_cache |= ISR_RXDESC;
971    writel(dev->IMR_cache, dev->base + IMR);
972    spin_unlock_irq(&dev->misc_lock);
973
974    rx_irq(ndev);
975    ns83820_rx_kick(ndev);
976}
977
978/* Packet Transmit code
979 */
980static inline void kick_tx(struct ns83820 *dev)
981{
982    dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
983        dev, dev->tx_idx, dev->tx_free_idx);
984    writel(CR_TXE, dev->base + CR);
985}
986
987/* No spinlock needed on the transmit irq path as the interrupt handler is
988 * serialized.
989 */
990static void do_tx_done(struct net_device *ndev)
991{
992    struct ns83820 *dev = PRIV(ndev);
993    u32 cmdsts, tx_done_idx;
994    __le32 *desc;
995
996    dprintk("do_tx_done(%p)\n", ndev);
997    tx_done_idx = dev->tx_done_idx;
998    desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
999
1000    dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1001        tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1002    while ((tx_done_idx != dev->tx_free_idx) &&
1003           !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1004        struct sk_buff *skb;
1005        unsigned len;
1006        dma_addr_t addr;
1007
1008        if (cmdsts & CMDSTS_ERR)
1009            dev->stats.tx_errors ++;
1010        if (cmdsts & CMDSTS_OK)
1011            dev->stats.tx_packets ++;
1012        if (cmdsts & CMDSTS_OK)
1013            dev->stats.tx_bytes += cmdsts & 0xffff;
1014
1015        dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1016            tx_done_idx, dev->tx_free_idx, cmdsts);
1017        skb = dev->tx_skbs[tx_done_idx];
1018        dev->tx_skbs[tx_done_idx] = NULL;
1019        dprintk("done(%p)\n", skb);
1020
1021        len = cmdsts & CMDSTS_LEN_MASK;
1022        addr = desc_addr_get(desc + DESC_BUFPTR);
1023        if (skb) {
1024            pci_unmap_single(dev->pci_dev,
1025                    addr,
1026                    len,
1027                    PCI_DMA_TODEVICE);
1028            dev_kfree_skb_irq(skb);
1029            atomic_dec(&dev->nr_tx_skbs);
1030        } else
1031            pci_unmap_page(dev->pci_dev,
1032                    addr,
1033                    len,
1034                    PCI_DMA_TODEVICE);
1035
1036        tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1037        dev->tx_done_idx = tx_done_idx;
1038        desc[DESC_CMDSTS] = cpu_to_le32(0);
1039        mb();
1040        desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1041    }
1042
1043    /* Allow network stack to resume queueing packets after we've
1044     * finished transmitting at least 1/4 of the packets in the queue.
1045     */
1046    if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1047        dprintk("start_queue(%p)\n", ndev);
1048        netif_start_queue(ndev);
1049        netif_wake_queue(ndev);
1050    }
1051}
1052
1053static void ns83820_cleanup_tx(struct ns83820 *dev)
1054{
1055    unsigned i;
1056
1057    for (i=0; i<NR_TX_DESC; i++) {
1058        struct sk_buff *skb = dev->tx_skbs[i];
1059        dev->tx_skbs[i] = NULL;
1060        if (skb) {
1061            __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1062            pci_unmap_single(dev->pci_dev,
1063                    desc_addr_get(desc + DESC_BUFPTR),
1064                    le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1065                    PCI_DMA_TODEVICE);
1066            dev_kfree_skb_irq(skb);
1067            atomic_dec(&dev->nr_tx_skbs);
1068        }
1069    }
1070
1071    memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1072}
1073
1074/* transmit routine. This code relies on the network layer serializing
1075 * its calls in, but will run happily in parallel with the interrupt
1076 * handler. This code currently has provisions for fragmenting tx buffers
1077 * while trying to track down a bug in either the zero copy code or
1078 * the tx fifo (hence the MAX_FRAG_LEN).
1079 */
1080static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1081{
1082    struct ns83820 *dev = PRIV(ndev);
1083    u32 free_idx, cmdsts, extsts;
1084    int nr_free, nr_frags;
1085    unsigned tx_done_idx, last_idx;
1086    dma_addr_t buf;
1087    unsigned len;
1088    skb_frag_t *frag;
1089    int stopped = 0;
1090    int do_intr = 0;
1091    volatile __le32 *first_desc;
1092
1093    dprintk("ns83820_hard_start_xmit\n");
1094
1095    nr_frags = skb_shinfo(skb)->nr_frags;
1096again:
1097    if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1098        netif_stop_queue(ndev);
1099        if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1100            return NETDEV_TX_BUSY;
1101        netif_start_queue(ndev);
1102    }
1103
1104    last_idx = free_idx = dev->tx_free_idx;
1105    tx_done_idx = dev->tx_done_idx;
1106    nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1107    nr_free -= 1;
1108    if (nr_free <= nr_frags) {
1109        dprintk("stop_queue - not enough(%p)\n", ndev);
1110        netif_stop_queue(ndev);
1111
1112        /* Check again: we may have raced with a tx done irq */
1113        if (dev->tx_done_idx != tx_done_idx) {
1114            dprintk("restart queue(%p)\n", ndev);
1115            netif_start_queue(ndev);
1116            goto again;
1117        }
1118        return NETDEV_TX_BUSY;
1119    }
1120
1121    if (free_idx == dev->tx_intr_idx) {
1122        do_intr = 1;
1123        dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1124    }
1125
1126    nr_free -= nr_frags;
1127    if (nr_free < MIN_TX_DESC_FREE) {
1128        dprintk("stop_queue - last entry(%p)\n", ndev);
1129        netif_stop_queue(ndev);
1130        stopped = 1;
1131    }
1132
1133    frag = skb_shinfo(skb)->frags;
1134    if (!nr_frags)
1135        frag = NULL;
1136    extsts = 0;
1137    if (skb->ip_summed == CHECKSUM_PARTIAL) {
1138        extsts |= EXTSTS_IPPKT;
1139        if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1140            extsts |= EXTSTS_TCPPKT;
1141        else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1142            extsts |= EXTSTS_UDPPKT;
1143    }
1144
1145#ifdef NS83820_VLAN_ACCEL_SUPPORT
1146    if(vlan_tx_tag_present(skb)) {
1147        /* fetch the vlan tag info out of the
1148         * ancilliary data if the vlan code
1149         * is using hw vlan acceleration
1150         */
1151        short tag = vlan_tx_tag_get(skb);
1152        extsts |= (EXTSTS_VPKT | htons(tag));
1153    }
1154#endif
1155
1156    len = skb->len;
1157    if (nr_frags)
1158        len -= skb->data_len;
1159    buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1160
1161    first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1162
1163    for (;;) {
1164        volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1165
1166        dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1167            (unsigned long long)buf);
1168        last_idx = free_idx;
1169        free_idx = (free_idx + 1) % NR_TX_DESC;
1170        desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1171        desc_addr_set(desc + DESC_BUFPTR, buf);
1172        desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1173
1174        cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1175        cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1176        cmdsts |= len;
1177        desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1178
1179        if (!nr_frags)
1180            break;
1181
1182        buf = pci_map_page(dev->pci_dev, frag->page,
1183                   frag->page_offset,
1184                   frag->size, PCI_DMA_TODEVICE);
1185        dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1186            (long long)buf, (long) page_to_pfn(frag->page),
1187            frag->page_offset);
1188        len = frag->size;
1189        frag++;
1190        nr_frags--;
1191    }
1192    dprintk("done pkt\n");
1193
1194    spin_lock_irq(&dev->tx_lock);
1195    dev->tx_skbs[last_idx] = skb;
1196    first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1197    dev->tx_free_idx = free_idx;
1198    atomic_inc(&dev->nr_tx_skbs);
1199    spin_unlock_irq(&dev->tx_lock);
1200
1201    kick_tx(dev);
1202
1203    /* Check again: we may have raced with a tx done irq */
1204    if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1205        netif_start_queue(ndev);
1206
1207    return NETDEV_TX_OK;
1208}
1209
1210static void ns83820_update_stats(struct ns83820 *dev)
1211{
1212    u8 __iomem *base = dev->base;
1213
1214    /* the DP83820 will freeze counters, so we need to read all of them */
1215    dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1216    dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1217    dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1218    dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1219    /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1220    dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1221    dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1222    /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1223    /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1224    /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1225    dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1226}
1227
1228static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1229{
1230    struct ns83820 *dev = PRIV(ndev);
1231
1232    /* somewhat overkill */
1233    spin_lock_irq(&dev->misc_lock);
1234    ns83820_update_stats(dev);
1235    spin_unlock_irq(&dev->misc_lock);
1236
1237    return &dev->stats;
1238}
1239
1240/* Let ethtool retrieve info */
1241static int ns83820_get_settings(struct net_device *ndev,
1242                struct ethtool_cmd *cmd)
1243{
1244    struct ns83820 *dev = PRIV(ndev);
1245    u32 cfg, tanar, tbicr;
1246    int have_optical = 0;
1247    int fullduplex = 0;
1248
1249    /*
1250     * Here's the list of available ethtool commands from other drivers:
1251     * cmd->advertising =
1252     * cmd->speed =
1253     * cmd->duplex =
1254     * cmd->port = 0;
1255     * cmd->phy_address =
1256     * cmd->transceiver = 0;
1257     * cmd->autoneg =
1258     * cmd->maxtxpkt = 0;
1259     * cmd->maxrxpkt = 0;
1260     */
1261
1262    /* read current configuration */
1263    cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1264    tanar = readl(dev->base + TANAR);
1265    tbicr = readl(dev->base + TBICR);
1266
1267    if (dev->CFG_cache & CFG_TBI_EN) {
1268        /* we have an optical interface */
1269        have_optical = 1;
1270        fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1271
1272    } else {
1273        /* We have copper */
1274        fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1275        }
1276
1277    cmd->supported = SUPPORTED_Autoneg;
1278
1279    /* we have optical interface */
1280    if (dev->CFG_cache & CFG_TBI_EN) {
1281        cmd->supported |= SUPPORTED_1000baseT_Half |
1282                    SUPPORTED_1000baseT_Full |
1283                    SUPPORTED_FIBRE;
1284        cmd->port = PORT_FIBRE;
1285    } /* TODO: else copper related support */
1286
1287    cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1288    switch (cfg / CFG_SPDSTS0 & 3) {
1289    case 2:
1290        cmd->speed = SPEED_1000;
1291        break;
1292    case 1:
1293        cmd->speed = SPEED_100;
1294        break;
1295    default:
1296        cmd->speed = SPEED_10;
1297        break;
1298    }
1299    cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE) ? 1: 0;
1300    return 0;
1301}
1302
1303/* Let ethool change settings*/
1304static int ns83820_set_settings(struct net_device *ndev,
1305                struct ethtool_cmd *cmd)
1306{
1307    struct ns83820 *dev = PRIV(ndev);
1308    u32 cfg, tanar;
1309    int have_optical = 0;
1310    int fullduplex = 0;
1311
1312    /* read current configuration */
1313    cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1314    tanar = readl(dev->base + TANAR);
1315
1316    if (dev->CFG_cache & CFG_TBI_EN) {
1317        /* we have optical */
1318        have_optical = 1;
1319        fullduplex = (tanar & TANAR_FULL_DUP);
1320
1321    } else {
1322        /* we have copper */
1323        fullduplex = cfg & CFG_DUPSTS;
1324    }
1325
1326    spin_lock_irq(&dev->misc_lock);
1327    spin_lock(&dev->tx_lock);
1328
1329    /* Set duplex */
1330    if (cmd->duplex != fullduplex) {
1331        if (have_optical) {
1332            /*set full duplex*/
1333            if (cmd->duplex == DUPLEX_FULL) {
1334                /* force full duplex */
1335                writel(readl(dev->base + TXCFG)
1336                    | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1337                    dev->base + TXCFG);
1338                writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1339                    dev->base + RXCFG);
1340                /* Light up full duplex LED */
1341                writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1342                    dev->base + GPIOR);
1343            } else {
1344                /*TODO: set half duplex */
1345            }
1346
1347        } else {
1348            /*we have copper*/
1349            /* TODO: Set duplex for copper cards */
1350        }
1351        printk(KERN_INFO "%s: Duplex set via ethtool\n",
1352        ndev->name);
1353    }
1354
1355    /* Set autonegotiation */
1356    if (1) {
1357        if (cmd->autoneg == AUTONEG_ENABLE) {
1358            /* restart auto negotiation */
1359            writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1360                dev->base + TBICR);
1361            writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1362                dev->linkstate = LINK_AUTONEGOTIATE;
1363
1364            printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1365                ndev->name);
1366        } else {
1367            /* disable auto negotiation */
1368            writel(0x00000000, dev->base + TBICR);
1369        }
1370
1371        printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1372                cmd->autoneg ? "ENABLED" : "DISABLED");
1373    }
1374
1375    phy_intr(ndev);
1376    spin_unlock(&dev->tx_lock);
1377    spin_unlock_irq(&dev->misc_lock);
1378
1379    return 0;
1380}
1381/* end ethtool get/set support -df */
1382
1383static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1384{
1385    struct ns83820 *dev = PRIV(ndev);
1386    strcpy(info->driver, "ns83820");
1387    strcpy(info->version, VERSION);
1388    strcpy(info->bus_info, pci_name(dev->pci_dev));
1389}
1390
1391static u32 ns83820_get_link(struct net_device *ndev)
1392{
1393    struct ns83820 *dev = PRIV(ndev);
1394    u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1395    return cfg & CFG_LNKSTS ? 1 : 0;
1396}
1397
1398static const struct ethtool_ops ops = {
1399    .get_settings = ns83820_get_settings,
1400    .set_settings = ns83820_set_settings,
1401    .get_drvinfo = ns83820_get_drvinfo,
1402    .get_link = ns83820_get_link
1403};
1404
1405/* this function is called in irq context from the ISR */
1406static void ns83820_mib_isr(struct ns83820 *dev)
1407{
1408    unsigned long flags;
1409    spin_lock_irqsave(&dev->misc_lock, flags);
1410    ns83820_update_stats(dev);
1411    spin_unlock_irqrestore(&dev->misc_lock, flags);
1412}
1413
1414static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1415static irqreturn_t ns83820_irq(int foo, void *data)
1416{
1417    struct net_device *ndev = data;
1418    struct ns83820 *dev = PRIV(ndev);
1419    u32 isr;
1420    dprintk("ns83820_irq(%p)\n", ndev);
1421
1422    dev->ihr = 0;
1423
1424    isr = readl(dev->base + ISR);
1425    dprintk("irq: %08x\n", isr);
1426    ns83820_do_isr(ndev, isr);
1427    return IRQ_HANDLED;
1428}
1429
1430static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1431{
1432    struct ns83820 *dev = PRIV(ndev);
1433    unsigned long flags;
1434
1435#ifdef DEBUG
1436    if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1437        Dprintk("odd isr? 0x%08x\n", isr);
1438#endif
1439
1440    if (ISR_RXIDLE & isr) {
1441        dev->rx_info.idle = 1;
1442        Dprintk("oh dear, we are idle\n");
1443        ns83820_rx_kick(ndev);
1444    }
1445
1446    if ((ISR_RXDESC | ISR_RXOK) & isr) {
1447        prefetch(dev->rx_info.next_rx_desc);
1448
1449        spin_lock_irqsave(&dev->misc_lock, flags);
1450        dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1451        writel(dev->IMR_cache, dev->base + IMR);
1452        spin_unlock_irqrestore(&dev->misc_lock, flags);
1453
1454        tasklet_schedule(&dev->rx_tasklet);
1455        //rx_irq(ndev);
1456        //writel(4, dev->base + IHR);
1457    }
1458
1459    if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1460        ns83820_rx_kick(ndev);
1461
1462    if (unlikely(ISR_RXSOVR & isr)) {
1463        //printk("overrun: rxsovr\n");
1464        dev->stats.rx_fifo_errors ++;
1465    }
1466
1467    if (unlikely(ISR_RXORN & isr)) {
1468        //printk("overrun: rxorn\n");
1469        dev->stats.rx_fifo_errors ++;
1470    }
1471
1472    if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1473        writel(CR_RXE, dev->base + CR);
1474
1475    if (ISR_TXIDLE & isr) {
1476        u32 txdp;
1477        txdp = readl(dev->base + TXDP);
1478        dprintk("txdp: %08x\n", txdp);
1479        txdp -= dev->tx_phy_descs;
1480        dev->tx_idx = txdp / (DESC_SIZE * 4);
1481        if (dev->tx_idx >= NR_TX_DESC) {
1482            printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1483            dev->tx_idx = 0;
1484        }
1485        /* The may have been a race between a pci originated read
1486         * and the descriptor update from the cpu. Just in case,
1487         * kick the transmitter if the hardware thinks it is on a
1488         * different descriptor than we are.
1489         */
1490        if (dev->tx_idx != dev->tx_free_idx)
1491            kick_tx(dev);
1492    }
1493
1494    /* Defer tx ring processing until more than a minimum amount of
1495     * work has accumulated
1496     */
1497    if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1498        spin_lock_irqsave(&dev->tx_lock, flags);
1499        do_tx_done(ndev);
1500        spin_unlock_irqrestore(&dev->tx_lock, flags);
1501
1502        /* Disable TxOk if there are no outstanding tx packets.
1503         */
1504        if ((dev->tx_done_idx == dev->tx_free_idx) &&
1505            (dev->IMR_cache & ISR_TXOK)) {
1506            spin_lock_irqsave(&dev->misc_lock, flags);
1507            dev->IMR_cache &= ~ISR_TXOK;
1508            writel(dev->IMR_cache, dev->base + IMR);
1509            spin_unlock_irqrestore(&dev->misc_lock, flags);
1510        }
1511    }
1512
1513    /* The TxIdle interrupt can come in before the transmit has
1514     * completed. Normally we reap packets off of the combination
1515     * of TxDesc and TxIdle and leave TxOk disabled (since it
1516     * occurs on every packet), but when no further irqs of this
1517     * nature are expected, we must enable TxOk.
1518     */
1519    if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1520        spin_lock_irqsave(&dev->misc_lock, flags);
1521        dev->IMR_cache |= ISR_TXOK;
1522        writel(dev->IMR_cache, dev->base + IMR);
1523        spin_unlock_irqrestore(&dev->misc_lock, flags);
1524    }
1525
1526    /* MIB interrupt: one of the statistics counters is about to overflow */
1527    if (unlikely(ISR_MIB & isr))
1528        ns83820_mib_isr(dev);
1529
1530    /* PHY: Link up/down/negotiation state change */
1531    if (unlikely(ISR_PHY & isr))
1532        phy_intr(ndev);
1533
1534#if 0 /* Still working on the interrupt mitigation strategy */
1535    if (dev->ihr)
1536        writel(dev->ihr, dev->base + IHR);
1537#endif
1538}
1539
1540static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1541{
1542    Dprintk("resetting chip...\n");
1543    writel(which, dev->base + CR);
1544    do {
1545        schedule();
1546    } while (readl(dev->base + CR) & which);
1547    Dprintk("okay!\n");
1548}
1549
1550static int ns83820_stop(struct net_device *ndev)
1551{
1552    struct ns83820 *dev = PRIV(ndev);
1553
1554    /* FIXME: protect against interrupt handler? */
1555    del_timer_sync(&dev->tx_watchdog);
1556
1557    /* disable interrupts */
1558    writel(0, dev->base + IMR);
1559    writel(0, dev->base + IER);
1560    readl(dev->base + IER);
1561
1562    dev->rx_info.up = 0;
1563    synchronize_irq(dev->pci_dev->irq);
1564
1565    ns83820_do_reset(dev, CR_RST);
1566
1567    synchronize_irq(dev->pci_dev->irq);
1568
1569    spin_lock_irq(&dev->misc_lock);
1570    dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1571    spin_unlock_irq(&dev->misc_lock);
1572
1573    ns83820_cleanup_rx(dev);
1574    ns83820_cleanup_tx(dev);
1575
1576    return 0;
1577}
1578
1579static void ns83820_tx_timeout(struct net_device *ndev)
1580{
1581    struct ns83820 *dev = PRIV(ndev);
1582        u32 tx_done_idx;
1583    __le32 *desc;
1584    unsigned long flags;
1585
1586    spin_lock_irqsave(&dev->tx_lock, flags);
1587
1588    tx_done_idx = dev->tx_done_idx;
1589    desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1590
1591    printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1592        ndev->name,
1593        tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1594
1595#if defined(DEBUG)
1596    {
1597        u32 isr;
1598        isr = readl(dev->base + ISR);
1599        printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1600        ns83820_do_isr(ndev, isr);
1601    }
1602#endif
1603
1604    do_tx_done(ndev);
1605
1606    tx_done_idx = dev->tx_done_idx;
1607    desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1608
1609    printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1610        ndev->name,
1611        tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1612
1613    spin_unlock_irqrestore(&dev->tx_lock, flags);
1614}
1615
1616static void ns83820_tx_watch(unsigned long data)
1617{
1618    struct net_device *ndev = (void *)data;
1619    struct ns83820 *dev = PRIV(ndev);
1620
1621#if defined(DEBUG)
1622    printk("ns83820_tx_watch: %u %u %d\n",
1623        dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1624        );
1625#endif
1626
1627    if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
1628        dev->tx_done_idx != dev->tx_free_idx) {
1629        printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1630            ndev->name,
1631            dev->tx_done_idx, dev->tx_free_idx,
1632            atomic_read(&dev->nr_tx_skbs));
1633        ns83820_tx_timeout(ndev);
1634    }
1635
1636    mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1637}
1638
1639static int ns83820_open(struct net_device *ndev)
1640{
1641    struct ns83820 *dev = PRIV(ndev);
1642    unsigned i;
1643    u32 desc;
1644    int ret;
1645
1646    dprintk("ns83820_open\n");
1647
1648    writel(0, dev->base + PQCR);
1649
1650    ret = ns83820_setup_rx(ndev);
1651    if (ret)
1652        goto failed;
1653
1654    memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1655    for (i=0; i<NR_TX_DESC; i++) {
1656        dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1657                = cpu_to_le32(
1658                  dev->tx_phy_descs
1659                  + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1660    }
1661
1662    dev->tx_idx = 0;
1663    dev->tx_done_idx = 0;
1664    desc = dev->tx_phy_descs;
1665    writel(0, dev->base + TXDP_HI);
1666    writel(desc, dev->base + TXDP);
1667
1668    init_timer(&dev->tx_watchdog);
1669    dev->tx_watchdog.data = (unsigned long)ndev;
1670    dev->tx_watchdog.function = ns83820_tx_watch;
1671    mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1672
1673    netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1674
1675    return 0;
1676
1677failed:
1678    ns83820_stop(ndev);
1679    return ret;
1680}
1681
1682static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1683{
1684    unsigned i;
1685    for (i=0; i<3; i++) {
1686        u32 data;
1687
1688        /* Read from the perfect match memory: this is loaded by
1689         * the chip from the EEPROM via the EELOAD self test.
1690         */
1691        writel(i*2, dev->base + RFCR);
1692        data = readl(dev->base + RFDR);
1693
1694        *mac++ = data;
1695        *mac++ = data >> 8;
1696    }
1697}
1698
1699static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1700{
1701    if (new_mtu > RX_BUF_SIZE)
1702        return -EINVAL;
1703    ndev->mtu = new_mtu;
1704    return 0;
1705}
1706
1707static void ns83820_set_multicast(struct net_device *ndev)
1708{
1709    struct ns83820 *dev = PRIV(ndev);
1710    u8 __iomem *rfcr = dev->base + RFCR;
1711    u32 and_mask = 0xffffffff;
1712    u32 or_mask = 0;
1713    u32 val;
1714
1715    if (ndev->flags & IFF_PROMISC)
1716        or_mask |= RFCR_AAU | RFCR_AAM;
1717    else
1718        and_mask &= ~(RFCR_AAU | RFCR_AAM);
1719
1720    if (ndev->flags & IFF_ALLMULTI || ndev->mc_count)
1721        or_mask |= RFCR_AAM;
1722    else
1723        and_mask &= ~RFCR_AAM;
1724
1725    spin_lock_irq(&dev->misc_lock);
1726    val = (readl(rfcr) & and_mask) | or_mask;
1727    /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1728    writel(val & ~RFCR_RFEN, rfcr);
1729    writel(val, rfcr);
1730    spin_unlock_irq(&dev->misc_lock);
1731}
1732
1733static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1734{
1735    struct ns83820 *dev = PRIV(ndev);
1736    int timed_out = 0;
1737    unsigned long start;
1738    u32 status;
1739    int loops = 0;
1740
1741    dprintk("%s: start %s\n", ndev->name, name);
1742
1743    start = jiffies;
1744
1745    writel(enable, dev->base + PTSCR);
1746    for (;;) {
1747        loops++;
1748        status = readl(dev->base + PTSCR);
1749        if (!(status & enable))
1750            break;
1751        if (status & done)
1752            break;
1753        if (status & fail)
1754            break;
1755        if (time_after_eq(jiffies, start + HZ)) {
1756            timed_out = 1;
1757            break;
1758        }
1759        schedule_timeout_uninterruptible(1);
1760    }
1761
1762    if (status & fail)
1763        printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1764            ndev->name, name, status, fail);
1765    else if (timed_out)
1766        printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1767            ndev->name, name, status);
1768
1769    dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1770}
1771
1772#ifdef PHY_CODE_IS_FINISHED
1773static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1774{
1775    /* drive MDC low */
1776    dev->MEAR_cache &= ~MEAR_MDC;
1777    writel(dev->MEAR_cache, dev->base + MEAR);
1778    readl(dev->base + MEAR);
1779
1780    /* enable output, set bit */
1781    dev->MEAR_cache |= MEAR_MDDIR;
1782    if (bit)
1783        dev->MEAR_cache |= MEAR_MDIO;
1784    else
1785        dev->MEAR_cache &= ~MEAR_MDIO;
1786
1787    /* set the output bit */
1788    writel(dev->MEAR_cache, dev->base + MEAR);
1789    readl(dev->base + MEAR);
1790
1791    /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1792    udelay(1);
1793
1794    /* drive MDC high causing the data bit to be latched */
1795    dev->MEAR_cache |= MEAR_MDC;
1796    writel(dev->MEAR_cache, dev->base + MEAR);
1797    readl(dev->base + MEAR);
1798
1799    /* Wait again... */
1800    udelay(1);
1801}
1802
1803static int ns83820_mii_read_bit(struct ns83820 *dev)
1804{
1805    int bit;
1806
1807    /* drive MDC low, disable output */
1808    dev->MEAR_cache &= ~MEAR_MDC;
1809    dev->MEAR_cache &= ~MEAR_MDDIR;
1810    writel(dev->MEAR_cache, dev->base + MEAR);
1811    readl(dev->base + MEAR);
1812
1813    /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1814    udelay(1);
1815
1816    /* drive MDC high causing the data bit to be latched */
1817    bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1818    dev->MEAR_cache |= MEAR_MDC;
1819    writel(dev->MEAR_cache, dev->base + MEAR);
1820
1821    /* Wait again... */
1822    udelay(1);
1823
1824    return bit;
1825}
1826
1827static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1828{
1829    unsigned data = 0;
1830    int i;
1831
1832    /* read some garbage so that we eventually sync up */
1833    for (i=0; i<64; i++)
1834        ns83820_mii_read_bit(dev);
1835
1836    ns83820_mii_write_bit(dev, 0); /* start */
1837    ns83820_mii_write_bit(dev, 1);
1838    ns83820_mii_write_bit(dev, 1); /* opcode read */
1839    ns83820_mii_write_bit(dev, 0);
1840
1841    /* write out the phy address: 5 bits, msb first */
1842    for (i=0; i<5; i++)
1843        ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1844
1845    /* write out the register address, 5 bits, msb first */
1846    for (i=0; i<5; i++)
1847        ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1848
1849    ns83820_mii_read_bit(dev); /* turn around cycles */
1850    ns83820_mii_read_bit(dev);
1851
1852    /* read in the register data, 16 bits msb first */
1853    for (i=0; i<16; i++) {
1854        data <<= 1;
1855        data |= ns83820_mii_read_bit(dev);
1856    }
1857
1858    return data;
1859}
1860
1861static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1862{
1863    int i;
1864
1865    /* read some garbage so that we eventually sync up */
1866    for (i=0; i<64; i++)
1867        ns83820_mii_read_bit(dev);
1868
1869    ns83820_mii_write_bit(dev, 0); /* start */
1870    ns83820_mii_write_bit(dev, 1);
1871    ns83820_mii_write_bit(dev, 0); /* opcode read */
1872    ns83820_mii_write_bit(dev, 1);
1873
1874    /* write out the phy address: 5 bits, msb first */
1875    for (i=0; i<5; i++)
1876        ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1877
1878    /* write out the register address, 5 bits, msb first */
1879    for (i=0; i<5; i++)
1880        ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1881
1882    ns83820_mii_read_bit(dev); /* turn around cycles */
1883    ns83820_mii_read_bit(dev);
1884
1885    /* read in the register data, 16 bits msb first */
1886    for (i=0; i<16; i++)
1887        ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1888
1889    return data;
1890}
1891
1892static void ns83820_probe_phy(struct net_device *ndev)
1893{
1894    struct ns83820 *dev = PRIV(ndev);
1895    static int first;
1896    int i;
1897#define MII_PHYIDR1 0x02
1898#define MII_PHYIDR2 0x03
1899
1900#if 0
1901    if (!first) {
1902        unsigned tmp;
1903        ns83820_mii_read_reg(dev, 1, 0x09);
1904        ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1905
1906        tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1907        ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1908        udelay(1300);
1909        ns83820_mii_read_reg(dev, 1, 0x09);
1910    }
1911#endif
1912    first = 1;
1913
1914    for (i=1; i<2; i++) {
1915        int j;
1916        unsigned a, b;
1917        a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1918        b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1919
1920        //printk("%s: phy %d: 0x%04x 0x%04x\n",
1921        // ndev->name, i, a, b);
1922
1923        for (j=0; j<0x16; j+=4) {
1924            dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1925                ndev->name, j,
1926                ns83820_mii_read_reg(dev, i, 0 + j),
1927                ns83820_mii_read_reg(dev, i, 1 + j),
1928                ns83820_mii_read_reg(dev, i, 2 + j),
1929                ns83820_mii_read_reg(dev, i, 3 + j)
1930                );
1931        }
1932    }
1933    {
1934        unsigned a, b;
1935        /* read firmware version: memory addr is 0x8402 and 0x8403 */
1936        ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1937        ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1938        a = ns83820_mii_read_reg(dev, 1, 0x1d);
1939
1940        ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1941        ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1942        b = ns83820_mii_read_reg(dev, 1, 0x1d);
1943        dprintk("version: 0x%04x 0x%04x\n", a, b);
1944    }
1945}
1946#endif
1947
1948static const struct net_device_ops netdev_ops = {
1949    .ndo_open = ns83820_open,
1950    .ndo_stop = ns83820_stop,
1951    .ndo_start_xmit = ns83820_hard_start_xmit,
1952    .ndo_get_stats = ns83820_get_stats,
1953    .ndo_change_mtu = ns83820_change_mtu,
1954    .ndo_set_multicast_list = ns83820_set_multicast,
1955    .ndo_validate_addr = eth_validate_addr,
1956    .ndo_set_mac_address = eth_mac_addr,
1957    .ndo_tx_timeout = ns83820_tx_timeout,
1958#ifdef NS83820_VLAN_ACCEL_SUPPORT
1959    .ndo_vlan_rx_register = ns83820_vlan_rx_register,
1960#endif
1961};
1962
1963static int __devinit ns83820_init_one(struct pci_dev *pci_dev,
1964                      const struct pci_device_id *id)
1965{
1966    struct net_device *ndev;
1967    struct ns83820 *dev;
1968    long addr;
1969    int err;
1970    int using_dac = 0;
1971
1972    /* See if we can set the dma mask early on; failure is fatal. */
1973    if (sizeof(dma_addr_t) == 8 &&
1974        !pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
1975        using_dac = 1;
1976    } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
1977        using_dac = 0;
1978    } else {
1979        dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1980        return -ENODEV;
1981    }
1982
1983    ndev = alloc_etherdev(sizeof(struct ns83820));
1984    dev = PRIV(ndev);
1985
1986    err = -ENOMEM;
1987    if (!dev)
1988        goto out;
1989
1990    dev->ndev = ndev;
1991
1992    spin_lock_init(&dev->rx_info.lock);
1993    spin_lock_init(&dev->tx_lock);
1994    spin_lock_init(&dev->misc_lock);
1995    dev->pci_dev = pci_dev;
1996
1997    SET_NETDEV_DEV(ndev, &pci_dev->dev);
1998
1999    INIT_WORK(&dev->tq_refill, queue_refill);
2000    tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
2001
2002    err = pci_enable_device(pci_dev);
2003    if (err) {
2004        dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
2005        goto out_free;
2006    }
2007
2008    pci_set_master(pci_dev);
2009    addr = pci_resource_start(pci_dev, 1);
2010    dev->base = ioremap_nocache(addr, PAGE_SIZE);
2011    dev->tx_descs = pci_alloc_consistent(pci_dev,
2012            4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
2013    dev->rx_info.descs = pci_alloc_consistent(pci_dev,
2014            4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
2015    err = -ENOMEM;
2016    if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
2017        goto out_disable;
2018
2019    dprintk("%p: %08lx %p: %08lx\n",
2020        dev->tx_descs, (long)dev->tx_phy_descs,
2021        dev->rx_info.descs, (long)dev->rx_info.phy_descs);
2022
2023    /* disable interrupts */
2024    writel(0, dev->base + IMR);
2025    writel(0, dev->base + IER);
2026    readl(dev->base + IER);
2027
2028    dev->IMR_cache = 0;
2029
2030    err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
2031              DRV_NAME, ndev);
2032    if (err) {
2033        dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
2034            pci_dev->irq, err);
2035        goto out_disable;
2036    }
2037
2038    /*
2039     * FIXME: we are holding rtnl_lock() over obscenely long area only
2040     * because some of the setup code uses dev->name. It's Wrong(tm) -
2041     * we should be using driver-specific names for all that stuff.
2042     * For now that will do, but we really need to come back and kill
2043     * most of the dev_alloc_name() users later.
2044     */
2045    rtnl_lock();
2046    err = dev_alloc_name(ndev, ndev->name);
2047    if (err < 0) {
2048        dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
2049        goto out_free_irq;
2050    }
2051
2052    printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
2053        ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2054        pci_dev->subsystem_vendor, pci_dev->subsystem_device);
2055
2056    ndev->netdev_ops = &netdev_ops;
2057    SET_ETHTOOL_OPS(ndev, &ops);
2058    ndev->watchdog_timeo = 5 * HZ;
2059    pci_set_drvdata(pci_dev, ndev);
2060
2061    ns83820_do_reset(dev, CR_RST);
2062
2063    /* Must reset the ram bist before running it */
2064    writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2065    ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
2066             PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
2067    ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
2068             PTSCR_EEBIST_FAIL);
2069    ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
2070
2071    /* I love config registers */
2072    dev->CFG_cache = readl(dev->base + CFG);
2073
2074    if ((dev->CFG_cache & CFG_PCI64_DET)) {
2075        printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2076            ndev->name);
2077        /*dev->CFG_cache |= CFG_DATA64_EN;*/
2078        if (!(dev->CFG_cache & CFG_DATA64_EN))
2079            printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2080                ndev->name);
2081    } else
2082        dev->CFG_cache &= ~(CFG_DATA64_EN);
2083
2084    dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2085               CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2086               CFG_M64ADDR);
2087    dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2088              CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2089    dev->CFG_cache |= CFG_REQALG;
2090    dev->CFG_cache |= CFG_POW;
2091    dev->CFG_cache |= CFG_TMRTEST;
2092
2093    /* When compiled with 64 bit addressing, we must always enable
2094     * the 64 bit descriptor format.
2095     */
2096    if (sizeof(dma_addr_t) == 8)
2097        dev->CFG_cache |= CFG_M64ADDR;
2098    if (using_dac)
2099        dev->CFG_cache |= CFG_T64ADDR;
2100
2101    /* Big endian mode does not seem to do what the docs suggest */
2102    dev->CFG_cache &= ~CFG_BEM;
2103
2104    /* setup optical transceiver if we have one */
2105    if (dev->CFG_cache & CFG_TBI_EN) {
2106        printk(KERN_INFO "%s: enabling optical transceiver\n",
2107            ndev->name);
2108        writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2109
2110        /* setup auto negotiation feature advertisement */
2111        writel(readl(dev->base + TANAR)
2112               | TANAR_HALF_DUP | TANAR_FULL_DUP,
2113               dev->base + TANAR);
2114
2115        /* start auto negotiation */
2116        writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2117               dev->base + TBICR);
2118        writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2119        dev->linkstate = LINK_AUTONEGOTIATE;
2120
2121        dev->CFG_cache |= CFG_MODE_1000;
2122    }
2123
2124    writel(dev->CFG_cache, dev->base + CFG);
2125    dprintk("CFG: %08x\n", dev->CFG_cache);
2126
2127    if (reset_phy) {
2128        printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2129        writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2130        msleep(10);
2131        writel(dev->CFG_cache, dev->base + CFG);
2132    }
2133
2134#if 0 /* Huh? This sets the PCI latency register. Should be done via
2135     * the PCI layer. FIXME.
2136     */
2137    if (readl(dev->base + SRR))
2138        writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2139#endif
2140
2141    /* Note! The DMA burst size interacts with packet
2142     * transmission, such that the largest packet that
2143     * can be transmitted is 8192 - FLTH - burst size.
2144     * If only the transmit fifo was larger...
2145     */
2146    /* Ramit : 1024 DMA is not a good idea, it ends up banging
2147     * some DELL and COMPAQ SMP systems */
2148    writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2149        | ((1600 / 32) * 0x100),
2150        dev->base + TXCFG);
2151
2152    /* Flush the interrupt holdoff timer */
2153    writel(0x000, dev->base + IHR);
2154    writel(0x100, dev->base + IHR);
2155    writel(0x000, dev->base + IHR);
2156
2157    /* Set Rx to full duplex, don't accept runt, errored, long or length
2158     * range errored packets. Use 512 byte DMA.
2159     */
2160    /* Ramit : 1024 DMA is not a good idea, it ends up banging
2161     * some DELL and COMPAQ SMP systems
2162     * Turn on ALP, only we are accpeting Jumbo Packets */
2163    writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2164        | RXCFG_STRIPCRC
2165        //| RXCFG_ALP
2166        | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2167
2168    /* Disable priority queueing */
2169    writel(0, dev->base + PQCR);
2170
2171    /* Enable IP checksum validation and detetion of VLAN headers.
2172     * Note: do not set the reject options as at least the 0x102
2173     * revision of the chip does not properly accept IP fragments
2174     * at least for UDP.
2175     */
2176    /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2177     * the MAC it calculates the packetsize AFTER stripping the VLAN
2178     * header, and if a VLAN Tagged packet of 64 bytes is received (like
2179     * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2180     * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2181     * it discrards it!. These guys......
2182     * also turn on tag stripping if hardware acceleration is enabled
2183     */
2184#ifdef NS83820_VLAN_ACCEL_SUPPORT
2185#define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2186#else
2187#define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2188#endif
2189    writel(VRCR_INIT_VALUE, dev->base + VRCR);
2190
2191    /* Enable per-packet TCP/UDP/IP checksumming
2192     * and per packet vlan tag insertion if
2193     * vlan hardware acceleration is enabled
2194     */
2195#ifdef NS83820_VLAN_ACCEL_SUPPORT
2196#define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2197#else
2198#define VTCR_INIT_VALUE VTCR_PPCHK
2199#endif
2200    writel(VTCR_INIT_VALUE, dev->base + VTCR);
2201
2202    /* Ramit : Enable async and sync pause frames */
2203    /* writel(0, dev->base + PCR); */
2204    writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2205        PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2206        dev->base + PCR);
2207
2208    /* Disable Wake On Lan */
2209    writel(0, dev->base + WCSR);
2210
2211    ns83820_getmac(dev, ndev->dev_addr);
2212
2213    /* Yes, we support dumb IP checksum on transmit */
2214    ndev->features |= NETIF_F_SG;
2215    ndev->features |= NETIF_F_IP_CSUM;
2216
2217#ifdef NS83820_VLAN_ACCEL_SUPPORT
2218    /* We also support hardware vlan acceleration */
2219    ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2220#endif
2221
2222    if (using_dac) {
2223        printk(KERN_INFO "%s: using 64 bit addressing.\n",
2224            ndev->name);
2225        ndev->features |= NETIF_F_HIGHDMA;
2226    }
2227
2228    printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
2229        ndev->name,
2230        (unsigned)readl(dev->base + SRR) >> 8,
2231        (unsigned)readl(dev->base + SRR) & 0xff,
2232        ndev->dev_addr, addr, pci_dev->irq,
2233        (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2234        );
2235
2236#ifdef PHY_CODE_IS_FINISHED
2237    ns83820_probe_phy(ndev);
2238#endif
2239
2240    err = register_netdevice(ndev);
2241    if (err) {
2242        printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2243        goto out_cleanup;
2244    }
2245    rtnl_unlock();
2246
2247    return 0;
2248
2249out_cleanup:
2250    writel(0, dev->base + IMR); /* paranoia */
2251    writel(0, dev->base + IER);
2252    readl(dev->base + IER);
2253out_free_irq:
2254    rtnl_unlock();
2255    free_irq(pci_dev->irq, ndev);
2256out_disable:
2257    if (dev->base)
2258        iounmap(dev->base);
2259    pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2260    pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2261    pci_disable_device(pci_dev);
2262out_free:
2263    free_netdev(ndev);
2264    pci_set_drvdata(pci_dev, NULL);
2265out:
2266    return err;
2267}
2268
2269static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2270{
2271    struct net_device *ndev = pci_get_drvdata(pci_dev);
2272    struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2273
2274    if (!ndev) /* paranoia */
2275        return;
2276
2277    writel(0, dev->base + IMR); /* paranoia */
2278    writel(0, dev->base + IER);
2279    readl(dev->base + IER);
2280
2281    unregister_netdev(ndev);
2282    free_irq(dev->pci_dev->irq, ndev);
2283    iounmap(dev->base);
2284    pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2285            dev->tx_descs, dev->tx_phy_descs);
2286    pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2287            dev->rx_info.descs, dev->rx_info.phy_descs);
2288    pci_disable_device(dev->pci_dev);
2289    free_netdev(ndev);
2290    pci_set_drvdata(pci_dev, NULL);
2291}
2292
2293static struct pci_device_id ns83820_pci_tbl[] = {
2294    { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2295    { 0, },
2296};
2297
2298static struct pci_driver driver = {
2299    .name = "ns83820",
2300    .id_table = ns83820_pci_tbl,
2301    .probe = ns83820_init_one,
2302    .remove = __devexit_p(ns83820_remove_one),
2303#if 0 /* FIXME: implement */
2304    .suspend = ,
2305    .resume = ,
2306#endif
2307};
2308
2309
2310static int __init ns83820_init(void)
2311{
2312    printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2313    return pci_register_driver(&driver);
2314}
2315
2316static void __exit ns83820_exit(void)
2317{
2318    pci_unregister_driver(&driver);
2319}
2320
2321MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2322MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2323MODULE_LICENSE("GPL");
2324
2325MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2326
2327module_param(lnksts, int, 0);
2328MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2329
2330module_param(ihr, int, 0);
2331MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2332
2333module_param(reset_phy, int, 0);
2334MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2335
2336module_init(ns83820_init);
2337module_exit(ns83820_exit);
2338

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