Root/drivers/net/qla3xxx.h

1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7#ifndef _QLA3XXX_H_
8#define _QLA3XXX_H_
9
10/*
11 * IOCB Definitions...
12 */
13#pragma pack(1)
14
15#define OPCODE_OB_MAC_IOCB_FN0 0x01
16#define OPCODE_OB_MAC_IOCB_FN2 0x21
17
18#define OPCODE_IB_MAC_IOCB 0xF9
19#define OPCODE_IB_3032_MAC_IOCB 0x09
20#define OPCODE_IB_IP_IOCB 0xFA
21#define OPCODE_IB_3032_IP_IOCB 0x0A
22
23#define OPCODE_FUNC_ID_MASK 0x30
24#define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
25
26#define FN0_MA_BITS_MASK 0x00
27#define FN1_MA_BITS_MASK 0x80
28
29struct ob_mac_iocb_req {
30    u8 opcode;
31    u8 flags;
32#define OB_MAC_IOCB_REQ_MA 0xe0
33#define OB_MAC_IOCB_REQ_F 0x10
34#define OB_MAC_IOCB_REQ_X 0x08
35#define OB_MAC_IOCB_REQ_D 0x02
36#define OB_MAC_IOCB_REQ_I 0x01
37    u8 flags1;
38#define OB_3032MAC_IOCB_REQ_IC 0x04
39#define OB_3032MAC_IOCB_REQ_TC 0x02
40#define OB_3032MAC_IOCB_REQ_UC 0x01
41    u8 reserved0;
42
43    u32 transaction_id; /* opaque for hardware */
44    __le16 data_len;
45    u8 ip_hdr_off;
46    u8 ip_hdr_len;
47    __le32 reserved1;
48    __le32 reserved2;
49    __le32 buf_addr0_low;
50    __le32 buf_addr0_high;
51    __le32 buf_0_len;
52    __le32 buf_addr1_low;
53    __le32 buf_addr1_high;
54    __le32 buf_1_len;
55    __le32 buf_addr2_low;
56    __le32 buf_addr2_high;
57    __le32 buf_2_len;
58    __le32 reserved3;
59    __le32 reserved4;
60};
61/*
62 * The following constants define control bits for buffer
63 * length fields for all IOCB's.
64 */
65#define OB_MAC_IOCB_REQ_E 0x80000000 /* Last valid buffer in list. */
66#define OB_MAC_IOCB_REQ_C 0x40000000 /* points to an OAL. (continuation) */
67#define OB_MAC_IOCB_REQ_L 0x20000000 /* Auburn local address pointer. */
68#define OB_MAC_IOCB_REQ_R 0x10000000 /* 32-bit address pointer. */
69
70struct ob_mac_iocb_rsp {
71    u8 opcode;
72    u8 flags;
73#define OB_MAC_IOCB_RSP_P 0x08
74#define OB_MAC_IOCB_RSP_L 0x04
75#define OB_MAC_IOCB_RSP_S 0x02
76#define OB_MAC_IOCB_RSP_I 0x01
77
78    __le16 reserved0;
79    u32 transaction_id; /* opaque for hardware */
80    __le32 reserved1;
81    __le32 reserved2;
82};
83
84struct ib_mac_iocb_rsp {
85    u8 opcode;
86#define IB_MAC_IOCB_RSP_V 0x80
87    u8 flags;
88#define IB_MAC_IOCB_RSP_S 0x80
89#define IB_MAC_IOCB_RSP_H1 0x40
90#define IB_MAC_IOCB_RSP_H0 0x20
91#define IB_MAC_IOCB_RSP_B 0x10
92#define IB_MAC_IOCB_RSP_M 0x08
93#define IB_MAC_IOCB_RSP_MA 0x07
94
95    __le16 length;
96    __le32 reserved;
97    __le32 ial_low;
98    __le32 ial_high;
99
100};
101
102struct ob_ip_iocb_req {
103    u8 opcode;
104    __le16 flags;
105#define OB_IP_IOCB_REQ_O 0x100
106#define OB_IP_IOCB_REQ_H 0x008
107#define OB_IP_IOCB_REQ_U 0x004
108#define OB_IP_IOCB_REQ_D 0x002
109#define OB_IP_IOCB_REQ_I 0x001
110
111    u8 reserved0;
112
113    __le32 transaction_id;
114    __le16 data_len;
115    __le16 reserved1;
116    __le32 hncb_ptr_low;
117    __le32 hncb_ptr_high;
118    __le32 buf_addr0_low;
119    __le32 buf_addr0_high;
120    __le32 buf_0_len;
121    __le32 buf_addr1_low;
122    __le32 buf_addr1_high;
123    __le32 buf_1_len;
124    __le32 buf_addr2_low;
125    __le32 buf_addr2_high;
126    __le32 buf_2_len;
127    __le32 reserved2;
128    __le32 reserved3;
129};
130
131/* defines for BufferLength fields above */
132#define OB_IP_IOCB_REQ_E 0x80000000
133#define OB_IP_IOCB_REQ_C 0x40000000
134#define OB_IP_IOCB_REQ_L 0x20000000
135#define OB_IP_IOCB_REQ_R 0x10000000
136
137struct ob_ip_iocb_rsp {
138    u8 opcode;
139    u8 flags;
140#define OB_MAC_IOCB_RSP_H 0x10
141#define OB_MAC_IOCB_RSP_E 0x08
142#define OB_MAC_IOCB_RSP_L 0x04
143#define OB_MAC_IOCB_RSP_S 0x02
144#define OB_MAC_IOCB_RSP_I 0x01
145
146    __le16 reserved0;
147    __le32 transaction_id;
148    __le32 reserved1;
149    __le32 reserved2;
150};
151
152struct ib_ip_iocb_rsp {
153    u8 opcode;
154#define IB_IP_IOCB_RSP_3032_V 0x80
155#define IB_IP_IOCB_RSP_3032_O 0x40
156#define IB_IP_IOCB_RSP_3032_I 0x20
157#define IB_IP_IOCB_RSP_3032_R 0x10
158    u8 flags;
159#define IB_IP_IOCB_RSP_S 0x80
160#define IB_IP_IOCB_RSP_H1 0x40
161#define IB_IP_IOCB_RSP_H0 0x20
162#define IB_IP_IOCB_RSP_B 0x10
163#define IB_IP_IOCB_RSP_M 0x08
164#define IB_IP_IOCB_RSP_MA 0x07
165
166    __le16 length;
167    __le16 checksum;
168#define IB_IP_IOCB_RSP_3032_ICE 0x01
169#define IB_IP_IOCB_RSP_3032_CE 0x02
170#define IB_IP_IOCB_RSP_3032_NUC 0x04
171#define IB_IP_IOCB_RSP_3032_UDP 0x08
172#define IB_IP_IOCB_RSP_3032_TCP 0x10
173#define IB_IP_IOCB_RSP_3032_IPE 0x20
174    __le16 reserved;
175#define IB_IP_IOCB_RSP_R 0x01
176    __le32 ial_low;
177    __le32 ial_high;
178};
179
180struct net_rsp_iocb {
181    u8 opcode;
182    u8 flags;
183    __le16 reserved0;
184    __le32 reserved[3];
185};
186#pragma pack()
187
188/*
189 * Register Definitions...
190 */
191#define PORT0_PHY_ADDRESS 0x1e00
192#define PORT1_PHY_ADDRESS 0x1f00
193
194#define ETHERNET_CRC_SIZE 4
195
196#define MII_SCAN_REGISTER 0x00000001
197
198#define PHY_ID_0_REG 2
199#define PHY_ID_1_REG 3
200
201#define PHY_OUI_1_MASK 0xfc00
202#define PHY_MODEL_MASK 0x03f0
203
204/* Address for the Agere Phy */
205#define MII_AGERE_ADDR_1 0x00001000
206#define MII_AGERE_ADDR_2 0x00001100
207
208/* 32-bit ispControlStatus */
209enum {
210    ISP_CONTROL_NP_MASK = 0x0003,
211    ISP_CONTROL_NP_PCSR = 0x0000,
212    ISP_CONTROL_NP_HMCR = 0x0001,
213    ISP_CONTROL_NP_LRAMCR = 0x0002,
214    ISP_CONTROL_NP_PSR = 0x0003,
215    ISP_CONTROL_RI = 0x0008,
216    ISP_CONTROL_CI = 0x0010,
217    ISP_CONTROL_PI = 0x0020,
218    ISP_CONTROL_IN = 0x0040,
219    ISP_CONTROL_BE = 0x0080,
220    ISP_CONTROL_FN_MASK = 0x0700,
221    ISP_CONTROL_FN0_NET = 0x0400,
222    ISP_CONTROL_FN0_SCSI = 0x0500,
223    ISP_CONTROL_FN1_NET = 0x0600,
224    ISP_CONTROL_FN1_SCSI = 0x0700,
225    ISP_CONTROL_LINK_DN_0 = 0x0800,
226    ISP_CONTROL_LINK_DN_1 = 0x1000,
227    ISP_CONTROL_FSR = 0x2000,
228    ISP_CONTROL_FE = 0x4000,
229    ISP_CONTROL_SR = 0x8000,
230};
231
232/* 32-bit ispInterruptMaskReg */
233enum {
234    ISP_IMR_ENABLE_INT = 0x0004,
235    ISP_IMR_DISABLE_RESET_INT = 0x0008,
236    ISP_IMR_DISABLE_CMPL_INT = 0x0010,
237    ISP_IMR_DISABLE_PROC_INT = 0x0020,
238};
239
240/* 32-bit serialPortInterfaceReg */
241enum {
242    ISP_SERIAL_PORT_IF_CLK = 0x0001,
243    ISP_SERIAL_PORT_IF_CS = 0x0002,
244    ISP_SERIAL_PORT_IF_D0 = 0x0004,
245    ISP_SERIAL_PORT_IF_DI = 0x0008,
246    ISP_NVRAM_MASK = (0x000F << 16),
247    ISP_SERIAL_PORT_IF_WE = 0x0010,
248    ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
249    ISP_SERIAL_PORT_IF_SCI = 0x0400,
250    ISP_SERIAL_PORT_IF_SC0 = 0x0800,
251    ISP_SERIAL_PORT_IF_SCE = 0x1000,
252    ISP_SERIAL_PORT_IF_SDI = 0x2000,
253    ISP_SERIAL_PORT_IF_SDO = 0x4000,
254    ISP_SERIAL_PORT_IF_SDE = 0x8000,
255    ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
256};
257
258/* semaphoreReg */
259enum {
260    QL_RESOURCE_MASK_BASE_CODE = 0x7,
261    QL_RESOURCE_BITS_BASE_CODE = 0x4,
262    QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
263    QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
264    QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
265    QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
266    QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
267    QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
268    QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
269    QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
270    QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
271    QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
272};
273
274 /*
275  * QL3XXX memory-mapped registers
276  * QL3XXX has 4 "pages" of registers, each page occupying
277  * 256 bytes. Each page has a "common" area at the start and then
278  * page-specific registers after that.
279  */
280struct ql3xxx_common_registers {
281    u32 MB0; /* Offset 0x00 */
282    u32 MB1; /* Offset 0x04 */
283    u32 MB2; /* Offset 0x08 */
284    u32 MB3; /* Offset 0x0c */
285    u32 MB4; /* Offset 0x10 */
286    u32 MB5; /* Offset 0x14 */
287    u32 MB6; /* Offset 0x18 */
288    u32 MB7; /* Offset 0x1c */
289    u32 flashBiosAddr;
290    u32 flashBiosData;
291    u32 ispControlStatus;
292    u32 ispInterruptMaskReg;
293    u32 serialPortInterfaceReg;
294    u32 semaphoreReg;
295    u32 reqQProducerIndex;
296    u32 rspQConsumerIndex;
297
298    u32 rxLargeQProducerIndex;
299    u32 rxSmallQProducerIndex;
300    u32 arcMadiCommand;
301    u32 arcMadiData;
302};
303
304enum {
305    EXT_HW_CONFIG_SP_MASK = 0x0006,
306    EXT_HW_CONFIG_SP_NONE = 0x0000,
307    EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
308    EXT_HW_CONFIG_SP_ECC = 0x0004,
309    EXT_HW_CONFIG_SP_ECCx = 0x0006,
310    EXT_HW_CONFIG_SIZE_MASK = 0x0060,
311    EXT_HW_CONFIG_SIZE_128M = 0x0000,
312    EXT_HW_CONFIG_SIZE_256M = 0x0020,
313    EXT_HW_CONFIG_SIZE_512M = 0x0040,
314    EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
315    EXT_HW_CONFIG_PD = 0x0080,
316    EXT_HW_CONFIG_FW = 0x0200,
317    EXT_HW_CONFIG_US = 0x0400,
318    EXT_HW_CONFIG_DCS_MASK = 0x1800,
319    EXT_HW_CONFIG_DCS_9MA = 0x0000,
320    EXT_HW_CONFIG_DCS_15MA = 0x0800,
321    EXT_HW_CONFIG_DCS_18MA = 0x1000,
322    EXT_HW_CONFIG_DCS_24MA = 0x1800,
323    EXT_HW_CONFIG_DDS_MASK = 0x6000,
324    EXT_HW_CONFIG_DDS_9MA = 0x0000,
325    EXT_HW_CONFIG_DDS_15MA = 0x2000,
326    EXT_HW_CONFIG_DDS_18MA = 0x4000,
327    EXT_HW_CONFIG_DDS_24MA = 0x6000,
328};
329
330/* InternalChipConfig */
331enum {
332    INTERNAL_CHIP_DM = 0x0001,
333    INTERNAL_CHIP_SD = 0x0002,
334    INTERNAL_CHIP_RAP_MASK = 0x000C,
335    INTERNAL_CHIP_RAP_RR = 0x0000,
336    INTERNAL_CHIP_RAP_NRM = 0x0004,
337    INTERNAL_CHIP_RAP_ERM = 0x0008,
338    INTERNAL_CHIP_RAP_ERMx = 0x000C,
339    INTERNAL_CHIP_WE = 0x0010,
340    INTERNAL_CHIP_EF = 0x0020,
341    INTERNAL_CHIP_FR = 0x0040,
342    INTERNAL_CHIP_FW = 0x0080,
343    INTERNAL_CHIP_FI = 0x0100,
344    INTERNAL_CHIP_FT = 0x0200,
345};
346
347/* portControl */
348enum {
349    PORT_CONTROL_DS = 0x0001,
350    PORT_CONTROL_HH = 0x0002,
351    PORT_CONTROL_EI = 0x0004,
352    PORT_CONTROL_ET = 0x0008,
353    PORT_CONTROL_EF = 0x0010,
354    PORT_CONTROL_DRM = 0x0020,
355    PORT_CONTROL_RLB = 0x0040,
356    PORT_CONTROL_RCB = 0x0080,
357    PORT_CONTROL_MAC = 0x0100,
358    PORT_CONTROL_IPV = 0x0200,
359    PORT_CONTROL_IFP = 0x0400,
360    PORT_CONTROL_ITP = 0x0800,
361    PORT_CONTROL_FI = 0x1000,
362    PORT_CONTROL_DFP = 0x2000,
363    PORT_CONTROL_OI = 0x4000,
364    PORT_CONTROL_CC = 0x8000,
365};
366
367/* portStatus */
368enum {
369    PORT_STATUS_SM0 = 0x0001,
370    PORT_STATUS_SM1 = 0x0002,
371    PORT_STATUS_X = 0x0008,
372    PORT_STATUS_DL = 0x0080,
373    PORT_STATUS_IC = 0x0200,
374    PORT_STATUS_MRC = 0x0400,
375    PORT_STATUS_NL = 0x0800,
376    PORT_STATUS_REV_ID_MASK = 0x7000,
377    PORT_STATUS_REV_ID_1 = 0x1000,
378    PORT_STATUS_REV_ID_2 = 0x2000,
379    PORT_STATUS_REV_ID_3 = 0x3000,
380    PORT_STATUS_64 = 0x8000,
381    PORT_STATUS_UP0 = 0x10000,
382    PORT_STATUS_AC0 = 0x20000,
383    PORT_STATUS_AE0 = 0x40000,
384    PORT_STATUS_UP1 = 0x100000,
385    PORT_STATUS_AC1 = 0x200000,
386    PORT_STATUS_AE1 = 0x400000,
387    PORT_STATUS_F0_ENABLED = 0x1000000,
388    PORT_STATUS_F1_ENABLED = 0x2000000,
389    PORT_STATUS_F2_ENABLED = 0x4000000,
390    PORT_STATUS_F3_ENABLED = 0x8000000,
391};
392
393/* macMIIMgmtControlReg */
394enum {
395    MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
396    MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
397    MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
398    MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
399    MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
400    MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
401    MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
402    MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
403    MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
404    MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
405};
406
407/* macMIIMgmtControlReg */
408enum {
409    MAC_MII_CONTROL_RC = 0x0001,
410    MAC_MII_CONTROL_SC = 0x0002,
411    MAC_MII_CONTROL_AS = 0x0004,
412    MAC_MII_CONTROL_NP = 0x0008,
413    MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
414    MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
415    MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
416    MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
417    MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
418    MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
419    MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
420    MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
421    MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
422    MAC_MII_CONTROL_RM = 0x8000,
423};
424
425/* macMIIStatusReg */
426enum {
427    MAC_MII_STATUS_BSY = 0x0001,
428    MAC_MII_STATUS_SC = 0x0002,
429    MAC_MII_STATUS_NV = 0x0004,
430};
431
432enum {
433    MAC_CONFIG_REG_PE = 0x0001,
434    MAC_CONFIG_REG_TF = 0x0002,
435    MAC_CONFIG_REG_RF = 0x0004,
436    MAC_CONFIG_REG_FD = 0x0008,
437    MAC_CONFIG_REG_GM = 0x0010,
438    MAC_CONFIG_REG_LB = 0x0020,
439    MAC_CONFIG_REG_SR = 0x8000,
440};
441
442enum {
443    MAC_HALF_DUPLEX_REG_ED = 0x10000,
444    MAC_HALF_DUPLEX_REG_NB = 0x20000,
445    MAC_HALF_DUPLEX_REG_BNB = 0x40000,
446    MAC_HALF_DUPLEX_REG_ALT = 0x80000,
447};
448
449enum {
450    IP_ADDR_INDEX_REG_MASK = 0x000f,
451    IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
452    IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
453    IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
454    IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
455    IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
456    IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
457    IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
458    IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
459    IP_ADDR_INDEX_REG_6 = 0x0008,
460    IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
461    IP_ADDR_INDEX_REG_E = 0x0040,
462};
463enum {
464    QL3032_PORT_CONTROL_DS = 0x0001,
465    QL3032_PORT_CONTROL_HH = 0x0002,
466    QL3032_PORT_CONTROL_EIv6 = 0x0004,
467    QL3032_PORT_CONTROL_EIv4 = 0x0008,
468    QL3032_PORT_CONTROL_ET = 0x0010,
469    QL3032_PORT_CONTROL_EF = 0x0020,
470    QL3032_PORT_CONTROL_DRM = 0x0040,
471    QL3032_PORT_CONTROL_RLB = 0x0080,
472    QL3032_PORT_CONTROL_RCB = 0x0100,
473    QL3032_PORT_CONTROL_KIE = 0x0200,
474};
475
476enum {
477    PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
478    PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
479    PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
480    PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
481    PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
482    PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
483    PROBE_MUX_ADDR_REG_UP = 0x4000,
484    PROBE_MUX_ADDR_REG_RE = 0x8000,
485};
486
487enum {
488    STATISTICS_INDEX_REG_MASK = 0x01ff,
489    STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
490    STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
491    STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
492    STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
493    STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
494    STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
495    STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
496    STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
497    STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
498    STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
499    STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
500    STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
501    STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
502    STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
503    STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
504    STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
505    STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
506    STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
507    STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
508    STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
509    STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
510    STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
511    STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
512    STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
513    STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
514    STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
515    STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
516    STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
517    STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
518    STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
519    STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
520    STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
521    STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
522    STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
523    STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
524    STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
525    STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
526    STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
527    STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
528    STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
529    STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
530    STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
531    STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
532    STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
533    STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
534    STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
535    STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
536    STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
537    STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
538    STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
539    STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
540    STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
541};
542
543enum {
544    PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
545    PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
546    PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
547    PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
548    PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
549    PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
550    PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
551    PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
552    PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
553    PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
554    PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
555    PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
556    PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
557    PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
558    PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
559    PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
560    PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
561    PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
562    PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
563    PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
564    PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
565    PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
566    PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
567    PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
568    PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
569};
570
571/*
572 * port control and status page - page 0
573 */
574
575struct ql3xxx_port_registers {
576    struct ql3xxx_common_registers CommonRegs;
577
578    u32 ExternalHWConfig;
579    u32 InternalChipConfig;
580    u32 portControl;
581    u32 portStatus;
582    u32 macAddrIndirectPtrReg;
583    u32 macAddrDataReg;
584    u32 macMIIMgmtControlReg;
585    u32 macMIIMgmtAddrReg;
586    u32 macMIIMgmtDataReg;
587    u32 macMIIStatusReg;
588    u32 mac0ConfigReg;
589    u32 mac0IpgIfgReg;
590    u32 mac0HalfDuplexReg;
591    u32 mac0MaxFrameLengthReg;
592    u32 mac0PauseThresholdReg;
593    u32 mac1ConfigReg;
594    u32 mac1IpgIfgReg;
595    u32 mac1HalfDuplexReg;
596    u32 mac1MaxFrameLengthReg;
597    u32 mac1PauseThresholdReg;
598    u32 ipAddrIndexReg;
599    u32 ipAddrDataReg;
600    u32 ipReassemblyTimeout;
601    u32 tcpMaxWindow;
602    u32 currentTcpTimestamp[2];
603    u32 internalRamRWAddrReg;
604    u32 internalRamWDataReg;
605    u32 reclaimedBufferAddrRegLow;
606    u32 reclaimedBufferAddrRegHigh;
607    u32 tcpConfiguration;
608    u32 functionControl;
609    u32 fpgaRevID;
610    u32 localRamAddr;
611    u32 localRamDataAutoIncr;
612    u32 localRamDataNonIncr;
613    u32 gpOutput;
614    u32 gpInput;
615    u32 probeMuxAddr;
616    u32 probeMuxData;
617    u32 statisticsIndexReg;
618    u32 statisticsReadDataRegAutoIncr;
619    u32 statisticsReadDataRegNoIncr;
620    u32 PortFatalErrStatus;
621};
622
623/*
624 * port host memory config page - page 1
625 */
626struct ql3xxx_host_memory_registers {
627    struct ql3xxx_common_registers CommonRegs;
628
629    u32 reserved[12];
630
631    /* Network Request Queue */
632    u32 reqConsumerIndex;
633    u32 reqConsumerIndexAddrLow;
634    u32 reqConsumerIndexAddrHigh;
635    u32 reqBaseAddrLow;
636    u32 reqBaseAddrHigh;
637    u32 reqLength;
638
639    /* Network Completion Queue */
640    u32 rspProducerIndex;
641    u32 rspProducerIndexAddrLow;
642    u32 rspProducerIndexAddrHigh;
643    u32 rspBaseAddrLow;
644    u32 rspBaseAddrHigh;
645    u32 rspLength;
646
647    /* RX Large Buffer Queue */
648    u32 rxLargeQConsumerIndex;
649    u32 rxLargeQBaseAddrLow;
650    u32 rxLargeQBaseAddrHigh;
651    u32 rxLargeQLength;
652    u32 rxLargeBufferLength;
653
654    /* RX Small Buffer Queue */
655    u32 rxSmallQConsumerIndex;
656    u32 rxSmallQBaseAddrLow;
657    u32 rxSmallQBaseAddrHigh;
658    u32 rxSmallQLength;
659    u32 rxSmallBufferLength;
660
661};
662
663/*
664 * port local RAM page - page 2
665 */
666struct ql3xxx_local_ram_registers {
667    struct ql3xxx_common_registers CommonRegs;
668    u32 bufletSize;
669    u32 maxBufletCount;
670    u32 currentBufletCount;
671    u32 reserved;
672    u32 freeBufletThresholdLow;
673    u32 freeBufletThresholdHigh;
674    u32 ipHashTableBase;
675    u32 ipHashTableCount;
676    u32 tcpHashTableBase;
677    u32 tcpHashTableCount;
678    u32 ncbBase;
679    u32 maxNcbCount;
680    u32 currentNcbCount;
681    u32 drbBase;
682    u32 maxDrbCount;
683    u32 currentDrbCount;
684};
685
686/*
687 * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
688 */
689
690#define LS_64BITS(x) (u32)(0xffffffff & ((u64)x))
691#define MS_64BITS(x) (u32)(0xffffffff & (((u64)x)>>16>>16) )
692
693/*
694 * I/O register
695 */
696
697enum {
698    CONTROL_REG = 0,
699    STATUS_REG = 1,
700    PHY_STAT_LINK_UP = 0x0004,
701    PHY_CTRL_LOOPBACK = 0x4000,
702
703    PETBI_CONTROL_REG = 0x00,
704    PETBI_CTRL_ALL_PARAMS = 0x7140,
705    PETBI_CTRL_SOFT_RESET = 0x8000,
706    PETBI_CTRL_AUTO_NEG = 0x1000,
707    PETBI_CTRL_RESTART_NEG = 0x0200,
708    PETBI_CTRL_FULL_DUPLEX = 0x0100,
709    PETBI_CTRL_SPEED_1000 = 0x0040,
710
711    PETBI_STATUS_REG = 0x01,
712    PETBI_STAT_NEG_DONE = 0x0020,
713    PETBI_STAT_LINK_UP = 0x0004,
714
715    PETBI_NEG_ADVER = 0x04,
716    PETBI_NEG_PAUSE = 0x0080,
717    PETBI_NEG_PAUSE_MASK = 0x0180,
718    PETBI_NEG_DUPLEX = 0x0020,
719    PETBI_NEG_DUPLEX_MASK = 0x0060,
720
721    PETBI_NEG_PARTNER = 0x05,
722    PETBI_NEG_ERROR_MASK = 0x3000,
723
724    PETBI_EXPANSION_REG = 0x06,
725    PETBI_EXP_PAGE_RX = 0x0002,
726
727    PHY_GIG_CONTROL = 9,
728    PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/
729    PHY_GIG_SET_MASTER = 0x0800, /* Set Master (slave if clear)*/
730    PHY_GIG_ALL_PARAMS = 0x0300,
731    PHY_GIG_ADV_1000F = 0x0200,
732    PHY_GIG_ADV_1000H = 0x0100,
733
734    PHY_NEG_ADVER = 4,
735    PHY_NEG_ALL_PARAMS = 0x0fe0,
736    PHY_NEG_ASY_PAUSE = 0x0800,
737    PHY_NEG_SYM_PAUSE = 0x0400,
738    PHY_NEG_ADV_SPEED = 0x01e0,
739    PHY_NEG_ADV_100F = 0x0100,
740    PHY_NEG_ADV_100H = 0x0080,
741    PHY_NEG_ADV_10F = 0x0040,
742    PHY_NEG_ADV_10H = 0x0020,
743
744    PETBI_TBI_CTRL = 0x11,
745    PETBI_TBI_RESET = 0x8000,
746    PETBI_TBI_AUTO_SENSE = 0x0100,
747    PETBI_TBI_SERDES_MODE = 0x0010,
748    PETBI_TBI_SERDES_WRAP = 0x0002,
749
750    AUX_CONTROL_STATUS = 0x1c,
751    PHY_AUX_NEG_DONE = 0x8000,
752    PHY_NEG_PARTNER = 5,
753    PHY_AUX_DUPLEX_STAT = 0x0020,
754    PHY_AUX_SPEED_STAT = 0x0018,
755    PHY_AUX_NO_HW_STRAP = 0x0004,
756    PHY_AUX_RESET_STICK = 0x0002,
757    PHY_NEG_PAUSE = 0x0400,
758    PHY_CTRL_SOFT_RESET = 0x8000,
759    PHY_CTRL_AUTO_NEG = 0x1000,
760    PHY_CTRL_RESTART_NEG = 0x0200,
761};
762enum {
763/* AM29LV Flash definitions */
764    FM93C56A_START = 0x1,
765/* Commands */
766    FM93C56A_READ = 0x2,
767    FM93C56A_WEN = 0x0,
768    FM93C56A_WRITE = 0x1,
769    FM93C56A_WRITE_ALL = 0x0,
770    FM93C56A_WDS = 0x0,
771    FM93C56A_ERASE = 0x3,
772    FM93C56A_ERASE_ALL = 0x0,
773/* Command Extentions */
774    FM93C56A_WEN_EXT = 0x3,
775    FM93C56A_WRITE_ALL_EXT = 0x1,
776    FM93C56A_WDS_EXT = 0x0,
777    FM93C56A_ERASE_ALL_EXT = 0x2,
778/* Special Bits */
779    FM93C56A_READ_DUMMY_BITS = 1,
780    FM93C56A_READY = 0,
781    FM93C56A_BUSY = 1,
782    FM93C56A_CMD_BITS = 2,
783/* AM29LV Flash definitions */
784    FM93C56A_SIZE_8 = 0x100,
785    FM93C56A_SIZE_16 = 0x80,
786    FM93C66A_SIZE_8 = 0x200,
787    FM93C66A_SIZE_16 = 0x100,
788    FM93C86A_SIZE_16 = 0x400,
789/* Address Bits */
790    FM93C56A_NO_ADDR_BITS_16 = 8,
791    FM93C56A_NO_ADDR_BITS_8 = 9,
792    FM93C86A_NO_ADDR_BITS_16 = 10,
793/* Data Bits */
794    FM93C56A_DATA_BITS_16 = 16,
795    FM93C56A_DATA_BITS_8 = 8,
796};
797enum {
798/* Auburn Bits */
799        AUBURN_EEPROM_DI = 0x8,
800    AUBURN_EEPROM_DI_0 = 0x0,
801    AUBURN_EEPROM_DI_1 = 0x8,
802    AUBURN_EEPROM_DO = 0x4,
803    AUBURN_EEPROM_DO_0 = 0x0,
804    AUBURN_EEPROM_DO_1 = 0x4,
805    AUBURN_EEPROM_CS = 0x2,
806    AUBURN_EEPROM_CS_0 = 0x0,
807    AUBURN_EEPROM_CS_1 = 0x2,
808    AUBURN_EEPROM_CLK_RISE = 0x1,
809    AUBURN_EEPROM_CLK_FALL = 0x0,
810};
811enum {EEPROM_SIZE = FM93C86A_SIZE_16,
812    EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
813    EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
814};
815
816/*
817 * MAC Config data structure
818 */
819    struct eeprom_port_cfg {
820    u16 etherMtu_mac;
821    u16 pauseThreshold_mac;
822    u16 resumeThreshold_mac;
823    u16 portConfiguration;
824#define PORT_CONFIG_DEFAULT 0xf700
825#define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000
826#define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000
827#define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000
828#define PORT_CONFIG_HALF_DUPLEX_ENABLED 0x1000
829#define PORT_CONFIG_1000MB_SPEED 0x0400
830#define PORT_CONFIG_100MB_SPEED 0x0200
831#define PORT_CONFIG_10MB_SPEED 0x0100
832#define PORT_CONFIG_LINK_SPEED_MASK 0x0F00
833    u16 reserved[12];
834
835};
836
837/*
838 * BIOS data structure
839 */
840struct eeprom_bios_cfg {
841    u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;
842
843    u8 bootID0:7, boodID0Valid:1;
844    u8 bootLun0[8];
845
846    u8 bootID1:7, boodID1Valid:1;
847    u8 bootLun1[8];
848
849    u16 MaxLunsTrgt;
850    u8 reserved[10];
851};
852
853/*
854 * Function Specific Data structure
855 */
856struct eeprom_function_cfg {
857    u8 reserved[30];
858    u16 macAddress[3];
859    u16 macAddressSecondary[3];
860
861    u16 subsysVendorId;
862    u16 subsysDeviceId;
863};
864
865/*
866 * EEPROM format
867 */
868struct eeprom_data {
869    u8 asicId[4];
870    u16 version_and_numPorts; /* together to avoid endianness crap */
871    u16 boardId;
872
873#define EEPROM_BOARDID_STR_SIZE 16
874#define EEPROM_SERIAL_NUM_SIZE 16
875
876    u8 boardIdStr[16];
877    u8 serialNumber[16];
878    u16 extHwConfig;
879    struct eeprom_port_cfg macCfg_port0;
880    struct eeprom_port_cfg macCfg_port1;
881    u16 bufletSize;
882    u16 bufletCount;
883    u16 tcpWindowThreshold50;
884    u16 tcpWindowThreshold25;
885    u16 tcpWindowThreshold0;
886    u16 ipHashTableBaseHi;
887    u16 ipHashTableBaseLo;
888    u16 ipHashTableSize;
889    u16 tcpHashTableBaseHi;
890    u16 tcpHashTableBaseLo;
891    u16 tcpHashTableSize;
892    u16 ncbTableBaseHi;
893    u16 ncbTableBaseLo;
894    u16 ncbTableSize;
895    u16 drbTableBaseHi;
896    u16 drbTableBaseLo;
897    u16 drbTableSize;
898    u16 reserved_142[4];
899    u16 ipReassemblyTimeout;
900    u16 tcpMaxWindowSize;
901    u16 ipSecurity;
902#define IPSEC_CONFIG_PRESENT 0x0001
903    u8 reserved_156[294];
904    u16 qDebug[8];
905    struct eeprom_function_cfg funcCfg_fn0;
906    u16 reserved_510;
907    u8 oemSpace[432];
908    struct eeprom_bios_cfg biosCfg_fn1;
909    struct eeprom_function_cfg funcCfg_fn1;
910    u16 reserved_1022;
911    u8 reserved_1024[464];
912    struct eeprom_function_cfg funcCfg_fn2;
913    u16 reserved_1534;
914    u8 reserved_1536[432];
915    struct eeprom_bios_cfg biosCfg_fn3;
916    struct eeprom_function_cfg funcCfg_fn3;
917    u16 checksum;
918};
919
920/*
921 * General definitions...
922 */
923
924/*
925 * Below are a number compiler switches for controlling driver behavior.
926 * Some are not supported under certain conditions and are notated as such.
927 */
928
929#define QL3XXX_VENDOR_ID 0x1077
930#define QL3022_DEVICE_ID 0x3022
931#define QL3032_DEVICE_ID 0x3032
932
933/* MTU & Frame Size stuff */
934#define NORMAL_MTU_SIZE ETH_DATA_LEN
935#define JUMBO_MTU_SIZE 9000
936#define VLAN_ID_LEN 2
937
938/* Request Queue Related Definitions */
939#define NUM_REQ_Q_ENTRIES 256 /* so that 64 * 64 = 4096 (1 page) */
940
941/* Response Queue Related Definitions */
942#define NUM_RSP_Q_ENTRIES 256 /* so that 256 * 16 = 4096 (1 page) */
943
944/* Transmit and Receive Buffers */
945#define NUM_LBUFQ_ENTRIES 128
946#define JUMBO_NUM_LBUFQ_ENTRIES 32
947#define NUM_SBUFQ_ENTRIES 64
948#define QL_SMALL_BUFFER_SIZE 32
949#define QL_ADDR_ELE_PER_BUFQ_ENTRY \
950(sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
951    /* Each send has at least control block. This is how many we keep. */
952#define NUM_SMALL_BUFFERS NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
953
954#define QL_HEADER_SPACE 32 /* make header space at top of skb. */
955/*
956 * Large & Small Buffers for Receives
957 */
958struct lrg_buf_q_entry {
959
960    __le32 addr0_lower;
961#define IAL_LAST_ENTRY 0x00000001
962#define IAL_CONT_ENTRY 0x00000002
963#define IAL_FLAG_MASK 0x00000003
964    __le32 addr0_upper;
965    __le32 addr1_lower;
966    __le32 addr1_upper;
967    __le32 addr2_lower;
968    __le32 addr2_upper;
969    __le32 addr3_lower;
970    __le32 addr3_upper;
971    __le32 addr4_lower;
972    __le32 addr4_upper;
973    __le32 addr5_lower;
974    __le32 addr5_upper;
975    __le32 addr6_lower;
976    __le32 addr6_upper;
977    __le32 addr7_lower;
978    __le32 addr7_upper;
979
980};
981
982struct bufq_addr_element {
983    __le32 addr_low;
984    __le32 addr_high;
985};
986
987#define QL_NO_RESET 0
988#define QL_DO_RESET 1
989
990enum link_state_t {
991    LS_UNKNOWN = 0,
992    LS_DOWN,
993    LS_DEGRADE,
994    LS_RECOVER,
995    LS_UP,
996};
997
998struct ql_rcv_buf_cb {
999    struct ql_rcv_buf_cb *next;
1000    struct sk_buff *skb;
1001     DECLARE_PCI_UNMAP_ADDR(mapaddr);
1002     DECLARE_PCI_UNMAP_LEN(maplen);
1003    __le32 buf_phy_addr_low;
1004    __le32 buf_phy_addr_high;
1005    int index;
1006};
1007
1008/*
1009 * Original IOCB has 3 sg entries:
1010 * first points to skb-data area
1011 * second points to first frag
1012 * third points to next oal.
1013 * OAL has 5 entries:
1014 * 1 thru 4 point to frags
1015 * fifth points to next oal.
1016 */
1017#define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
1018
1019struct oal_entry {
1020    __le32 dma_lo;
1021    __le32 dma_hi;
1022    __le32 len;
1023#define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */
1024#define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */
1025};
1026
1027struct oal {
1028    struct oal_entry oal_entry[5];
1029};
1030
1031struct map_list {
1032     DECLARE_PCI_UNMAP_ADDR(mapaddr);
1033     DECLARE_PCI_UNMAP_LEN(maplen);
1034};
1035
1036struct ql_tx_buf_cb {
1037    struct sk_buff *skb;
1038    struct ob_mac_iocb_req *queue_entry ;
1039    int seg_count;
1040    struct oal *oal;
1041    struct map_list map[MAX_SKB_FRAGS+1];
1042};
1043
1044/* definitions for type field */
1045#define QL_BUF_TYPE_MACIOCB 0x01
1046#define QL_BUF_TYPE_IPIOCB 0x02
1047#define QL_BUF_TYPE_TCPIOCB 0x03
1048
1049/* qdev->flags definitions. */
1050enum { QL_RESET_DONE = 1, /* Reset finished. */
1051    QL_RESET_ACTIVE = 2, /* Waiting for reset to finish. */
1052    QL_RESET_START = 3, /* Please reset the chip. */
1053    QL_RESET_PER_SCSI = 4, /* SCSI driver requests reset. */
1054    QL_TX_TIMEOUT = 5, /* Timeout in progress. */
1055    QL_LINK_MASTER = 6, /* This driver controls the link. */
1056    QL_ADAPTER_UP = 7, /* Adapter has been brought up. */
1057    QL_THREAD_UP = 8, /* This flag is available. */
1058    QL_LINK_UP = 9, /* Link Status. */
1059    QL_ALLOC_REQ_RSP_Q_DONE = 10,
1060    QL_ALLOC_BUFQS_DONE = 11,
1061    QL_ALLOC_SMALL_BUF_DONE = 12,
1062    QL_LINK_OPTICAL = 13,
1063    QL_MSI_ENABLED = 14,
1064};
1065
1066/*
1067 * ql3_adapter - The main Adapter structure definition.
1068 * This structure has all fields relevant to the hardware.
1069 */
1070
1071struct ql3_adapter {
1072    u32 reserved_00;
1073    unsigned long flags;
1074
1075    /* PCI Configuration information for this device */
1076    struct pci_dev *pdev;
1077    struct net_device *ndev; /* Parent NET device */
1078
1079    struct napi_struct napi;
1080
1081    /* Hardware information */
1082    u8 chip_rev_id;
1083    u8 pci_slot;
1084    u8 pci_width;
1085    u8 pci_x;
1086    u32 msi;
1087    int index;
1088    struct timer_list adapter_timer; /* timer used for various functions */
1089
1090    spinlock_t adapter_lock;
1091    spinlock_t hw_lock;
1092
1093    /* PCI Bus Relative Register Addresses */
1094    u8 __iomem *mmap_virt_base; /* stores return value from ioremap() */
1095    struct ql3xxx_port_registers __iomem *mem_map_registers;
1096    u32 current_page; /* tracks current register page */
1097
1098    u32 msg_enable;
1099    u8 reserved_01[2];
1100    u8 reserved_02[2];
1101
1102    /* Page for Shadow Registers */
1103    void *shadow_reg_virt_addr;
1104    dma_addr_t shadow_reg_phy_addr;
1105
1106    /* Net Request Queue */
1107    u32 req_q_size;
1108    u32 reserved_03;
1109    struct ob_mac_iocb_req *req_q_virt_addr;
1110    dma_addr_t req_q_phy_addr;
1111    u16 req_producer_index;
1112    u16 reserved_04;
1113    u16 *preq_consumer_index;
1114    u32 req_consumer_index_phy_addr_high;
1115    u32 req_consumer_index_phy_addr_low;
1116    atomic_t tx_count;
1117    struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];
1118
1119    /* Net Response Queue */
1120    u32 rsp_q_size;
1121    u32 eeprom_cmd_data;
1122    struct net_rsp_iocb *rsp_q_virt_addr;
1123    dma_addr_t rsp_q_phy_addr;
1124    struct net_rsp_iocb *rsp_current;
1125    u16 rsp_consumer_index;
1126    u16 reserved_06;
1127    volatile __le32 *prsp_producer_index;
1128    u32 rsp_producer_index_phy_addr_high;
1129    u32 rsp_producer_index_phy_addr_low;
1130
1131    /* Large Buffer Queue */
1132    u32 lrg_buf_q_alloc_size;
1133    u32 lrg_buf_q_size;
1134    void *lrg_buf_q_alloc_virt_addr;
1135    void *lrg_buf_q_virt_addr;
1136    dma_addr_t lrg_buf_q_alloc_phy_addr;
1137    dma_addr_t lrg_buf_q_phy_addr;
1138    u32 lrg_buf_q_producer_index;
1139    u32 lrg_buf_release_cnt;
1140    struct bufq_addr_element *lrg_buf_next_free;
1141    u32 num_large_buffers;
1142    u32 num_lbufq_entries;
1143
1144    /* Large (Receive) Buffers */
1145    struct ql_rcv_buf_cb *lrg_buf;
1146    struct ql_rcv_buf_cb *lrg_buf_free_head;
1147    struct ql_rcv_buf_cb *lrg_buf_free_tail;
1148    u32 lrg_buf_free_count;
1149    u32 lrg_buffer_len;
1150    u32 lrg_buf_index;
1151    u32 lrg_buf_skb_check;
1152
1153    /* Small Buffer Queue */
1154    u32 small_buf_q_alloc_size;
1155    u32 small_buf_q_size;
1156    u32 small_buf_q_producer_index;
1157    void *small_buf_q_alloc_virt_addr;
1158    void *small_buf_q_virt_addr;
1159    dma_addr_t small_buf_q_alloc_phy_addr;
1160    dma_addr_t small_buf_q_phy_addr;
1161    u32 small_buf_index;
1162
1163    /* Small (Receive) Buffers */
1164    void *small_buf_virt_addr;
1165    dma_addr_t small_buf_phy_addr;
1166    u32 small_buf_phy_addr_low;
1167    u32 small_buf_phy_addr_high;
1168    u32 small_buf_release_cnt;
1169    u32 small_buf_total_size;
1170
1171    struct eeprom_data nvram_data;
1172    u32 port_link_state;
1173
1174    /* 4022 specific */
1175    u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
1176    u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
1177    u32 mac_ob_opcode; /* Opcode to use on mac transmission */
1178    u32 mb_bit_mask; /* MA Bits mask to use on transmission */
1179    u32 numPorts;
1180    struct workqueue_struct *workqueue;
1181    struct delayed_work reset_work;
1182    struct delayed_work tx_timeout_work;
1183    struct delayed_work link_state_work;
1184    u32 max_frame_size;
1185    u32 device_id;
1186    u16 phyType;
1187};
1188
1189#endif /* _QLA3XXX_H_ */
1190

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