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Root/drivers/net/r8169.c

1	/*
2	* r8169.c: RealTek 8169/8168/8101 ethernet driver.
3	*
4	* Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5	* Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6	* Copyright (c) a lot of people too. Please respect their work.
7	*
8	* See MAINTAINERS file for support contact information.
9	*/
10
11	#include <linux/module.h>
12	#include <linux/moduleparam.h>
13	#include <linux/pci.h>
14	#include <linux/netdevice.h>
15	#include <linux/etherdevice.h>
16	#include <linux/delay.h>
17	#include <linux/ethtool.h>
18	#include <linux/mii.h>
19	#include <linux/if_vlan.h>
20	#include <linux/crc32.h>
21	#include <linux/in.h>
22	#include <linux/ip.h>
23	#include <linux/tcp.h>
24	#include <linux/init.h>
25	#include <linux/dma-mapping.h>
26
27	#include <asm/system.h>
28	#include <asm/io.h>
29	#include <asm/irq.h>
30
31	#define RTL8169_VERSION "2.3LK-NAPI"
32	#define MODULENAME "r8169"
33	#define PFX MODULENAME ": "
34
35	#ifdef RTL8169_DEBUG
36	#define assert(expr) \
37	if (!(expr)) { \
38	printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39	#expr,__FILE__,__func__,__LINE__); \
40	}
41	#define dprintk(fmt, args...) \
42	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43	#else
44	#define assert(expr) do {} while (0)
45	#define dprintk(fmt, args...) do {} while (0)
46	#endif /* RTL8169_DEBUG */
47
48	#define R8169_MSG_DEFAULT \
49	(NETIF_MSG_DRV \| NETIF_MSG_PROBE \| NETIF_MSG_IFUP \| NETIF_MSG_IFDOWN)
50
51	#define TX_BUFFS_AVAIL(tp) \
52	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54	/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55	The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56	static const int multicast_filter_limit = 32;
57
58	/* MAC address length */
59	#define MAC_ADDR_LEN 6
60
61	#define MAX_READ_REQUEST_SHIFT 12
62	#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63	#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64	#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65	#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66	#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67	#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69	#define R8169_REGS_SIZE 256
70	#define R8169_NAPI_WEIGHT 64
71	#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72	#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73	#define RX_BUF_SIZE 1536 /* Rx Buffer size */
74	#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75	#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77	#define RTL8169_TX_TIMEOUT (6*HZ)
78	#define RTL8169_PHY_TIMEOUT (10*HZ)
79
80	#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81	#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82	#define RTL_EEPROM_SIG_ADDR 0x0000
83
84	/* write/read MMIO register */
85	#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86	#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87	#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88	#define RTL_R8(reg) readb (ioaddr + (reg))
89	#define RTL_R16(reg) readw (ioaddr + (reg))
90	#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92	enum mac_version {
93	RTL_GIGA_MAC_NONE = 0x00,
94	RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
99	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
100	RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101	RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102	RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103	RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
104	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
105	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
113	RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
114	RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
115	RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
116	RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
117	RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118	RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
119	};
120
121	#define _R(NAME,MAC,MASK) \
122	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
123
124	static const struct {
125	const char *name;
126	u8 mac_version;
127	u32 RxConfigMask; /* Clears the bits supported by this chip */
128	} rtl_chip_info[] = {
129	_R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
130	_R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
131	_R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
132	_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
133	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
134	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
135	_R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
136	_R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
137	_R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
138	_R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
139	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
140	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
141	_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
142	_R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
143	_R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
144	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
145	_R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
146	_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
147	_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
148	_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
149	_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
150	_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
151	_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
152	_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
153	_R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
154	};
155	#undef _R
156
157	enum cfg_version {
158	RTL_CFG_0 = 0x00,
159	RTL_CFG_1,
160	RTL_CFG_2
161	};
162
163	static void rtl_hw_start_8169(struct net_device *);
164	static void rtl_hw_start_8168(struct net_device *);
165	static void rtl_hw_start_8101(struct net_device *);
166
167	static struct pci_device_id rtl8169_pci_tbl[] = {
168	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
169	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
170	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
171	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
172	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
173	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
174	{ PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
175	{ PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
176	{ PCI_VENDOR_ID_LINKSYS, 0x1032,
177	PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
178	{ 0x0001, 0x8168,
179	PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
180	{0,},
181	};
182
183	MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
184
185	static int rx_copybreak = 200;
186	static int use_dac;
187	static struct {
188	u32 msg_enable;
189	} debug = { -1 };
190
191	enum rtl_registers {
192	MAC0 = 0, /* Ethernet hardware address. */
193	MAC4 = 4,
194	MAR0 = 8, /* Multicast filter. */
195	CounterAddrLow = 0x10,
196	CounterAddrHigh = 0x14,
197	TxDescStartAddrLow = 0x20,
198	TxDescStartAddrHigh = 0x24,
199	TxHDescStartAddrLow = 0x28,
200	TxHDescStartAddrHigh = 0x2c,
201	FLASH = 0x30,
202	ERSR = 0x36,
203	ChipCmd = 0x37,
204	TxPoll = 0x38,
205	IntrMask = 0x3c,
206	IntrStatus = 0x3e,
207	TxConfig = 0x40,
208	RxConfig = 0x44,
209	RxMissed = 0x4c,
210	Cfg9346 = 0x50,
211	Config0 = 0x51,
212	Config1 = 0x52,
213	Config2 = 0x53,
214	Config3 = 0x54,
215	Config4 = 0x55,
216	Config5 = 0x56,
217	MultiIntr = 0x5c,
218	PHYAR = 0x60,
219	PHYstatus = 0x6c,
220	RxMaxSize = 0xda,
221	CPlusCmd = 0xe0,
222	IntrMitigate = 0xe2,
223	RxDescAddrLow = 0xe4,
224	RxDescAddrHigh = 0xe8,
225	EarlyTxThres = 0xec,
226	FuncEvent = 0xf0,
227	FuncEventMask = 0xf4,
228	FuncPresetState = 0xf8,
229	FuncForceEvent = 0xfc,
230	};
231
232	enum rtl8110_registers {
233	TBICSR = 0x64,
234	TBI_ANAR = 0x68,
235	TBI_LPAR = 0x6a,
236	};
237
238	enum rtl8168_8101_registers {
239	CSIDR = 0x64,
240	CSIAR = 0x68,
241	#define CSIAR_FLAG 0x80000000
242	#define CSIAR_WRITE_CMD 0x80000000
243	#define CSIAR_BYTE_ENABLE 0x0f
244	#define CSIAR_BYTE_ENABLE_SHIFT 12
245	#define CSIAR_ADDR_MASK 0x0fff
246
247	EPHYAR = 0x80,
248	#define EPHYAR_FLAG 0x80000000
249	#define EPHYAR_WRITE_CMD 0x80000000
250	#define EPHYAR_REG_MASK 0x1f
251	#define EPHYAR_REG_SHIFT 16
252	#define EPHYAR_DATA_MASK 0xffff
253	DBG_REG = 0xd1,
254	#define FIX_NAK_1 (1 << 4)
255	#define FIX_NAK_2 (1 << 3)
256	};
257
258	enum rtl_register_content {
259	/* InterruptStatusBits */
260	SYSErr = 0x8000,
261	PCSTimeout = 0x4000,
262	SWInt = 0x0100,
263	TxDescUnavail = 0x0080,
264	RxFIFOOver = 0x0040,
265	LinkChg = 0x0020,
266	RxOverflow = 0x0010,
267	TxErr = 0x0008,
268	TxOK = 0x0004,
269	RxErr = 0x0002,
270	RxOK = 0x0001,
271
272	/* RxStatusDesc */
273	RxFOVF = (1 << 23),
274	RxRWT = (1 << 22),
275	RxRES = (1 << 21),
276	RxRUNT = (1 << 20),
277	RxCRC = (1 << 19),
278
279	/* ChipCmdBits */
280	CmdReset = 0x10,
281	CmdRxEnb = 0x08,
282	CmdTxEnb = 0x04,
283	RxBufEmpty = 0x01,
284
285	/* TXPoll register p.5 */
286	HPQ = 0x80, /* Poll cmd on the high prio queue */
287	NPQ = 0x40, /* Poll cmd on the low prio queue */
288	FSWInt = 0x01, /* Forced software interrupt */
289
290	/* Cfg9346Bits */
291	Cfg9346_Lock = 0x00,
292	Cfg9346_Unlock = 0xc0,
293
294	/* rx_mode_bits */
295	AcceptErr = 0x20,
296	AcceptRunt = 0x10,
297	AcceptBroadcast = 0x08,
298	AcceptMulticast = 0x04,
299	AcceptMyPhys = 0x02,
300	AcceptAllPhys = 0x01,
301
302	/* RxConfigBits */
303	RxCfgFIFOShift = 13,
304	RxCfgDMAShift = 8,
305
306	/* TxConfigBits */
307	TxInterFrameGapShift = 24,
308	TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
309
310	/* Config1 register p.24 */
311	LEDS1 = (1 << 7),
312	LEDS0 = (1 << 6),
313	MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
314	Speed_down = (1 << 4),
315	MEMMAP = (1 << 3),
316	IOMAP = (1 << 2),
317	VPD = (1 << 1),
318	PMEnable = (1 << 0), /* Power Management Enable */
319
320	/* Config2 register p. 25 */
321	PCI_Clock_66MHz = 0x01,
322	PCI_Clock_33MHz = 0x00,
323
324	/* Config3 register p.25 */
325	MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
326	LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
327	Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
328
329	/* Config5 register p.27 */
330	BWF = (1 << 6), /* Accept Broadcast wakeup frame */
331	MWF = (1 << 5), /* Accept Multicast wakeup frame */
332	UWF = (1 << 4), /* Accept Unicast wakeup frame */
333	LanWake = (1 << 1), /* LanWake enable/disable */
334	PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
335
336	/* TBICSR p.28 */
337	TBIReset = 0x80000000,
338	TBILoopback = 0x40000000,
339	TBINwEnable = 0x20000000,
340	TBINwRestart = 0x10000000,
341	TBILinkOk = 0x02000000,
342	TBINwComplete = 0x01000000,
343
344	/* CPlusCmd p.31 */
345	EnableBist = (1 << 15), // 8168 8101
346	Mac_dbgo_oe = (1 << 14), // 8168 8101
347	Normal_mode = (1 << 13), // unused
348	Force_half_dup = (1 << 12), // 8168 8101
349	Force_rxflow_en = (1 << 11), // 8168 8101
350	Force_txflow_en = (1 << 10), // 8168 8101
351	Cxpl_dbg_sel = (1 << 9), // 8168 8101
352	ASF = (1 << 8), // 8168 8101
353	PktCntrDisable = (1 << 7), // 8168 8101
354	Mac_dbgo_sel = 0x001c, // 8168
355	RxVlan = (1 << 6),
356	RxChkSum = (1 << 5),
357	PCIDAC = (1 << 4),
358	PCIMulRW = (1 << 3),
359	INTT_0 = 0x0000, // 8168
360	INTT_1 = 0x0001, // 8168
361	INTT_2 = 0x0002, // 8168
362	INTT_3 = 0x0003, // 8168
363
364	/* rtl8169_PHYstatus */
365	TBI_Enable = 0x80,
366	TxFlowCtrl = 0x40,
367	RxFlowCtrl = 0x20,
368	_1000bpsF = 0x10,
369	_100bps = 0x08,
370	_10bps = 0x04,
371	LinkStatus = 0x02,
372	FullDup = 0x01,
373
374	/* _TBICSRBit */
375	TBILinkOK = 0x02000000,
376
377	/* DumpCounterCommand */
378	CounterDump = 0x8,
379	};
380
381	enum desc_status_bit {
382	DescOwn = (1 << 31), /* Descriptor is owned by NIC */
383	RingEnd = (1 << 30), /* End of descriptor ring */
384	FirstFrag = (1 << 29), /* First segment of a packet */
385	LastFrag = (1 << 28), /* Final segment of a packet */
386
387	/* Tx private */
388	LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
389	MSSShift = 16, /* MSS value position */
390	MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
391	IPCS = (1 << 18), /* Calculate IP checksum */
392	UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
393	TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
394	TxVlanTag = (1 << 17), /* Add VLAN tag */
395
396	/* Rx private */
397	PID1 = (1 << 18), /* Protocol ID bit 1/2 */
398	PID0 = (1 << 17), /* Protocol ID bit 2/2 */
399
400	#define RxProtoUDP (PID1)
401	#define RxProtoTCP (PID0)
402	#define RxProtoIP (PID1 \| PID0)
403	#define RxProtoMask RxProtoIP
404
405	IPFail = (1 << 16), /* IP checksum failed */
406	UDPFail = (1 << 15), /* UDP/IP checksum failed */
407	TCPFail = (1 << 14), /* TCP/IP checksum failed */
408	RxVlanTag = (1 << 16), /* VLAN tag available */
409	};
410
411	#define RsvdMask 0x3fffc000
412
413	struct TxDesc {
414	__le32 opts1;
415	__le32 opts2;
416	__le64 addr;
417	};
418
419	struct RxDesc {
420	__le32 opts1;
421	__le32 opts2;
422	__le64 addr;
423	};
424
425	struct ring_info {
426	struct sk_buff *skb;
427	u32 len;
428	u8 __pad[sizeof(void *) - sizeof(u32)];
429	};
430
431	enum features {
432	RTL_FEATURE_WOL = (1 << 0),
433	RTL_FEATURE_MSI = (1 << 1),
434	RTL_FEATURE_GMII = (1 << 2),
435	};
436
437	struct rtl8169_counters {
438	__le64 tx_packets;
439	__le64 rx_packets;
440	__le64 tx_errors;
441	__le32 rx_errors;
442	__le16 rx_missed;
443	__le16 align_errors;
444	__le32 tx_one_collision;
445	__le32 tx_multi_collision;
446	__le64 rx_unicast;
447	__le64 rx_broadcast;
448	__le32 rx_multicast;
449	__le16 tx_aborted;
450	__le16 tx_underun;
451	};
452
453	struct rtl8169_private {
454	void __iomem mmio_addr; / memory map physical address */
455	struct pci_dev pci_dev; / Index of PCI device */
456	struct net_device *dev;
457	struct napi_struct napi;
458	spinlock_t lock; /* spin lock flag */
459	u32 msg_enable;
460	int chipset;
461	int mac_version;
462	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
463	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
464	u32 dirty_rx;
465	u32 dirty_tx;
466	struct TxDesc TxDescArray; / 256-aligned Tx descriptor ring */
467	struct RxDesc RxDescArray; / 256-aligned Rx descriptor ring */
468	dma_addr_t TxPhyAddr;
469	dma_addr_t RxPhyAddr;
470	struct sk_buff Rx_skbuff[NUM_RX_DESC]; / Rx data buffers */
471	struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
472	unsigned align;
473	unsigned rx_buf_sz;
474	struct timer_list timer;
475	u16 cp_cmd;
476	u16 intr_event;
477	u16 napi_event;
478	u16 intr_mask;
479	int phy_1000_ctrl_reg;
480	#ifdef CONFIG_R8169_VLAN
481	struct vlan_group *vlgrp;
482	#endif
483	int (set_speed)(struct net_device , u8 autoneg, u16 speed, u8 duplex);
484	int (get_settings)(struct net_device , struct ethtool_cmd *);
485	void (phy_reset_enable)(void __iomem );
486	void (hw_start)(struct net_device );
487	unsigned int (phy_reset_pending)(void __iomem );
488	unsigned int (link_ok)(void __iomem );
489	int (do_ioctl)(struct rtl8169_private tp, struct mii_ioctl_data *data, int cmd);
490	int pcie_cap;
491	struct delayed_work task;
492	unsigned features;
493
494	struct mii_if_info mii;
495	struct rtl8169_counters counters;
496	};
497
498	MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
499	MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
500	module_param(rx_copybreak, int, 0);
501	MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
502	module_param(use_dac, int, 0);
503	MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
504	module_param_named(debug, debug.msg_enable, int, 0);
505	MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
506	MODULE_LICENSE("GPL");
507	MODULE_VERSION(RTL8169_VERSION);
508
509	static int rtl8169_open(struct net_device *dev);
510	static int rtl8169_start_xmit(struct sk_buff skb, struct net_device dev);
511	static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
512	static int rtl8169_init_ring(struct net_device *dev);
513	static void rtl_hw_start(struct net_device *dev);
514	static int rtl8169_close(struct net_device *dev);
515	static void rtl_set_rx_mode(struct net_device *dev);
516	static void rtl8169_tx_timeout(struct net_device *dev);
517	static struct net_device_stats rtl8169_get_stats(struct net_device dev);
518	static int rtl8169_rx_interrupt(struct net_device , struct rtl8169_private ,
519	void __iomem *, u32 budget);
520	static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
521	static void rtl8169_down(struct net_device *dev);
522	static void rtl8169_rx_clear(struct rtl8169_private *tp);
523	static int rtl8169_poll(struct napi_struct *napi, int budget);
524
525	static const unsigned int rtl8169_rx_config =
526	(RX_FIFO_THRESH << RxCfgFIFOShift) \| (RX_DMA_BURST << RxCfgDMAShift);
527
528	static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
529	{
530	int i;
531
532	RTL_W32(PHYAR, 0x80000000 \| (reg_addr & 0x1f) << 16 \| (value & 0xffff));
533
534	for (i = 20; i > 0; i--) {
535	/*
536	* Check if the RTL8169 has completed writing to the specified
537	* MII register.
538	*/
539	if (!(RTL_R32(PHYAR) & 0x80000000))
540	break;
541	udelay(25);
542	}
543	}
544
545	static int mdio_read(void __iomem *ioaddr, int reg_addr)
546	{
547	int i, value = -1;
548
549	RTL_W32(PHYAR, 0x0 \| (reg_addr & 0x1f) << 16);
550
551	for (i = 20; i > 0; i--) {
552	/*
553	* Check if the RTL8169 has completed retrieving data from
554	* the specified MII register.
555	*/
556	if (RTL_R32(PHYAR) & 0x80000000) {
557	value = RTL_R32(PHYAR) & 0xffff;
558	break;
559	}
560	udelay(25);
561	}
562	return value;
563	}
564
565	static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
566	{
567	mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) \| value);
568	}
569
570	static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
571	int val)
572	{
573	struct rtl8169_private *tp = netdev_priv(dev);
574	void __iomem *ioaddr = tp->mmio_addr;
575
576	mdio_write(ioaddr, location, val);
577	}
578
579	static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
580	{
581	struct rtl8169_private *tp = netdev_priv(dev);
582	void __iomem *ioaddr = tp->mmio_addr;
583
584	return mdio_read(ioaddr, location);
585	}
586
587	static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
588	{
589	unsigned int i;
590
591	RTL_W32(EPHYAR, EPHYAR_WRITE_CMD \| (value & EPHYAR_DATA_MASK) \|
592	(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
593
594	for (i = 0; i < 100; i++) {
595	if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
596	break;
597	udelay(10);
598	}
599	}
600
601	static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
602	{
603	u16 value = 0xffff;
604	unsigned int i;
605
606	RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
607
608	for (i = 0; i < 100; i++) {
609	if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
610	value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
611	break;
612	}
613	udelay(10);
614	}
615
616	return value;
617	}
618
619	static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
620	{
621	unsigned int i;
622
623	RTL_W32(CSIDR, value);
624	RTL_W32(CSIAR, CSIAR_WRITE_CMD \| (addr & CSIAR_ADDR_MASK) \|
625	CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
626
627	for (i = 0; i < 100; i++) {
628	if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
629	break;
630	udelay(10);
631	}
632	}
633
634	static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
635	{
636	u32 value = ~0x00;
637	unsigned int i;
638
639	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) \|
640	CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
641
642	for (i = 0; i < 100; i++) {
643	if (RTL_R32(CSIAR) & CSIAR_FLAG) {
644	value = RTL_R32(CSIDR);
645	break;
646	}
647	udelay(10);
648	}
649
650	return value;
651	}
652
653	static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
654	{
655	RTL_W16(IntrMask, 0x0000);
656
657	RTL_W16(IntrStatus, 0xffff);
658	}
659
660	static void rtl8169_asic_down(void __iomem *ioaddr)
661	{
662	RTL_W8(ChipCmd, 0x00);
663	rtl8169_irq_mask_and_ack(ioaddr);
664	RTL_R16(CPlusCmd);
665	}
666
667	static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
668	{
669	return RTL_R32(TBICSR) & TBIReset;
670	}
671
672	static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
673	{
674	return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
675	}
676
677	static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
678	{
679	return RTL_R32(TBICSR) & TBILinkOk;
680	}
681
682	static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
683	{
684	return RTL_R8(PHYstatus) & LinkStatus;
685	}
686
687	static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
688	{
689	RTL_W32(TBICSR, RTL_R32(TBICSR) \| TBIReset);
690	}
691
692	static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
693	{
694	unsigned int val;
695
696	val = mdio_read(ioaddr, MII_BMCR) \| BMCR_RESET;
697	mdio_write(ioaddr, MII_BMCR, val & 0xffff);
698	}
699
700	static void rtl8169_check_link_status(struct net_device *dev,
701	struct rtl8169_private *tp,
702	void __iomem *ioaddr)
703	{
704	unsigned long flags;
705
706	spin_lock_irqsave(&tp->lock, flags);
707	if (tp->link_ok(ioaddr)) {
708	netif_carrier_on(dev);
709	if (netif_msg_ifup(tp))
710	printk(KERN_INFO PFX "%s: link up\n", dev->name);
711	} else {
712	if (netif_msg_ifdown(tp))
713	printk(KERN_INFO PFX "%s: link down\n", dev->name);
714	netif_carrier_off(dev);
715	}
716	spin_unlock_irqrestore(&tp->lock, flags);
717	}
718
719	static void rtl8169_get_wol(struct net_device dev, struct ethtool_wolinfo wol)
720	{
721	struct rtl8169_private *tp = netdev_priv(dev);
722	void __iomem *ioaddr = tp->mmio_addr;
723	u8 options;
724
725	wol->wolopts = 0;
726
727	#define WAKE_ANY (WAKE_PHY \| WAKE_MAGIC \| WAKE_UCAST \| WAKE_BCAST \| WAKE_MCAST)
728	wol->supported = WAKE_ANY;
729
730	spin_lock_irq(&tp->lock);
731
732	options = RTL_R8(Config1);
733	if (!(options & PMEnable))
734	goto out_unlock;
735
736	options = RTL_R8(Config3);
737	if (options & LinkUp)
738	wol->wolopts \|= WAKE_PHY;
739	if (options & MagicPacket)
740	wol->wolopts \|= WAKE_MAGIC;
741
742	options = RTL_R8(Config5);
743	if (options & UWF)
744	wol->wolopts \|= WAKE_UCAST;
745	if (options & BWF)
746	wol->wolopts \|= WAKE_BCAST;
747	if (options & MWF)
748	wol->wolopts \|= WAKE_MCAST;
749
750	out_unlock:
751	spin_unlock_irq(&tp->lock);
752	}
753
754	static int rtl8169_set_wol(struct net_device dev, struct ethtool_wolinfo wol)
755	{
756	struct rtl8169_private *tp = netdev_priv(dev);
757	void __iomem *ioaddr = tp->mmio_addr;
758	unsigned int i;
759	static struct {
760	u32 opt;
761	u16 reg;
762	u8 mask;
763	} cfg[] = {
764	{ WAKE_ANY, Config1, PMEnable },
765	{ WAKE_PHY, Config3, LinkUp },
766	{ WAKE_MAGIC, Config3, MagicPacket },
767	{ WAKE_UCAST, Config5, UWF },
768	{ WAKE_BCAST, Config5, BWF },
769	{ WAKE_MCAST, Config5, MWF },
770	{ WAKE_ANY, Config5, LanWake }
771	};
772
773	spin_lock_irq(&tp->lock);
774
775	RTL_W8(Cfg9346, Cfg9346_Unlock);
776
777	for (i = 0; i < ARRAY_SIZE(cfg); i++) {
778	u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
779	if (wol->wolopts & cfg[i].opt)
780	options \|= cfg[i].mask;
781	RTL_W8(cfg[i].reg, options);
782	}
783
784	RTL_W8(Cfg9346, Cfg9346_Lock);
785
786	if (wol->wolopts)
787	tp->features \|= RTL_FEATURE_WOL;
788	else
789	tp->features &= ~RTL_FEATURE_WOL;
790	device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
791
792	spin_unlock_irq(&tp->lock);
793
794	return 0;
795	}
796
797	static void rtl8169_get_drvinfo(struct net_device *dev,
798	struct ethtool_drvinfo *info)
799	{
800	struct rtl8169_private *tp = netdev_priv(dev);
801
802	strcpy(info->driver, MODULENAME);
803	strcpy(info->version, RTL8169_VERSION);
804	strcpy(info->bus_info, pci_name(tp->pci_dev));
805	}
806
807	static int rtl8169_get_regs_len(struct net_device *dev)
808	{
809	return R8169_REGS_SIZE;
810	}
811
812	static int rtl8169_set_speed_tbi(struct net_device *dev,
813	u8 autoneg, u16 speed, u8 duplex)
814	{
815	struct rtl8169_private *tp = netdev_priv(dev);
816	void __iomem *ioaddr = tp->mmio_addr;
817	int ret = 0;
818	u32 reg;
819
820	reg = RTL_R32(TBICSR);
821	if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
822	(duplex == DUPLEX_FULL)) {
823	RTL_W32(TBICSR, reg & ~(TBINwEnable \| TBINwRestart));
824	} else if (autoneg == AUTONEG_ENABLE)
825	RTL_W32(TBICSR, reg \| TBINwEnable \| TBINwRestart);
826	else {
827	if (netif_msg_link(tp)) {
828	printk(KERN_WARNING "%s: "
829	"incorrect speed setting refused in TBI mode\n",
830	dev->name);
831	}
832	ret = -EOPNOTSUPP;
833	}
834
835	return ret;
836	}
837
838	static int rtl8169_set_speed_xmii(struct net_device *dev,
839	u8 autoneg, u16 speed, u8 duplex)
840	{
841	struct rtl8169_private *tp = netdev_priv(dev);
842	void __iomem *ioaddr = tp->mmio_addr;
843	int giga_ctrl, bmcr;
844
845	if (autoneg == AUTONEG_ENABLE) {
846	int auto_nego;
847
848	auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
849	auto_nego \|= (ADVERTISE_10HALF \| ADVERTISE_10FULL \|
850	ADVERTISE_100HALF \| ADVERTISE_100FULL);
851	auto_nego \|= ADVERTISE_PAUSE_CAP \| ADVERTISE_PAUSE_ASYM;
852
853	giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
854	giga_ctrl &= ~(ADVERTISE_1000FULL \| ADVERTISE_1000HALF);
855
856	/* The 8100e/8101e/8102e do Fast Ethernet only. */
857	if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
858	(tp->mac_version != RTL_GIGA_MAC_VER_08) &&
859	(tp->mac_version != RTL_GIGA_MAC_VER_09) &&
860	(tp->mac_version != RTL_GIGA_MAC_VER_10) &&
861	(tp->mac_version != RTL_GIGA_MAC_VER_13) &&
862	(tp->mac_version != RTL_GIGA_MAC_VER_14) &&
863	(tp->mac_version != RTL_GIGA_MAC_VER_15) &&
864	(tp->mac_version != RTL_GIGA_MAC_VER_16)) {
865	giga_ctrl \|= ADVERTISE_1000FULL \| ADVERTISE_1000HALF;
866	} else if (netif_msg_link(tp)) {
867	printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
868	dev->name);
869	}
870
871	bmcr = BMCR_ANENABLE \| BMCR_ANRESTART;
872
873	if ((tp->mac_version == RTL_GIGA_MAC_VER_11) \|\|
874	(tp->mac_version == RTL_GIGA_MAC_VER_12) \|\|
875	(tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
876	/*
877	* Wake up the PHY.
878	* Vendor specific (0x1f) and reserved (0x0e) MII
879	* registers.
880	*/
881	mdio_write(ioaddr, 0x1f, 0x0000);
882	mdio_write(ioaddr, 0x0e, 0x0000);
883	}
884
885	mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
886	mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
887	} else {
888	giga_ctrl = 0;
889
890	if (speed == SPEED_10)
891	bmcr = 0;
892	else if (speed == SPEED_100)
893	bmcr = BMCR_SPEED100;
894	else
895	return -EINVAL;
896
897	if (duplex == DUPLEX_FULL)
898	bmcr \|= BMCR_FULLDPLX;
899
900	mdio_write(ioaddr, 0x1f, 0x0000);
901	}
902
903	tp->phy_1000_ctrl_reg = giga_ctrl;
904
905	mdio_write(ioaddr, MII_BMCR, bmcr);
906
907	if ((tp->mac_version == RTL_GIGA_MAC_VER_02) \|\|
908	(tp->mac_version == RTL_GIGA_MAC_VER_03)) {
909	if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
910	mdio_write(ioaddr, 0x17, 0x2138);
911	mdio_write(ioaddr, 0x0e, 0x0260);
912	} else {
913	mdio_write(ioaddr, 0x17, 0x2108);
914	mdio_write(ioaddr, 0x0e, 0x0000);
915	}
916	}
917
918	return 0;
919	}
920
921	static int rtl8169_set_speed(struct net_device *dev,
922	u8 autoneg, u16 speed, u8 duplex)
923	{
924	struct rtl8169_private *tp = netdev_priv(dev);
925	int ret;
926
927	ret = tp->set_speed(dev, autoneg, speed, duplex);
928
929	if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
930	mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
931
932	return ret;
933	}
934
935	static int rtl8169_set_settings(struct net_device dev, struct ethtool_cmd cmd)
936	{
937	struct rtl8169_private *tp = netdev_priv(dev);
938	unsigned long flags;
939	int ret;
940
941	spin_lock_irqsave(&tp->lock, flags);
942	ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
943	spin_unlock_irqrestore(&tp->lock, flags);
944
945	return ret;
946	}
947
948	static u32 rtl8169_get_rx_csum(struct net_device *dev)
949	{
950	struct rtl8169_private *tp = netdev_priv(dev);
951
952	return tp->cp_cmd & RxChkSum;
953	}
954
955	static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
956	{
957	struct rtl8169_private *tp = netdev_priv(dev);
958	void __iomem *ioaddr = tp->mmio_addr;
959	unsigned long flags;
960
961	spin_lock_irqsave(&tp->lock, flags);
962
963	if (data)
964	tp->cp_cmd \|= RxChkSum;
965	else
966	tp->cp_cmd &= ~RxChkSum;
967
968	RTL_W16(CPlusCmd, tp->cp_cmd);
969	RTL_R16(CPlusCmd);
970
971	spin_unlock_irqrestore(&tp->lock, flags);
972
973	return 0;
974	}
975
976	#ifdef CONFIG_R8169_VLAN
977
978	static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
979	struct sk_buff *skb)
980	{
981	return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
982	TxVlanTag \| swab16(vlan_tx_tag_get(skb)) : 0x00;
983	}
984
985	static void rtl8169_vlan_rx_register(struct net_device *dev,
986	struct vlan_group *grp)
987	{
988	struct rtl8169_private *tp = netdev_priv(dev);
989	void __iomem *ioaddr = tp->mmio_addr;
990	unsigned long flags;
991
992	spin_lock_irqsave(&tp->lock, flags);
993	tp->vlgrp = grp;
994	if (tp->vlgrp)
995	tp->cp_cmd \|= RxVlan;
996	else
997	tp->cp_cmd &= ~RxVlan;
998	RTL_W16(CPlusCmd, tp->cp_cmd);
999	RTL_R16(CPlusCmd);
1000	spin_unlock_irqrestore(&tp->lock, flags);
1001	}
1002
1003	static int rtl8169_rx_vlan_skb(struct rtl8169_private tp, struct RxDesc desc,
1004	struct sk_buff *skb)
1005	{
1006	u32 opts2 = le32_to_cpu(desc->opts2);
1007	struct vlan_group *vlgrp = tp->vlgrp;
1008	int ret;
1009
1010	if (vlgrp && (opts2 & RxVlanTag)) {
1011	vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1012	ret = 0;
1013	} else
1014	ret = -1;
1015	desc->opts2 = 0;
1016	return ret;
1017	}
1018
1019	#else /* !CONFIG_R8169_VLAN */
1020
1021	static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1022	struct sk_buff *skb)
1023	{
1024	return 0;
1025	}
1026
1027	static int rtl8169_rx_vlan_skb(struct rtl8169_private tp, struct RxDesc desc,
1028	struct sk_buff *skb)
1029	{
1030	return -1;
1031	}
1032
1033	#endif
1034
1035	static int rtl8169_gset_tbi(struct net_device dev, struct ethtool_cmd cmd)
1036	{
1037	struct rtl8169_private *tp = netdev_priv(dev);
1038	void __iomem *ioaddr = tp->mmio_addr;
1039	u32 status;
1040
1041	cmd->supported =
1042	SUPPORTED_1000baseT_Full \| SUPPORTED_Autoneg \| SUPPORTED_FIBRE;
1043	cmd->port = PORT_FIBRE;
1044	cmd->transceiver = XCVR_INTERNAL;
1045
1046	status = RTL_R32(TBICSR);
1047	cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1048	cmd->autoneg = !!(status & TBINwEnable);
1049
1050	cmd->speed = SPEED_1000;
1051	cmd->duplex = DUPLEX_FULL; /* Always set */
1052
1053	return 0;
1054	}
1055
1056	static int rtl8169_gset_xmii(struct net_device dev, struct ethtool_cmd cmd)
1057	{
1058	struct rtl8169_private *tp = netdev_priv(dev);
1059
1060	return mii_ethtool_gset(&tp->mii, cmd);
1061	}
1062
1063	static int rtl8169_get_settings(struct net_device dev, struct ethtool_cmd cmd)
1064	{
1065	struct rtl8169_private *tp = netdev_priv(dev);
1066	unsigned long flags;
1067	int rc;
1068
1069	spin_lock_irqsave(&tp->lock, flags);
1070
1071	rc = tp->get_settings(dev, cmd);
1072
1073	spin_unlock_irqrestore(&tp->lock, flags);
1074	return rc;
1075	}
1076
1077	static void rtl8169_get_regs(struct net_device dev, struct ethtool_regs regs,
1078	void *p)
1079	{
1080	struct rtl8169_private *tp = netdev_priv(dev);
1081	unsigned long flags;
1082
1083	if (regs->len > R8169_REGS_SIZE)
1084	regs->len = R8169_REGS_SIZE;
1085
1086	spin_lock_irqsave(&tp->lock, flags);
1087	memcpy_fromio(p, tp->mmio_addr, regs->len);
1088	spin_unlock_irqrestore(&tp->lock, flags);
1089	}
1090
1091	static u32 rtl8169_get_msglevel(struct net_device *dev)
1092	{
1093	struct rtl8169_private *tp = netdev_priv(dev);
1094
1095	return tp->msg_enable;
1096	}
1097
1098	static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1099	{
1100	struct rtl8169_private *tp = netdev_priv(dev);
1101
1102	tp->msg_enable = value;
1103	}
1104
1105	static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1106	"tx_packets",
1107	"rx_packets",
1108	"tx_errors",
1109	"rx_errors",
1110	"rx_missed",
1111	"align_errors",
1112	"tx_single_collisions",
1113	"tx_multi_collisions",
1114	"unicast",
1115	"broadcast",
1116	"multicast",
1117	"tx_aborted",
1118	"tx_underrun",
1119	};
1120
1121	static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1122	{
1123	switch (sset) {
1124	case ETH_SS_STATS:
1125	return ARRAY_SIZE(rtl8169_gstrings);
1126	default:
1127	return -EOPNOTSUPP;
1128	}
1129	}
1130
1131	static void rtl8169_update_counters(struct net_device *dev)
1132	{
1133	struct rtl8169_private *tp = netdev_priv(dev);
1134	void __iomem *ioaddr = tp->mmio_addr;
1135	struct rtl8169_counters *counters;
1136	dma_addr_t paddr;
1137	u32 cmd;
1138	int wait = 1000;
1139
1140	/*
1141	* Some chips are unable to dump tally counters when the receiver
1142	* is disabled.
1143	*/
1144	if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1145	return;
1146
1147	counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1148	if (!counters)
1149	return;
1150
1151	RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1152	cmd = (u64)paddr & DMA_BIT_MASK(32);
1153	RTL_W32(CounterAddrLow, cmd);
1154	RTL_W32(CounterAddrLow, cmd \| CounterDump);
1155
1156	while (wait--) {
1157	if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1158	/* copy updated counters */
1159	memcpy(&tp->counters, counters, sizeof(*counters));
1160	break;
1161	}
1162	udelay(10);
1163	}
1164
1165	RTL_W32(CounterAddrLow, 0);
1166	RTL_W32(CounterAddrHigh, 0);
1167
1168	pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1169	}
1170
1171	static void rtl8169_get_ethtool_stats(struct net_device *dev,
1172	struct ethtool_stats stats, u64 data)
1173	{
1174	struct rtl8169_private *tp = netdev_priv(dev);
1175
1176	ASSERT_RTNL();
1177
1178	rtl8169_update_counters(dev);
1179
1180	data[0] = le64_to_cpu(tp->counters.tx_packets);
1181	data[1] = le64_to_cpu(tp->counters.rx_packets);
1182	data[2] = le64_to_cpu(tp->counters.tx_errors);
1183	data[3] = le32_to_cpu(tp->counters.rx_errors);
1184	data[4] = le16_to_cpu(tp->counters.rx_missed);
1185	data[5] = le16_to_cpu(tp->counters.align_errors);
1186	data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1187	data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1188	data[8] = le64_to_cpu(tp->counters.rx_unicast);
1189	data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1190	data[10] = le32_to_cpu(tp->counters.rx_multicast);
1191	data[11] = le16_to_cpu(tp->counters.tx_aborted);
1192	data[12] = le16_to_cpu(tp->counters.tx_underun);
1193	}
1194
1195	static void rtl8169_get_strings(struct net_device dev, u32 stringset, u8 data)
1196	{
1197	switch(stringset) {
1198	case ETH_SS_STATS:
1199	memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1200	break;
1201	}
1202	}
1203
1204	static const struct ethtool_ops rtl8169_ethtool_ops = {
1205	.get_drvinfo = rtl8169_get_drvinfo,
1206	.get_regs_len = rtl8169_get_regs_len,
1207	.get_link = ethtool_op_get_link,
1208	.get_settings = rtl8169_get_settings,
1209	.set_settings = rtl8169_set_settings,
1210	.get_msglevel = rtl8169_get_msglevel,
1211	.set_msglevel = rtl8169_set_msglevel,
1212	.get_rx_csum = rtl8169_get_rx_csum,
1213	.set_rx_csum = rtl8169_set_rx_csum,
1214	.set_tx_csum = ethtool_op_set_tx_csum,
1215	.set_sg = ethtool_op_set_sg,
1216	.set_tso = ethtool_op_set_tso,
1217	.get_regs = rtl8169_get_regs,
1218	.get_wol = rtl8169_get_wol,
1219	.set_wol = rtl8169_set_wol,
1220	.get_strings = rtl8169_get_strings,
1221	.get_sset_count = rtl8169_get_sset_count,
1222	.get_ethtool_stats = rtl8169_get_ethtool_stats,
1223	};
1224
1225	static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1226	int bitnum, int bitval)
1227	{
1228	int val;
1229
1230	val = mdio_read(ioaddr, reg);
1231	val = (bitval == 1) ?
1232	val \| (bitval << bitnum) : val & ~(0x0001 << bitnum);
1233	mdio_write(ioaddr, reg, val & 0xffff);
1234	}
1235
1236	static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1237	void __iomem *ioaddr)
1238	{
1239	/*
1240	* The driver currently handles the 8168Bf and the 8168Be identically
1241	* but they can be identified more specifically through the test below
1242	* if needed:
1243	*
1244	* (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1245	*
1246	* Same thing for the 8101Eb and the 8101Ec:
1247	*
1248	* (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1249	*/
1250	const struct {
1251	u32 mask;
1252	u32 val;
1253	int mac_version;
1254	} mac_info[] = {
1255	/* 8168D family. */
1256	{ 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1257
1258	/* 8168C family. */
1259	{ 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1260	{ 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1261	{ 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1262	{ 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1263	{ 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1264	{ 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1265	{ 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1266	{ 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1267	{ 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1268
1269	/* 8168B family. */
1270	{ 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1271	{ 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1272	{ 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1273	{ 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1274
1275	/* 8101 family. */
1276	{ 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1277	{ 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1278	{ 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1279	{ 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1280	{ 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1281	{ 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1282	{ 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1283	{ 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1284	{ 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1285	{ 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1286	{ 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1287	{ 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1288	/* FIXME: where did these entries come from ? -- FR */
1289	{ 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1290	{ 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1291
1292	/* 8110 family. */
1293	{ 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1294	{ 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1295	{ 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1296	{ 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1297	{ 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1298	{ 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1299
1300	/* Catch-all */
1301	{ 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1302	}, *p = mac_info;
1303	u32 reg;
1304
1305	reg = RTL_R32(TxConfig);
1306	while ((reg & p->mask) != p->val)
1307	p++;
1308	tp->mac_version = p->mac_version;
1309	}
1310
1311	static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1312	{
1313	dprintk("mac_version = 0x%02x\n", tp->mac_version);
1314	}
1315
1316	struct phy_reg {
1317	u16 reg;
1318	u16 val;
1319	};
1320
1321	static void rtl_phy_write(void __iomem ioaddr, struct phy_reg regs, int len)
1322	{
1323	while (len-- > 0) {
1324	mdio_write(ioaddr, regs->reg, regs->val);
1325	regs++;
1326	}
1327	}
1328
1329	static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1330	{
1331	struct {
1332	u16 regs[5]; /* Beware of bit-sign propagation */
1333	} phy_magic[5] = { {
1334	{ 0x0000, //w 4 15 12 0
1335	0x00a1, //w 3 15 0 00a1
1336	0x0008, //w 2 15 0 0008
1337	0x1020, //w 1 15 0 1020
1338	0x1000 } },{ //w 0 15 0 1000
1339	{ 0x7000, //w 4 15 12 7
1340	0xff41, //w 3 15 0 ff41
1341	0xde60, //w 2 15 0 de60
1342	0x0140, //w 1 15 0 0140
1343	0x0077 } },{ //w 0 15 0 0077
1344	{ 0xa000, //w 4 15 12 a
1345	0xdf01, //w 3 15 0 df01
1346	0xdf20, //w 2 15 0 df20
1347	0xff95, //w 1 15 0 ff95
1348	0xfa00 } },{ //w 0 15 0 fa00
1349	{ 0xb000, //w 4 15 12 b
1350	0xff41, //w 3 15 0 ff41
1351	0xde20, //w 2 15 0 de20
1352	0x0140, //w 1 15 0 0140
1353	0x00bb } },{ //w 0 15 0 00bb
1354	{ 0xf000, //w 4 15 12 f
1355	0xdf01, //w 3 15 0 df01
1356	0xdf20, //w 2 15 0 df20
1357	0xff95, //w 1 15 0 ff95
1358	0xbf00 } //w 0 15 0 bf00
1359	}
1360	}, *p = phy_magic;
1361	unsigned int i;
1362
1363	mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1364	mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1365	mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1366	rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1367
1368	for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1369	int val, pos = 4;
1370
1371	val = (mdio_read(ioaddr, pos) & 0x0fff) \| (p->regs[0] & 0xffff);
1372	mdio_write(ioaddr, pos, val);
1373	while (--pos >= 0)
1374	mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1375	rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1376	rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1377	}
1378	mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1379	}
1380
1381	static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1382	{
1383	struct phy_reg phy_reg_init[] = {
1384	{ 0x1f, 0x0002 },
1385	{ 0x01, 0x90d0 },
1386	{ 0x1f, 0x0000 }
1387	};
1388
1389	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1390	}
1391
1392	static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1393	{
1394	struct phy_reg phy_reg_init[] = {
1395	{ 0x10, 0xf41b },
1396	{ 0x1f, 0x0000 }
1397	};
1398
1399	mdio_write(ioaddr, 0x1f, 0x0001);
1400	mdio_patch(ioaddr, 0x16, 1 << 0);
1401
1402	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1403	}
1404
1405	static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1406	{
1407	struct phy_reg phy_reg_init[] = {
1408	{ 0x1f, 0x0001 },
1409	{ 0x10, 0xf41b },
1410	{ 0x1f, 0x0000 }
1411	};
1412
1413	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1414	}
1415
1416	static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1417	{
1418	struct phy_reg phy_reg_init[] = {
1419	{ 0x1f, 0x0000 },
1420	{ 0x1d, 0x0f00 },
1421	{ 0x1f, 0x0002 },
1422	{ 0x0c, 0x1ec8 },
1423	{ 0x1f, 0x0000 }
1424	};
1425
1426	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1427	}
1428
1429	static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1430	{
1431	struct phy_reg phy_reg_init[] = {
1432	{ 0x1f, 0x0001 },
1433	{ 0x1d, 0x3d98 },
1434	{ 0x1f, 0x0000 }
1435	};
1436
1437	mdio_write(ioaddr, 0x1f, 0x0000);
1438	mdio_patch(ioaddr, 0x14, 1 << 5);
1439	mdio_patch(ioaddr, 0x0d, 1 << 5);
1440
1441	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1442	}
1443
1444	static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1445	{
1446	struct phy_reg phy_reg_init[] = {
1447	{ 0x1f, 0x0001 },
1448	{ 0x12, 0x2300 },
1449	{ 0x1f, 0x0002 },
1450	{ 0x00, 0x88d4 },
1451	{ 0x01, 0x82b1 },
1452	{ 0x03, 0x7002 },
1453	{ 0x08, 0x9e30 },
1454	{ 0x09, 0x01f0 },
1455	{ 0x0a, 0x5500 },
1456	{ 0x0c, 0x00c8 },
1457	{ 0x1f, 0x0003 },
1458	{ 0x12, 0xc096 },
1459	{ 0x16, 0x000a },
1460	{ 0x1f, 0x0000 },
1461	{ 0x1f, 0x0000 },
1462	{ 0x09, 0x2000 },
1463	{ 0x09, 0x0000 }
1464	};
1465
1466	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1467
1468	mdio_patch(ioaddr, 0x14, 1 << 5);
1469	mdio_patch(ioaddr, 0x0d, 1 << 5);
1470	mdio_write(ioaddr, 0x1f, 0x0000);
1471	}
1472
1473	static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1474	{
1475	struct phy_reg phy_reg_init[] = {
1476	{ 0x1f, 0x0001 },
1477	{ 0x12, 0x2300 },
1478	{ 0x03, 0x802f },
1479	{ 0x02, 0x4f02 },
1480	{ 0x01, 0x0409 },
1481	{ 0x00, 0xf099 },
1482	{ 0x04, 0x9800 },
1483	{ 0x04, 0x9000 },
1484	{ 0x1d, 0x3d98 },
1485	{ 0x1f, 0x0002 },
1486	{ 0x0c, 0x7eb8 },
1487	{ 0x06, 0x0761 },
1488	{ 0x1f, 0x0003 },
1489	{ 0x16, 0x0f0a },
1490	{ 0x1f, 0x0000 }
1491	};
1492
1493	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1494
1495	mdio_patch(ioaddr, 0x16, 1 << 0);
1496	mdio_patch(ioaddr, 0x14, 1 << 5);
1497	mdio_patch(ioaddr, 0x0d, 1 << 5);
1498	mdio_write(ioaddr, 0x1f, 0x0000);
1499	}
1500
1501	static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1502	{
1503	struct phy_reg phy_reg_init[] = {
1504	{ 0x1f, 0x0001 },
1505	{ 0x12, 0x2300 },
1506	{ 0x1d, 0x3d98 },
1507	{ 0x1f, 0x0002 },
1508	{ 0x0c, 0x7eb8 },
1509	{ 0x06, 0x5461 },
1510	{ 0x1f, 0x0003 },
1511	{ 0x16, 0x0f0a },
1512	{ 0x1f, 0x0000 }
1513	};
1514
1515	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1516
1517	mdio_patch(ioaddr, 0x16, 1 << 0);
1518	mdio_patch(ioaddr, 0x14, 1 << 5);
1519	mdio_patch(ioaddr, 0x0d, 1 << 5);
1520	mdio_write(ioaddr, 0x1f, 0x0000);
1521	}
1522
1523	static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1524	{
1525	rtl8168c_3_hw_phy_config(ioaddr);
1526	}
1527
1528	static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1529	{
1530	struct phy_reg phy_reg_init_0[] = {
1531	{ 0x1f, 0x0001 },
1532	{ 0x09, 0x2770 },
1533	{ 0x08, 0x04d0 },
1534	{ 0x0b, 0xad15 },
1535	{ 0x0c, 0x5bf0 },
1536	{ 0x1c, 0xf101 },
1537	{ 0x1f, 0x0003 },
1538	{ 0x14, 0x94d7 },
1539	{ 0x12, 0xf4d6 },
1540	{ 0x09, 0xca0f },
1541	{ 0x1f, 0x0002 },
1542	{ 0x0b, 0x0b10 },
1543	{ 0x0c, 0xd1f7 },
1544	{ 0x1f, 0x0002 },
1545	{ 0x06, 0x5461 },
1546	{ 0x1f, 0x0002 },
1547	{ 0x05, 0x6662 },
1548	{ 0x1f, 0x0000 },
1549	{ 0x14, 0x0060 },
1550	{ 0x1f, 0x0000 },
1551	{ 0x0d, 0xf8a0 },
1552	{ 0x1f, 0x0005 },
1553	{ 0x05, 0xffc2 }
1554	};
1555
1556	rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1557
1558	if (mdio_read(ioaddr, 0x06) == 0xc400) {
1559	struct phy_reg phy_reg_init_1[] = {
1560	{ 0x1f, 0x0005 },
1561	{ 0x01, 0x0300 },
1562	{ 0x1f, 0x0000 },
1563	{ 0x11, 0x401c },
1564	{ 0x16, 0x4100 },
1565	{ 0x1f, 0x0005 },
1566	{ 0x07, 0x0010 },
1567	{ 0x05, 0x83dc },
1568	{ 0x06, 0x087d },
1569	{ 0x05, 0x8300 },
1570	{ 0x06, 0x0101 },
1571	{ 0x06, 0x05f8 },
1572	{ 0x06, 0xf9fa },
1573	{ 0x06, 0xfbef },
1574	{ 0x06, 0x79e2 },
1575	{ 0x06, 0x835f },
1576	{ 0x06, 0xe0f8 },
1577	{ 0x06, 0x9ae1 },
1578	{ 0x06, 0xf89b },
1579	{ 0x06, 0xef31 },
1580	{ 0x06, 0x3b65 },
1581	{ 0x06, 0xaa07 },
1582	{ 0x06, 0x81e4 },
1583	{ 0x06, 0xf89a },
1584	{ 0x06, 0xe5f8 },
1585	{ 0x06, 0x9baf },
1586	{ 0x06, 0x06ae },
1587	{ 0x05, 0x83dc },
1588	{ 0x06, 0x8300 },
1589	};
1590
1591	rtl_phy_write(ioaddr, phy_reg_init_1,
1592	ARRAY_SIZE(phy_reg_init_1));
1593	}
1594
1595	mdio_write(ioaddr, 0x1f, 0x0000);
1596	}
1597
1598	static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1599	{
1600	struct phy_reg phy_reg_init[] = {
1601	{ 0x1f, 0x0003 },
1602	{ 0x08, 0x441d },
1603	{ 0x01, 0x9100 },
1604	{ 0x1f, 0x0000 }
1605	};
1606
1607	mdio_write(ioaddr, 0x1f, 0x0000);
1608	mdio_patch(ioaddr, 0x11, 1 << 12);
1609	mdio_patch(ioaddr, 0x19, 1 << 13);
1610
1611	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1612	}
1613
1614	static void rtl_hw_phy_config(struct net_device *dev)
1615	{
1616	struct rtl8169_private *tp = netdev_priv(dev);
1617	void __iomem *ioaddr = tp->mmio_addr;
1618
1619	rtl8169_print_mac_version(tp);
1620
1621	switch (tp->mac_version) {
1622	case RTL_GIGA_MAC_VER_01:
1623	break;
1624	case RTL_GIGA_MAC_VER_02:
1625	case RTL_GIGA_MAC_VER_03:
1626	rtl8169s_hw_phy_config(ioaddr);
1627	break;
1628	case RTL_GIGA_MAC_VER_04:
1629	rtl8169sb_hw_phy_config(ioaddr);
1630	break;
1631	case RTL_GIGA_MAC_VER_07:
1632	case RTL_GIGA_MAC_VER_08:
1633	case RTL_GIGA_MAC_VER_09:
1634	rtl8102e_hw_phy_config(ioaddr);
1635	break;
1636	case RTL_GIGA_MAC_VER_11:
1637	rtl8168bb_hw_phy_config(ioaddr);
1638	break;
1639	case RTL_GIGA_MAC_VER_12:
1640	rtl8168bef_hw_phy_config(ioaddr);
1641	break;
1642	case RTL_GIGA_MAC_VER_17:
1643	rtl8168bef_hw_phy_config(ioaddr);
1644	break;
1645	case RTL_GIGA_MAC_VER_18:
1646	rtl8168cp_1_hw_phy_config(ioaddr);
1647	break;
1648	case RTL_GIGA_MAC_VER_19:
1649	rtl8168c_1_hw_phy_config(ioaddr);
1650	break;
1651	case RTL_GIGA_MAC_VER_20:
1652	rtl8168c_2_hw_phy_config(ioaddr);
1653	break;
1654	case RTL_GIGA_MAC_VER_21:
1655	rtl8168c_3_hw_phy_config(ioaddr);
1656	break;
1657	case RTL_GIGA_MAC_VER_22:
1658	rtl8168c_4_hw_phy_config(ioaddr);
1659	break;
1660	case RTL_GIGA_MAC_VER_23:
1661	case RTL_GIGA_MAC_VER_24:
1662	rtl8168cp_2_hw_phy_config(ioaddr);
1663	break;
1664	case RTL_GIGA_MAC_VER_25:
1665	rtl8168d_hw_phy_config(ioaddr);
1666	break;
1667
1668	default:
1669	break;
1670	}
1671	}
1672
1673	static void rtl8169_phy_timer(unsigned long __opaque)
1674	{
1675	struct net_device dev = (struct net_device )__opaque;
1676	struct rtl8169_private *tp = netdev_priv(dev);
1677	struct timer_list *timer = &tp->timer;
1678	void __iomem *ioaddr = tp->mmio_addr;
1679	unsigned long timeout = RTL8169_PHY_TIMEOUT;
1680
1681	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1682
1683	if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1684	return;
1685
1686	spin_lock_irq(&tp->lock);
1687
1688	if (tp->phy_reset_pending(ioaddr)) {
1689	/*
1690	* A busy loop could burn quite a few cycles on nowadays CPU.
1691	* Let's delay the execution of the timer for a few ticks.
1692	*/
1693	timeout = HZ/10;
1694	goto out_mod_timer;
1695	}
1696
1697	if (tp->link_ok(ioaddr))
1698	goto out_unlock;
1699
1700	if (netif_msg_link(tp))
1701	printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1702
1703	tp->phy_reset_enable(ioaddr);
1704
1705	out_mod_timer:
1706	mod_timer(timer, jiffies + timeout);
1707	out_unlock:
1708	spin_unlock_irq(&tp->lock);
1709	}
1710
1711	static inline void rtl8169_delete_timer(struct net_device *dev)
1712	{
1713	struct rtl8169_private *tp = netdev_priv(dev);
1714	struct timer_list *timer = &tp->timer;
1715
1716	if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1717	return;
1718
1719	del_timer_sync(timer);
1720	}
1721
1722	static inline void rtl8169_request_timer(struct net_device *dev)
1723	{
1724	struct rtl8169_private *tp = netdev_priv(dev);
1725	struct timer_list *timer = &tp->timer;
1726
1727	if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1728	return;
1729
1730	mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1731	}
1732
1733	#ifdef CONFIG_NET_POLL_CONTROLLER
1734	/*
1735	* Polling 'interrupt' - used by things like netconsole to send skbs
1736	* without having to re-enable interrupts. It's not called while
1737	* the interrupt routine is executing.
1738	*/
1739	static void rtl8169_netpoll(struct net_device *dev)
1740	{
1741	struct rtl8169_private *tp = netdev_priv(dev);
1742	struct pci_dev *pdev = tp->pci_dev;
1743
1744	disable_irq(pdev->irq);
1745	rtl8169_interrupt(pdev->irq, dev);
1746	enable_irq(pdev->irq);
1747	}
1748	#endif
1749
1750	static void rtl8169_release_board(struct pci_dev pdev, struct net_device dev,
1751	void __iomem *ioaddr)
1752	{
1753	iounmap(ioaddr);
1754	pci_release_regions(pdev);
1755	pci_disable_device(pdev);
1756	free_netdev(dev);
1757	}
1758
1759	static void rtl8169_phy_reset(struct net_device *dev,
1760	struct rtl8169_private *tp)
1761	{
1762	void __iomem *ioaddr = tp->mmio_addr;
1763	unsigned int i;
1764
1765	tp->phy_reset_enable(ioaddr);
1766	for (i = 0; i < 100; i++) {
1767	if (!tp->phy_reset_pending(ioaddr))
1768	return;
1769	msleep(1);
1770	}
1771	if (netif_msg_link(tp))
1772	printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1773	}
1774
1775	static void rtl8169_init_phy(struct net_device dev, struct rtl8169_private tp)
1776	{
1777	void __iomem *ioaddr = tp->mmio_addr;
1778
1779	rtl_hw_phy_config(dev);
1780
1781	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1782	dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1783	RTL_W8(0x82, 0x01);
1784	}
1785
1786	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1787
1788	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1789	pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1790
1791	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1792	dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1793	RTL_W8(0x82, 0x01);
1794	dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1795	mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1796	}
1797
1798	rtl8169_phy_reset(dev, tp);
1799
1800	/*
1801	* rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1802	* only 8101. Don't panic.
1803	*/
1804	rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1805
1806	if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1807	printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1808	}
1809
1810	static void rtl_rar_set(struct rtl8169_private tp, u8 addr)
1811	{
1812	void __iomem *ioaddr = tp->mmio_addr;
1813	u32 high;
1814	u32 low;
1815
1816	low = addr[0] \| (addr[1] << 8) \| (addr[2] << 16) \| (addr[3] << 24);
1817	high = addr[4] \| (addr[5] << 8);
1818
1819	spin_lock_irq(&tp->lock);
1820
1821	RTL_W8(Cfg9346, Cfg9346_Unlock);
1822	RTL_W32(MAC0, low);
1823	RTL_W32(MAC4, high);
1824	RTL_W8(Cfg9346, Cfg9346_Lock);
1825
1826	spin_unlock_irq(&tp->lock);
1827	}
1828
1829	static int rtl_set_mac_address(struct net_device dev, void p)
1830	{
1831	struct rtl8169_private *tp = netdev_priv(dev);
1832	struct sockaddr *addr = p;
1833
1834	if (!is_valid_ether_addr(addr->sa_data))
1835	return -EADDRNOTAVAIL;
1836
1837	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1838
1839	rtl_rar_set(tp, dev->dev_addr);
1840
1841	return 0;
1842	}
1843
1844	static int rtl8169_ioctl(struct net_device dev, struct ifreq ifr, int cmd)
1845	{
1846	struct rtl8169_private *tp = netdev_priv(dev);
1847	struct mii_ioctl_data *data = if_mii(ifr);
1848
1849	return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1850	}
1851
1852	static int rtl_xmii_ioctl(struct rtl8169_private tp, struct mii_ioctl_data data, int cmd)
1853	{
1854	switch (cmd) {
1855	case SIOCGMIIPHY:
1856	data->phy_id = 32; /* Internal PHY */
1857	return 0;
1858
1859	case SIOCGMIIREG:
1860	data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1861	return 0;
1862
1863	case SIOCSMIIREG:
1864	if (!capable(CAP_NET_ADMIN))
1865	return -EPERM;
1866	mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1867	return 0;
1868	}
1869	return -EOPNOTSUPP;
1870	}
1871
1872	static int rtl_tbi_ioctl(struct rtl8169_private tp, struct mii_ioctl_data data, int cmd)
1873	{
1874	return -EOPNOTSUPP;
1875	}
1876
1877	static const struct rtl_cfg_info {
1878	void (hw_start)(struct net_device );
1879	unsigned int region;
1880	unsigned int align;
1881	u16 intr_event;
1882	u16 napi_event;
1883	unsigned features;
1884	u8 default_ver;
1885	} rtl_cfg_infos [] = {
1886	[RTL_CFG_0] = {
1887	.hw_start = rtl_hw_start_8169,
1888	.region = 1,
1889	.align = 0,
1890	.intr_event = SYSErr \| LinkChg \| RxOverflow \|
1891	RxFIFOOver \| TxErr \| TxOK \| RxOK \| RxErr,
1892	.napi_event = RxFIFOOver \| TxErr \| TxOK \| RxOK \| RxOverflow,
1893	.features = RTL_FEATURE_GMII,
1894	.default_ver = RTL_GIGA_MAC_VER_01,
1895	},
1896	[RTL_CFG_1] = {
1897	.hw_start = rtl_hw_start_8168,
1898	.region = 2,
1899	.align = 8,
1900	.intr_event = SYSErr \| LinkChg \| RxOverflow \|
1901	TxErr \| TxOK \| RxOK \| RxErr,
1902	.napi_event = TxErr \| TxOK \| RxOK \| RxOverflow,
1903	.features = RTL_FEATURE_GMII \| RTL_FEATURE_MSI,
1904	.default_ver = RTL_GIGA_MAC_VER_11,
1905	},
1906	[RTL_CFG_2] = {
1907	.hw_start = rtl_hw_start_8101,
1908	.region = 2,
1909	.align = 8,
1910	.intr_event = SYSErr \| LinkChg \| RxOverflow \| PCSTimeout \|
1911	RxFIFOOver \| TxErr \| TxOK \| RxOK \| RxErr,
1912	.napi_event = RxFIFOOver \| TxErr \| TxOK \| RxOK \| RxOverflow,
1913	.features = RTL_FEATURE_MSI,
1914	.default_ver = RTL_GIGA_MAC_VER_13,
1915	}
1916	};
1917
1918	/* Cfg9346_Unlock assumed. */
1919	static unsigned rtl_try_msi(struct pci_dev pdev, void __iomem ioaddr,
1920	const struct rtl_cfg_info *cfg)
1921	{
1922	unsigned msi = 0;
1923	u8 cfg2;
1924
1925	cfg2 = RTL_R8(Config2) & ~MSIEnable;
1926	if (cfg->features & RTL_FEATURE_MSI) {
1927	if (pci_enable_msi(pdev)) {
1928	dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1929	} else {
1930	cfg2 \|= MSIEnable;
1931	msi = RTL_FEATURE_MSI;
1932	}
1933	}
1934	RTL_W8(Config2, cfg2);
1935	return msi;
1936	}
1937
1938	static void rtl_disable_msi(struct pci_dev pdev, struct rtl8169_private tp)
1939	{
1940	if (tp->features & RTL_FEATURE_MSI) {
1941	pci_disable_msi(pdev);
1942	tp->features &= ~RTL_FEATURE_MSI;
1943	}
1944	}
1945
1946	static const struct net_device_ops rtl8169_netdev_ops = {
1947	.ndo_open = rtl8169_open,
1948	.ndo_stop = rtl8169_close,
1949	.ndo_get_stats = rtl8169_get_stats,
1950	.ndo_start_xmit = rtl8169_start_xmit,
1951	.ndo_tx_timeout = rtl8169_tx_timeout,
1952	.ndo_validate_addr = eth_validate_addr,
1953	.ndo_change_mtu = rtl8169_change_mtu,
1954	.ndo_set_mac_address = rtl_set_mac_address,
1955	.ndo_do_ioctl = rtl8169_ioctl,
1956	.ndo_set_multicast_list = rtl_set_rx_mode,
1957	#ifdef CONFIG_R8169_VLAN
1958	.ndo_vlan_rx_register = rtl8169_vlan_rx_register,
1959	#endif
1960	#ifdef CONFIG_NET_POLL_CONTROLLER
1961	.ndo_poll_controller = rtl8169_netpoll,
1962	#endif
1963
1964	};
1965
1966	static int __devinit
1967	rtl8169_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1968	{
1969	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1970	const unsigned int region = cfg->region;
1971	struct rtl8169_private *tp;
1972	struct mii_if_info *mii;
1973	struct net_device *dev;
1974	void __iomem *ioaddr;
1975	unsigned int i;
1976	int rc;
1977
1978	if (netif_msg_drv(&debug)) {
1979	printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1980	MODULENAME, RTL8169_VERSION);
1981	}
1982
1983	dev = alloc_etherdev(sizeof (*tp));
1984	if (!dev) {
1985	if (netif_msg_drv(&debug))
1986	dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1987	rc = -ENOMEM;
1988	goto out;
1989	}
1990
1991	SET_NETDEV_DEV(dev, &pdev->dev);
1992	dev->netdev_ops = &rtl8169_netdev_ops;
1993	tp = netdev_priv(dev);
1994	tp->dev = dev;
1995	tp->pci_dev = pdev;
1996	tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1997
1998	mii = &tp->mii;
1999	mii->dev = dev;
2000	mii->mdio_read = rtl_mdio_read;
2001	mii->mdio_write = rtl_mdio_write;
2002	mii->phy_id_mask = 0x1f;
2003	mii->reg_num_mask = 0x1f;
2004	mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2005
2006	/* enable device (incl. PCI PM wakeup and hotplug setup) */
2007	rc = pci_enable_device(pdev);
2008	if (rc < 0) {
2009	if (netif_msg_probe(tp))
2010	dev_err(&pdev->dev, "enable failure\n");
2011	goto err_out_free_dev_1;
2012	}
2013
2014	rc = pci_set_mwi(pdev);
2015	if (rc < 0)
2016	goto err_out_disable_2;
2017
2018	/* make sure PCI base addr 1 is MMIO */
2019	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2020	if (netif_msg_probe(tp)) {
2021	dev_err(&pdev->dev,
2022	"region #%d not an MMIO resource, aborting\n",
2023	region);
2024	}
2025	rc = -ENODEV;
2026	goto err_out_mwi_3;
2027	}
2028
2029	/* check for weird/broken PCI region reporting */
2030	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2031	if (netif_msg_probe(tp)) {
2032	dev_err(&pdev->dev,
2033	"Invalid PCI region size(s), aborting\n");
2034	}
2035	rc = -ENODEV;
2036	goto err_out_mwi_3;
2037	}
2038
2039	rc = pci_request_regions(pdev, MODULENAME);
2040	if (rc < 0) {
2041	if (netif_msg_probe(tp))
2042	dev_err(&pdev->dev, "could not request regions.\n");
2043	goto err_out_mwi_3;
2044	}
2045
2046	tp->cp_cmd = PCIMulRW \| RxChkSum;
2047
2048	if ((sizeof(dma_addr_t) > 4) &&
2049	!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2050	tp->cp_cmd \|= PCIDAC;
2051	dev->features \|= NETIF_F_HIGHDMA;
2052	} else {
2053	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2054	if (rc < 0) {
2055	if (netif_msg_probe(tp)) {
2056	dev_err(&pdev->dev,
2057	"DMA configuration failed.\n");
2058	}
2059	goto err_out_free_res_4;
2060	}
2061	}
2062
2063	/* ioremap MMIO region */
2064	ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2065	if (!ioaddr) {
2066	if (netif_msg_probe(tp))
2067	dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2068	rc = -EIO;
2069	goto err_out_free_res_4;
2070	}
2071
2072	tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2073	if (!tp->pcie_cap && netif_msg_probe(tp))
2074	dev_info(&pdev->dev, "no PCI Express capability\n");
2075
2076	RTL_W16(IntrMask, 0x0000);
2077
2078	/* Soft reset the chip. */
2079	RTL_W8(ChipCmd, CmdReset);
2080
2081	/* Check that the chip has finished the reset. */
2082	for (i = 0; i < 100; i++) {
2083	if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2084	break;
2085	msleep_interruptible(1);
2086	}
2087
2088	RTL_W16(IntrStatus, 0xffff);
2089
2090	pci_set_master(pdev);
2091
2092	/* Identify chip attached to board */
2093	rtl8169_get_mac_version(tp, ioaddr);
2094
2095	/* Use appropriate default if unknown */
2096	if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2097	if (netif_msg_probe(tp)) {
2098	dev_notice(&pdev->dev,
2099	"unknown MAC, using family default\n");
2100	}
2101	tp->mac_version = cfg->default_ver;
2102	}
2103
2104	rtl8169_print_mac_version(tp);
2105
2106	for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2107	if (tp->mac_version == rtl_chip_info[i].mac_version)
2108	break;
2109	}
2110	if (i == ARRAY_SIZE(rtl_chip_info)) {
2111	dev_err(&pdev->dev,
2112	"driver bug, MAC version not found in rtl_chip_info\n");
2113	goto err_out_msi_5;
2114	}
2115	tp->chipset = i;
2116
2117	RTL_W8(Cfg9346, Cfg9346_Unlock);
2118	RTL_W8(Config1, RTL_R8(Config1) \| PMEnable);
2119	RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2120	if ((RTL_R8(Config3) & (LinkUp \| MagicPacket)) != 0)
2121	tp->features \|= RTL_FEATURE_WOL;
2122	if ((RTL_R8(Config5) & (UWF \| BWF \| MWF)) != 0)
2123	tp->features \|= RTL_FEATURE_WOL;
2124	tp->features \|= rtl_try_msi(pdev, ioaddr, cfg);
2125	RTL_W8(Cfg9346, Cfg9346_Lock);
2126
2127	if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2128	(RTL_R8(PHYstatus) & TBI_Enable)) {
2129	tp->set_speed = rtl8169_set_speed_tbi;
2130	tp->get_settings = rtl8169_gset_tbi;
2131	tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2132	tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2133	tp->link_ok = rtl8169_tbi_link_ok;
2134	tp->do_ioctl = rtl_tbi_ioctl;
2135
2136	tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2137	} else {
2138	tp->set_speed = rtl8169_set_speed_xmii;
2139	tp->get_settings = rtl8169_gset_xmii;
2140	tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2141	tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2142	tp->link_ok = rtl8169_xmii_link_ok;
2143	tp->do_ioctl = rtl_xmii_ioctl;
2144	}
2145
2146	spin_lock_init(&tp->lock);
2147
2148	tp->mmio_addr = ioaddr;
2149
2150	/* Get MAC address */
2151	for (i = 0; i < MAC_ADDR_LEN; i++)
2152	dev->dev_addr[i] = RTL_R8(MAC0 + i);
2153	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2154
2155	SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2156	dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2157	dev->irq = pdev->irq;
2158	dev->base_addr = (unsigned long) ioaddr;
2159
2160	netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2161
2162	#ifdef CONFIG_R8169_VLAN
2163	dev->features \|= NETIF_F_HW_VLAN_TX \| NETIF_F_HW_VLAN_RX;
2164	#endif
2165
2166	tp->intr_mask = 0xffff;
2167	tp->align = cfg->align;
2168	tp->hw_start = cfg->hw_start;
2169	tp->intr_event = cfg->intr_event;
2170	tp->napi_event = cfg->napi_event;
2171
2172	init_timer(&tp->timer);
2173	tp->timer.data = (unsigned long) dev;
2174	tp->timer.function = rtl8169_phy_timer;
2175
2176	rc = register_netdev(dev);
2177	if (rc < 0)
2178	goto err_out_msi_5;
2179
2180	pci_set_drvdata(pdev, dev);
2181
2182	if (netif_msg_probe(tp)) {
2183	u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2184
2185	printk(KERN_INFO "%s: %s at 0x%lx, "
2186	"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2187	"XID %08x IRQ %d\n",
2188	dev->name,
2189	rtl_chip_info[tp->chipset].name,
2190	dev->base_addr,
2191	dev->dev_addr[0], dev->dev_addr[1],
2192	dev->dev_addr[2], dev->dev_addr[3],
2193	dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2194	}
2195
2196	rtl8169_init_phy(dev, tp);
2197	device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2198
2199	out:
2200	return rc;
2201
2202	err_out_msi_5:
2203	rtl_disable_msi(pdev, tp);
2204	iounmap(ioaddr);
2205	err_out_free_res_4:
2206	pci_release_regions(pdev);
2207	err_out_mwi_3:
2208	pci_clear_mwi(pdev);
2209	err_out_disable_2:
2210	pci_disable_device(pdev);
2211	err_out_free_dev_1:
2212	free_netdev(dev);
2213	goto out;
2214	}
2215
2216	static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2217	{
2218	struct net_device *dev = pci_get_drvdata(pdev);
2219	struct rtl8169_private *tp = netdev_priv(dev);
2220
2221	flush_scheduled_work();
2222
2223	unregister_netdev(dev);
2224	rtl_disable_msi(pdev, tp);
2225	rtl8169_release_board(pdev, dev, tp->mmio_addr);
2226	pci_set_drvdata(pdev, NULL);
2227	}
2228
2229	static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2230	struct net_device *dev)
2231	{
2232	unsigned int mtu = dev->mtu;
2233
2234	tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2235	}
2236
2237	static int rtl8169_open(struct net_device *dev)
2238	{
2239	struct rtl8169_private *tp = netdev_priv(dev);
2240	struct pci_dev *pdev = tp->pci_dev;
2241	int retval = -ENOMEM;
2242
2243
2244	rtl8169_set_rxbufsize(tp, dev);
2245
2246	/*
2247	* Rx and Tx desscriptors needs 256 bytes alignment.
2248	* pci_alloc_consistent provides more.
2249	*/
2250	tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2251	&tp->TxPhyAddr);
2252	if (!tp->TxDescArray)
2253	goto out;
2254
2255	tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2256	&tp->RxPhyAddr);
2257	if (!tp->RxDescArray)
2258	goto err_free_tx_0;
2259
2260	retval = rtl8169_init_ring(dev);
2261	if (retval < 0)
2262	goto err_free_rx_1;
2263
2264	INIT_DELAYED_WORK(&tp->task, NULL);
2265
2266	smp_mb();
2267
2268	retval = request_irq(dev->irq, rtl8169_interrupt,
2269	(tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2270	dev->name, dev);
2271	if (retval < 0)
2272	goto err_release_ring_2;
2273
2274	napi_enable(&tp->napi);
2275
2276	rtl_hw_start(dev);
2277
2278	rtl8169_request_timer(dev);
2279
2280	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2281	out:
2282	return retval;
2283
2284	err_release_ring_2:
2285	rtl8169_rx_clear(tp);
2286	err_free_rx_1:
2287	pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2288	tp->RxPhyAddr);
2289	err_free_tx_0:
2290	pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2291	tp->TxPhyAddr);
2292	goto out;
2293	}
2294
2295	static void rtl8169_hw_reset(void __iomem *ioaddr)
2296	{
2297	/* Disable interrupts */
2298	rtl8169_irq_mask_and_ack(ioaddr);
2299
2300	/* Reset the chipset */
2301	RTL_W8(ChipCmd, CmdReset);
2302
2303	/* PCI commit */
2304	RTL_R8(ChipCmd);
2305	}
2306
2307	static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2308	{
2309	void __iomem *ioaddr = tp->mmio_addr;
2310	u32 cfg = rtl8169_rx_config;
2311
2312	cfg \|= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2313	RTL_W32(RxConfig, cfg);
2314
2315	/* Set DMA burst size and Interframe Gap Time */
2316	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) \|
2317	(InterFrameGap << TxInterFrameGapShift));
2318	}
2319
2320	static void rtl_hw_start(struct net_device *dev)
2321	{
2322	struct rtl8169_private *tp = netdev_priv(dev);
2323	void __iomem *ioaddr = tp->mmio_addr;
2324	unsigned int i;
2325
2326	/* Soft reset the chip. */
2327	RTL_W8(ChipCmd, CmdReset);
2328
2329	/* Check that the chip has finished the reset. */
2330	for (i = 0; i < 100; i++) {
2331	if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2332	break;
2333	msleep_interruptible(1);
2334	}
2335
2336	tp->hw_start(dev);
2337
2338	netif_start_queue(dev);
2339	}
2340
2341
2342	static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2343	void __iomem *ioaddr)
2344	{
2345	/*
2346	* Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2347	* register to be written before TxDescAddrLow to work.
2348	* Switching from MMIO to I/O access fixes the issue as well.
2349	*/
2350	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2351	RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2352	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2353	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2354	}
2355
2356	static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2357	{
2358	u16 cmd;
2359
2360	cmd = RTL_R16(CPlusCmd);
2361	RTL_W16(CPlusCmd, cmd);
2362	return cmd;
2363	}
2364
2365	static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
2366	{
2367	/* Low hurts. Let's disable the filtering. */
2368	RTL_W16(RxMaxSize, rx_buf_sz);
2369	}
2370
2371	static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2372	{
2373	struct {
2374	u32 mac_version;
2375	u32 clk;
2376	u32 val;
2377	} cfg2_info [] = {
2378	{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2379	{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2380	{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2381	{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2382	}, *p = cfg2_info;
2383	unsigned int i;
2384	u32 clk;
2385
2386	clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2387	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2388	if ((p->mac_version == mac_version) && (p->clk == clk)) {
2389	RTL_W32(0x7c, p->val);
2390	break;
2391	}
2392	}
2393	}
2394
2395	static void rtl_hw_start_8169(struct net_device *dev)
2396	{
2397	struct rtl8169_private *tp = netdev_priv(dev);
2398	void __iomem *ioaddr = tp->mmio_addr;
2399	struct pci_dev *pdev = tp->pci_dev;
2400
2401	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2402	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) \| PCIMulRW);
2403	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2404	}
2405
2406	RTL_W8(Cfg9346, Cfg9346_Unlock);
2407	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) \|\|
2408	(tp->mac_version == RTL_GIGA_MAC_VER_02) \|\|
2409	(tp->mac_version == RTL_GIGA_MAC_VER_03) \|\|
2410	(tp->mac_version == RTL_GIGA_MAC_VER_04))
2411	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);
2412
2413	RTL_W8(EarlyTxThres, EarlyTxThld);
2414
2415	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2416
2417	if ((tp->mac_version == RTL_GIGA_MAC_VER_01) \|\|
2418	(tp->mac_version == RTL_GIGA_MAC_VER_02) \|\|
2419	(tp->mac_version == RTL_GIGA_MAC_VER_03) \|\|
2420	(tp->mac_version == RTL_GIGA_MAC_VER_04))
2421	rtl_set_rx_tx_config_registers(tp);
2422
2423	tp->cp_cmd \|= rtl_rw_cpluscmd(ioaddr) \| PCIMulRW;
2424
2425	if ((tp->mac_version == RTL_GIGA_MAC_VER_02) \|\|
2426	(tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2427	dprintk("Set MAC Reg C+CR Offset 0xE0. "
2428	"Bit-3 and bit-14 MUST be 1\n");
2429	tp->cp_cmd \|= (1 << 14);
2430	}
2431
2432	RTL_W16(CPlusCmd, tp->cp_cmd);
2433
2434	rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2435
2436	/*
2437	* Undocumented corner. Supposedly:
2438	* (TxTimer << 12) \| (TxPackets << 8) \| (RxTimer << 4) \| RxPackets
2439	*/
2440	RTL_W16(IntrMitigate, 0x0000);
2441
2442	rtl_set_rx_tx_desc_registers(tp, ioaddr);
2443
2444	if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2445	(tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2446	(tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2447	(tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2448	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);
2449	rtl_set_rx_tx_config_registers(tp);
2450	}
2451
2452	RTL_W8(Cfg9346, Cfg9346_Lock);
2453
2454	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2455	RTL_R8(IntrMask);
2456
2457	RTL_W32(RxMissed, 0);
2458
2459	rtl_set_rx_mode(dev);
2460
2461	/* no early-rx interrupts */
2462	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2463
2464	/* Enable all known interrupts by setting the interrupt mask. */
2465	RTL_W16(IntrMask, tp->intr_event);
2466	}
2467
2468	static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2469	{
2470	struct net_device *dev = pci_get_drvdata(pdev);
2471	struct rtl8169_private *tp = netdev_priv(dev);
2472	int cap = tp->pcie_cap;
2473
2474	if (cap) {
2475	u16 ctl;
2476
2477	pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2478	ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) \| force;
2479	pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2480	}
2481	}
2482
2483	static void rtl_csi_access_enable(void __iomem *ioaddr)
2484	{
2485	u32 csi;
2486
2487	csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2488	rtl_csi_write(ioaddr, 0x070c, csi \| 0x27000000);
2489	}
2490
2491	struct ephy_info {
2492	unsigned int offset;
2493	u16 mask;
2494	u16 bits;
2495	};
2496
2497	static void rtl_ephy_init(void __iomem ioaddr, struct ephy_info e, int len)
2498	{
2499	u16 w;
2500
2501	while (len-- > 0) {
2502	w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) \| e->bits;
2503	rtl_ephy_write(ioaddr, e->offset, w);
2504	e++;
2505	}
2506	}
2507
2508	static void rtl_disable_clock_request(struct pci_dev *pdev)
2509	{
2510	struct net_device *dev = pci_get_drvdata(pdev);
2511	struct rtl8169_private *tp = netdev_priv(dev);
2512	int cap = tp->pcie_cap;
2513
2514	if (cap) {
2515	u16 ctl;
2516
2517	pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2518	ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2519	pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2520	}
2521	}
2522
2523	#define R8168_CPCMD_QUIRK_MASK (\
2524	EnableBist \| \
2525	Mac_dbgo_oe \| \
2526	Force_half_dup \| \
2527	Force_rxflow_en \| \
2528	Force_txflow_en \| \
2529	Cxpl_dbg_sel \| \
2530	ASF \| \
2531	PktCntrDisable \| \
2532	Mac_dbgo_sel)
2533
2534	static void rtl_hw_start_8168bb(void __iomem ioaddr, struct pci_dev pdev)
2535	{
2536	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2537
2538	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2539
2540	rtl_tx_performance_tweak(pdev,
2541	(0x5 << MAX_READ_REQUEST_SHIFT) \| PCI_EXP_DEVCTL_NOSNOOP_EN);
2542	}
2543
2544	static void rtl_hw_start_8168bef(void __iomem ioaddr, struct pci_dev pdev)
2545	{
2546	rtl_hw_start_8168bb(ioaddr, pdev);
2547
2548	RTL_W8(EarlyTxThres, EarlyTxThld);
2549
2550	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2551	}
2552
2553	static void __rtl_hw_start_8168cp(void __iomem ioaddr, struct pci_dev pdev)
2554	{
2555	RTL_W8(Config1, RTL_R8(Config1) \| Speed_down);
2556
2557	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2558
2559	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2560
2561	rtl_disable_clock_request(pdev);
2562
2563	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2564	}
2565
2566	static void rtl_hw_start_8168cp_1(void __iomem ioaddr, struct pci_dev pdev)
2567	{
2568	static struct ephy_info e_info_8168cp[] = {
2569	{ 0x01, 0, 0x0001 },
2570	{ 0x02, 0x0800, 0x1000 },
2571	{ 0x03, 0, 0x0042 },
2572	{ 0x06, 0x0080, 0x0000 },
2573	{ 0x07, 0, 0x2000 }
2574	};
2575
2576	rtl_csi_access_enable(ioaddr);
2577
2578	rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2579
2580	__rtl_hw_start_8168cp(ioaddr, pdev);
2581	}
2582
2583	static void rtl_hw_start_8168cp_2(void __iomem ioaddr, struct pci_dev pdev)
2584	{
2585	rtl_csi_access_enable(ioaddr);
2586
2587	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2588
2589	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2590
2591	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2592	}
2593
2594	static void rtl_hw_start_8168cp_3(void __iomem ioaddr, struct pci_dev pdev)
2595	{
2596	rtl_csi_access_enable(ioaddr);
2597
2598	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2599
2600	/* Magic. */
2601	RTL_W8(DBG_REG, 0x20);
2602
2603	RTL_W8(EarlyTxThres, EarlyTxThld);
2604
2605	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2606
2607	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2608	}
2609
2610	static void rtl_hw_start_8168c_1(void __iomem ioaddr, struct pci_dev pdev)
2611	{
2612	static struct ephy_info e_info_8168c_1[] = {
2613	{ 0x02, 0x0800, 0x1000 },
2614	{ 0x03, 0, 0x0002 },
2615	{ 0x06, 0x0080, 0x0000 }
2616	};
2617
2618	rtl_csi_access_enable(ioaddr);
2619
2620	RTL_W8(DBG_REG, 0x06 \| FIX_NAK_1 \| FIX_NAK_2);
2621
2622	rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2623
2624	__rtl_hw_start_8168cp(ioaddr, pdev);
2625	}
2626
2627	static void rtl_hw_start_8168c_2(void __iomem ioaddr, struct pci_dev pdev)
2628	{
2629	static struct ephy_info e_info_8168c_2[] = {
2630	{ 0x01, 0, 0x0001 },
2631	{ 0x03, 0x0400, 0x0220 }
2632	};
2633
2634	rtl_csi_access_enable(ioaddr);
2635
2636	rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2637
2638	__rtl_hw_start_8168cp(ioaddr, pdev);
2639	}
2640
2641	static void rtl_hw_start_8168c_3(void __iomem ioaddr, struct pci_dev pdev)
2642	{
2643	rtl_hw_start_8168c_2(ioaddr, pdev);
2644	}
2645
2646	static void rtl_hw_start_8168c_4(void __iomem ioaddr, struct pci_dev pdev)
2647	{
2648	rtl_csi_access_enable(ioaddr);
2649
2650	__rtl_hw_start_8168cp(ioaddr, pdev);
2651	}
2652
2653	static void rtl_hw_start_8168d(void __iomem ioaddr, struct pci_dev pdev)
2654	{
2655	rtl_csi_access_enable(ioaddr);
2656
2657	rtl_disable_clock_request(pdev);
2658
2659	RTL_W8(EarlyTxThres, EarlyTxThld);
2660
2661	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2662
2663	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2664	}
2665
2666	static void rtl_hw_start_8168(struct net_device *dev)
2667	{
2668	struct rtl8169_private *tp = netdev_priv(dev);
2669	void __iomem *ioaddr = tp->mmio_addr;
2670	struct pci_dev *pdev = tp->pci_dev;
2671
2672	RTL_W8(Cfg9346, Cfg9346_Unlock);
2673
2674	RTL_W8(EarlyTxThres, EarlyTxThld);
2675
2676	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2677
2678	tp->cp_cmd \|= RTL_R16(CPlusCmd) \| PktCntrDisable \| INTT_1;
2679
2680	RTL_W16(CPlusCmd, tp->cp_cmd);
2681
2682	RTL_W16(IntrMitigate, 0x5151);
2683
2684	/* Work around for RxFIFO overflow. */
2685	if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2686	tp->intr_event \|= RxFIFOOver \| PCSTimeout;
2687	tp->intr_event &= ~RxOverflow;
2688	}
2689
2690	rtl_set_rx_tx_desc_registers(tp, ioaddr);
2691
2692	rtl_set_rx_mode(dev);
2693
2694	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) \|
2695	(InterFrameGap << TxInterFrameGapShift));
2696
2697	RTL_R8(IntrMask);
2698
2699	switch (tp->mac_version) {
2700	case RTL_GIGA_MAC_VER_11:
2701	rtl_hw_start_8168bb(ioaddr, pdev);
2702	break;
2703
2704	case RTL_GIGA_MAC_VER_12:
2705	case RTL_GIGA_MAC_VER_17:
2706	rtl_hw_start_8168bef(ioaddr, pdev);
2707	break;
2708
2709	case RTL_GIGA_MAC_VER_18:
2710	rtl_hw_start_8168cp_1(ioaddr, pdev);
2711	break;
2712
2713	case RTL_GIGA_MAC_VER_19:
2714	rtl_hw_start_8168c_1(ioaddr, pdev);
2715	break;
2716
2717	case RTL_GIGA_MAC_VER_20:
2718	rtl_hw_start_8168c_2(ioaddr, pdev);
2719	break;
2720
2721	case RTL_GIGA_MAC_VER_21:
2722	rtl_hw_start_8168c_3(ioaddr, pdev);
2723	break;
2724
2725	case RTL_GIGA_MAC_VER_22:
2726	rtl_hw_start_8168c_4(ioaddr, pdev);
2727	break;
2728
2729	case RTL_GIGA_MAC_VER_23:
2730	rtl_hw_start_8168cp_2(ioaddr, pdev);
2731	break;
2732
2733	case RTL_GIGA_MAC_VER_24:
2734	rtl_hw_start_8168cp_3(ioaddr, pdev);
2735	break;
2736
2737	case RTL_GIGA_MAC_VER_25:
2738	rtl_hw_start_8168d(ioaddr, pdev);
2739	break;
2740
2741	default:
2742	printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2743	dev->name, tp->mac_version);
2744	break;
2745	}
2746
2747	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);
2748
2749	RTL_W8(Cfg9346, Cfg9346_Lock);
2750
2751	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2752
2753	RTL_W16(IntrMask, tp->intr_event);
2754	}
2755
2756	#define R810X_CPCMD_QUIRK_MASK (\
2757	EnableBist \| \
2758	Mac_dbgo_oe \| \
2759	Force_half_dup \| \
2760	Force_half_dup \| \
2761	Force_txflow_en \| \
2762	Cxpl_dbg_sel \| \
2763	ASF \| \
2764	PktCntrDisable \| \
2765	PCIDAC \| \
2766	PCIMulRW)
2767
2768	static void rtl_hw_start_8102e_1(void __iomem ioaddr, struct pci_dev pdev)
2769	{
2770	static struct ephy_info e_info_8102e_1[] = {
2771	{ 0x01, 0, 0x6e65 },
2772	{ 0x02, 0, 0x091f },
2773	{ 0x03, 0, 0xc2f9 },
2774	{ 0x06, 0, 0xafb5 },
2775	{ 0x07, 0, 0x0e00 },
2776	{ 0x19, 0, 0xec80 },
2777	{ 0x01, 0, 0x2e65 },
2778	{ 0x01, 0, 0x6e65 }
2779	};
2780	u8 cfg1;
2781
2782	rtl_csi_access_enable(ioaddr);
2783
2784	RTL_W8(DBG_REG, FIX_NAK_1);
2785
2786	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2787
2788	RTL_W8(Config1,
2789	LEDS1 \| LEDS0 \| Speed_down \| MEMMAP \| IOMAP \| VPD \| PMEnable);
2790	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2791
2792	cfg1 = RTL_R8(Config1);
2793	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2794	RTL_W8(Config1, cfg1 & ~LEDS0);
2795
2796	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2797
2798	rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2799	}
2800
2801	static void rtl_hw_start_8102e_2(void __iomem ioaddr, struct pci_dev pdev)
2802	{
2803	rtl_csi_access_enable(ioaddr);
2804
2805	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2806
2807	RTL_W8(Config1, MEMMAP \| IOMAP \| VPD \| PMEnable);
2808	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2809
2810	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2811	}
2812
2813	static void rtl_hw_start_8102e_3(void __iomem ioaddr, struct pci_dev pdev)
2814	{
2815	rtl_hw_start_8102e_2(ioaddr, pdev);
2816
2817	rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2818	}
2819
2820	static void rtl_hw_start_8101(struct net_device *dev)
2821	{
2822	struct rtl8169_private *tp = netdev_priv(dev);
2823	void __iomem *ioaddr = tp->mmio_addr;
2824	struct pci_dev *pdev = tp->pci_dev;
2825
2826	if ((tp->mac_version == RTL_GIGA_MAC_VER_13) \|\|
2827	(tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2828	int cap = tp->pcie_cap;
2829
2830	if (cap) {
2831	pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2832	PCI_EXP_DEVCTL_NOSNOOP_EN);
2833	}
2834	}
2835
2836	switch (tp->mac_version) {
2837	case RTL_GIGA_MAC_VER_07:
2838	rtl_hw_start_8102e_1(ioaddr, pdev);
2839	break;
2840
2841	case RTL_GIGA_MAC_VER_08:
2842	rtl_hw_start_8102e_3(ioaddr, pdev);
2843	break;
2844
2845	case RTL_GIGA_MAC_VER_09:
2846	rtl_hw_start_8102e_2(ioaddr, pdev);
2847	break;
2848	}
2849
2850	RTL_W8(Cfg9346, Cfg9346_Unlock);
2851
2852	RTL_W8(EarlyTxThres, EarlyTxThld);
2853
2854	rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2855
2856	tp->cp_cmd \|= rtl_rw_cpluscmd(ioaddr) \| PCIMulRW;
2857
2858	RTL_W16(CPlusCmd, tp->cp_cmd);
2859
2860	RTL_W16(IntrMitigate, 0x0000);
2861
2862	rtl_set_rx_tx_desc_registers(tp, ioaddr);
2863
2864	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);
2865	rtl_set_rx_tx_config_registers(tp);
2866
2867	RTL_W8(Cfg9346, Cfg9346_Lock);
2868
2869	RTL_R8(IntrMask);
2870
2871	rtl_set_rx_mode(dev);
2872
2873	RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);
2874
2875	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2876
2877	RTL_W16(IntrMask, tp->intr_event);
2878	}
2879
2880	static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2881	{
2882	struct rtl8169_private *tp = netdev_priv(dev);
2883	int ret = 0;
2884
2885	if (new_mtu < ETH_ZLEN \|\| new_mtu > SafeMtu)
2886	return -EINVAL;
2887
2888	dev->mtu = new_mtu;
2889
2890	if (!netif_running(dev))
2891	goto out;
2892
2893	rtl8169_down(dev);
2894
2895	rtl8169_set_rxbufsize(tp, dev);
2896
2897	ret = rtl8169_init_ring(dev);
2898	if (ret < 0)
2899	goto out;
2900
2901	napi_enable(&tp->napi);
2902
2903	rtl_hw_start(dev);
2904
2905	rtl8169_request_timer(dev);
2906
2907	out:
2908	return ret;
2909	}
2910
2911	static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2912	{
2913	desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2914	desc->opts1 &= ~cpu_to_le32(DescOwn \| RsvdMask);
2915	}
2916
2917	static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2918	struct sk_buff *sk_buff, struct RxDesc desc)
2919	{
2920	struct pci_dev *pdev = tp->pci_dev;
2921
2922	pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2923	PCI_DMA_FROMDEVICE);
2924	dev_kfree_skb(*sk_buff);
2925	*sk_buff = NULL;
2926	rtl8169_make_unusable_by_asic(desc);
2927	}
2928
2929	static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2930	{
2931	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2932
2933	desc->opts1 = cpu_to_le32(DescOwn \| eor \| rx_buf_sz);
2934	}
2935
2936	static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2937	u32 rx_buf_sz)
2938	{
2939	desc->addr = cpu_to_le64(mapping);
2940	wmb();
2941	rtl8169_mark_to_asic(desc, rx_buf_sz);
2942	}
2943
2944	static struct sk_buff rtl8169_alloc_rx_skb(struct pci_dev pdev,
2945	struct net_device *dev,
2946	struct RxDesc *desc, int rx_buf_sz,
2947	unsigned int align)
2948	{
2949	struct sk_buff *skb;
2950	dma_addr_t mapping;
2951	unsigned int pad;
2952
2953	pad = align ? align : NET_IP_ALIGN;
2954
2955	skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2956	if (!skb)
2957	goto err_out;
2958
2959	skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2960
2961	mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2962	PCI_DMA_FROMDEVICE);
2963
2964	rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2965	out:
2966	return skb;
2967
2968	err_out:
2969	rtl8169_make_unusable_by_asic(desc);
2970	goto out;
2971	}
2972
2973	static void rtl8169_rx_clear(struct rtl8169_private *tp)
2974	{
2975	unsigned int i;
2976
2977	for (i = 0; i < NUM_RX_DESC; i++) {
2978	if (tp->Rx_skbuff[i]) {
2979	rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2980	tp->RxDescArray + i);
2981	}
2982	}
2983	}
2984
2985	static u32 rtl8169_rx_fill(struct rtl8169_private tp, struct net_device dev,
2986	u32 start, u32 end)
2987	{
2988	u32 cur;
2989
2990	for (cur = start; end - cur != 0; cur++) {
2991	struct sk_buff *skb;
2992	unsigned int i = cur % NUM_RX_DESC;
2993
2994	WARN_ON((s32)(end - cur) < 0);
2995
2996	if (tp->Rx_skbuff[i])
2997	continue;
2998
2999	skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3000	tp->RxDescArray + i,
3001	tp->rx_buf_sz, tp->align);
3002	if (!skb)
3003	break;
3004
3005	tp->Rx_skbuff[i] = skb;
3006	}
3007	return cur - start;
3008	}
3009
3010	static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3011	{
3012	desc->opts1 \|= cpu_to_le32(RingEnd);
3013	}
3014
3015	static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3016	{
3017	tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3018	}
3019
3020	static int rtl8169_init_ring(struct net_device *dev)
3021	{
3022	struct rtl8169_private *tp = netdev_priv(dev);
3023
3024	rtl8169_init_ring_indexes(tp);
3025
3026	memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3027	memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3028
3029	if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3030	goto err_out;
3031
3032	rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3033
3034	return 0;
3035
3036	err_out:
3037	rtl8169_rx_clear(tp);
3038	return -ENOMEM;
3039	}
3040
3041	static void rtl8169_unmap_tx_skb(struct pci_dev pdev, struct ring_info tx_skb,
3042	struct TxDesc *desc)
3043	{
3044	unsigned int len = tx_skb->len;
3045
3046	pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3047	desc->opts1 = 0x00;
3048	desc->opts2 = 0x00;
3049	desc->addr = 0x00;
3050	tx_skb->len = 0;
3051	}
3052
3053	static void rtl8169_tx_clear(struct rtl8169_private *tp)
3054	{
3055	unsigned int i;
3056
3057	for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3058	unsigned int entry = i % NUM_TX_DESC;
3059	struct ring_info *tx_skb = tp->tx_skb + entry;
3060	unsigned int len = tx_skb->len;
3061
3062	if (len) {
3063	struct sk_buff *skb = tx_skb->skb;
3064
3065	rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3066	tp->TxDescArray + entry);
3067	if (skb) {
3068	dev_kfree_skb(skb);
3069	tx_skb->skb = NULL;
3070	}
3071	tp->dev->stats.tx_dropped++;
3072	}
3073	}
3074	tp->cur_tx = tp->dirty_tx = 0;
3075	}
3076
3077	static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3078	{
3079	struct rtl8169_private *tp = netdev_priv(dev);
3080
3081	PREPARE_DELAYED_WORK(&tp->task, task);
3082	schedule_delayed_work(&tp->task, 4);
3083	}
3084
3085	static void rtl8169_wait_for_quiescence(struct net_device *dev)
3086	{
3087	struct rtl8169_private *tp = netdev_priv(dev);
3088	void __iomem *ioaddr = tp->mmio_addr;
3089
3090	synchronize_irq(dev->irq);
3091
3092	/* Wait for any pending NAPI task to complete */
3093	napi_disable(&tp->napi);
3094
3095	rtl8169_irq_mask_and_ack(ioaddr);
3096
3097	tp->intr_mask = 0xffff;
3098	RTL_W16(IntrMask, tp->intr_event);
3099	napi_enable(&tp->napi);
3100	}
3101
3102	static void rtl8169_reinit_task(struct work_struct *work)
3103	{
3104	struct rtl8169_private *tp =
3105	container_of(work, struct rtl8169_private, task.work);
3106	struct net_device *dev = tp->dev;
3107	int ret;
3108
3109	rtnl_lock();
3110
3111	if (!netif_running(dev))
3112	goto out_unlock;
3113
3114	rtl8169_wait_for_quiescence(dev);
3115	rtl8169_close(dev);
3116
3117	ret = rtl8169_open(dev);
3118	if (unlikely(ret < 0)) {
3119	if (net_ratelimit() && netif_msg_drv(tp)) {
3120	printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3121	" Rescheduling.\n", dev->name, ret);
3122	}
3123	rtl8169_schedule_work(dev, rtl8169_reinit_task);
3124	}
3125
3126	out_unlock:
3127	rtnl_unlock();
3128	}
3129
3130	static void rtl8169_reset_task(struct work_struct *work)
3131	{
3132	struct rtl8169_private *tp =
3133	container_of(work, struct rtl8169_private, task.work);
3134	struct net_device *dev = tp->dev;
3135
3136	rtnl_lock();
3137
3138	if (!netif_running(dev))
3139	goto out_unlock;
3140
3141	rtl8169_wait_for_quiescence(dev);
3142
3143	rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3144	rtl8169_tx_clear(tp);
3145
3146	if (tp->dirty_rx == tp->cur_rx) {
3147	rtl8169_init_ring_indexes(tp);
3148	rtl_hw_start(dev);
3149	netif_wake_queue(dev);
3150	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3151	} else {
3152	if (net_ratelimit() && netif_msg_intr(tp)) {
3153	printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3154	dev->name);
3155	}
3156	rtl8169_schedule_work(dev, rtl8169_reset_task);
3157	}
3158
3159	out_unlock:
3160	rtnl_unlock();
3161	}
3162
3163	static void rtl8169_tx_timeout(struct net_device *dev)
3164	{
3165	struct rtl8169_private *tp = netdev_priv(dev);
3166
3167	rtl8169_hw_reset(tp->mmio_addr);
3168
3169	/* Let's wait a bit while any (async) irq lands on */
3170	rtl8169_schedule_work(dev, rtl8169_reset_task);
3171	}
3172
3173	static int rtl8169_xmit_frags(struct rtl8169_private tp, struct sk_buff skb,
3174	u32 opts1)
3175	{
3176	struct skb_shared_info *info = skb_shinfo(skb);
3177	unsigned int cur_frag, entry;
3178	struct TxDesc * uninitialized_var(txd);
3179
3180	entry = tp->cur_tx;
3181	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3182	skb_frag_t *frag = info->frags + cur_frag;
3183	dma_addr_t mapping;
3184	u32 status, len;
3185	void *addr;
3186
3187	entry = (entry + 1) % NUM_TX_DESC;
3188
3189	txd = tp->TxDescArray + entry;
3190	len = frag->size;
3191	addr = ((void *) page_address(frag->page)) + frag->page_offset;
3192	mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3193
3194	/* anti gcc 2.95.3 bugware (sic) */
3195	status = opts1 \| len \| (RingEnd * !((entry + 1) % NUM_TX_DESC));
3196
3197	txd->opts1 = cpu_to_le32(status);
3198	txd->addr = cpu_to_le64(mapping);
3199
3200	tp->tx_skb[entry].len = len;
3201	}
3202
3203	if (cur_frag) {
3204	tp->tx_skb[entry].skb = skb;
3205	txd->opts1 \|= cpu_to_le32(LastFrag);
3206	}
3207
3208	return cur_frag;
3209	}
3210
3211	static inline u32 rtl8169_tso_csum(struct sk_buff skb, struct net_device dev)
3212	{
3213	if (dev->features & NETIF_F_TSO) {
3214	u32 mss = skb_shinfo(skb)->gso_size;
3215
3216	if (mss)
3217	return LargeSend \| ((mss & MSSMask) << MSSShift);
3218	}
3219	if (skb->ip_summed == CHECKSUM_PARTIAL) {
3220	const struct iphdr *ip = ip_hdr(skb);
3221
3222	if (ip->protocol == IPPROTO_TCP)
3223	return IPCS \| TCPCS;
3224	else if (ip->protocol == IPPROTO_UDP)
3225	return IPCS \| UDPCS;
3226	WARN_ON(1); /* we need a WARN() */
3227	}
3228	return 0;
3229	}
3230
3231	static int rtl8169_start_xmit(struct sk_buff skb, struct net_device dev)
3232	{
3233	struct rtl8169_private *tp = netdev_priv(dev);
3234	unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3235	struct TxDesc *txd = tp->TxDescArray + entry;
3236	void __iomem *ioaddr = tp->mmio_addr;
3237	dma_addr_t mapping;
3238	u32 status, len;
3239	u32 opts1;
3240	int ret = NETDEV_TX_OK;
3241
3242	if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3243	if (netif_msg_drv(tp)) {
3244	printk(KERN_ERR
3245	"%s: BUG! Tx Ring full when queue awake!\n",
3246	dev->name);
3247	}
3248	goto err_stop;
3249	}
3250
3251	if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3252	goto err_stop;
3253
3254	opts1 = DescOwn \| rtl8169_tso_csum(skb, dev);
3255
3256	frags = rtl8169_xmit_frags(tp, skb, opts1);
3257	if (frags) {
3258	len = skb_headlen(skb);
3259	opts1 \|= FirstFrag;
3260	} else {
3261	len = skb->len;
3262	opts1 \|= FirstFrag \| LastFrag;
3263	tp->tx_skb[entry].skb = skb;
3264	}
3265
3266	mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3267
3268	tp->tx_skb[entry].len = len;
3269	txd->addr = cpu_to_le64(mapping);
3270	txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3271
3272	wmb();
3273
3274	/* anti gcc 2.95.3 bugware (sic) */
3275	status = opts1 \| len \| (RingEnd * !((entry + 1) % NUM_TX_DESC));
3276	txd->opts1 = cpu_to_le32(status);
3277
3278	tp->cur_tx += frags + 1;
3279
3280	smp_wmb();
3281
3282	RTL_W8(TxPoll, NPQ); /* set polling bit */
3283
3284	if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3285	netif_stop_queue(dev);
3286	smp_rmb();
3287	if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3288	netif_wake_queue(dev);
3289	}
3290
3291	out:
3292	return ret;
3293
3294	err_stop:
3295	netif_stop_queue(dev);
3296	ret = NETDEV_TX_BUSY;
3297	dev->stats.tx_dropped++;
3298	goto out;
3299	}
3300
3301	static void rtl8169_pcierr_interrupt(struct net_device *dev)
3302	{
3303	struct rtl8169_private *tp = netdev_priv(dev);
3304	struct pci_dev *pdev = tp->pci_dev;
3305	void __iomem *ioaddr = tp->mmio_addr;
3306	u16 pci_status, pci_cmd;
3307
3308	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3309	pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3310
3311	if (netif_msg_intr(tp)) {
3312	printk(KERN_ERR
3313	"%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3314	dev->name, pci_cmd, pci_status);
3315	}
3316
3317	/*
3318	* The recovery sequence below admits a very elaborated explanation:
3319	* - it seems to work;
3320	* - I did not see what else could be done;
3321	* - it makes iop3xx happy.
3322	*
3323	* Feel free to adjust to your needs.
3324	*/
3325	if (pdev->broken_parity_status)
3326	pci_cmd &= ~PCI_COMMAND_PARITY;
3327	else
3328	pci_cmd \|= PCI_COMMAND_SERR \| PCI_COMMAND_PARITY;
3329
3330	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3331
3332	pci_write_config_word(pdev, PCI_STATUS,
3333	pci_status & (PCI_STATUS_DETECTED_PARITY \|
3334	PCI_STATUS_SIG_SYSTEM_ERROR \| PCI_STATUS_REC_MASTER_ABORT \|
3335	PCI_STATUS_REC_TARGET_ABORT \| PCI_STATUS_SIG_TARGET_ABORT));
3336
3337	/* The infamous DAC fckup only happens at boot time /
3338	if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3339	if (netif_msg_intr(tp))
3340	printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3341	tp->cp_cmd &= ~PCIDAC;
3342	RTL_W16(CPlusCmd, tp->cp_cmd);
3343	dev->features &= ~NETIF_F_HIGHDMA;
3344	}
3345
3346	rtl8169_hw_reset(ioaddr);
3347
3348	rtl8169_schedule_work(dev, rtl8169_reinit_task);
3349	}
3350
3351	static void rtl8169_tx_interrupt(struct net_device *dev,
3352	struct rtl8169_private *tp,
3353	void __iomem *ioaddr)
3354	{
3355	unsigned int dirty_tx, tx_left;
3356
3357	dirty_tx = tp->dirty_tx;
3358	smp_rmb();
3359	tx_left = tp->cur_tx - dirty_tx;
3360
3361	while (tx_left > 0) {
3362	unsigned int entry = dirty_tx % NUM_TX_DESC;
3363	struct ring_info *tx_skb = tp->tx_skb + entry;
3364	u32 len = tx_skb->len;
3365	u32 status;
3366
3367	rmb();
3368	status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3369	if (status & DescOwn)
3370	break;
3371
3372	dev->stats.tx_bytes += len;
3373	dev->stats.tx_packets++;
3374
3375	rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3376
3377	if (status & LastFrag) {
3378	dev_kfree_skb(tx_skb->skb);
3379	tx_skb->skb = NULL;
3380	}
3381	dirty_tx++;
3382	tx_left--;
3383	}
3384
3385	if (tp->dirty_tx != dirty_tx) {
3386	tp->dirty_tx = dirty_tx;
3387	smp_wmb();
3388	if (netif_queue_stopped(dev) &&
3389	(TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3390	netif_wake_queue(dev);
3391	}
3392	/*
3393	* 8168 hack: TxPoll requests are lost when the Tx packets are
3394	* too close. Let's kick an extra TxPoll request when a burst
3395	* of start_xmit activity is detected (if it is not detected,
3396	* it is slow enough). -- FR
3397	*/
3398	smp_rmb();
3399	if (tp->cur_tx != dirty_tx)
3400	RTL_W8(TxPoll, NPQ);
3401	}
3402	}
3403
3404	static inline int rtl8169_fragmented_frame(u32 status)
3405	{
3406	return (status & (FirstFrag \| LastFrag)) != (FirstFrag \| LastFrag);
3407	}
3408
3409	static inline void rtl8169_rx_csum(struct sk_buff skb, struct RxDesc desc)
3410	{
3411	u32 opts1 = le32_to_cpu(desc->opts1);
3412	u32 status = opts1 & RxProtoMask;
3413
3414	if (((status == RxProtoTCP) && !(opts1 & TCPFail)) \|\|
3415	((status == RxProtoUDP) && !(opts1 & UDPFail)) \|\|
3416	((status == RxProtoIP) && !(opts1 & IPFail)))
3417	skb->ip_summed = CHECKSUM_UNNECESSARY;
3418	else
3419	skb->ip_summed = CHECKSUM_NONE;
3420	}
3421
3422	static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3423	struct rtl8169_private *tp, int pkt_size,
3424	dma_addr_t addr)
3425	{
3426	struct sk_buff *skb;
3427	bool done = false;
3428
3429	if (pkt_size >= rx_copybreak)
3430	goto out;
3431
3432	skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3433	if (!skb)
3434	goto out;
3435
3436	pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3437	PCI_DMA_FROMDEVICE);
3438	skb_reserve(skb, NET_IP_ALIGN);
3439	skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3440	*sk_buff = skb;
3441	done = true;
3442	out:
3443	return done;
3444	}
3445
3446	static int rtl8169_rx_interrupt(struct net_device *dev,
3447	struct rtl8169_private *tp,
3448	void __iomem *ioaddr, u32 budget)
3449	{
3450	unsigned int cur_rx, rx_left;
3451	unsigned int delta, count;
3452
3453	cur_rx = tp->cur_rx;
3454	rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3455	rx_left = min(rx_left, budget);
3456
3457	for (; rx_left > 0; rx_left--, cur_rx++) {
3458	unsigned int entry = cur_rx % NUM_RX_DESC;
3459	struct RxDesc *desc = tp->RxDescArray + entry;
3460	u32 status;
3461
3462	rmb();
3463	status = le32_to_cpu(desc->opts1);
3464
3465	if (status & DescOwn)
3466	break;
3467	if (unlikely(status & RxRES)) {
3468	if (netif_msg_rx_err(tp)) {
3469	printk(KERN_INFO
3470	"%s: Rx ERROR. status = %08x\n",
3471	dev->name, status);
3472	}
3473	dev->stats.rx_errors++;
3474	if (status & (RxRWT \| RxRUNT))
3475	dev->stats.rx_length_errors++;
3476	if (status & RxCRC)
3477	dev->stats.rx_crc_errors++;
3478	if (status & RxFOVF) {
3479	rtl8169_schedule_work(dev, rtl8169_reset_task);
3480	dev->stats.rx_fifo_errors++;
3481	}
3482	rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3483	} else {
3484	struct sk_buff *skb = tp->Rx_skbuff[entry];
3485	dma_addr_t addr = le64_to_cpu(desc->addr);
3486	int pkt_size = (status & 0x00001FFF) - 4;
3487	struct pci_dev *pdev = tp->pci_dev;
3488
3489	/*
3490	* The driver does not support incoming fragmented
3491	* frames. They are seen as a symptom of over-mtu
3492	* sized frames.
3493	*/
3494	if (unlikely(rtl8169_fragmented_frame(status))) {
3495	dev->stats.rx_dropped++;
3496	dev->stats.rx_length_errors++;
3497	rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3498	continue;
3499	}
3500
3501	rtl8169_rx_csum(skb, desc);
3502
3503	if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3504	pci_dma_sync_single_for_device(pdev, addr,
3505	pkt_size, PCI_DMA_FROMDEVICE);
3506	rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3507	} else {
3508	pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3509	PCI_DMA_FROMDEVICE);
3510	tp->Rx_skbuff[entry] = NULL;
3511	}
3512
3513	skb_put(skb, pkt_size);
3514	skb->protocol = eth_type_trans(skb, dev);
3515
3516	if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3517	netif_receive_skb(skb);
3518
3519	dev->stats.rx_bytes += pkt_size;
3520	dev->stats.rx_packets++;
3521	}
3522
3523	/* Work around for AMD plateform. */
3524	if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3525	(tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3526	desc->opts2 = 0;
3527	cur_rx++;
3528	}
3529	}
3530
3531	count = cur_rx - tp->cur_rx;
3532	tp->cur_rx = cur_rx;
3533
3534	delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3535	if (!delta && count && netif_msg_intr(tp))
3536	printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3537	tp->dirty_rx += delta;
3538
3539	/*
3540	* FIXME: until there is periodic timer to try and refill the ring,
3541	* a temporary shortage may definitely kill the Rx process.
3542	* - disable the asic to try and avoid an overflow and kick it again
3543	* after refill ?
3544	* - how do others driver handle this condition (Uh oh...).
3545	*/
3546	if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3547	printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3548
3549	return count;
3550	}
3551
3552	static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3553	{
3554	struct net_device *dev = dev_instance;
3555	struct rtl8169_private *tp = netdev_priv(dev);
3556	void __iomem *ioaddr = tp->mmio_addr;
3557	int handled = 0;
3558	int status;
3559
3560	/* loop handling interrupts until we have no new ones or
3561	* we hit a invalid/hotplug case.
3562	*/
3563	status = RTL_R16(IntrStatus);
3564	while (status && status != 0xffff) {
3565	handled = 1;
3566
3567	/* Handle all of the error cases first. These will reset
3568	* the chip, so just exit the loop.
3569	*/
3570	if (unlikely(!netif_running(dev))) {
3571	rtl8169_asic_down(ioaddr);
3572	break;
3573	}
3574
3575	/* Work around for rx fifo overflow */
3576	if (unlikely(status & RxFIFOOver) &&
3577	(tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3578	netif_stop_queue(dev);
3579	rtl8169_tx_timeout(dev);
3580	break;
3581	}
3582
3583	if (unlikely(status & SYSErr)) {
3584	rtl8169_pcierr_interrupt(dev);
3585	break;
3586	}
3587
3588	if (status & LinkChg)
3589	rtl8169_check_link_status(dev, tp, ioaddr);
3590
3591	/* We need to see the lastest version of tp->intr_mask to
3592	* avoid ignoring an MSI interrupt and having to wait for
3593	* another event which may never come.
3594	*/
3595	smp_rmb();
3596	if (status & tp->intr_mask & tp->napi_event) {
3597	RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3598	tp->intr_mask = ~tp->napi_event;
3599
3600	if (likely(napi_schedule_prep(&tp->napi)))
3601	__napi_schedule(&tp->napi);
3602	else if (netif_msg_intr(tp)) {
3603	printk(KERN_INFO "%s: interrupt %04x in poll\n",
3604	dev->name, status);
3605	}
3606	}
3607
3608	/* We only get a new MSI interrupt when all active irq
3609	* sources on the chip have been acknowledged. So, ack
3610	* everything we've seen and check if new sources have become
3611	* active to avoid blocking all interrupts from the chip.
3612	*/
3613	RTL_W16(IntrStatus,
3614	(status & RxFIFOOver) ? (status \| RxOverflow) : status);
3615	status = RTL_R16(IntrStatus);
3616	}
3617
3618	return IRQ_RETVAL(handled);
3619	}
3620
3621	static int rtl8169_poll(struct napi_struct *napi, int budget)
3622	{
3623	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3624	struct net_device *dev = tp->dev;
3625	void __iomem *ioaddr = tp->mmio_addr;
3626	int work_done;
3627
3628	work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3629	rtl8169_tx_interrupt(dev, tp, ioaddr);
3630
3631	if (work_done < budget) {
3632	napi_complete(napi);
3633
3634	/* We need for force the visibility of tp->intr_mask
3635	* for other CPUs, as we can loose an MSI interrupt
3636	* and potentially wait for a retransmit timeout if we don't.
3637	* The posted write to IntrMask is safe, as it will
3638	* eventually make it to the chip and we won't loose anything
3639	* until it does.
3640	*/
3641	tp->intr_mask = 0xffff;
3642	smp_wmb();
3643	RTL_W16(IntrMask, tp->intr_event);
3644	}
3645
3646	return work_done;
3647	}
3648
3649	static void rtl8169_rx_missed(struct net_device dev, void __iomem ioaddr)
3650	{
3651	struct rtl8169_private *tp = netdev_priv(dev);
3652
3653	if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3654	return;
3655
3656	dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3657	RTL_W32(RxMissed, 0);
3658	}
3659
3660	static void rtl8169_down(struct net_device *dev)
3661	{
3662	struct rtl8169_private *tp = netdev_priv(dev);
3663	void __iomem *ioaddr = tp->mmio_addr;
3664	unsigned int intrmask;
3665
3666	rtl8169_delete_timer(dev);
3667
3668	netif_stop_queue(dev);
3669
3670	napi_disable(&tp->napi);
3671
3672	core_down:
3673	spin_lock_irq(&tp->lock);
3674
3675	rtl8169_asic_down(ioaddr);
3676
3677	rtl8169_rx_missed(dev, ioaddr);
3678
3679	spin_unlock_irq(&tp->lock);
3680
3681	synchronize_irq(dev->irq);
3682
3683	/* Give a racing hard_start_xmit a few cycles to complete. */
3684	synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3685
3686	/*
3687	* And now for the 50k$ question: are IRQ disabled or not ?
3688	*
3689	* Two paths lead here:
3690	* 1) dev->close
3691	* -> netif_running() is available to sync the current code and the
3692	* IRQ handler. See rtl8169_interrupt for details.
3693	* 2) dev->change_mtu
3694	* -> rtl8169_poll can not be issued again and re-enable the
3695	* interruptions. Let's simply issue the IRQ down sequence again.
3696	*
3697	* No loop if hotpluged or major error (0xffff).
3698	*/
3699	intrmask = RTL_R16(IntrMask);
3700	if (intrmask && (intrmask != 0xffff))
3701	goto core_down;
3702
3703	rtl8169_tx_clear(tp);
3704
3705	rtl8169_rx_clear(tp);
3706	}
3707
3708	static int rtl8169_close(struct net_device *dev)
3709	{
3710	struct rtl8169_private *tp = netdev_priv(dev);
3711	struct pci_dev *pdev = tp->pci_dev;
3712
3713	/* update counters before going down */
3714	rtl8169_update_counters(dev);
3715
3716	rtl8169_down(dev);
3717
3718	free_irq(dev->irq, dev);
3719
3720	pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3721	tp->RxPhyAddr);
3722	pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3723	tp->TxPhyAddr);
3724	tp->TxDescArray = NULL;
3725	tp->RxDescArray = NULL;
3726
3727	return 0;
3728	}
3729
3730	static void rtl_set_rx_mode(struct net_device *dev)
3731	{
3732	struct rtl8169_private *tp = netdev_priv(dev);
3733	void __iomem *ioaddr = tp->mmio_addr;
3734	unsigned long flags;
3735	u32 mc_filter[2]; /* Multicast hash filter */
3736	int rx_mode;
3737	u32 tmp = 0;
3738
3739	if (dev->flags & IFF_PROMISC) {
3740	/* Unconditionally log net taps. */
3741	if (netif_msg_link(tp)) {
3742	printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3743	dev->name);
3744	}
3745	rx_mode =
3746	AcceptBroadcast \| AcceptMulticast \| AcceptMyPhys \|
3747	AcceptAllPhys;
3748	mc_filter[1] = mc_filter[0] = 0xffffffff;
3749	} else if ((dev->mc_count > multicast_filter_limit)
3750	\|\| (dev->flags & IFF_ALLMULTI)) {
3751	/* Too many to filter perfectly -- accept all multicasts. */
3752	rx_mode = AcceptBroadcast \| AcceptMulticast \| AcceptMyPhys;
3753	mc_filter[1] = mc_filter[0] = 0xffffffff;
3754	} else {
3755	struct dev_mc_list *mclist;
3756	unsigned int i;
3757
3758	rx_mode = AcceptBroadcast \| AcceptMyPhys;
3759	mc_filter[1] = mc_filter[0] = 0;
3760	for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3761	i++, mclist = mclist->next) {
3762	int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3763	mc_filter[bit_nr >> 5] \|= 1 << (bit_nr & 31);
3764	rx_mode \|= AcceptMulticast;
3765	}
3766	}
3767
3768	spin_lock_irqsave(&tp->lock, flags);
3769
3770	tmp = rtl8169_rx_config \| rx_mode \|
3771	(RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3772
3773	if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3774	u32 data = mc_filter[0];
3775
3776	mc_filter[0] = swab32(mc_filter[1]);
3777	mc_filter[1] = swab32(data);
3778	}
3779
3780	RTL_W32(MAR0 + 0, mc_filter[0]);
3781	RTL_W32(MAR0 + 4, mc_filter[1]);
3782
3783	RTL_W32(RxConfig, tmp);
3784
3785	spin_unlock_irqrestore(&tp->lock, flags);
3786	}
3787
3788	/**
3789	* rtl8169_get_stats - Get rtl8169 read/write statistics
3790	* @dev: The Ethernet Device to get statistics for
3791	*
3792	* Get TX/RX statistics for rtl8169
3793	*/
3794	static struct net_device_stats rtl8169_get_stats(struct net_device dev)
3795	{
3796	struct rtl8169_private *tp = netdev_priv(dev);
3797	void __iomem *ioaddr = tp->mmio_addr;
3798	unsigned long flags;
3799
3800	if (netif_running(dev)) {
3801	spin_lock_irqsave(&tp->lock, flags);
3802	rtl8169_rx_missed(dev, ioaddr);
3803	spin_unlock_irqrestore(&tp->lock, flags);
3804	}
3805
3806	return &dev->stats;
3807	}
3808
3809	static void rtl8169_net_suspend(struct net_device *dev)
3810	{
3811	if (!netif_running(dev))
3812	return;
3813
3814	netif_device_detach(dev);
3815	netif_stop_queue(dev);
3816	}
3817
3818	#ifdef CONFIG_PM
3819
3820	static int rtl8169_suspend(struct device *device)
3821	{
3822	struct pci_dev *pdev = to_pci_dev(device);
3823	struct net_device *dev = pci_get_drvdata(pdev);
3824
3825	rtl8169_net_suspend(dev);
3826
3827	return 0;
3828	}
3829
3830	static int rtl8169_resume(struct device *device)
3831	{
3832	struct pci_dev *pdev = to_pci_dev(device);
3833	struct net_device *dev = pci_get_drvdata(pdev);
3834
3835	if (!netif_running(dev))
3836	goto out;
3837
3838	netif_device_attach(dev);
3839
3840	rtl8169_schedule_work(dev, rtl8169_reset_task);
3841	out:
3842	return 0;
3843	}
3844
3845	static struct dev_pm_ops rtl8169_pm_ops = {
3846	.suspend = rtl8169_suspend,
3847	.resume = rtl8169_resume,
3848	.freeze = rtl8169_suspend,
3849	.thaw = rtl8169_resume,
3850	.poweroff = rtl8169_suspend,
3851	.restore = rtl8169_resume,
3852	};
3853
3854	#define RTL8169_PM_OPS (&rtl8169_pm_ops)
3855
3856	#else /* !CONFIG_PM */
3857
3858	#define RTL8169_PM_OPS NULL
3859
3860	#endif /* !CONFIG_PM */
3861
3862	static void rtl_shutdown(struct pci_dev *pdev)
3863	{
3864	struct net_device *dev = pci_get_drvdata(pdev);
3865	struct rtl8169_private *tp = netdev_priv(dev);
3866	void __iomem *ioaddr = tp->mmio_addr;
3867
3868	rtl8169_net_suspend(dev);
3869
3870	spin_lock_irq(&tp->lock);
3871
3872	rtl8169_asic_down(ioaddr);
3873
3874	spin_unlock_irq(&tp->lock);
3875
3876	if (system_state == SYSTEM_POWER_OFF) {
3877	/* WoL fails with some 8168 when the receiver is disabled. */
3878	if (tp->features & RTL_FEATURE_WOL) {
3879	pci_clear_master(pdev);
3880
3881	RTL_W8(ChipCmd, CmdRxEnb);
3882	/* PCI commit */
3883	RTL_R8(ChipCmd);
3884	}
3885
3886	pci_wake_from_d3(pdev, true);
3887	pci_set_power_state(pdev, PCI_D3hot);
3888	}
3889	}
3890
3891	static struct pci_driver rtl8169_pci_driver = {
3892	.name = MODULENAME,
3893	.id_table = rtl8169_pci_tbl,
3894	.probe = rtl8169_init_one,
3895	.remove = __devexit_p(rtl8169_remove_one),
3896	.shutdown = rtl_shutdown,
3897	.driver.pm = RTL8169_PM_OPS,
3898	};
3899
3900	static int __init rtl8169_init_module(void)
3901	{
3902	return pci_register_driver(&rtl8169_pci_driver);
3903	}
3904
3905	static void __exit rtl8169_cleanup_module(void)
3906	{
3907	pci_unregister_driver(&rtl8169_pci_driver);
3908	}
3909
3910	module_init(rtl8169_init_module);
3911	module_exit(rtl8169_cleanup_module);
3912

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