Root/drivers/net/s2io.h

1/************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
17#define s2BIT(loc) (0x8000000000000000ULL >> (loc))
18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#undef SUCCESS
22#define SUCCESS 0
23#define FAILURE -1
24#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
25#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
26#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
27#define S2IO_BIT_RESET 1
28#define S2IO_BIT_SET 2
29#define CHECKBIT(value, nbit) (value & (1 << nbit))
30
31/* Maximum time to flicker LED when asked to identify NIC using ethtool */
32#define MAX_FLICKER_TIME 60000 /* 60 Secs */
33
34/* Maximum outstanding splits to be configured into xena. */
35enum {
36    XENA_ONE_SPLIT_TRANSACTION = 0,
37    XENA_TWO_SPLIT_TRANSACTION = 1,
38    XENA_THREE_SPLIT_TRANSACTION = 2,
39    XENA_FOUR_SPLIT_TRANSACTION = 3,
40    XENA_EIGHT_SPLIT_TRANSACTION = 4,
41    XENA_TWELVE_SPLIT_TRANSACTION = 5,
42    XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
43    XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
44};
45#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
46
47/* OS concerned variables and constants */
48#define WATCH_DOG_TIMEOUT 15*HZ
49#define EFILL 0x1234
50#define ALIGN_SIZE 127
51#define PCIX_COMMAND_REGISTER 0x62
52
53/*
54 * Debug related variables.
55 */
56/* different debug levels. */
57#define ERR_DBG 0
58#define INIT_DBG 1
59#define INFO_DBG 2
60#define TX_DBG 3
61#define INTR_DBG 4
62
63/* Global variable that defines the present debug level of the driver. */
64static int debug_level = ERR_DBG;
65
66/* DEBUG message print. */
67#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
68
69/* Protocol assist features of the NIC */
70#define L3_CKSUM_OK 0xFFFF
71#define L4_CKSUM_OK 0xFFFF
72#define S2IO_JUMBO_SIZE 9600
73
74/* Driver statistics maintained by driver */
75struct swStat {
76    unsigned long long single_ecc_errs;
77    unsigned long long double_ecc_errs;
78    unsigned long long parity_err_cnt;
79    unsigned long long serious_err_cnt;
80    unsigned long long soft_reset_cnt;
81    unsigned long long fifo_full_cnt;
82    unsigned long long ring_full_cnt[8];
83    /* LRO statistics */
84    unsigned long long clubbed_frms_cnt;
85    unsigned long long sending_both;
86    unsigned long long outof_sequence_pkts;
87    unsigned long long flush_max_pkts;
88    unsigned long long sum_avg_pkts_aggregated;
89    unsigned long long num_aggregations;
90    /* Other statistics */
91    unsigned long long mem_alloc_fail_cnt;
92    unsigned long long pci_map_fail_cnt;
93    unsigned long long watchdog_timer_cnt;
94    unsigned long long mem_allocated;
95    unsigned long long mem_freed;
96    unsigned long long link_up_cnt;
97    unsigned long long link_down_cnt;
98    unsigned long long link_up_time;
99    unsigned long long link_down_time;
100
101    /* Transfer Code statistics */
102    unsigned long long tx_buf_abort_cnt;
103    unsigned long long tx_desc_abort_cnt;
104    unsigned long long tx_parity_err_cnt;
105    unsigned long long tx_link_loss_cnt;
106    unsigned long long tx_list_proc_err_cnt;
107
108    unsigned long long rx_parity_err_cnt;
109    unsigned long long rx_abort_cnt;
110    unsigned long long rx_parity_abort_cnt;
111    unsigned long long rx_rda_fail_cnt;
112    unsigned long long rx_unkn_prot_cnt;
113    unsigned long long rx_fcs_err_cnt;
114    unsigned long long rx_buf_size_err_cnt;
115    unsigned long long rx_rxd_corrupt_cnt;
116    unsigned long long rx_unkn_err_cnt;
117
118    /* Error/alarm statistics*/
119    unsigned long long tda_err_cnt;
120    unsigned long long pfc_err_cnt;
121    unsigned long long pcc_err_cnt;
122    unsigned long long tti_err_cnt;
123    unsigned long long lso_err_cnt;
124    unsigned long long tpa_err_cnt;
125    unsigned long long sm_err_cnt;
126    unsigned long long mac_tmac_err_cnt;
127    unsigned long long mac_rmac_err_cnt;
128    unsigned long long xgxs_txgxs_err_cnt;
129    unsigned long long xgxs_rxgxs_err_cnt;
130    unsigned long long rc_err_cnt;
131    unsigned long long prc_pcix_err_cnt;
132    unsigned long long rpa_err_cnt;
133    unsigned long long rda_err_cnt;
134    unsigned long long rti_err_cnt;
135    unsigned long long mc_err_cnt;
136
137};
138
139/* Xpak releated alarm and warnings */
140struct xpakStat {
141    u64 alarm_transceiver_temp_high;
142    u64 alarm_transceiver_temp_low;
143    u64 alarm_laser_bias_current_high;
144    u64 alarm_laser_bias_current_low;
145    u64 alarm_laser_output_power_high;
146    u64 alarm_laser_output_power_low;
147    u64 warn_transceiver_temp_high;
148    u64 warn_transceiver_temp_low;
149    u64 warn_laser_bias_current_high;
150    u64 warn_laser_bias_current_low;
151    u64 warn_laser_output_power_high;
152    u64 warn_laser_output_power_low;
153    u64 xpak_regs_stat;
154    u32 xpak_timer_count;
155};
156
157
158/* The statistics block of Xena */
159struct stat_block {
160/* Tx MAC statistics counters. */
161    __le32 tmac_data_octets;
162    __le32 tmac_frms;
163    __le64 tmac_drop_frms;
164    __le32 tmac_bcst_frms;
165    __le32 tmac_mcst_frms;
166    __le64 tmac_pause_ctrl_frms;
167    __le32 tmac_ucst_frms;
168    __le32 tmac_ttl_octets;
169    __le32 tmac_any_err_frms;
170    __le32 tmac_nucst_frms;
171    __le64 tmac_ttl_less_fb_octets;
172    __le64 tmac_vld_ip_octets;
173    __le32 tmac_drop_ip;
174    __le32 tmac_vld_ip;
175    __le32 tmac_rst_tcp;
176    __le32 tmac_icmp;
177    __le64 tmac_tcp;
178    __le32 reserved_0;
179    __le32 tmac_udp;
180
181/* Rx MAC Statistics counters. */
182    __le32 rmac_data_octets;
183    __le32 rmac_vld_frms;
184    __le64 rmac_fcs_err_frms;
185    __le64 rmac_drop_frms;
186    __le32 rmac_vld_bcst_frms;
187    __le32 rmac_vld_mcst_frms;
188    __le32 rmac_out_rng_len_err_frms;
189    __le32 rmac_in_rng_len_err_frms;
190    __le64 rmac_long_frms;
191    __le64 rmac_pause_ctrl_frms;
192    __le64 rmac_unsup_ctrl_frms;
193    __le32 rmac_accepted_ucst_frms;
194    __le32 rmac_ttl_octets;
195    __le32 rmac_discarded_frms;
196    __le32 rmac_accepted_nucst_frms;
197    __le32 reserved_1;
198    __le32 rmac_drop_events;
199    __le64 rmac_ttl_less_fb_octets;
200    __le64 rmac_ttl_frms;
201    __le64 reserved_2;
202    __le32 rmac_usized_frms;
203    __le32 reserved_3;
204    __le32 rmac_frag_frms;
205    __le32 rmac_osized_frms;
206    __le32 reserved_4;
207    __le32 rmac_jabber_frms;
208    __le64 rmac_ttl_64_frms;
209    __le64 rmac_ttl_65_127_frms;
210    __le64 reserved_5;
211    __le64 rmac_ttl_128_255_frms;
212    __le64 rmac_ttl_256_511_frms;
213    __le64 reserved_6;
214    __le64 rmac_ttl_512_1023_frms;
215    __le64 rmac_ttl_1024_1518_frms;
216    __le32 rmac_ip;
217    __le32 reserved_7;
218    __le64 rmac_ip_octets;
219    __le32 rmac_drop_ip;
220    __le32 rmac_hdr_err_ip;
221    __le32 reserved_8;
222    __le32 rmac_icmp;
223    __le64 rmac_tcp;
224    __le32 rmac_err_drp_udp;
225    __le32 rmac_udp;
226    __le64 rmac_xgmii_err_sym;
227    __le64 rmac_frms_q0;
228    __le64 rmac_frms_q1;
229    __le64 rmac_frms_q2;
230    __le64 rmac_frms_q3;
231    __le64 rmac_frms_q4;
232    __le64 rmac_frms_q5;
233    __le64 rmac_frms_q6;
234    __le64 rmac_frms_q7;
235    __le16 rmac_full_q3;
236    __le16 rmac_full_q2;
237    __le16 rmac_full_q1;
238    __le16 rmac_full_q0;
239    __le16 rmac_full_q7;
240    __le16 rmac_full_q6;
241    __le16 rmac_full_q5;
242    __le16 rmac_full_q4;
243    __le32 reserved_9;
244    __le32 rmac_pause_cnt;
245    __le64 rmac_xgmii_data_err_cnt;
246    __le64 rmac_xgmii_ctrl_err_cnt;
247    __le32 rmac_err_tcp;
248    __le32 rmac_accepted_ip;
249
250/* PCI/PCI-X Read transaction statistics. */
251    __le32 new_rd_req_cnt;
252    __le32 rd_req_cnt;
253    __le32 rd_rtry_cnt;
254    __le32 new_rd_req_rtry_cnt;
255
256/* PCI/PCI-X Write/Read transaction statistics. */
257    __le32 wr_req_cnt;
258    __le32 wr_rtry_rd_ack_cnt;
259    __le32 new_wr_req_rtry_cnt;
260    __le32 new_wr_req_cnt;
261    __le32 wr_disc_cnt;
262    __le32 wr_rtry_cnt;
263
264/* PCI/PCI-X Write / DMA Transaction statistics. */
265    __le32 txp_wr_cnt;
266    __le32 rd_rtry_wr_ack_cnt;
267    __le32 txd_wr_cnt;
268    __le32 txd_rd_cnt;
269    __le32 rxd_wr_cnt;
270    __le32 rxd_rd_cnt;
271    __le32 rxf_wr_cnt;
272    __le32 txf_rd_cnt;
273
274/* Tx MAC statistics overflow counters. */
275    __le32 tmac_data_octets_oflow;
276    __le32 tmac_frms_oflow;
277    __le32 tmac_bcst_frms_oflow;
278    __le32 tmac_mcst_frms_oflow;
279    __le32 tmac_ucst_frms_oflow;
280    __le32 tmac_ttl_octets_oflow;
281    __le32 tmac_any_err_frms_oflow;
282    __le32 tmac_nucst_frms_oflow;
283    __le64 tmac_vlan_frms;
284    __le32 tmac_drop_ip_oflow;
285    __le32 tmac_vld_ip_oflow;
286    __le32 tmac_rst_tcp_oflow;
287    __le32 tmac_icmp_oflow;
288    __le32 tpa_unknown_protocol;
289    __le32 tmac_udp_oflow;
290    __le32 reserved_10;
291    __le32 tpa_parse_failure;
292
293/* Rx MAC Statistics overflow counters. */
294    __le32 rmac_data_octets_oflow;
295    __le32 rmac_vld_frms_oflow;
296    __le32 rmac_vld_bcst_frms_oflow;
297    __le32 rmac_vld_mcst_frms_oflow;
298    __le32 rmac_accepted_ucst_frms_oflow;
299    __le32 rmac_ttl_octets_oflow;
300    __le32 rmac_discarded_frms_oflow;
301    __le32 rmac_accepted_nucst_frms_oflow;
302    __le32 rmac_usized_frms_oflow;
303    __le32 rmac_drop_events_oflow;
304    __le32 rmac_frag_frms_oflow;
305    __le32 rmac_osized_frms_oflow;
306    __le32 rmac_ip_oflow;
307    __le32 rmac_jabber_frms_oflow;
308    __le32 rmac_icmp_oflow;
309    __le32 rmac_drop_ip_oflow;
310    __le32 rmac_err_drp_udp_oflow;
311    __le32 rmac_udp_oflow;
312    __le32 reserved_11;
313    __le32 rmac_pause_cnt_oflow;
314    __le64 rmac_ttl_1519_4095_frms;
315    __le64 rmac_ttl_4096_8191_frms;
316    __le64 rmac_ttl_8192_max_frms;
317    __le64 rmac_ttl_gt_max_frms;
318    __le64 rmac_osized_alt_frms;
319    __le64 rmac_jabber_alt_frms;
320    __le64 rmac_gt_max_alt_frms;
321    __le64 rmac_vlan_frms;
322    __le32 rmac_len_discard;
323    __le32 rmac_fcs_discard;
324    __le32 rmac_pf_discard;
325    __le32 rmac_da_discard;
326    __le32 rmac_red_discard;
327    __le32 rmac_rts_discard;
328    __le32 reserved_12;
329    __le32 rmac_ingm_full_discard;
330    __le32 reserved_13;
331    __le32 rmac_accepted_ip_oflow;
332    __le32 reserved_14;
333    __le32 link_fault_cnt;
334    u8 buffer[20];
335    struct swStat sw_stat;
336    struct xpakStat xpak_stat;
337};
338
339/* Default value for 'vlan_strip_tag' configuration parameter */
340#define NO_STRIP_IN_PROMISC 2
341
342/*
343 * Structures representing different init time configuration
344 * parameters of the NIC.
345 */
346
347#define MAX_TX_FIFOS 8
348#define MAX_RX_RINGS 8
349
350#define FIFO_DEFAULT_NUM 5
351#define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */
352#define FIFO_OTHER_MAX_NUM 1
353
354
355#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
356#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
357#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
358#define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
359
360/* FIFO mappings for all possible number of fifos configured */
361static int fifo_map[][MAX_TX_FIFOS] = {
362    {0, 0, 0, 0, 0, 0, 0, 0},
363    {0, 0, 0, 0, 1, 1, 1, 1},
364    {0, 0, 0, 1, 1, 1, 2, 2},
365    {0, 0, 1, 1, 2, 2, 3, 3},
366    {0, 0, 1, 1, 2, 2, 3, 4},
367    {0, 0, 1, 1, 2, 3, 4, 5},
368    {0, 0, 1, 2, 3, 4, 5, 6},
369    {0, 1, 2, 3, 4, 5, 6, 7},
370};
371
372static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
373
374/* Maintains Per FIFO related information. */
375struct tx_fifo_config {
376#define MAX_AVAILABLE_TXDS 8192
377    u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
378/* Priority definition */
379#define TX_FIFO_PRI_0 0 /*Highest */
380#define TX_FIFO_PRI_1 1
381#define TX_FIFO_PRI_2 2
382#define TX_FIFO_PRI_3 3
383#define TX_FIFO_PRI_4 4
384#define TX_FIFO_PRI_5 5
385#define TX_FIFO_PRI_6 6
386#define TX_FIFO_PRI_7 7 /*lowest */
387    u8 fifo_priority; /* specifies pointer level for FIFO */
388    /* user should not set twos fifos with same pri */
389    u8 f_no_snoop;
390#define NO_SNOOP_TXD 0x01
391#define NO_SNOOP_TXD_BUFFER 0x02
392};
393
394
395/* Maintains per Ring related information */
396struct rx_ring_config {
397    u32 num_rxd; /*No of RxDs per Rx Ring */
398#define RX_RING_PRI_0 0 /* highest */
399#define RX_RING_PRI_1 1
400#define RX_RING_PRI_2 2
401#define RX_RING_PRI_3 3
402#define RX_RING_PRI_4 4
403#define RX_RING_PRI_5 5
404#define RX_RING_PRI_6 6
405#define RX_RING_PRI_7 7 /* lowest */
406
407    u8 ring_priority; /*Specifies service priority of ring */
408    /* OSM should not set any two rings with same priority */
409    u8 ring_org; /*Organization of ring */
410#define RING_ORG_BUFF1 0x01
411#define RX_RING_ORG_BUFF3 0x03
412#define RX_RING_ORG_BUFF5 0x05
413
414    u8 f_no_snoop;
415#define NO_SNOOP_RXD 0x01
416#define NO_SNOOP_RXD_BUFFER 0x02
417};
418
419/* This structure provides contains values of the tunable parameters
420 * of the H/W
421 */
422struct config_param {
423/* Tx Side */
424    u32 tx_fifo_num; /*Number of Tx FIFOs */
425
426    /* 0-No steering, 1-Priority steering, 2-Default fifo map */
427#define NO_STEERING 0
428#define TX_PRIORITY_STEERING 0x1
429#define TX_DEFAULT_STEERING 0x2
430    u8 tx_steering_type;
431
432    u8 fifo_mapping[MAX_TX_FIFOS];
433    struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
434    u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
435    u64 tx_intr_type;
436#define INTA 0
437#define MSI_X 2
438    u8 intr_type;
439    u8 napi;
440
441    /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
442
443/* Rx Side */
444    u32 rx_ring_num; /*Number of receive rings */
445#define MAX_RX_BLOCKS_PER_RING 150
446
447    struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
448
449#define HEADER_ETHERNET_II_802_3_SIZE 14
450#define HEADER_802_2_SIZE 3
451#define HEADER_SNAP_SIZE 5
452#define HEADER_VLAN_SIZE 4
453
454#define MIN_MTU 46
455#define MAX_PYLD 1500
456#define MAX_MTU (MAX_PYLD+18)
457#define MAX_MTU_VLAN (MAX_PYLD+22)
458#define MAX_PYLD_JUMBO 9600
459#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
460#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
461    u16 bus_speed;
462    int max_mc_addr; /* xena=64 herc=256 */
463    int max_mac_addr; /* xena=16 herc=64 */
464    int mc_start_offset; /* xena=16 herc=64 */
465    u8 multiq;
466};
467
468/* Structure representing MAC Addrs */
469struct mac_addr {
470    u8 mac_addr[ETH_ALEN];
471};
472
473/* Structure that represent every FIFO element in the BAR1
474 * Address location.
475 */
476struct TxFIFO_element {
477    u64 TxDL_Pointer;
478
479    u64 List_Control;
480#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
481#define TX_FIFO_FIRST_LIST s2BIT(14)
482#define TX_FIFO_LAST_LIST s2BIT(15)
483#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
484#define TX_FIFO_SPECIAL_FUNC s2BIT(23)
485#define TX_FIFO_DS_NO_SNOOP s2BIT(31)
486#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
487};
488
489/* Tx descriptor structure */
490struct TxD {
491    u64 Control_1;
492/* bit mask */
493#define TXD_LIST_OWN_XENA s2BIT(7)
494#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
495#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
496#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
497#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
498#define TXD_GATHER_CODE_FIRST s2BIT(22)
499#define TXD_GATHER_CODE_LAST s2BIT(23)
500#define TXD_TCP_LSO_EN s2BIT(30)
501#define TXD_UDP_COF_EN s2BIT(31)
502#define TXD_UFO_EN s2BIT(31) | s2BIT(30)
503#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
504#define TXD_UFO_MSS(val) vBIT(val,34,14)
505#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
506
507    u64 Control_2;
508#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
509#define TXD_TX_CKO_IPV4_EN s2BIT(5)
510#define TXD_TX_CKO_TCP_EN s2BIT(6)
511#define TXD_TX_CKO_UDP_EN s2BIT(7)
512#define TXD_VLAN_ENABLE s2BIT(15)
513#define TXD_VLAN_TAG(val) vBIT(val,16,16)
514#define TXD_INT_NUMBER(val) vBIT(val,34,6)
515#define TXD_INT_TYPE_PER_LIST s2BIT(47)
516#define TXD_INT_TYPE_UTILZ s2BIT(46)
517#define TXD_SET_MARKER vBIT(0x6,0,4)
518
519    u64 Buffer_Pointer;
520    u64 Host_Control; /* reserved for host */
521};
522
523/* Structure to hold the phy and virt addr of every TxDL. */
524struct list_info_hold {
525    dma_addr_t list_phy_addr;
526    void *list_virt_addr;
527};
528
529/* Rx descriptor structure for 1 buffer mode */
530struct RxD_t {
531    u64 Host_Control; /* reserved for host */
532    u64 Control_1;
533#define RXD_OWN_XENA s2BIT(7)
534#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
535#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
536#define RXD_FRAME_VLAN_TAG s2BIT(24)
537#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
538#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
539#define RXD_FRAME_IP_FRAG s2BIT(29)
540#define RXD_FRAME_PROTO_TCP s2BIT(30)
541#define RXD_FRAME_PROTO_UDP s2BIT(31)
542#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
543#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
544#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
545
546    u64 Control_2;
547#define THE_RXD_MARK 0x3
548#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
549#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
550
551#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
552#define SET_VLAN_TAG(val) vBIT(val,48,16)
553#define SET_NUM_TAG(val) vBIT(val,16,32)
554
555
556};
557/* Rx descriptor structure for 1 buffer mode */
558struct RxD1 {
559    struct RxD_t h;
560
561#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
562#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
563#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
564    (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
565    u64 Buffer0_ptr;
566};
567/* Rx descriptor structure for 3 or 2 buffer mode */
568
569struct RxD3 {
570    struct RxD_t h;
571
572#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
573#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
574#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
575#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
576#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
577#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
578#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
579    (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
580#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
581    (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
582#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
583    (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
584#define BUF0_LEN 40
585#define BUF1_LEN 1
586
587    u64 Buffer0_ptr;
588    u64 Buffer1_ptr;
589    u64 Buffer2_ptr;
590};
591
592
593/* Structure that represents the Rx descriptor block which contains
594 * 128 Rx descriptors.
595 */
596struct RxD_block {
597#define MAX_RXDS_PER_BLOCK_1 127
598    struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
599
600    u64 reserved_0;
601#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
602    u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
603                 * Rxd in this blk */
604    u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
605    u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
606                     * the upper 32 bits should
607                     * be 0 */
608};
609
610#define SIZE_OF_BLOCK 4096
611
612#define RXD_MODE_1 0 /* One Buffer mode */
613#define RXD_MODE_3B 1 /* Two Buffer mode */
614
615/* Structure to hold virtual addresses of Buf0 and Buf1 in
616 * 2buf mode. */
617struct buffAdd {
618    void *ba_0_org;
619    void *ba_1_org;
620    void *ba_0;
621    void *ba_1;
622};
623
624/* Structure which stores all the MAC control parameters */
625
626/* This structure stores the offset of the RxD in the ring
627 * from which the Rx Interrupt processor can start picking
628 * up the RxDs for processing.
629 */
630struct rx_curr_get_info {
631    u32 block_index;
632    u32 offset;
633    u32 ring_len;
634};
635
636struct rx_curr_put_info {
637    u32 block_index;
638    u32 offset;
639    u32 ring_len;
640};
641
642/* This structure stores the offset of the TxDl in the FIFO
643 * from which the Tx Interrupt processor can start picking
644 * up the TxDLs for send complete interrupt processing.
645 */
646struct tx_curr_get_info {
647    u32 offset;
648    u32 fifo_len;
649};
650
651struct tx_curr_put_info {
652    u32 offset;
653    u32 fifo_len;
654};
655
656struct rxd_info {
657    void *virt_addr;
658    dma_addr_t dma_addr;
659};
660
661/* Structure that holds the Phy and virt addresses of the Blocks */
662struct rx_block_info {
663    void *block_virt_addr;
664    dma_addr_t block_dma_addr;
665    struct rxd_info *rxds;
666};
667
668/* Data structure to represent a LRO session */
669struct lro {
670    struct sk_buff *parent;
671    struct sk_buff *last_frag;
672    u8 *l2h;
673    struct iphdr *iph;
674    struct tcphdr *tcph;
675    u32 tcp_next_seq;
676    __be32 tcp_ack;
677    int total_len;
678    int frags_len;
679    int sg_num;
680    int in_use;
681    __be16 window;
682    u16 vlan_tag;
683    u32 cur_tsval;
684    __be32 cur_tsecr;
685    u8 saw_ts;
686} ____cacheline_aligned;
687
688/* Ring specific structure */
689struct ring_info {
690    /* The ring number */
691    int ring_no;
692
693    /* per-ring buffer counter */
694    u32 rx_bufs_left;
695
696#define MAX_LRO_SESSIONS 32
697    struct lro lro0_n[MAX_LRO_SESSIONS];
698    u8 lro;
699
700    /* copy of sp->rxd_mode flag */
701    int rxd_mode;
702
703    /* Number of rxds per block for the rxd_mode */
704    int rxd_count;
705
706    /* copy of sp pointer */
707    struct s2io_nic *nic;
708
709    /* copy of sp->dev pointer */
710    struct net_device *dev;
711
712    /* copy of sp->pdev pointer */
713    struct pci_dev *pdev;
714
715    /* Per ring napi struct */
716    struct napi_struct napi;
717
718    unsigned long interrupt_count;
719
720    /*
721     * Place holders for the virtual and physical addresses of
722     * all the Rx Blocks
723     */
724    struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
725    int block_count;
726    int pkt_cnt;
727
728    /*
729     * Put pointer info which indictes which RxD has to be replenished
730     * with a new buffer.
731     */
732    struct rx_curr_put_info rx_curr_put_info;
733
734    /*
735     * Get pointer info which indictes which is the last RxD that was
736     * processed by the driver.
737     */
738    struct rx_curr_get_info rx_curr_get_info;
739
740    /* interface MTU value */
741        unsigned mtu;
742
743    /* Buffer Address store. */
744    struct buffAdd **ba;
745
746    /* per-Ring statistics */
747    unsigned long rx_packets;
748    unsigned long rx_bytes;
749} ____cacheline_aligned;
750
751/* Fifo specific structure */
752struct fifo_info {
753    /* FIFO number */
754    int fifo_no;
755
756    /* Maximum TxDs per TxDL */
757    int max_txds;
758
759    /* Place holder of all the TX List's Phy and Virt addresses. */
760    struct list_info_hold *list_info;
761
762    /*
763     * Current offset within the tx FIFO where driver would write
764     * new Tx frame
765     */
766    struct tx_curr_put_info tx_curr_put_info;
767
768    /*
769     * Current offset within tx FIFO from where the driver would start freeing
770     * the buffers
771     */
772    struct tx_curr_get_info tx_curr_get_info;
773#define FIFO_QUEUE_START 0
774#define FIFO_QUEUE_STOP 1
775    int queue_state;
776
777    /* copy of sp->dev pointer */
778    struct net_device *dev;
779
780    /* copy of multiq status */
781    u8 multiq;
782
783    /* Per fifo lock */
784    spinlock_t tx_lock;
785
786    /* Per fifo UFO in band structure */
787    u64 *ufo_in_band_v;
788
789    struct s2io_nic *nic;
790} ____cacheline_aligned;
791
792/* Information related to the Tx and Rx FIFOs and Rings of Xena
793 * is maintained in this structure.
794 */
795struct mac_info {
796/* tx side stuff */
797    /* logical pointer of start of each Tx FIFO */
798    struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
799
800    /* Fifo specific structure */
801    struct fifo_info fifos[MAX_TX_FIFOS];
802
803    /* Save virtual address of TxD page with zero DMA addr(if any) */
804    void *zerodma_virt_addr;
805
806/* rx side stuff */
807    /* Ring specific structure */
808    struct ring_info rings[MAX_RX_RINGS];
809
810    u16 rmac_pause_time;
811    u16 mc_pause_threshold_q0q3;
812    u16 mc_pause_threshold_q4q7;
813
814    void *stats_mem; /* orignal pointer to allocated mem */
815    dma_addr_t stats_mem_phy; /* Physical address of the stat block */
816    u32 stats_mem_sz;
817    struct stat_block *stats_info; /* Logical address of the stat block */
818};
819
820/* structure representing the user defined MAC addresses */
821struct usr_addr {
822    char addr[ETH_ALEN];
823    int usage_cnt;
824};
825
826/* Default Tunable parameters of the NIC. */
827#define DEFAULT_FIFO_0_LEN 4096
828#define DEFAULT_FIFO_1_7_LEN 512
829#define SMALL_BLK_CNT 30
830#define LARGE_BLK_CNT 100
831
832/*
833 * Structure to keep track of the MSI-X vectors and the corresponding
834 * argument registered against each vector
835 */
836#define MAX_REQUESTED_MSI_X 9
837struct s2io_msix_entry
838{
839    u16 vector;
840    u16 entry;
841    void *arg;
842
843    u8 type;
844#define MSIX_ALARM_TYPE 1
845#define MSIX_RING_TYPE 2
846
847    u8 in_use;
848#define MSIX_REGISTERED_SUCCESS 0xAA
849};
850
851struct msix_info_st {
852    u64 addr;
853    u64 data;
854};
855
856/* These flags represent the devices temporary state */
857enum s2io_device_state_t
858{
859    __S2IO_STATE_LINK_TASK=0,
860    __S2IO_STATE_CARD_UP
861};
862
863/* Structure representing one instance of the NIC */
864struct s2io_nic {
865    int rxd_mode;
866    /*
867     * Count of packets to be processed in a given iteration, it will be indicated
868     * by the quota field of the device structure when NAPI is enabled.
869     */
870    int pkts_to_process;
871    struct net_device *dev;
872    struct mac_info mac_control;
873    struct config_param config;
874    struct pci_dev *pdev;
875    void __iomem *bar0;
876    void __iomem *bar1;
877#define MAX_MAC_SUPPORTED 16
878#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
879
880    struct mac_addr def_mac_addr[256];
881
882    struct net_device_stats stats;
883    int high_dma_flag;
884    int device_enabled_once;
885
886    char name[60];
887
888    /* Timer that handles I/O errors/exceptions */
889    struct timer_list alarm_timer;
890
891    /* Space to back up the PCI config space */
892    u32 config_space[256 / sizeof(u32)];
893
894#define PROMISC 1
895#define ALL_MULTI 2
896
897#define MAX_ADDRS_SUPPORTED 64
898    u16 usr_addr_count;
899    u16 mc_addr_count;
900    struct usr_addr usr_addrs[256];
901
902    u16 m_cast_flg;
903    u16 all_multi_pos;
904    u16 promisc_flg;
905
906    /* Id timer, used to blink NIC to physically identify NIC. */
907    struct timer_list id_timer;
908
909    /* Restart timer, used to restart NIC if the device is stuck and
910     * a schedule task that will set the correct Link state once the
911     * NIC's PHY has stabilized after a state change.
912     */
913    struct work_struct rst_timer_task;
914    struct work_struct set_link_task;
915
916    /* Flag that can be used to turn on or turn off the Rx checksum
917     * offload feature.
918     */
919    int rx_csum;
920
921    /* Below variables are used for fifo selection to transmit a packet */
922    u16 fifo_selector[MAX_TX_FIFOS];
923
924    /* Total fifos for tcp packets */
925    u8 total_tcp_fifos;
926
927    /*
928    * Beginning index of udp for udp packets
929    * Value will be equal to
930    * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
931    */
932    u8 udp_fifo_idx;
933
934    u8 total_udp_fifos;
935
936    /*
937     * Beginning index of fifo for all other packets
938     * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
939    */
940    u8 other_fifo_idx;
941
942    struct napi_struct napi;
943    /* after blink, the adapter must be restored with original
944     * values.
945     */
946    u64 adapt_ctrl_org;
947
948    /* Last known link state. */
949    u16 last_link_state;
950#define LINK_DOWN 1
951#define LINK_UP 2
952
953    int task_flag;
954    unsigned long long start_time;
955    struct vlan_group *vlgrp;
956    int vlan_strip_flag;
957#define MSIX_FLG 0xA5
958    int num_entries;
959    struct msix_entry *entries;
960    int msi_detected;
961    wait_queue_head_t msi_wait;
962    struct s2io_msix_entry *s2io_entries;
963    char desc[MAX_REQUESTED_MSI_X][25];
964
965    int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
966
967    struct msix_info_st msix_info[0x3f];
968
969#define XFRAME_I_DEVICE 1
970#define XFRAME_II_DEVICE 2
971    u8 device_type;
972
973    unsigned long clubbed_frms_cnt;
974    unsigned long sending_both;
975    u8 lro;
976    u16 lro_max_aggr_per_sess;
977    volatile unsigned long state;
978    u64 general_int_mask;
979
980#define VPD_STRING_LEN 80
981    u8 product_name[VPD_STRING_LEN];
982    u8 serial_num[VPD_STRING_LEN];
983};
984
985#define RESET_ERROR 1;
986#define CMD_ERROR 2;
987
988/* OS related system calls */
989#ifndef readq
990static inline u64 readq(void __iomem *addr)
991{
992    u64 ret = 0;
993    ret = readl(addr + 4);
994    ret <<= 32;
995    ret |= readl(addr);
996
997    return ret;
998}
999#endif
1000
1001#ifndef writeq
1002static inline void writeq(u64 val, void __iomem *addr)
1003{
1004    writel((u32) (val), addr);
1005    writel((u32) (val >> 32), (addr + 4));
1006}
1007#endif
1008
1009/*
1010 * Some registers have to be written in a particular order to
1011 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
1012 * is used to perform such ordered writes. Defines UF (Upper First)
1013 * and LF (Lower First) will be used to specify the required write order.
1014 */
1015#define UF 1
1016#define LF 2
1017static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
1018{
1019    u32 ret;
1020
1021    if (order == LF) {
1022        writel((u32) (val), addr);
1023        ret = readl(addr);
1024        writel((u32) (val >> 32), (addr + 4));
1025        ret = readl(addr + 4);
1026    } else {
1027        writel((u32) (val >> 32), (addr + 4));
1028        ret = readl(addr + 4);
1029        writel((u32) (val), addr);
1030        ret = readl(addr);
1031    }
1032}
1033
1034/* Interrupt related values of Xena */
1035
1036#define ENABLE_INTRS 1
1037#define DISABLE_INTRS 2
1038
1039/* Highest level interrupt blocks */
1040#define TX_PIC_INTR (0x0001<<0)
1041#define TX_DMA_INTR (0x0001<<1)
1042#define TX_MAC_INTR (0x0001<<2)
1043#define TX_XGXS_INTR (0x0001<<3)
1044#define TX_TRAFFIC_INTR (0x0001<<4)
1045#define RX_PIC_INTR (0x0001<<5)
1046#define RX_DMA_INTR (0x0001<<6)
1047#define RX_MAC_INTR (0x0001<<7)
1048#define RX_XGXS_INTR (0x0001<<8)
1049#define RX_TRAFFIC_INTR (0x0001<<9)
1050#define MC_INTR (0x0001<<10)
1051#define ENA_ALL_INTRS ( TX_PIC_INTR | \
1052                            TX_DMA_INTR | \
1053                            TX_MAC_INTR | \
1054                            TX_XGXS_INTR | \
1055                            TX_TRAFFIC_INTR | \
1056                            RX_PIC_INTR | \
1057                            RX_DMA_INTR | \
1058                            RX_MAC_INTR | \
1059                            RX_XGXS_INTR | \
1060                            RX_TRAFFIC_INTR | \
1061                            MC_INTR )
1062
1063/* Interrupt masks for the general interrupt mask register */
1064#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
1065
1066#define TXPIC_INT_M s2BIT(0)
1067#define TXDMA_INT_M s2BIT(1)
1068#define TXMAC_INT_M s2BIT(2)
1069#define TXXGXS_INT_M s2BIT(3)
1070#define TXTRAFFIC_INT_M s2BIT(8)
1071#define PIC_RX_INT_M s2BIT(32)
1072#define RXDMA_INT_M s2BIT(33)
1073#define RXMAC_INT_M s2BIT(34)
1074#define MC_INT_M s2BIT(35)
1075#define RXXGXS_INT_M s2BIT(36)
1076#define RXTRAFFIC_INT_M s2BIT(40)
1077
1078/* PIC level Interrupts TODO*/
1079
1080/* DMA level Inressupts */
1081#define TXDMA_PFC_INT_M s2BIT(0)
1082#define TXDMA_PCC_INT_M s2BIT(2)
1083
1084/* PFC block interrupts */
1085#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
1086
1087/* PCC block interrupts. */
1088#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
1089                           PCC_FB_ECC Error. */
1090
1091#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1092/*
1093 * Prototype declaration.
1094 */
1095static int __devinit s2io_init_nic(struct pci_dev *pdev,
1096                   const struct pci_device_id *pre);
1097static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1098static int init_shared_mem(struct s2io_nic *sp);
1099static void free_shared_mem(struct s2io_nic *sp);
1100static int init_nic(struct s2io_nic *nic);
1101static int rx_intr_handler(struct ring_info *ring_data, int budget);
1102static void s2io_txpic_intr_handle(struct s2io_nic *sp);
1103static void tx_intr_handler(struct fifo_info *fifo_data);
1104static void s2io_handle_errors(void * dev_id);
1105
1106static int s2io_starter(void);
1107static void s2io_closer(void);
1108static void s2io_tx_watchdog(struct net_device *dev);
1109static void s2io_set_multicast(struct net_device *dev);
1110static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1111static void s2io_link(struct s2io_nic * sp, int link);
1112static void s2io_reset(struct s2io_nic * sp);
1113static int s2io_poll_msix(struct napi_struct *napi, int budget);
1114static int s2io_poll_inta(struct napi_struct *napi, int budget);
1115static void s2io_init_pci(struct s2io_nic * sp);
1116static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
1117static void s2io_alarm_handle(unsigned long data);
1118static irqreturn_t
1119s2io_msix_ring_handle(int irq, void *dev_id);
1120static irqreturn_t
1121s2io_msix_fifo_handle(int irq, void *dev_id);
1122static irqreturn_t s2io_isr(int irq, void *dev_id);
1123static int verify_xena_quiescence(struct s2io_nic *sp);
1124static const struct ethtool_ops netdev_ethtool_ops;
1125static void s2io_set_link(struct work_struct *work);
1126static int s2io_set_swapper(struct s2io_nic * sp);
1127static void s2io_card_down(struct s2io_nic *nic);
1128static int s2io_card_up(struct s2io_nic *nic);
1129static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1130                    int bit_state);
1131static int s2io_add_isr(struct s2io_nic * sp);
1132static void s2io_rem_isr(struct s2io_nic * sp);
1133
1134static void restore_xmsi_data(struct s2io_nic *nic);
1135static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1136static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1137static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1138static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1139static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1140static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
1141
1142static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
1143    u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
1144    struct s2io_nic *sp);
1145static void clear_lro_session(struct lro *lro);
1146static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
1147static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1148static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1149               struct sk_buff *skb, u32 tcp_len);
1150static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1151
1152static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1153                                  pci_channel_state_t state);
1154static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1155static void s2io_io_resume(struct pci_dev *pdev);
1156
1157#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1158#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1159#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1160
1161#define S2IO_PARM_INT(X, def_val) \
1162    static unsigned int X = def_val;\
1163        module_param(X , uint, 0);
1164
1165#endif /* _S2IO_H */
1166

Archive Download this file

Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.2
jz-3.3
jz-3.4
jz47xx
jz47xx-2.6.38
master
xiangfu/openwrt/v3.0.0
xiangfu/openwrt/v3.2.1

Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7



interactive