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Root/drivers/net/sb1250-mac.c

1	/*
2	* Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
3	* Copyright (c) 2006, 2007 Maciej W. Rozycki
4	*
5	* This program is free software; you can redistribute it and/or
6	* modify it under the terms of the GNU General Public License
7	* as published by the Free Software Foundation; either version 2
8	* of the License, or (at your option) any later version.
9	*
10	* This program is distributed in the hope that it will be useful,
11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	* GNU General Public License for more details.
14	*
15	* You should have received a copy of the GNU General Public License
16	* along with this program; if not, write to the Free Software
17	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18	*
19	*
20	* This driver is designed for the Broadcom SiByte SOC built-in
21	* Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
22	*
23	* Updated to the driver model and the PHY abstraction layer
24	* by Maciej W. Rozycki.
25	*/
26
27	#include <linux/bug.h>
28	#include <linux/module.h>
29	#include <linux/kernel.h>
30	#include <linux/string.h>
31	#include <linux/timer.h>
32	#include <linux/errno.h>
33	#include <linux/ioport.h>
34	#include <linux/slab.h>
35	#include <linux/interrupt.h>
36	#include <linux/netdevice.h>
37	#include <linux/etherdevice.h>
38	#include <linux/skbuff.h>
39	#include <linux/init.h>
40	#include <linux/bitops.h>
41	#include <linux/err.h>
42	#include <linux/ethtool.h>
43	#include <linux/mii.h>
44	#include <linux/phy.h>
45	#include <linux/platform_device.h>
46
47	#include <asm/cache.h>
48	#include <asm/io.h>
49	#include <asm/processor.h> /* Processor type for cache alignment. */
50
51	/* This is only here until the firmware is ready. In that case,
52	the firmware leaves the ethernet address in the register for us. */
53	#ifdef CONFIG_SIBYTE_STANDALONE
54	#define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
55	#define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
56	#define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
57	#define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
58	#endif
59
60
61	/* These identify the driver base version and may not be removed. */
62	#if 0
63	static char version1[] __initdata =
64	"sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
65	#endif
66
67
68	/* Operational parameters that usually are not changed. */
69
70	#define CONFIG_SBMAC_COALESCE
71
72	/* Time in jiffies before concluding the transmitter is hung. */
73	#define TX_TIMEOUT (2*HZ)
74
75
76	MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
77	MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
78
79	/* A few user-configurable values which may be modified when a driver
80	module is loaded. */
81
82	/* 1 normal messages, 0 quiet .. 7 verbose. */
83	static int debug = 1;
84	module_param(debug, int, S_IRUGO);
85	MODULE_PARM_DESC(debug, "Debug messages");
86
87	#ifdef CONFIG_SBMAC_COALESCE
88	static int int_pktcnt_tx = 255;
89	module_param(int_pktcnt_tx, int, S_IRUGO);
90	MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
91
92	static int int_timeout_tx = 255;
93	module_param(int_timeout_tx, int, S_IRUGO);
94	MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
95
96	static int int_pktcnt_rx = 64;
97	module_param(int_pktcnt_rx, int, S_IRUGO);
98	MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
99
100	static int int_timeout_rx = 64;
101	module_param(int_timeout_rx, int, S_IRUGO);
102	MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
103	#endif
104
105	#include <asm/sibyte/board.h>
106	#include <asm/sibyte/sb1250.h>
107	#if defined(CONFIG_SIBYTE_BCM1x55) \|\| defined(CONFIG_SIBYTE_BCM1x80)
108	#include <asm/sibyte/bcm1480_regs.h>
109	#include <asm/sibyte/bcm1480_int.h>
110	#define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
111	#elif defined(CONFIG_SIBYTE_SB1250) \|\| defined(CONFIG_SIBYTE_BCM112X)
112	#include <asm/sibyte/sb1250_regs.h>
113	#include <asm/sibyte/sb1250_int.h>
114	#else
115	#error invalid SiByte MAC configuation
116	#endif
117	#include <asm/sibyte/sb1250_scd.h>
118	#include <asm/sibyte/sb1250_mac.h>
119	#include <asm/sibyte/sb1250_dma.h>
120
121	#if defined(CONFIG_SIBYTE_BCM1x55) \|\| defined(CONFIG_SIBYTE_BCM1x80)
122	#define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
123	#elif defined(CONFIG_SIBYTE_SB1250) \|\| defined(CONFIG_SIBYTE_BCM112X)
124	#define UNIT_INT(n) (K_INT_MAC_0 + (n))
125	#else
126	#error invalid SiByte MAC configuation
127	#endif
128
129	#ifdef K_INT_PHY
130	#define SBMAC_PHY_INT K_INT_PHY
131	#else
132	#define SBMAC_PHY_INT PHY_POLL
133	#endif
134
135	/**********************************************************************
136	* Simple types
137	********************************************************************* */
138
139	enum sbmac_speed {
140	sbmac_speed_none = 0,
141	sbmac_speed_10 = SPEED_10,
142	sbmac_speed_100 = SPEED_100,
143	sbmac_speed_1000 = SPEED_1000,
144	};
145
146	enum sbmac_duplex {
147	sbmac_duplex_none = -1,
148	sbmac_duplex_half = DUPLEX_HALF,
149	sbmac_duplex_full = DUPLEX_FULL,
150	};
151
152	enum sbmac_fc {
153	sbmac_fc_none,
154	sbmac_fc_disabled,
155	sbmac_fc_frame,
156	sbmac_fc_collision,
157	sbmac_fc_carrier,
158	};
159
160	enum sbmac_state {
161	sbmac_state_uninit,
162	sbmac_state_off,
163	sbmac_state_on,
164	sbmac_state_broken,
165	};
166
167
168	/**********************************************************************
169	* Macros
170	********************************************************************* */
171
172
173	#define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
174	(d)->sbdma_dscrtable : (d)->f+1)
175
176
177	#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
178
179	#define SBMAC_MAX_TXDESCR 256
180	#define SBMAC_MAX_RXDESCR 256
181
182	#define ETHER_ADDR_LEN 6
183	#define ENET_PACKET_SIZE 1518
184	/#define ENET_PACKET_SIZE 9216 /
185
186	/**********************************************************************
187	* DMA Descriptor structure
188	********************************************************************* */
189
190	struct sbdmadscr {
191	uint64_t dscr_a;
192	uint64_t dscr_b;
193	};
194
195	/**********************************************************************
196	* DMA Controller structure
197	********************************************************************* */
198
199	struct sbmacdma {
200
201	/*
202	* This stuff is used to identify the channel and the registers
203	* associated with it.
204	*/
205	struct sbmac_softc sbdma_eth; / back pointer to associated
206	MAC */
207	int sbdma_channel; /* channel number */
208	int sbdma_txdir; /* direction (1=transmit) */
209	int sbdma_maxdescr; /* total # of descriptors
210	in ring */
211	#ifdef CONFIG_SBMAC_COALESCE
212	int sbdma_int_pktcnt;
213	/* # descriptors rx/tx
214	before interrupt */
215	int sbdma_int_timeout;
216	/* # usec rx/tx interrupt */
217	#endif
218	void __iomem sbdma_config0; / DMA config register 0 */
219	void __iomem sbdma_config1; / DMA config register 1 */
220	void __iomem *sbdma_dscrbase;
221	/* descriptor base address */
222	void __iomem sbdma_dscrcnt; / descriptor count register */
223	void __iomem sbdma_curdscr; / current descriptor
224	address */
225	void __iomem *sbdma_oodpktlost;
226	/* pkt drop (rx only) */
227
228	/*
229	* This stuff is for maintenance of the ring
230	*/
231	void *sbdma_dscrtable_unaligned;
232	struct sbdmadscr *sbdma_dscrtable;
233	/* base of descriptor table */
234	struct sbdmadscr *sbdma_dscrtable_end;
235	/* end of descriptor table */
236	struct sk_buff **sbdma_ctxtable;
237	/* context table, one
238	per descr */
239	dma_addr_t sbdma_dscrtable_phys;
240	/* and also the phys addr */
241	struct sbdmadscr sbdma_addptr; / next dscr for sw to add */
242	struct sbdmadscr sbdma_remptr; / next dscr for sw
243	to remove */
244	};
245
246
247	/**********************************************************************
248	* Ethernet softc structure
249	********************************************************************* */
250
251	struct sbmac_softc {
252
253	/*
254	* Linux-specific things
255	*/
256	struct net_device sbm_dev; / pointer to linux device */
257	struct napi_struct napi;
258	struct phy_device phy_dev; / the associated PHY device */
259	struct mii_bus mii_bus; / the MII bus */
260	int phy_irq[PHY_MAX_ADDR];
261	spinlock_t sbm_lock; /* spin lock */
262	int sbm_devflags; /* current device flags */
263
264	/*
265	* Controller-specific things
266	*/
267	void __iomem sbm_base; / MAC's base address */
268	enum sbmac_state sbm_state; /* current state */
269
270	void __iomem sbm_macenable; / MAC Enable Register */
271	void __iomem sbm_maccfg; / MAC Config Register */
272	void __iomem sbm_fifocfg; / FIFO Config Register */
273	void __iomem sbm_framecfg; / Frame Config Register */
274	void __iomem sbm_rxfilter; / Receive Filter Register */
275	void __iomem sbm_isr; / Interrupt Status Register */
276	void __iomem sbm_imr; / Interrupt Mask Register */
277	void __iomem sbm_mdio; / MDIO Register */
278
279	enum sbmac_speed sbm_speed; /* current speed */
280	enum sbmac_duplex sbm_duplex; /* current duplex */
281	enum sbmac_fc sbm_fc; /* cur. flow control setting */
282	int sbm_pause; /* current pause setting */
283	int sbm_link; /* current link state */
284
285	unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
286
287	struct sbmacdma sbm_txdma; /* only channel 0 for now */
288	struct sbmacdma sbm_rxdma;
289	int rx_hw_checksum;
290	int sbe_idx;
291	};
292
293
294	/**********************************************************************
295	* Externs
296	********************************************************************* */
297
298	/**********************************************************************
299	* Prototypes
300	********************************************************************* */
301
302	static void sbdma_initctx(struct sbmacdma d, struct sbmac_softc s, int chan,
303	int txrx, int maxdescr);
304	static void sbdma_channel_start(struct sbmacdma *d, int rxtx);
305	static int sbdma_add_rcvbuffer(struct sbmac_softc sc, struct sbmacdma d,
306	struct sk_buff *m);
307	static int sbdma_add_txbuffer(struct sbmacdma d, struct sk_buff m);
308	static void sbdma_emptyring(struct sbmacdma *d);
309	static void sbdma_fillring(struct sbmac_softc sc, struct sbmacdma d);
310	static int sbdma_rx_process(struct sbmac_softc sc, struct sbmacdma d,
311	int work_to_do, int poll);
312	static void sbdma_tx_process(struct sbmac_softc sc, struct sbmacdma d,
313	int poll);
314	static int sbmac_initctx(struct sbmac_softc *s);
315	static void sbmac_channel_start(struct sbmac_softc *s);
316	static void sbmac_channel_stop(struct sbmac_softc *s);
317	static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
318	enum sbmac_state);
319	static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);
320	static uint64_t sbmac_addr2reg(unsigned char *ptr);
321	static irqreturn_t sbmac_intr(int irq, void *dev_instance);
322	static int sbmac_start_tx(struct sk_buff skb, struct net_device dev);
323	static void sbmac_setmulti(struct sbmac_softc *sc);
324	static int sbmac_init(struct platform_device *pldev, long long base);
325	static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
326	static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
327	enum sbmac_fc fc);
328
329	static int sbmac_open(struct net_device *dev);
330	static void sbmac_tx_timeout (struct net_device *dev);
331	static void sbmac_set_rx_mode(struct net_device *dev);
332	static int sbmac_mii_ioctl(struct net_device dev, struct ifreq rq, int cmd);
333	static int sbmac_close(struct net_device *dev);
334	static int sbmac_poll(struct napi_struct *napi, int budget);
335
336	static void sbmac_mii_poll(struct net_device *dev);
337	static int sbmac_mii_probe(struct net_device *dev);
338
339	static void sbmac_mii_sync(void __iomem *sbm_mdio);
340	static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
341	int bitcnt);
342	static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
343	static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
344	u16 val);
345
346
347	/**********************************************************************
348	* Globals
349	********************************************************************* */
350
351	static char sbmac_string[] = "sb1250-mac";
352	static char sbmac_pretty[] = "SB1250 MAC";
353
354	static char sbmac_mdio_string[] = "sb1250-mac-mdio";
355
356
357	/**********************************************************************
358	* MDIO constants
359	********************************************************************* */
360
361	#define MII_COMMAND_START 0x01
362	#define MII_COMMAND_READ 0x02
363	#define MII_COMMAND_WRITE 0x01
364	#define MII_COMMAND_ACK 0x02
365
366	#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
367
368	#define ENABLE 1
369	#define DISABLE 0
370
371	/**********************************************************************
372	* SBMAC_MII_SYNC(sbm_mdio)
373	*
374	* Synchronize with the MII - send a pattern of bits to the MII
375	* that will guarantee that it is ready to accept a command.
376	*
377	* Input parameters:
378	* sbm_mdio - address of the MAC's MDIO register
379	*
380	* Return value:
381	* nothing
382	********************************************************************* */
383
384	static void sbmac_mii_sync(void __iomem *sbm_mdio)
385	{
386	int cnt;
387	uint64_t bits;
388	int mac_mdio_genc;
389
390	mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
391
392	bits = M_MAC_MDIO_DIR_OUTPUT \| M_MAC_MDIO_OUT;
393
394	__raw_writeq(bits \| mac_mdio_genc, sbm_mdio);
395
396	for (cnt = 0; cnt < 32; cnt++) {
397	__raw_writeq(bits \| M_MAC_MDC \| mac_mdio_genc, sbm_mdio);
398	__raw_writeq(bits \| mac_mdio_genc, sbm_mdio);
399	}
400	}
401
402	/**********************************************************************
403	* SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)
404	*
405	* Send some bits to the MII. The bits to be sent are right-
406	* justified in the 'data' parameter.
407	*
408	* Input parameters:
409	* sbm_mdio - address of the MAC's MDIO register
410	* data - data to send
411	* bitcnt - number of bits to send
412	********************************************************************* */
413
414	static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
415	int bitcnt)
416	{
417	int i;
418	uint64_t bits;
419	unsigned int curmask;
420	int mac_mdio_genc;
421
422	mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
423
424	bits = M_MAC_MDIO_DIR_OUTPUT;
425	__raw_writeq(bits \| mac_mdio_genc, sbm_mdio);
426
427	curmask = 1 << (bitcnt - 1);
428
429	for (i = 0; i < bitcnt; i++) {
430	if (data & curmask)
431	bits \|= M_MAC_MDIO_OUT;
432	else bits &= ~M_MAC_MDIO_OUT;
433	__raw_writeq(bits \| mac_mdio_genc, sbm_mdio);
434	__raw_writeq(bits \| M_MAC_MDC \| mac_mdio_genc, sbm_mdio);
435	__raw_writeq(bits \| mac_mdio_genc, sbm_mdio);
436	curmask >>= 1;
437	}
438	}
439
440
441
442	/**********************************************************************
443	* SBMAC_MII_READ(bus, phyaddr, regidx)
444	* Read a PHY register.
445	*
446	* Input parameters:
447	* bus - MDIO bus handle
448	* phyaddr - PHY's address
449	* regnum - index of register to read
450	*
451	* Return value:
452	* value read, or 0xffff if an error occurred.
453	********************************************************************* */
454
455	static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
456	{
457	struct sbmac_softc sc = (struct sbmac_softc )bus->priv;
458	void __iomem *sbm_mdio = sc->sbm_mdio;
459	int idx;
460	int error;
461	int regval;
462	int mac_mdio_genc;
463
464	/*
465	* Synchronize ourselves so that the PHY knows the next
466	* thing coming down is a command
467	*/
468	sbmac_mii_sync(sbm_mdio);
469
470	/*
471	* Send the data to the PHY. The sequence is
472	* a "start" command (2 bits)
473	* a "read" command (2 bits)
474	* the PHY addr (5 bits)
475	* the register index (5 bits)
476	*/
477	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
478	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
479	sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
480	sbmac_mii_senddata(sbm_mdio, regidx, 5);
481
482	mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
483
484	/*
485	* Switch the port around without a clock transition.
486	*/
487	__raw_writeq(M_MAC_MDIO_DIR_INPUT \| mac_mdio_genc, sbm_mdio);
488
489	/*
490	* Send out a clock pulse to signal we want the status
491	*/
492	__raw_writeq(M_MAC_MDIO_DIR_INPUT \| M_MAC_MDC \| mac_mdio_genc,
493	sbm_mdio);
494	__raw_writeq(M_MAC_MDIO_DIR_INPUT \| mac_mdio_genc, sbm_mdio);
495
496	/*
497	* If an error occurred, the PHY will signal '1' back
498	*/
499	error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;
500
501	/*
502	* Issue an 'idle' clock pulse, but keep the direction
503	* the same.
504	*/
505	__raw_writeq(M_MAC_MDIO_DIR_INPUT \| M_MAC_MDC \| mac_mdio_genc,
506	sbm_mdio);
507	__raw_writeq(M_MAC_MDIO_DIR_INPUT \| mac_mdio_genc, sbm_mdio);
508
509	regval = 0;
510
511	for (idx = 0; idx < 16; idx++) {
512	regval <<= 1;
513
514	if (error == 0) {
515	if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)
516	regval \|= 1;
517	}
518
519	__raw_writeq(M_MAC_MDIO_DIR_INPUT \| M_MAC_MDC \| mac_mdio_genc,
520	sbm_mdio);
521	__raw_writeq(M_MAC_MDIO_DIR_INPUT \| mac_mdio_genc, sbm_mdio);
522	}
523
524	/* Switch back to output */
525	__raw_writeq(M_MAC_MDIO_DIR_OUTPUT \| mac_mdio_genc, sbm_mdio);
526
527	if (error == 0)
528	return regval;
529	return 0xffff;
530	}
531
532
533	/**********************************************************************
534	* SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)
535	*
536	* Write a value to a PHY register.
537	*
538	* Input parameters:
539	* bus - MDIO bus handle
540	* phyaddr - PHY to use
541	* regidx - register within the PHY
542	* regval - data to write to register
543	*
544	* Return value:
545	* 0 for success
546	********************************************************************* */
547
548	static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
549	u16 regval)
550	{
551	struct sbmac_softc sc = (struct sbmac_softc )bus->priv;
552	void __iomem *sbm_mdio = sc->sbm_mdio;
553	int mac_mdio_genc;
554
555	sbmac_mii_sync(sbm_mdio);
556
557	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
558	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
559	sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
560	sbmac_mii_senddata(sbm_mdio, regidx, 5);
561	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
562	sbmac_mii_senddata(sbm_mdio, regval, 16);
563
564	mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;
565
566	__raw_writeq(M_MAC_MDIO_DIR_OUTPUT \| mac_mdio_genc, sbm_mdio);
567
568	return 0;
569	}
570
571
572
573	/**********************************************************************
574	* SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
575	*
576	* Initialize a DMA channel context. Since there are potentially
577	* eight DMA channels per MAC, it's nice to do this in a standard
578	* way.
579	*
580	* Input parameters:
581	* d - struct sbmacdma (DMA channel context)
582	* s - struct sbmac_softc (pointer to a MAC)
583	* chan - channel number (0..1 right now)
584	* txrx - Identifies DMA_TX or DMA_RX for channel direction
585	* maxdescr - number of descriptors
586	*
587	* Return value:
588	* nothing
589	********************************************************************* */
590
591	static void sbdma_initctx(struct sbmacdma d, struct sbmac_softc s, int chan,
592	int txrx, int maxdescr)
593	{
594	#ifdef CONFIG_SBMAC_COALESCE
595	int int_pktcnt, int_timeout;
596	#endif
597
598	/*
599	* Save away interesting stuff in the structure
600	*/
601
602	d->sbdma_eth = s;
603	d->sbdma_channel = chan;
604	d->sbdma_txdir = txrx;
605
606	#if 0
607	/* RMON clearing */
608	s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
609	#endif
610
611	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
612	__raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
613	__raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
614	__raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
615	__raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
616	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
617	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
618	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
619	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
620	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
621	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
622	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
623	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
624	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
625	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
626	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
627	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
628	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
629	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
630	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
631	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);
632
633	/*
634	* initialize register pointers
635	*/
636
637	d->sbdma_config0 =
638	s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
639	d->sbdma_config1 =
640	s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
641	d->sbdma_dscrbase =
642	s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
643	d->sbdma_dscrcnt =
644	s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
645	d->sbdma_curdscr =
646	s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
647	if (d->sbdma_txdir)
648	d->sbdma_oodpktlost = NULL;
649	else
650	d->sbdma_oodpktlost =
651	s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
652
653	/*
654	* Allocate memory for the ring
655	*/
656
657	d->sbdma_maxdescr = maxdescr;
658
659	d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
660	sizeof(*d->sbdma_dscrtable),
661	GFP_KERNEL);
662
663	/*
664	* The descriptor table must be aligned to at least 16 bytes or the
665	* MAC will corrupt it.
666	*/
667	d->sbdma_dscrtable = (struct sbdmadscr *)
668	ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
669	sizeof(*d->sbdma_dscrtable));
670
671	d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
672
673	d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
674
675	/*
676	* And context table
677	*/
678
679	d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,
680	sizeof(*d->sbdma_ctxtable), GFP_KERNEL);
681
682	#ifdef CONFIG_SBMAC_COALESCE
683	/*
684	* Setup Rx/Tx DMA coalescing defaults
685	*/
686
687	int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
688	if ( int_pktcnt ) {
689	d->sbdma_int_pktcnt = int_pktcnt;
690	} else {
691	d->sbdma_int_pktcnt = 1;
692	}
693
694	int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
695	if ( int_timeout ) {
696	d->sbdma_int_timeout = int_timeout;
697	} else {
698	d->sbdma_int_timeout = 0;
699	}
700	#endif
701
702	}
703
704	/**********************************************************************
705	* SBDMA_CHANNEL_START(d)
706	*
707	* Initialize the hardware registers for a DMA channel.
708	*
709	* Input parameters:
710	* d - DMA channel to init (context must be previously init'd
711	* rxtx - DMA_RX or DMA_TX depending on what type of channel
712	*
713	* Return value:
714	* nothing
715	********************************************************************* */
716
717	static void sbdma_channel_start(struct sbmacdma *d, int rxtx)
718	{
719	/*
720	* Turn on the DMA channel
721	*/
722
723	#ifdef CONFIG_SBMAC_COALESCE
724	__raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) \|
725	0, d->sbdma_config1);
726	__raw_writeq(M_DMA_EOP_INT_EN \|
727	V_DMA_RINGSZ(d->sbdma_maxdescr) \|
728	V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) \|
729	0, d->sbdma_config0);
730	#else
731	__raw_writeq(0, d->sbdma_config1);
732	__raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) \|
733	0, d->sbdma_config0);
734	#endif
735
736	__raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
737
738	/*
739	* Initialize ring pointers
740	*/
741
742	d->sbdma_addptr = d->sbdma_dscrtable;
743	d->sbdma_remptr = d->sbdma_dscrtable;
744	}
745
746	/**********************************************************************
747	* SBDMA_CHANNEL_STOP(d)
748	*
749	* Initialize the hardware registers for a DMA channel.
750	*
751	* Input parameters:
752	* d - DMA channel to init (context must be previously init'd
753	*
754	* Return value:
755	* nothing
756	********************************************************************* */
757
758	static void sbdma_channel_stop(struct sbmacdma *d)
759	{
760	/*
761	* Turn off the DMA channel
762	*/
763
764	__raw_writeq(0, d->sbdma_config1);
765
766	__raw_writeq(0, d->sbdma_dscrbase);
767
768	__raw_writeq(0, d->sbdma_config0);
769
770	/*
771	* Zero ring pointers
772	*/
773
774	d->sbdma_addptr = NULL;
775	d->sbdma_remptr = NULL;
776	}
777
778	static inline void sbdma_align_skb(struct sk_buff *skb,
779	unsigned int power2, unsigned int offset)
780	{
781	unsigned char *addr = skb->data;
782	unsigned char *newaddr = PTR_ALIGN(addr, power2);
783
784	skb_reserve(skb, newaddr - addr + offset);
785	}
786
787
788	/**********************************************************************
789	* SBDMA_ADD_RCVBUFFER(d,sb)
790	*
791	* Add a buffer to the specified DMA channel. For receive channels,
792	* this queues a buffer for inbound packets.
793	*
794	* Input parameters:
795	* sc - softc structure
796	* d - DMA channel descriptor
797	* sb - sk_buff to add, or NULL if we should allocate one
798	*
799	* Return value:
800	* 0 if buffer could not be added (ring is full)
801	* 1 if buffer added successfully
802	********************************************************************* */
803
804
805	static int sbdma_add_rcvbuffer(struct sbmac_softc sc, struct sbmacdma d,
806	struct sk_buff *sb)
807	{
808	struct net_device *dev = sc->sbm_dev;
809	struct sbdmadscr *dsc;
810	struct sbdmadscr *nextdsc;
811	struct sk_buff *sb_new = NULL;
812	int pktsize = ENET_PACKET_SIZE;
813
814	/* get pointer to our current place in the ring */
815
816	dsc = d->sbdma_addptr;
817	nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
818
819	/*
820	* figure out if the ring is full - if the next descriptor
821	* is the same as the one that we're going to remove from
822	* the ring, the ring is full
823	*/
824
825	if (nextdsc == d->sbdma_remptr) {
826	return -ENOSPC;
827	}
828
829	/*
830	* Allocate a sk_buff if we don't already have one.
831	* If we do have an sk_buff, reset it so that it's empty.
832	*
833	* Note: sk_buffs don't seem to be guaranteed to have any sort
834	* of alignment when they are allocated. Therefore, allocate enough
835	* extra space to make sure that:
836	*
837	* 1. the data does not start in the middle of a cache line.
838	* 2. The data does not end in the middle of a cache line
839	* 3. The buffer can be aligned such that the IP addresses are
840	* naturally aligned.
841	*
842	* Remember, the SOCs MAC writes whole cache lines at a time,
843	* without reading the old contents first. So, if the sk_buff's
844	* data portion starts in the middle of a cache line, the SOC
845	* DMA will trash the beginning (and ending) portions.
846	*/
847
848	if (sb == NULL) {
849	sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE +
850	SMP_CACHE_BYTES * 2 +
851	NET_IP_ALIGN);
852	if (sb_new == NULL) {
853	pr_info("%s: sk_buff allocation failed\n",
854	d->sbdma_eth->sbm_dev->name);
855	return -ENOBUFS;
856	}
857
858	sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN);
859	}
860	else {
861	sb_new = sb;
862	/*
863	* nothing special to reinit buffer, it's already aligned
864	* and sb->data already points to a good place.
865	*/
866	}
867
868	/*
869	* fill in the descriptor
870	*/
871
872	#ifdef CONFIG_SBMAC_COALESCE
873	/*
874	* Do not interrupt per DMA transfer.
875	*/
876	dsc->dscr_a = virt_to_phys(sb_new->data) \|
877	V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) \| 0;
878	#else
879	dsc->dscr_a = virt_to_phys(sb_new->data) \|
880	V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) \|
881	M_DMA_DSCRA_INTERRUPT;
882	#endif
883
884	/* receiving: no options */
885	dsc->dscr_b = 0;
886
887	/*
888	* fill in the context
889	*/
890
891	d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
892
893	/*
894	* point at next packet
895	*/
896
897	d->sbdma_addptr = nextdsc;
898
899	/*
900	* Give the buffer to the DMA engine.
901	*/
902
903	__raw_writeq(1, d->sbdma_dscrcnt);
904
905	return 0; /* we did it */
906	}
907
908	/**********************************************************************
909	* SBDMA_ADD_TXBUFFER(d,sb)
910	*
911	* Add a transmit buffer to the specified DMA channel, causing a
912	* transmit to start.
913	*
914	* Input parameters:
915	* d - DMA channel descriptor
916	* sb - sk_buff to add
917	*
918	* Return value:
919	* 0 transmit queued successfully
920	* otherwise error code
921	********************************************************************* */
922
923
924	static int sbdma_add_txbuffer(struct sbmacdma d, struct sk_buff sb)
925	{
926	struct sbdmadscr *dsc;
927	struct sbdmadscr *nextdsc;
928	uint64_t phys;
929	uint64_t ncb;
930	int length;
931
932	/* get pointer to our current place in the ring */
933
934	dsc = d->sbdma_addptr;
935	nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
936
937	/*
938	* figure out if the ring is full - if the next descriptor
939	* is the same as the one that we're going to remove from
940	* the ring, the ring is full
941	*/
942
943	if (nextdsc == d->sbdma_remptr) {
944	return -ENOSPC;
945	}
946
947	/*
948	* Under Linux, it's not necessary to copy/coalesce buffers
949	* like it is on NetBSD. We think they're all contiguous,
950	* but that may not be true for GBE.
951	*/
952
953	length = sb->len;
954
955	/*
956	* fill in the descriptor. Note that the number of cache
957	* blocks in the descriptor is the number of blocks
958	* spanned, so we need to add in the offset (if any)
959	* while doing the calculation.
960	*/
961
962	phys = virt_to_phys(sb->data);
963	ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
964
965	dsc->dscr_a = phys \|
966	V_DMA_DSCRA_A_SIZE(ncb) \|
967	#ifndef CONFIG_SBMAC_COALESCE
968	M_DMA_DSCRA_INTERRUPT \|
969	#endif
970	M_DMA_ETHTX_SOP;
971
972	/* transmitting: set outbound options and length */
973
974	dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) \|
975	V_DMA_DSCRB_PKT_SIZE(length);
976
977	/*
978	* fill in the context
979	*/
980
981	d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
982
983	/*
984	* point at next packet
985	*/
986
987	d->sbdma_addptr = nextdsc;
988
989	/*
990	* Give the buffer to the DMA engine.
991	*/
992
993	__raw_writeq(1, d->sbdma_dscrcnt);
994
995	return 0; /* we did it */
996	}
997
998
999
1000
1001	/**********************************************************************
1002	* SBDMA_EMPTYRING(d)
1003	*
1004	* Free all allocated sk_buffs on the specified DMA channel;
1005	*
1006	* Input parameters:
1007	* d - DMA channel
1008	*
1009	* Return value:
1010	* nothing
1011	********************************************************************* */
1012
1013	static void sbdma_emptyring(struct sbmacdma *d)
1014	{
1015	int idx;
1016	struct sk_buff *sb;
1017
1018	for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1019	sb = d->sbdma_ctxtable[idx];
1020	if (sb) {
1021	dev_kfree_skb(sb);
1022	d->sbdma_ctxtable[idx] = NULL;
1023	}
1024	}
1025	}
1026
1027
1028	/**********************************************************************
1029	* SBDMA_FILLRING(d)
1030	*
1031	* Fill the specified DMA channel (must be receive channel)
1032	* with sk_buffs
1033	*
1034	* Input parameters:
1035	* sc - softc structure
1036	* d - DMA channel
1037	*
1038	* Return value:
1039	* nothing
1040	********************************************************************* */
1041
1042	static void sbdma_fillring(struct sbmac_softc sc, struct sbmacdma d)
1043	{
1044	int idx;
1045
1046	for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) {
1047	if (sbdma_add_rcvbuffer(sc, d, NULL) != 0)
1048	break;
1049	}
1050	}
1051
1052	#ifdef CONFIG_NET_POLL_CONTROLLER
1053	static void sbmac_netpoll(struct net_device *netdev)
1054	{
1055	struct sbmac_softc *sc = netdev_priv(netdev);
1056	int irq = sc->sbm_dev->irq;
1057
1058	__raw_writeq(0, sc->sbm_imr);
1059
1060	sbmac_intr(irq, netdev);
1061
1062	#ifdef CONFIG_SBMAC_COALESCE
1063	__raw_writeq(((M_MAC_INT_EOP_COUNT \| M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) \|
1064	((M_MAC_INT_EOP_COUNT \| M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1065	sc->sbm_imr);
1066	#else
1067	__raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) \|
1068	(M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1069	#endif
1070	}
1071	#endif
1072
1073	/**********************************************************************
1074	* SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1075	*
1076	* Process "completed" receive buffers on the specified DMA channel.
1077	*
1078	* Input parameters:
1079	* sc - softc structure
1080	* d - DMA channel context
1081	* work_to_do - no. of packets to process before enabling interrupt
1082	* again (for NAPI)
1083	* poll - 1: using polling (for NAPI)
1084	*
1085	* Return value:
1086	* nothing
1087	********************************************************************* */
1088
1089	static int sbdma_rx_process(struct sbmac_softc sc, struct sbmacdma d,
1090	int work_to_do, int poll)
1091	{
1092	struct net_device *dev = sc->sbm_dev;
1093	int curidx;
1094	int hwidx;
1095	struct sbdmadscr *dsc;
1096	struct sk_buff *sb;
1097	int len;
1098	int work_done = 0;
1099	int dropped = 0;
1100
1101	prefetch(d);
1102
1103	again:
1104	/* Check if the HW dropped any frames */
1105	dev->stats.rx_fifo_errors
1106	+= __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1107	__raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1108
1109	while (work_to_do-- > 0) {
1110	/*
1111	* figure out where we are (as an index) and where
1112	* the hardware is (also as an index)
1113	*
1114	* This could be done faster if (for example) the
1115	* descriptor table was page-aligned and contiguous in
1116	* both virtual and physical memory -- you could then
1117	* just compare the low-order bits of the virtual address
1118	* (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1119	*/
1120
1121	dsc = d->sbdma_remptr;
1122	curidx = dsc - d->sbdma_dscrtable;
1123
1124	prefetch(dsc);
1125	prefetch(&d->sbdma_ctxtable[curidx]);
1126
1127	hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1128	d->sbdma_dscrtable_phys) /
1129	sizeof(*d->sbdma_dscrtable);
1130
1131	/*
1132	* If they're the same, that means we've processed all
1133	* of the descriptors up to (but not including) the one that
1134	* the hardware is working on right now.
1135	*/
1136
1137	if (curidx == hwidx)
1138	goto done;
1139
1140	/*
1141	* Otherwise, get the packet's sk_buff ptr back
1142	*/
1143
1144	sb = d->sbdma_ctxtable[curidx];
1145	d->sbdma_ctxtable[curidx] = NULL;
1146
1147	len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1148
1149	/*
1150	* Check packet status. If good, process it.
1151	* If not, silently drop it and put it back on the
1152	* receive ring.
1153	*/
1154
1155	if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1156
1157	/*
1158	* Add a new buffer to replace the old one. If we fail
1159	* to allocate a buffer, we're going to drop this
1160	* packet and put it right back on the receive ring.
1161	*/
1162
1163	if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) ==
1164	-ENOBUFS)) {
1165	dev->stats.rx_dropped++;
1166	/* Re-add old buffer */
1167	sbdma_add_rcvbuffer(sc, d, sb);
1168	/* No point in continuing at the moment */
1169	printk(KERN_ERR "dropped packet (1)\n");
1170	d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1171	goto done;
1172	} else {
1173	/*
1174	* Set length into the packet
1175	*/
1176	skb_put(sb,len);
1177
1178	/*
1179	* Buffer has been replaced on the
1180	* receive ring. Pass the buffer to
1181	* the kernel
1182	*/
1183	sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1184	/* Check hw IPv4/TCP checksum if supported */
1185	if (sc->rx_hw_checksum == ENABLE) {
1186	if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1187	!((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1188	sb->ip_summed = CHECKSUM_UNNECESSARY;
1189	/* don't need to set sb->csum */
1190	} else {
1191	sb->ip_summed = CHECKSUM_NONE;
1192	}
1193	}
1194	prefetch(sb->data);
1195	prefetch((const void )(((char )sb->data)+32));
1196	if (poll)
1197	dropped = netif_receive_skb(sb);
1198	else
1199	dropped = netif_rx(sb);
1200
1201	if (dropped == NET_RX_DROP) {
1202	dev->stats.rx_dropped++;
1203	d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1204	goto done;
1205	}
1206	else {
1207	dev->stats.rx_bytes += len;
1208	dev->stats.rx_packets++;
1209	}
1210	}
1211	} else {
1212	/*
1213	* Packet was mangled somehow. Just drop it and
1214	* put it back on the receive ring.
1215	*/
1216	dev->stats.rx_errors++;
1217	sbdma_add_rcvbuffer(sc, d, sb);
1218	}
1219
1220
1221	/*
1222	* .. and advance to the next buffer.
1223	*/
1224
1225	d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1226	work_done++;
1227	}
1228	if (!poll) {
1229	work_to_do = 32;
1230	goto again; /* collect fifo drop statistics again */
1231	}
1232	done:
1233	return work_done;
1234	}
1235
1236	/**********************************************************************
1237	* SBDMA_TX_PROCESS(sc,d)
1238	*
1239	* Process "completed" transmit buffers on the specified DMA channel.
1240	* This is normally called within the interrupt service routine.
1241	* Note that this isn't really ideal for priority channels, since
1242	* it processes all of the packets on a given channel before
1243	* returning.
1244	*
1245	* Input parameters:
1246	* sc - softc structure
1247	* d - DMA channel context
1248	* poll - 1: using polling (for NAPI)
1249	*
1250	* Return value:
1251	* nothing
1252	********************************************************************* */
1253
1254	static void sbdma_tx_process(struct sbmac_softc sc, struct sbmacdma d,
1255	int poll)
1256	{
1257	struct net_device *dev = sc->sbm_dev;
1258	int curidx;
1259	int hwidx;
1260	struct sbdmadscr *dsc;
1261	struct sk_buff *sb;
1262	unsigned long flags;
1263	int packets_handled = 0;
1264
1265	spin_lock_irqsave(&(sc->sbm_lock), flags);
1266
1267	if (d->sbdma_remptr == d->sbdma_addptr)
1268	goto end_unlock;
1269
1270	hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1271	d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);
1272
1273	for (;;) {
1274	/*
1275	* figure out where we are (as an index) and where
1276	* the hardware is (also as an index)
1277	*
1278	* This could be done faster if (for example) the
1279	* descriptor table was page-aligned and contiguous in
1280	* both virtual and physical memory -- you could then
1281	* just compare the low-order bits of the virtual address
1282	* (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1283	*/
1284
1285	curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1286
1287	/*
1288	* If they're the same, that means we've processed all
1289	* of the descriptors up to (but not including) the one that
1290	* the hardware is working on right now.
1291	*/
1292
1293	if (curidx == hwidx)
1294	break;
1295
1296	/*
1297	* Otherwise, get the packet's sk_buff ptr back
1298	*/
1299
1300	dsc = &(d->sbdma_dscrtable[curidx]);
1301	sb = d->sbdma_ctxtable[curidx];
1302	d->sbdma_ctxtable[curidx] = NULL;
1303
1304	/*
1305	* Stats
1306	*/
1307
1308	dev->stats.tx_bytes += sb->len;
1309	dev->stats.tx_packets++;
1310
1311	/*
1312	* for transmits, we just free buffers.
1313	*/
1314
1315	dev_kfree_skb_irq(sb);
1316
1317	/*
1318	* .. and advance to the next buffer.
1319	*/
1320
1321	d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1322
1323	packets_handled++;
1324
1325	}
1326
1327	/*
1328	* Decide if we should wake up the protocol or not.
1329	* Other drivers seem to do this when we reach a low
1330	* watermark on the transmit queue.
1331	*/
1332
1333	if (packets_handled)
1334	netif_wake_queue(d->sbdma_eth->sbm_dev);
1335
1336	end_unlock:
1337	spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1338
1339	}
1340
1341
1342
1343	/**********************************************************************
1344	* SBMAC_INITCTX(s)
1345	*
1346	* Initialize an Ethernet context structure - this is called
1347	* once per MAC on the 1250. Memory is allocated here, so don't
1348	* call it again from inside the ioctl routines that bring the
1349	* interface up/down
1350	*
1351	* Input parameters:
1352	* s - sbmac context structure
1353	*
1354	* Return value:
1355	* 0
1356	********************************************************************* */
1357
1358	static int sbmac_initctx(struct sbmac_softc *s)
1359	{
1360
1361	/*
1362	* figure out the addresses of some ports
1363	*/
1364
1365	s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1366	s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1367	s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1368	s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1369	s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1370	s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1371	s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1372	s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1373
1374	/*
1375	* Initialize the DMA channels. Right now, only one per MAC is used
1376	* Note: Only do this _once_, as it allocates memory from the kernel!
1377	*/
1378
1379	sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1380	sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1381
1382	/*
1383	* initial state is OFF
1384	*/
1385
1386	s->sbm_state = sbmac_state_off;
1387
1388	return 0;
1389	}
1390
1391
1392	static void sbdma_uninitctx(struct sbmacdma *d)
1393	{
1394	if (d->sbdma_dscrtable_unaligned) {
1395	kfree(d->sbdma_dscrtable_unaligned);
1396	d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1397	}
1398
1399	if (d->sbdma_ctxtable) {
1400	kfree(d->sbdma_ctxtable);
1401	d->sbdma_ctxtable = NULL;
1402	}
1403	}
1404
1405
1406	static void sbmac_uninitctx(struct sbmac_softc *sc)
1407	{
1408	sbdma_uninitctx(&(sc->sbm_txdma));
1409	sbdma_uninitctx(&(sc->sbm_rxdma));
1410	}
1411
1412
1413	/**********************************************************************
1414	* SBMAC_CHANNEL_START(s)
1415	*
1416	* Start packet processing on this MAC.
1417	*
1418	* Input parameters:
1419	* s - sbmac structure
1420	*
1421	* Return value:
1422	* nothing
1423	********************************************************************* */
1424
1425	static void sbmac_channel_start(struct sbmac_softc *s)
1426	{
1427	uint64_t reg;
1428	void __iomem *port;
1429	uint64_t cfg,fifo,framecfg;
1430	int idx, th_value;
1431
1432	/*
1433	* Don't do this if running
1434	*/
1435
1436	if (s->sbm_state == sbmac_state_on)
1437	return;
1438
1439	/*
1440	* Bring the controller out of reset, but leave it off.
1441	*/
1442
1443	__raw_writeq(0, s->sbm_macenable);
1444
1445	/*
1446	* Ignore all received packets
1447	*/
1448
1449	__raw_writeq(0, s->sbm_rxfilter);
1450
1451	/*
1452	* Calculate values for various control registers.
1453	*/
1454
1455	cfg = M_MAC_RETRY_EN \|
1456	M_MAC_TX_HOLD_SOP_EN \|
1457	V_MAC_TX_PAUSE_CNT_16K \|
1458	M_MAC_AP_STAT_EN \|
1459	M_MAC_FAST_SYNC \|
1460	M_MAC_SS_EN \|
1461	0;
1462
1463	/*
1464	* Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1465	* and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1466	* Use a larger RD_THRSH for gigabit
1467	*/
1468	if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1469	th_value = 28;
1470	else
1471	th_value = 64;
1472
1473	fifo = V_MAC_TX_WR_THRSH(4) \| /* Must be '4' or '8' */
1474	((s->sbm_speed == sbmac_speed_1000)
1475	? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) \|
1476	V_MAC_TX_RL_THRSH(4) \|
1477	V_MAC_RX_PL_THRSH(4) \|
1478	V_MAC_RX_RD_THRSH(4) \| /* Must be '4' */
1479	V_MAC_RX_PL_THRSH(4) \|
1480	V_MAC_RX_RL_THRSH(8) \|
1481	0;
1482
1483	framecfg = V_MAC_MIN_FRAMESZ_DEFAULT \|
1484	V_MAC_MAX_FRAMESZ_DEFAULT \|
1485	V_MAC_BACKOFF_SEL(1);
1486
1487	/*
1488	* Clear out the hash address map
1489	*/
1490
1491	port = s->sbm_base + R_MAC_HASH_BASE;
1492	for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1493	__raw_writeq(0, port);
1494	port += sizeof(uint64_t);
1495	}
1496
1497	/*
1498	* Clear out the exact-match table
1499	*/
1500
1501	port = s->sbm_base + R_MAC_ADDR_BASE;
1502	for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1503	__raw_writeq(0, port);
1504	port += sizeof(uint64_t);
1505	}
1506
1507	/*
1508	* Clear out the DMA Channel mapping table registers
1509	*/
1510
1511	port = s->sbm_base + R_MAC_CHUP0_BASE;
1512	for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1513	__raw_writeq(0, port);
1514	port += sizeof(uint64_t);
1515	}
1516
1517
1518	port = s->sbm_base + R_MAC_CHLO0_BASE;
1519	for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1520	__raw_writeq(0, port);
1521	port += sizeof(uint64_t);
1522	}
1523
1524	/*
1525	* Program the hardware address. It goes into the hardware-address
1526	* register as well as the first filter register.
1527	*/
1528
1529	reg = sbmac_addr2reg(s->sbm_hwaddr);
1530
1531	port = s->sbm_base + R_MAC_ADDR_BASE;
1532	__raw_writeq(reg, port);
1533	port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1534
1535	#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1536	/*
1537	* Pass1 SOCs do not receive packets addressed to the
1538	* destination address in the R_MAC_ETHERNET_ADDR register.
1539	* Set the value to zero.
1540	*/
1541	__raw_writeq(0, port);
1542	#else
1543	__raw_writeq(reg, port);
1544	#endif
1545
1546	/*
1547	* Set the receive filter for no packets, and write values
1548	* to the various config registers
1549	*/
1550
1551	__raw_writeq(0, s->sbm_rxfilter);
1552	__raw_writeq(0, s->sbm_imr);
1553	__raw_writeq(framecfg, s->sbm_framecfg);
1554	__raw_writeq(fifo, s->sbm_fifocfg);
1555	__raw_writeq(cfg, s->sbm_maccfg);
1556
1557	/*
1558	* Initialize DMA channels (rings should be ok now)
1559	*/
1560
1561	sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1562	sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1563
1564	/*
1565	* Configure the speed, duplex, and flow control
1566	*/
1567
1568	sbmac_set_speed(s,s->sbm_speed);
1569	sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1570
1571	/*
1572	* Fill the receive ring
1573	*/
1574
1575	sbdma_fillring(s, &(s->sbm_rxdma));
1576
1577	/*
1578	* Turn on the rest of the bits in the enable register
1579	*/
1580
1581	#if defined(CONFIG_SIBYTE_BCM1x55) \|\| defined(CONFIG_SIBYTE_BCM1x80)
1582	__raw_writeq(M_MAC_RXDMA_EN0 \|
1583	M_MAC_TXDMA_EN0, s->sbm_macenable);
1584	#elif defined(CONFIG_SIBYTE_SB1250) \|\| defined(CONFIG_SIBYTE_BCM112X)
1585	__raw_writeq(M_MAC_RXDMA_EN0 \|
1586	M_MAC_TXDMA_EN0 \|
1587	M_MAC_RX_ENABLE \|
1588	M_MAC_TX_ENABLE, s->sbm_macenable);
1589	#else
1590	#error invalid SiByte MAC configuation
1591	#endif
1592
1593	#ifdef CONFIG_SBMAC_COALESCE
1594	__raw_writeq(((M_MAC_INT_EOP_COUNT \| M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) \|
1595	((M_MAC_INT_EOP_COUNT \| M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1596	#else
1597	__raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) \|
1598	(M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1599	#endif
1600
1601	/*
1602	* Enable receiving unicasts and broadcasts
1603	*/
1604
1605	__raw_writeq(M_MAC_UCAST_EN \| M_MAC_BCAST_EN, s->sbm_rxfilter);
1606
1607	/*
1608	* we're running now.
1609	*/
1610
1611	s->sbm_state = sbmac_state_on;
1612
1613	/*
1614	* Program multicast addresses
1615	*/
1616
1617	sbmac_setmulti(s);
1618
1619	/*
1620	* If channel was in promiscuous mode before, turn that on
1621	*/
1622
1623	if (s->sbm_devflags & IFF_PROMISC) {
1624	sbmac_promiscuous_mode(s,1);
1625	}
1626
1627	}
1628
1629
1630	/**********************************************************************
1631	* SBMAC_CHANNEL_STOP(s)
1632	*
1633	* Stop packet processing on this MAC.
1634	*
1635	* Input parameters:
1636	* s - sbmac structure
1637	*
1638	* Return value:
1639	* nothing
1640	********************************************************************* */
1641
1642	static void sbmac_channel_stop(struct sbmac_softc *s)
1643	{
1644	/* don't do this if already stopped */
1645
1646	if (s->sbm_state == sbmac_state_off)
1647	return;
1648
1649	/* don't accept any packets, disable all interrupts */
1650
1651	__raw_writeq(0, s->sbm_rxfilter);
1652	__raw_writeq(0, s->sbm_imr);
1653
1654	/* Turn off ticker */
1655
1656	/* XXX */
1657
1658	/* turn off receiver and transmitter */
1659
1660	__raw_writeq(0, s->sbm_macenable);
1661
1662	/* We're stopped now. */
1663
1664	s->sbm_state = sbmac_state_off;
1665
1666	/*
1667	* Stop DMA channels (rings should be ok now)
1668	*/
1669
1670	sbdma_channel_stop(&(s->sbm_rxdma));
1671	sbdma_channel_stop(&(s->sbm_txdma));
1672
1673	/* Empty the receive and transmit rings */
1674
1675	sbdma_emptyring(&(s->sbm_rxdma));
1676	sbdma_emptyring(&(s->sbm_txdma));
1677
1678	}
1679
1680	/**********************************************************************
1681	* SBMAC_SET_CHANNEL_STATE(state)
1682	*
1683	* Set the channel's state ON or OFF
1684	*
1685	* Input parameters:
1686	* state - new state
1687	*
1688	* Return value:
1689	* old state
1690	********************************************************************* */
1691	static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc,
1692	enum sbmac_state state)
1693	{
1694	enum sbmac_state oldstate = sc->sbm_state;
1695
1696	/*
1697	* If same as previous state, return
1698	*/
1699
1700	if (state == oldstate) {
1701	return oldstate;
1702	}
1703
1704	/*
1705	* If new state is ON, turn channel on
1706	*/
1707
1708	if (state == sbmac_state_on) {
1709	sbmac_channel_start(sc);
1710	}
1711	else {
1712	sbmac_channel_stop(sc);
1713	}
1714
1715	/*
1716	* Return previous state
1717	*/
1718
1719	return oldstate;
1720	}
1721
1722
1723	/**********************************************************************
1724	* SBMAC_PROMISCUOUS_MODE(sc,onoff)
1725	*
1726	* Turn on or off promiscuous mode
1727	*
1728	* Input parameters:
1729	* sc - softc
1730	* onoff - 1 to turn on, 0 to turn off
1731	*
1732	* Return value:
1733	* nothing
1734	********************************************************************* */
1735
1736	static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1737	{
1738	uint64_t reg;
1739
1740	if (sc->sbm_state != sbmac_state_on)
1741	return;
1742
1743	if (onoff) {
1744	reg = __raw_readq(sc->sbm_rxfilter);
1745	reg \|= M_MAC_ALLPKT_EN;
1746	__raw_writeq(reg, sc->sbm_rxfilter);
1747	}
1748	else {
1749	reg = __raw_readq(sc->sbm_rxfilter);
1750	reg &= ~M_MAC_ALLPKT_EN;
1751	__raw_writeq(reg, sc->sbm_rxfilter);
1752	}
1753	}
1754
1755	/**********************************************************************
1756	* SBMAC_SETIPHDR_OFFSET(sc,onoff)
1757	*
1758	* Set the iphdr offset as 15 assuming ethernet encapsulation
1759	*
1760	* Input parameters:
1761	* sc - softc
1762	*
1763	* Return value:
1764	* nothing
1765	********************************************************************* */
1766
1767	static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1768	{
1769	uint64_t reg;
1770
1771	/* Hard code the off set to 15 for now */
1772	reg = __raw_readq(sc->sbm_rxfilter);
1773	reg &= ~M_MAC_IPHDR_OFFSET \| V_MAC_IPHDR_OFFSET(15);
1774	__raw_writeq(reg, sc->sbm_rxfilter);
1775
1776	/* BCM1250 pass1 didn't have hardware checksum. Everything
1777	later does. */
1778	if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1779	sc->rx_hw_checksum = DISABLE;
1780	} else {
1781	sc->rx_hw_checksum = ENABLE;
1782	}
1783	}
1784
1785
1786	/**********************************************************************
1787	* SBMAC_ADDR2REG(ptr)
1788	*
1789	* Convert six bytes into the 64-bit register value that
1790	* we typically write into the SBMAC's address/mcast registers
1791	*
1792	* Input parameters:
1793	* ptr - pointer to 6 bytes
1794	*
1795	* Return value:
1796	* register value
1797	********************************************************************* */
1798
1799	static uint64_t sbmac_addr2reg(unsigned char *ptr)
1800	{
1801	uint64_t reg = 0;
1802
1803	ptr += 6;
1804
1805	reg \|= (uint64_t) *(--ptr);
1806	reg <<= 8;
1807	reg \|= (uint64_t) *(--ptr);
1808	reg <<= 8;
1809	reg \|= (uint64_t) *(--ptr);
1810	reg <<= 8;
1811	reg \|= (uint64_t) *(--ptr);
1812	reg <<= 8;
1813	reg \|= (uint64_t) *(--ptr);
1814	reg <<= 8;
1815	reg \|= (uint64_t) *(--ptr);
1816
1817	return reg;
1818	}
1819
1820
1821	/**********************************************************************
1822	* SBMAC_SET_SPEED(s,speed)
1823	*
1824	* Configure LAN speed for the specified MAC.
1825	* Warning: must be called when MAC is off!
1826	*
1827	* Input parameters:
1828	* s - sbmac structure
1829	* speed - speed to set MAC to (see enum sbmac_speed)
1830	*
1831	* Return value:
1832	* 1 if successful
1833	* 0 indicates invalid parameters
1834	********************************************************************* */
1835
1836	static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed)
1837	{
1838	uint64_t cfg;
1839	uint64_t framecfg;
1840
1841	/*
1842	* Save new current values
1843	*/
1844
1845	s->sbm_speed = speed;
1846
1847	if (s->sbm_state == sbmac_state_on)
1848	return 0; /* save for next restart */
1849
1850	/*
1851	* Read current register values
1852	*/
1853
1854	cfg = __raw_readq(s->sbm_maccfg);
1855	framecfg = __raw_readq(s->sbm_framecfg);
1856
1857	/*
1858	* Mask out the stuff we want to change
1859	*/
1860
1861	cfg &= ~(M_MAC_BURST_EN \| M_MAC_SPEED_SEL);
1862	framecfg &= ~(M_MAC_IFG_RX \| M_MAC_IFG_TX \| M_MAC_IFG_THRSH \|
1863	M_MAC_SLOT_SIZE);
1864
1865	/*
1866	* Now add in the new bits
1867	*/
1868
1869	switch (speed) {
1870	case sbmac_speed_10:
1871	framecfg \|= V_MAC_IFG_RX_10 \|
1872	V_MAC_IFG_TX_10 \|
1873	K_MAC_IFG_THRSH_10 \|
1874	V_MAC_SLOT_SIZE_10;
1875	cfg \|= V_MAC_SPEED_SEL_10MBPS;
1876	break;
1877
1878	case sbmac_speed_100:
1879	framecfg \|= V_MAC_IFG_RX_100 \|
1880	V_MAC_IFG_TX_100 \|
1881	V_MAC_IFG_THRSH_100 \|
1882	V_MAC_SLOT_SIZE_100;
1883	cfg \|= V_MAC_SPEED_SEL_100MBPS ;
1884	break;
1885
1886	case sbmac_speed_1000:
1887	framecfg \|= V_MAC_IFG_RX_1000 \|
1888	V_MAC_IFG_TX_1000 \|
1889	V_MAC_IFG_THRSH_1000 \|
1890	V_MAC_SLOT_SIZE_1000;
1891	cfg \|= V_MAC_SPEED_SEL_1000MBPS \| M_MAC_BURST_EN;
1892	break;
1893
1894	default:
1895	return 0;
1896	}
1897
1898	/*
1899	* Send the bits back to the hardware
1900	*/
1901
1902	__raw_writeq(framecfg, s->sbm_framecfg);
1903	__raw_writeq(cfg, s->sbm_maccfg);
1904
1905	return 1;
1906	}
1907
1908	/**********************************************************************
1909	* SBMAC_SET_DUPLEX(s,duplex,fc)
1910	*
1911	* Set Ethernet duplex and flow control options for this MAC
1912	* Warning: must be called when MAC is off!
1913	*
1914	* Input parameters:
1915	* s - sbmac structure
1916	* duplex - duplex setting (see enum sbmac_duplex)
1917	* fc - flow control setting (see enum sbmac_fc)
1918	*
1919	* Return value:
1920	* 1 if ok
1921	* 0 if an invalid parameter combination was specified
1922	********************************************************************* */
1923
1924	static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
1925	enum sbmac_fc fc)
1926	{
1927	uint64_t cfg;
1928
1929	/*
1930	* Save new current values
1931	*/
1932
1933	s->sbm_duplex = duplex;
1934	s->sbm_fc = fc;
1935
1936	if (s->sbm_state == sbmac_state_on)
1937	return 0; /* save for next restart */
1938
1939	/*
1940	* Read current register values
1941	*/
1942
1943	cfg = __raw_readq(s->sbm_maccfg);
1944
1945	/*
1946	* Mask off the stuff we're about to change
1947	*/
1948
1949	cfg &= ~(M_MAC_FC_SEL \| M_MAC_FC_CMD \| M_MAC_HDX_EN);
1950
1951
1952	switch (duplex) {
1953	case sbmac_duplex_half:
1954	switch (fc) {
1955	case sbmac_fc_disabled:
1956	cfg \|= M_MAC_HDX_EN \| V_MAC_FC_CMD_DISABLED;
1957	break;
1958
1959	case sbmac_fc_collision:
1960	cfg \|= M_MAC_HDX_EN \| V_MAC_FC_CMD_ENABLED;
1961	break;
1962
1963	case sbmac_fc_carrier:
1964	cfg \|= M_MAC_HDX_EN \| V_MAC_FC_CMD_ENAB_FALSECARR;
1965	break;
1966
1967	case sbmac_fc_frame: /* not valid in half duplex */
1968	default: /* invalid selection */
1969	return 0;
1970	}
1971	break;
1972
1973	case sbmac_duplex_full:
1974	switch (fc) {
1975	case sbmac_fc_disabled:
1976	cfg \|= V_MAC_FC_CMD_DISABLED;
1977	break;
1978
1979	case sbmac_fc_frame:
1980	cfg \|= V_MAC_FC_CMD_ENABLED;
1981	break;
1982
1983	case sbmac_fc_collision: /* not valid in full duplex */
1984	case sbmac_fc_carrier: /* not valid in full duplex */
1985	default:
1986	return 0;
1987	}
1988	break;
1989	default:
1990	return 0;
1991	}
1992
1993	/*
1994	* Send the bits back to the hardware
1995	*/
1996
1997	__raw_writeq(cfg, s->sbm_maccfg);
1998
1999	return 1;
2000	}
2001
2002
2003
2004
2005	/**********************************************************************
2006	* SBMAC_INTR()
2007	*
2008	* Interrupt handler for MAC interrupts
2009	*
2010	* Input parameters:
2011	* MAC structure
2012	*
2013	* Return value:
2014	* nothing
2015	********************************************************************* */
2016	static irqreturn_t sbmac_intr(int irq,void *dev_instance)
2017	{
2018	struct net_device dev = (struct net_device ) dev_instance;
2019	struct sbmac_softc *sc = netdev_priv(dev);
2020	uint64_t isr;
2021	int handled = 0;
2022
2023	/*
2024	* Read the ISR (this clears the bits in the real
2025	* register, except for counter addr)
2026	*/
2027
2028	isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2029
2030	if (isr == 0)
2031	return IRQ_RETVAL(0);
2032	handled = 1;
2033
2034	/*
2035	* Transmits on channel 0
2036	*/
2037
2038	if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0))
2039	sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2040
2041	if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2042	if (napi_schedule_prep(&sc->napi)) {
2043	__raw_writeq(0, sc->sbm_imr);
2044	__napi_schedule(&sc->napi);
2045	/* Depend on the exit from poll to reenable intr */
2046	}
2047	else {
2048	/* may leave some packets behind */
2049	sbdma_rx_process(sc,&(sc->sbm_rxdma),
2050	SBMAC_MAX_RXDESCR * 2, 0);
2051	}
2052	}
2053	return IRQ_RETVAL(handled);
2054	}
2055
2056	/**********************************************************************
2057	* SBMAC_START_TX(skb,dev)
2058	*
2059	* Start output on the specified interface. Basically, we
2060	* queue as many buffers as we can until the ring fills up, or
2061	* we run off the end of the queue, whichever comes first.
2062	*
2063	* Input parameters:
2064	*
2065	*
2066	* Return value:
2067	* nothing
2068	********************************************************************* */
2069	static int sbmac_start_tx(struct sk_buff skb, struct net_device dev)
2070	{
2071	struct sbmac_softc *sc = netdev_priv(dev);
2072	unsigned long flags;
2073
2074	/* lock eth irq */
2075	spin_lock_irqsave(&sc->sbm_lock, flags);
2076
2077	/*
2078	* Put the buffer on the transmit ring. If we
2079	* don't have room, stop the queue.
2080	*/
2081
2082	if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2083	/* XXX save skb that we could not send */
2084	netif_stop_queue(dev);
2085	spin_unlock_irqrestore(&sc->sbm_lock, flags);
2086
2087	return NETDEV_TX_BUSY;
2088	}
2089
2090	dev->trans_start = jiffies;
2091
2092	spin_unlock_irqrestore(&sc->sbm_lock, flags);
2093
2094	return 0;
2095	}
2096
2097	/**********************************************************************
2098	* SBMAC_SETMULTI(sc)
2099	*
2100	* Reprogram the multicast table into the hardware, given
2101	* the list of multicasts associated with the interface
2102	* structure.
2103	*
2104	* Input parameters:
2105	* sc - softc
2106	*
2107	* Return value:
2108	* nothing
2109	********************************************************************* */
2110
2111	static void sbmac_setmulti(struct sbmac_softc *sc)
2112	{
2113	uint64_t reg;
2114	void __iomem *port;
2115	int idx;
2116	struct dev_mc_list *mclist;
2117	struct net_device *dev = sc->sbm_dev;
2118
2119	/*
2120	* Clear out entire multicast table. We do this by nuking
2121	* the entire hash table and all the direct matches except
2122	* the first one, which is used for our station address
2123	*/
2124
2125	for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2126	port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2127	__raw_writeq(0, port);
2128	}
2129
2130	for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2131	port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2132	__raw_writeq(0, port);
2133	}
2134
2135	/*
2136	* Clear the filter to say we don't want any multicasts.
2137	*/
2138
2139	reg = __raw_readq(sc->sbm_rxfilter);
2140	reg &= ~(M_MAC_MCAST_INV \| M_MAC_MCAST_EN);
2141	__raw_writeq(reg, sc->sbm_rxfilter);
2142
2143	if (dev->flags & IFF_ALLMULTI) {
2144	/*
2145	* Enable ALL multicasts. Do this by inverting the
2146	* multicast enable bit.
2147	*/
2148	reg = __raw_readq(sc->sbm_rxfilter);
2149	reg \|= (M_MAC_MCAST_INV \| M_MAC_MCAST_EN);
2150	__raw_writeq(reg, sc->sbm_rxfilter);
2151	return;
2152	}
2153
2154
2155	/*
2156	* Progam new multicast entries. For now, only use the
2157	* perfect filter. In the future we'll need to use the
2158	* hash filter if the perfect filter overflows
2159	*/
2160
2161	/* XXX only using perfect filter for now, need to use hash
2162	* XXX if the table overflows */
2163
2164	idx = 1; /* skip station address */
2165	mclist = dev->mc_list;
2166	while (mclist && (idx < MAC_ADDR_COUNT)) {
2167	reg = sbmac_addr2reg(mclist->dmi_addr);
2168	port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2169	__raw_writeq(reg, port);
2170	idx++;
2171	mclist = mclist->next;
2172	}
2173
2174	/*
2175	* Enable the "accept multicast bits" if we programmed at least one
2176	* multicast.
2177	*/
2178
2179	if (idx > 1) {
2180	reg = __raw_readq(sc->sbm_rxfilter);
2181	reg \|= M_MAC_MCAST_EN;
2182	__raw_writeq(reg, sc->sbm_rxfilter);
2183	}
2184	}
2185
2186	#if defined(SBMAC_ETH0_HWADDR) \|\| defined(SBMAC_ETH1_HWADDR) \|\| defined(SBMAC_ETH2_HWADDR) \|\| defined(SBMAC_ETH3_HWADDR)
2187	/**********************************************************************
2188	* SBMAC_PARSE_XDIGIT(str)
2189	*
2190	* Parse a hex digit, returning its value
2191	*
2192	* Input parameters:
2193	* str - character
2194	*
2195	* Return value:
2196	* hex value, or -1 if invalid
2197	********************************************************************* */
2198
2199	static int sbmac_parse_xdigit(char str)
2200	{
2201	int digit;
2202
2203	if ((str >= '0') && (str <= '9'))
2204	digit = str - '0';
2205	else if ((str >= 'a') && (str <= 'f'))
2206	digit = str - 'a' + 10;
2207	else if ((str >= 'A') && (str <= 'F'))
2208	digit = str - 'A' + 10;
2209	else
2210	return -1;
2211
2212	return digit;
2213	}
2214
2215	/**********************************************************************
2216	* SBMAC_PARSE_HWADDR(str,hwaddr)
2217	*
2218	* Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2219	* Ethernet address.
2220	*
2221	* Input parameters:
2222	* str - string
2223	* hwaddr - pointer to hardware address
2224	*
2225	* Return value:
2226	* 0 if ok, else -1
2227	********************************************************************* */
2228
2229	static int sbmac_parse_hwaddr(char str, unsigned char hwaddr)
2230	{
2231	int digit1,digit2;
2232	int idx = 6;
2233
2234	while (*str && (idx > 0)) {
2235	digit1 = sbmac_parse_xdigit(*str);
2236	if (digit1 < 0)
2237	return -1;
2238	str++;
2239	if (!*str)
2240	return -1;
2241
2242	if ((str == ':') \|\| (str == '-')) {
2243	digit2 = digit1;
2244	digit1 = 0;
2245	}
2246	else {
2247	digit2 = sbmac_parse_xdigit(*str);
2248	if (digit2 < 0)
2249	return -1;
2250	str++;
2251	}
2252
2253	*hwaddr++ = (digit1 << 4) \| digit2;
2254	idx--;
2255
2256	if (*str == '-')
2257	str++;
2258	if (*str == ':')
2259	str++;
2260	}
2261	return 0;
2262	}
2263	#endif
2264
2265	static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2266	{
2267	if (new_mtu > ENET_PACKET_SIZE)
2268	return -EINVAL;
2269	_dev->mtu = new_mtu;
2270	pr_info("changing the mtu to %d\n", new_mtu);
2271	return 0;
2272	}
2273
2274	static const struct net_device_ops sbmac_netdev_ops = {
2275	.ndo_open = sbmac_open,
2276	.ndo_stop = sbmac_close,
2277	.ndo_start_xmit = sbmac_start_tx,
2278	.ndo_set_multicast_list = sbmac_set_rx_mode,
2279	.ndo_tx_timeout = sbmac_tx_timeout,
2280	.ndo_do_ioctl = sbmac_mii_ioctl,
2281	.ndo_change_mtu = sb1250_change_mtu,
2282	.ndo_validate_addr = eth_validate_addr,
2283	.ndo_set_mac_address = eth_mac_addr,
2284	#ifdef CONFIG_NET_POLL_CONTROLLER
2285	.ndo_poll_controller = sbmac_netpoll,
2286	#endif
2287	};
2288
2289	/**********************************************************************
2290	* SBMAC_INIT(dev)
2291	*
2292	* Attach routine - init hardware and hook ourselves into linux
2293	*
2294	* Input parameters:
2295	* dev - net_device structure
2296	*
2297	* Return value:
2298	* status
2299	********************************************************************* */
2300
2301	static int sbmac_init(struct platform_device *pldev, long long base)
2302	{
2303	struct net_device *dev = dev_get_drvdata(&pldev->dev);
2304	int idx = pldev->id;
2305	struct sbmac_softc *sc = netdev_priv(dev);
2306	unsigned char *eaddr;
2307	uint64_t ea_reg;
2308	int i;
2309	int err;
2310
2311	sc->sbm_dev = dev;
2312	sc->sbe_idx = idx;
2313
2314	eaddr = sc->sbm_hwaddr;
2315
2316	/*
2317	* Read the ethernet address. The firmware left this programmed
2318	* for us in the ethernet address register for each mac.
2319	*/
2320
2321	ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2322	__raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2323	for (i = 0; i < 6; i++) {
2324	eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2325	ea_reg >>= 8;
2326	}
2327
2328	for (i = 0; i < 6; i++) {
2329	dev->dev_addr[i] = eaddr[i];
2330	}
2331
2332	/*
2333	* Initialize context (get pointers to registers and stuff), then
2334	* allocate the memory for the descriptor tables.
2335	*/
2336
2337	sbmac_initctx(sc);
2338
2339	/*
2340	* Set up Linux device callins
2341	*/
2342
2343	spin_lock_init(&(sc->sbm_lock));
2344
2345	dev->netdev_ops = &sbmac_netdev_ops;
2346	dev->watchdog_timeo = TX_TIMEOUT;
2347
2348	netif_napi_add(dev, &sc->napi, sbmac_poll, 16);
2349
2350	dev->irq = UNIT_INT(idx);
2351
2352	/* This is needed for PASS2 for Rx H/W checksum feature */
2353	sbmac_set_iphdr_offset(sc);
2354
2355	sc->mii_bus = mdiobus_alloc();
2356	if (sc->mii_bus == NULL) {
2357	sbmac_uninitctx(sc);
2358	return -ENOMEM;
2359	}
2360
2361	err = register_netdev(dev);
2362	if (err) {
2363	printk(KERN_ERR "%s.%d: unable to register netdev\n",
2364	sbmac_string, idx);
2365	mdiobus_free(sc->mii_bus);
2366	sbmac_uninitctx(sc);
2367	return err;
2368	}
2369
2370	pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name);
2371
2372	if (sc->rx_hw_checksum == ENABLE)
2373	pr_info("%s: enabling TCP rcv checksum\n", dev->name);
2374
2375	/*
2376	* Display Ethernet address (this is called during the config
2377	* process so we need to finish off the config message that
2378	* was being displayed)
2379	*/
2380	pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n",
2381	dev->name, base, eaddr);
2382
2383	sc->mii_bus->name = sbmac_mdio_string;
2384	snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%x", idx);
2385	sc->mii_bus->priv = sc;
2386	sc->mii_bus->read = sbmac_mii_read;
2387	sc->mii_bus->write = sbmac_mii_write;
2388	sc->mii_bus->irq = sc->phy_irq;
2389	for (i = 0; i < PHY_MAX_ADDR; ++i)
2390	sc->mii_bus->irq[i] = SBMAC_PHY_INT;
2391
2392	sc->mii_bus->parent = &pldev->dev;
2393	dev_set_drvdata(&pldev->dev, sc->mii_bus);
2394
2395	return 0;
2396	}
2397
2398
2399	static int sbmac_open(struct net_device *dev)
2400	{
2401	struct sbmac_softc *sc = netdev_priv(dev);
2402	int err;
2403
2404	if (debug > 1)
2405	pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2406
2407	/*
2408	* map/route interrupt (clear status first, in case something
2409	* weird is pending; we haven't initialized the mac registers
2410	* yet)
2411	*/
2412
2413	__raw_readq(sc->sbm_isr);
2414	err = request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev);
2415	if (err) {
2416	printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name,
2417	dev->irq);
2418	goto out_err;
2419	}
2420
2421	/*
2422	* Probe PHY address
2423	*/
2424	err = mdiobus_register(sc->mii_bus);
2425	if (err) {
2426	printk(KERN_ERR "%s: unable to register MDIO bus\n",
2427	dev->name);
2428	goto out_unirq;
2429	}
2430
2431	sc->sbm_speed = sbmac_speed_none;
2432	sc->sbm_duplex = sbmac_duplex_none;
2433	sc->sbm_fc = sbmac_fc_none;
2434	sc->sbm_pause = -1;
2435	sc->sbm_link = 0;
2436
2437	/*
2438	* Attach to the PHY
2439	*/
2440	err = sbmac_mii_probe(dev);
2441	if (err)
2442	goto out_unregister;
2443
2444	/*
2445	* Turn on the channel
2446	*/
2447
2448	sbmac_set_channel_state(sc,sbmac_state_on);
2449
2450	netif_start_queue(dev);
2451
2452	sbmac_set_rx_mode(dev);
2453
2454	phy_start(sc->phy_dev);
2455
2456	napi_enable(&sc->napi);
2457
2458	return 0;
2459
2460	out_unregister:
2461	mdiobus_unregister(sc->mii_bus);
2462
2463	out_unirq:
2464	free_irq(dev->irq, dev);
2465
2466	out_err:
2467	return err;
2468	}
2469
2470	static int sbmac_mii_probe(struct net_device *dev)
2471	{
2472	struct sbmac_softc *sc = netdev_priv(dev);
2473	struct phy_device *phy_dev;
2474	int i;
2475
2476	for (i = 0; i < PHY_MAX_ADDR; i++) {
2477	phy_dev = sc->mii_bus->phy_map[i];
2478	if (phy_dev)
2479	break;
2480	}
2481	if (!phy_dev) {
2482	printk(KERN_ERR "%s: no PHY found\n", dev->name);
2483	return -ENXIO;
2484	}
2485
2486	phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &sbmac_mii_poll, 0,
2487	PHY_INTERFACE_MODE_GMII);
2488	if (IS_ERR(phy_dev)) {
2489	printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
2490	return PTR_ERR(phy_dev);
2491	}
2492
2493	/* Remove any features not supported by the controller */
2494	phy_dev->supported &= SUPPORTED_10baseT_Half \|
2495	SUPPORTED_10baseT_Full \|
2496	SUPPORTED_100baseT_Half \|
2497	SUPPORTED_100baseT_Full \|
2498	SUPPORTED_1000baseT_Half \|
2499	SUPPORTED_1000baseT_Full \|
2500	SUPPORTED_Autoneg \|
2501	SUPPORTED_MII \|
2502	SUPPORTED_Pause \|
2503	SUPPORTED_Asym_Pause;
2504	phy_dev->advertising = phy_dev->supported;
2505
2506	pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2507	dev->name, phy_dev->drv->name,
2508	dev_name(&phy_dev->dev), phy_dev->irq);
2509
2510	sc->phy_dev = phy_dev;
2511
2512	return 0;
2513	}
2514
2515
2516	static void sbmac_mii_poll(struct net_device *dev)
2517	{
2518	struct sbmac_softc *sc = netdev_priv(dev);
2519	struct phy_device *phy_dev = sc->phy_dev;
2520	unsigned long flags;
2521	enum sbmac_fc fc;
2522	int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg;
2523
2524	link_chg = (sc->sbm_link != phy_dev->link);
2525	speed_chg = (sc->sbm_speed != phy_dev->speed);
2526	duplex_chg = (sc->sbm_duplex != phy_dev->duplex);
2527	pause_chg = (sc->sbm_pause != phy_dev->pause);
2528
2529	if (!link_chg && !speed_chg && !duplex_chg && !pause_chg)
2530	return; /* Hmmm... */
2531
2532	if (!phy_dev->link) {
2533	if (link_chg) {
2534	sc->sbm_link = phy_dev->link;
2535	sc->sbm_speed = sbmac_speed_none;
2536	sc->sbm_duplex = sbmac_duplex_none;
2537	sc->sbm_fc = sbmac_fc_disabled;
2538	sc->sbm_pause = -1;
2539	pr_info("%s: link unavailable\n", dev->name);
2540	}
2541	return;
2542	}
2543
2544	if (phy_dev->duplex == DUPLEX_FULL) {
2545	if (phy_dev->pause)
2546	fc = sbmac_fc_frame;
2547	else
2548	fc = sbmac_fc_disabled;
2549	} else
2550	fc = sbmac_fc_collision;
2551	fc_chg = (sc->sbm_fc != fc);
2552
2553	pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed,
2554	phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H');
2555
2556	spin_lock_irqsave(&sc->sbm_lock, flags);
2557
2558	sc->sbm_speed = phy_dev->speed;
2559	sc->sbm_duplex = phy_dev->duplex;
2560	sc->sbm_fc = fc;
2561	sc->sbm_pause = phy_dev->pause;
2562	sc->sbm_link = phy_dev->link;
2563
2564	if ((speed_chg \|\| duplex_chg \|\| fc_chg) &&
2565	sc->sbm_state != sbmac_state_off) {
2566	/*
2567	* something changed, restart the channel
2568	*/
2569	if (debug > 1)
2570	pr_debug("%s: restarting channel "
2571	"because PHY state changed\n", dev->name);
2572	sbmac_channel_stop(sc);
2573	sbmac_channel_start(sc);
2574	}
2575
2576	spin_unlock_irqrestore(&sc->sbm_lock, flags);
2577	}
2578
2579
2580	static void sbmac_tx_timeout (struct net_device *dev)
2581	{
2582	struct sbmac_softc *sc = netdev_priv(dev);
2583	unsigned long flags;
2584
2585	spin_lock_irqsave(&sc->sbm_lock, flags);
2586
2587
2588	dev->trans_start = jiffies;
2589	dev->stats.tx_errors++;
2590
2591	spin_unlock_irqrestore(&sc->sbm_lock, flags);
2592
2593	printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2594	}
2595
2596
2597
2598
2599	static void sbmac_set_rx_mode(struct net_device *dev)
2600	{
2601	unsigned long flags;
2602	struct sbmac_softc *sc = netdev_priv(dev);
2603
2604	spin_lock_irqsave(&sc->sbm_lock, flags);
2605	if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2606	/*
2607	* Promiscuous changed.
2608	*/
2609
2610	if (dev->flags & IFF_PROMISC) {
2611	sbmac_promiscuous_mode(sc,1);
2612	}
2613	else {
2614	sbmac_promiscuous_mode(sc,0);
2615	}
2616	}
2617	spin_unlock_irqrestore(&sc->sbm_lock, flags);
2618
2619	/*
2620	* Program the multicasts. Do this every time.
2621	*/
2622
2623	sbmac_setmulti(sc);
2624
2625	}
2626
2627	static int sbmac_mii_ioctl(struct net_device dev, struct ifreq rq, int cmd)
2628	{
2629	struct sbmac_softc *sc = netdev_priv(dev);
2630
2631	if (!netif_running(dev) \|\| !sc->phy_dev)
2632	return -EINVAL;
2633
2634	return phy_mii_ioctl(sc->phy_dev, if_mii(rq), cmd);
2635	}
2636
2637	static int sbmac_close(struct net_device *dev)
2638	{
2639	struct sbmac_softc *sc = netdev_priv(dev);
2640
2641	napi_disable(&sc->napi);
2642
2643	phy_stop(sc->phy_dev);
2644
2645	sbmac_set_channel_state(sc, sbmac_state_off);
2646
2647	netif_stop_queue(dev);
2648
2649	if (debug > 1)
2650	pr_debug("%s: Shutting down ethercard\n", dev->name);
2651
2652	phy_disconnect(sc->phy_dev);
2653	sc->phy_dev = NULL;
2654
2655	mdiobus_unregister(sc->mii_bus);
2656
2657	free_irq(dev->irq, dev);
2658
2659	sbdma_emptyring(&(sc->sbm_txdma));
2660	sbdma_emptyring(&(sc->sbm_rxdma));
2661
2662	return 0;
2663	}
2664
2665	static int sbmac_poll(struct napi_struct *napi, int budget)
2666	{
2667	struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi);
2668	struct net_device *dev = sc->sbm_dev;
2669	int work_done;
2670
2671	work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1);
2672	sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2673
2674	if (work_done < budget) {
2675	napi_complete(napi);
2676
2677	#ifdef CONFIG_SBMAC_COALESCE
2678	__raw_writeq(((M_MAC_INT_EOP_COUNT \| M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) \|
2679	((M_MAC_INT_EOP_COUNT \| M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2680	sc->sbm_imr);
2681	#else
2682	__raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) \|
2683	(M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2684	#endif
2685	}
2686
2687	return work_done;
2688	}
2689
2690
2691	static int __init sbmac_probe(struct platform_device *pldev)
2692	{
2693	struct net_device *dev;
2694	struct sbmac_softc *sc;
2695	void __iomem *sbm_base;
2696	struct resource *res;
2697	u64 sbmac_orig_hwaddr;
2698	int err;
2699
2700	res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
2701	BUG_ON(!res);
2702	sbm_base = ioremap_nocache(res->start, res->end - res->start + 1);
2703	if (!sbm_base) {
2704	printk(KERN_ERR "%s: unable to map device registers\n",
2705	dev_name(&pldev->dev));
2706	err = -ENOMEM;
2707	goto out_out;
2708	}
2709
2710	/*
2711	* The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2712	* value for us by the firmware if we're going to use this MAC.
2713	* If we find a zero, skip this MAC.
2714	*/
2715	sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2716	pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev),
2717	sbmac_orig_hwaddr ? "" : "not ", (long long)res->start);
2718	if (sbmac_orig_hwaddr == 0) {
2719	err = 0;
2720	goto out_unmap;
2721	}
2722
2723	/*
2724	* Okay, cool. Initialize this MAC.
2725	*/
2726	dev = alloc_etherdev(sizeof(struct sbmac_softc));
2727	if (!dev) {
2728	printk(KERN_ERR "%s: unable to allocate etherdev\n",
2729	dev_name(&pldev->dev));
2730	err = -ENOMEM;
2731	goto out_unmap;
2732	}
2733
2734	dev_set_drvdata(&pldev->dev, dev);
2735	SET_NETDEV_DEV(dev, &pldev->dev);
2736
2737	sc = netdev_priv(dev);
2738	sc->sbm_base = sbm_base;
2739
2740	err = sbmac_init(pldev, res->start);
2741	if (err)
2742	goto out_kfree;
2743
2744	return 0;
2745
2746	out_kfree:
2747	free_netdev(dev);
2748	__raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR);
2749
2750	out_unmap:
2751	iounmap(sbm_base);
2752
2753	out_out:
2754	return err;
2755	}
2756
2757	static int __exit sbmac_remove(struct platform_device *pldev)
2758	{
2759	struct net_device *dev = dev_get_drvdata(&pldev->dev);
2760	struct sbmac_softc *sc = netdev_priv(dev);
2761
2762	unregister_netdev(dev);
2763	sbmac_uninitctx(sc);
2764	mdiobus_free(sc->mii_bus);
2765	iounmap(sc->sbm_base);
2766	free_netdev(dev);
2767
2768	return 0;
2769	}
2770
2771
2772	static struct platform_device **sbmac_pldev;
2773	static int sbmac_max_units;
2774
2775	#if defined(SBMAC_ETH0_HWADDR) \|\| defined(SBMAC_ETH1_HWADDR) \|\| defined(SBMAC_ETH2_HWADDR) \|\| defined(SBMAC_ETH3_HWADDR)
2776	static void __init sbmac_setup_hwaddr(int idx, char *addr)
2777	{
2778	void __iomem *sbm_base;
2779	unsigned long start, end;
2780	uint8_t eaddr[6];
2781	uint64_t val;
2782
2783	if (idx >= sbmac_max_units)
2784	return;
2785
2786	start = A_MAC_CHANNEL_BASE(idx);
2787	end = A_MAC_CHANNEL_BASE(idx + 1) - 1;
2788
2789	sbm_base = ioremap_nocache(start, end - start + 1);
2790	if (!sbm_base) {
2791	printk(KERN_ERR "%s: unable to map device registers\n",
2792	sbmac_string);
2793	return;
2794	}
2795
2796	sbmac_parse_hwaddr(addr, eaddr);
2797	val = sbmac_addr2reg(eaddr);
2798	__raw_writeq(val, sbm_base + R_MAC_ETHERNET_ADDR);
2799	val = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR);
2800
2801	iounmap(sbm_base);
2802	}
2803	#endif
2804
2805	static int __init sbmac_platform_probe_one(int idx)
2806	{
2807	struct platform_device *pldev;
2808	struct {
2809	struct resource r;
2810	char name[strlen(sbmac_pretty) + 4];
2811	} *res;
2812	int err;
2813
2814	res = kzalloc(sizeof(*res), GFP_KERNEL);
2815	if (!res) {
2816	printk(KERN_ERR "%s.%d: unable to allocate memory\n",
2817	sbmac_string, idx);
2818	err = -ENOMEM;
2819	goto out_err;
2820	}
2821
2822	/*
2823	* This is the base address of the MAC.
2824	*/
2825	snprintf(res->name, sizeof(res->name), "%s %d", sbmac_pretty, idx);
2826	res->r.name = res->name;
2827	res->r.flags = IORESOURCE_MEM;
2828	res->r.start = A_MAC_CHANNEL_BASE(idx);
2829	res->r.end = A_MAC_CHANNEL_BASE(idx + 1) - 1;
2830
2831	pldev = platform_device_register_simple(sbmac_string, idx, &res->r, 1);
2832	if (IS_ERR(pldev)) {
2833	printk(KERN_ERR "%s.%d: unable to register platform device\n",
2834	sbmac_string, idx);
2835	err = PTR_ERR(pldev);
2836	goto out_kfree;
2837	}
2838
2839	if (!pldev->dev.driver) {
2840	err = 0; /* No hardware at this address. */
2841	goto out_unregister;
2842	}
2843
2844	sbmac_pldev[idx] = pldev;
2845	return 0;
2846
2847	out_unregister:
2848	platform_device_unregister(pldev);
2849
2850	out_kfree:
2851	kfree(res);
2852
2853	out_err:
2854	return err;
2855	}
2856
2857	static void __init sbmac_platform_probe(void)
2858	{
2859	int i;
2860
2861	/* Set the number of available units based on the SOC type. */
2862	switch (soc_type) {
2863	case K_SYS_SOC_TYPE_BCM1250:
2864	case K_SYS_SOC_TYPE_BCM1250_ALT:
2865	sbmac_max_units = 3;
2866	break;
2867	case K_SYS_SOC_TYPE_BCM1120:
2868	case K_SYS_SOC_TYPE_BCM1125:
2869	case K_SYS_SOC_TYPE_BCM1125H:
2870	case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2871	sbmac_max_units = 2;
2872	break;
2873	case K_SYS_SOC_TYPE_BCM1x55:
2874	case K_SYS_SOC_TYPE_BCM1x80:
2875	sbmac_max_units = 4;
2876	break;
2877	default:
2878	return; /* none */
2879	}
2880
2881	/*
2882	* For bringup when not using the firmware, we can pre-fill
2883	* the MAC addresses using the environment variables
2884	* specified in this file (or maybe from the config file?)
2885	*/
2886	#ifdef SBMAC_ETH0_HWADDR
2887	sbmac_setup_hwaddr(0, SBMAC_ETH0_HWADDR);
2888	#endif
2889	#ifdef SBMAC_ETH1_HWADDR
2890	sbmac_setup_hwaddr(1, SBMAC_ETH1_HWADDR);
2891	#endif
2892	#ifdef SBMAC_ETH2_HWADDR
2893	sbmac_setup_hwaddr(2, SBMAC_ETH2_HWADDR);
2894	#endif
2895	#ifdef SBMAC_ETH3_HWADDR
2896	sbmac_setup_hwaddr(3, SBMAC_ETH3_HWADDR);
2897	#endif
2898
2899	sbmac_pldev = kcalloc(sbmac_max_units, sizeof(*sbmac_pldev),
2900	GFP_KERNEL);
2901	if (!sbmac_pldev) {
2902	printk(KERN_ERR "%s: unable to allocate memory\n",
2903	sbmac_string);
2904	return;
2905	}
2906
2907	/*
2908	* Walk through the Ethernet controllers and find
2909	* those who have their MAC addresses set.
2910	*/
2911	for (i = 0; i < sbmac_max_units; i++)
2912	if (sbmac_platform_probe_one(i))
2913	break;
2914	}
2915
2916
2917	static void __exit sbmac_platform_cleanup(void)
2918	{
2919	int i;
2920
2921	for (i = 0; i < sbmac_max_units; i++)
2922	platform_device_unregister(sbmac_pldev[i]);
2923	kfree(sbmac_pldev);
2924	}
2925
2926
2927	static struct platform_driver sbmac_driver = {
2928	.probe = sbmac_probe,
2929	.remove = __exit_p(sbmac_remove),
2930	.driver = {
2931	.name = sbmac_string,
2932	},
2933	};
2934
2935	static int __init sbmac_init_module(void)
2936	{
2937	int err;
2938
2939	err = platform_driver_register(&sbmac_driver);
2940	if (err)
2941	return err;
2942
2943	sbmac_platform_probe();
2944
2945	return err;
2946	}
2947
2948	static void __exit sbmac_cleanup_module(void)
2949	{
2950	sbmac_platform_cleanup();
2951	platform_driver_unregister(&sbmac_driver);
2952	}
2953
2954	module_init(sbmac_init_module);
2955	module_exit(sbmac_cleanup_module);
2956

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