Root/drivers/net/sis900.h

1/* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
2 * Copyright 1999 Silicon Integrated System Corporation
3 * References:
4 * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
5 * preliminary Rev. 1.0 Jan. 14, 1998
6 * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
7 * preliminary Rev. 1.0 Nov. 10, 1998
8 * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
9 * preliminary Rev. 1.0 Jan. 18, 1998
10 * http://www.sis.com.tw/support/databook.htm
11 */
12
13/*
14 * SiS 7016 and SiS 900 ethernet controller registers
15 */
16
17/* The I/O extent, SiS 900 needs 256 bytes of io address */
18#define SIS900_TOTAL_SIZE 0x100
19
20/* Symbolic offsets to registers. */
21enum sis900_registers {
22    cr=0x0, //Command Register
23    cfg=0x4, //Configuration Register
24    mear=0x8, //EEPROM Access Register
25    ptscr=0xc, //PCI Test Control Register
26    isr=0x10, //Interrupt Status Register
27    imr=0x14, //Interrupt Mask Register
28    ier=0x18, //Interrupt Enable Register
29    epar=0x18, //Enhanced PHY Access Register
30    txdp=0x20, //Transmit Descriptor Pointer Register
31        txcfg=0x24, //Transmit Configuration Register
32        rxdp=0x30, //Receive Descriptor Pointer Register
33        rxcfg=0x34, //Receive Configuration Register
34        flctrl=0x38, //Flow Control Register
35        rxlen=0x3c, //Receive Packet Length Register
36        rfcr=0x48, //Receive Filter Control Register
37        rfdr=0x4C, //Receive Filter Data Register
38        pmctrl=0xB0, //Power Management Control Register
39        pmer=0xB4 //Power Management Wake-up Event Register
40};
41
42/* Symbolic names for bits in various registers */
43enum sis900_command_register_bits {
44    RELOAD = 0x00000400, ACCESSMODE = 0x00000200,/* ET */
45    RESET = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020,
46    TxRESET = 0x00000010, RxDIS = 0x00000008, RxENA = 0x00000004,
47    TxDIS = 0x00000002, TxENA = 0x00000001
48};
49
50enum sis900_configuration_register_bits {
51    DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080,
52    SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
53    PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
54    /* 635 & 900B Specific */
55    RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
56    EDB_MASTER_EN = 0x00002000
57};
58
59enum sis900_eeprom_access_reigster_bits {
60    MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
61    EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
62    EEDI = 0x00000001
63};
64
65enum sis900_interrupt_register_bits {
66    WKEVT = 0x10000000, TxPAUSEEND = 0x08000000, TxPAUSE = 0x04000000,
67    TxRCMP = 0x02000000, RxRCMP = 0x01000000, DPERR = 0x00800000,
68    SSERR = 0x00400000, RMABT = 0x00200000, RTABT = 0x00100000,
69    RxSOVR = 0x00010000, HIBERR = 0x00008000, SWINT = 0x00001000,
70    MIBINT = 0x00000800, TxURN = 0x00000400, TxIDLE = 0x00000200,
71    TxERR = 0x00000100, TxDESC = 0x00000080, TxOK = 0x00000040,
72    RxORN = 0x00000020, RxIDLE = 0x00000010, RxEARLY = 0x00000008,
73    RxERR = 0x00000004, RxDESC = 0x00000002, RxOK = 0x00000001
74};
75
76enum sis900_interrupt_enable_reigster_bits {
77    IE = 0x00000001
78};
79
80/* maximum dma burst for transmission and receive */
81#define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */
82#define TxMXDMA_shift 20
83#define RxMXDMA_shift 20
84
85enum sis900_tx_rx_dma{
86    DMA_BURST_512 = 0, DMA_BURST_64 = 5
87};
88
89/* transmit FIFO thresholds */
90#define TX_FILL_THRESH 16 /* 1/4 FIFO size */
91#define TxFILLT_shift 8
92#define TxDRNT_shift 0
93#define TxDRNT_100 48 /* 3/4 FIFO size */
94#define TxDRNT_10 16 /* 1/2 FIFO size */
95
96enum sis900_transmit_config_register_bits {
97    TxCSI = 0x80000000, TxHBI = 0x40000000, TxMLB = 0x20000000,
98    TxATP = 0x10000000, TxIFG = 0x0C000000, TxFILLT = 0x00003F00,
99    TxDRNT = 0x0000003F
100};
101
102/* recevie FIFO thresholds */
103#define RxDRNT_shift 1
104#define RxDRNT_100 16 /* 1/2 FIFO size */
105#define RxDRNT_10 24 /* 3/4 FIFO size */
106
107enum sis900_reveive_config_register_bits {
108    RxAEP = 0x80000000, RxARP = 0x40000000, RxATX = 0x10000000,
109    RxAJAB = 0x08000000, RxDRNT = 0x0000007F
110};
111
112#define RFAA_shift 28
113#define RFADDR_shift 16
114
115enum sis900_receive_filter_control_register_bits {
116    RFEN = 0x80000000, RFAAB = 0x40000000, RFAAM = 0x20000000,
117    RFAAP = 0x10000000, RFPromiscuous = (RFAAB|RFAAM|RFAAP)
118};
119
120enum sis900_reveive_filter_data_mask {
121    RFDAT = 0x0000FFFF
122};
123
124/* EEPROM Addresses */
125enum sis900_eeprom_address {
126    EEPROMSignature = 0x00, EEPROMVendorID = 0x02, EEPROMDeviceID = 0x03,
127    EEPROMMACAddr = 0x08, EEPROMChecksum = 0x0b
128};
129
130/* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
131enum sis900_eeprom_command {
132    EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0,
133    EEwriteEnable = 0x0130, EEwriteDisable = 0x0100,
134    EEeraseAll = 0x0120, EEwriteAll = 0x0110,
135    EEaddrMask = 0x013F, EEcmdShift = 16
136};
137
138/* For SiS962 or SiS963, request the eeprom software access */
139enum sis96x_eeprom_command {
140    EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
141};
142
143/* PCI Registers */
144enum sis900_pci_registers {
145    CFGPMC = 0x40,
146    CFGPMCSR = 0x44
147};
148
149/* Power management capabilities bits */
150enum sis900_cfgpmc_register_bits {
151    PMVER = 0x00070000,
152    DSI = 0x00100000,
153    PMESP = 0xf8000000
154};
155
156enum sis900_pmesp_bits {
157    PME_D0 = 0x1,
158    PME_D1 = 0x2,
159    PME_D2 = 0x4,
160    PME_D3H = 0x8,
161    PME_D3C = 0x10
162};
163
164/* Power management control/status bits */
165enum sis900_cfgpmcsr_register_bits {
166    PMESTS = 0x00004000,
167    PME_EN = 0x00000100, // Power management enable
168    PWR_STA = 0x00000003 // Current power state
169};
170
171/* Wake-on-LAN support. */
172enum sis900_power_management_control_register_bits {
173    LINKLOSS = 0x00000001,
174    LINKON = 0x00000002,
175    MAGICPKT = 0x00000400,
176    ALGORITHM = 0x00000800,
177    FRM1EN = 0x00100000,
178    FRM2EN = 0x00200000,
179    FRM3EN = 0x00400000,
180    FRM1ACS = 0x01000000,
181    FRM2ACS = 0x02000000,
182    FRM3ACS = 0x04000000,
183    WAKEALL = 0x40000000,
184    GATECLK = 0x80000000
185};
186
187/* Management Data I/O (mdio) frame */
188#define MIIread 0x6000
189#define MIIwrite 0x5002
190#define MIIpmdShift 7
191#define MIIregShift 2
192#define MIIcmdLen 16
193#define MIIcmdShift 16
194
195/* Buffer Descriptor Status*/
196enum sis900_buffer_status {
197    OWN = 0x80000000, MORE = 0x40000000, INTR = 0x20000000,
198    SUPCRC = 0x10000000, INCCRC = 0x10000000,
199    OK = 0x08000000, DSIZE = 0x00000FFF
200};
201/* Status for TX Buffers */
202enum sis900_tx_buffer_status {
203    ABORT = 0x04000000, UNDERRUN = 0x02000000, NOCARRIER = 0x01000000,
204    DEFERD = 0x00800000, EXCDEFER = 0x00400000, OWCOLL = 0x00200000,
205    EXCCOLL = 0x00100000, COLCNT = 0x000F0000
206};
207
208enum sis900_rx_bufer_status {
209    OVERRUN = 0x02000000, DEST = 0x00800000, BCAST = 0x01800000,
210    MCAST = 0x01000000, UNIMATCH = 0x00800000, TOOLONG = 0x00400000,
211    RUNT = 0x00200000, RXISERR = 0x00100000, CRCERR = 0x00080000,
212    FAERR = 0x00040000, LOOPBK = 0x00020000, RXCOL = 0x00010000
213};
214
215/* MII register offsets */
216enum mii_registers {
217    MII_CONTROL = 0x0000, MII_STATUS = 0x0001, MII_PHY_ID0 = 0x0002,
218    MII_PHY_ID1 = 0x0003, MII_ANADV = 0x0004, MII_ANLPAR = 0x0005,
219    MII_ANEXT = 0x0006
220};
221
222/* mii registers specific to SiS 900 */
223enum sis_mii_registers {
224    MII_CONFIG1 = 0x0010, MII_CONFIG2 = 0x0011, MII_STSOUT = 0x0012,
225    MII_MASK = 0x0013, MII_RESV = 0x0014
226};
227
228/* mii registers specific to ICS 1893 */
229enum ics_mii_registers {
230    MII_EXTCTRL = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
231    MII_EXTCTRL2 = 0x0013
232};
233
234/* mii registers specific to AMD 79C901 */
235enum amd_mii_registers {
236    MII_STATUS_SUMMARY = 0x0018
237};
238
239/* MII Control register bit definitions. */
240enum mii_control_register_bits {
241    MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
242    MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800,
243    MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000,
244    MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000
245};
246
247/* MII Status register bit */
248enum mii_status_register_bits {
249    MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002,
250    MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008,
251    MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020,
252    MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000,
253    MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000,
254    MII_STAT_CAN_T4 = 0x8000
255};
256
257#define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
258#define MII_ID1_MODEL 0x03F0 /* model number */
259#define MII_ID1_REV 0x000F /* model number */
260
261/* MII NWAY Register Bits ...
262   valid for the ANAR (Auto-Negotiation Advertisement) and
263   ANLPAR (Auto-Negotiation Link Partner) registers */
264enum mii_nway_register_bits {
265    MII_NWAY_NODE_SEL = 0x001f, MII_NWAY_CSMA_CD = 0x0001,
266    MII_NWAY_T = 0x0020, MII_NWAY_T_FDX = 0x0040,
267    MII_NWAY_TX = 0x0080, MII_NWAY_TX_FDX = 0x0100,
268    MII_NWAY_T4 = 0x0200, MII_NWAY_PAUSE = 0x0400,
269    MII_NWAY_RF = 0x2000, MII_NWAY_ACK = 0x4000,
270    MII_NWAY_NP = 0x8000
271};
272
273enum mii_stsout_register_bits {
274    MII_STSOUT_LINK_FAIL = 0x4000,
275    MII_STSOUT_SPD = 0x0080, MII_STSOUT_DPLX = 0x0040
276};
277
278enum mii_stsics_register_bits {
279    MII_STSICS_SPD = 0x8000, MII_STSICS_DPLX = 0x4000,
280    MII_STSICS_LINKSTS = 0x0001
281};
282
283enum mii_stssum_register_bits {
284    MII_STSSUM_LINK = 0x0008, MII_STSSUM_DPLX = 0x0004,
285    MII_STSSUM_AUTO = 0x0002, MII_STSSUM_SPD = 0x0001
286};
287
288enum sis900_revision_id {
289    SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81,
290    SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83,
291    SIS630ET_900_REV = 0x84, SIS635A_900_REV = 0x90,
292    SIS96x_900_REV = 0X91, SIS900B_900_REV = 0x03
293};
294
295enum sis630_revision_id {
296    SIS630A0 = 0x00, SIS630A1 = 0x01,
297    SIS630B0 = 0x10, SIS630B1 = 0x11
298};
299
300#define FDX_CAPABLE_DUPLEX_UNKNOWN 0
301#define FDX_CAPABLE_HALF_SELECTED 1
302#define FDX_CAPABLE_FULL_SELECTED 2
303
304#define HW_SPEED_UNCONFIG 0
305#define HW_SPEED_HOME 1
306#define HW_SPEED_10_MBPS 10
307#define HW_SPEED_100_MBPS 100
308#define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS)
309
310#define CRC_SIZE 4
311#define MAC_HEADER_SIZE 14
312
313#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
314#define MAX_FRAME_SIZE (1518 + 4)
315#else
316#define MAX_FRAME_SIZE 1518
317#endif /* CONFIG_VLAN_802_1Q */
318
319#define TX_BUF_SIZE (MAX_FRAME_SIZE+18)
320#define RX_BUF_SIZE (MAX_FRAME_SIZE+18)
321
322#define NUM_TX_DESC 16 /* Number of Tx descriptor registers. */
323#define NUM_RX_DESC 16 /* Number of Rx descriptor registers. */
324#define TX_TOTAL_SIZE NUM_TX_DESC*sizeof(BufferDesc)
325#define RX_TOTAL_SIZE NUM_RX_DESC*sizeof(BufferDesc)
326
327/* PCI stuff, should be move to pci.h */
328#define SIS630_VENDOR_ID 0x1039
329#define SIS630_DEVICE_ID 0x0630
330

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