Root/drivers/net/tc35815.c

1/*
2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
3 *
4 * Based on skelton.c by Donald Becker.
5 *
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
8 * -----<snip>-----
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15 * -----<snip>-----
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 *
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
23 */
24
25#ifdef TC35815_NAPI
26#define DRV_VERSION "1.37-NAPI"
27#else
28#define DRV_VERSION "1.37"
29#endif
30static const char *version = "tc35815.c:v" DRV_VERSION "\n";
31#define MODNAME "tc35815"
32
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/types.h>
36#include <linux/fcntl.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/in.h>
40#include <linux/if_vlan.h>
41#include <linux/slab.h>
42#include <linux/string.h>
43#include <linux/spinlock.h>
44#include <linux/errno.h>
45#include <linux/init.h>
46#include <linux/netdevice.h>
47#include <linux/etherdevice.h>
48#include <linux/skbuff.h>
49#include <linux/delay.h>
50#include <linux/pci.h>
51#include <linux/phy.h>
52#include <linux/workqueue.h>
53#include <linux/platform_device.h>
54#include <asm/io.h>
55#include <asm/byteorder.h>
56
57/* First, a few definitions that the brave might change. */
58
59#define GATHER_TXINT /* On-Demand Tx Interrupt */
60#define WORKAROUND_LOSTCAR
61#define WORKAROUND_100HALF_PROMISC
62/* #define TC35815_USE_PACKEDBUFFER */
63
64enum tc35815_chiptype {
65    TC35815CF = 0,
66    TC35815_NWU,
67    TC35815_TX4939,
68};
69
70/* indexed by tc35815_chiptype, above */
71static const struct {
72    const char *name;
73} chip_info[] __devinitdata = {
74    { "TOSHIBA TC35815CF 10/100BaseTX" },
75    { "TOSHIBA TC35815 with Wake on LAN" },
76    { "TOSHIBA TC35815/TX4939" },
77};
78
79static const struct pci_device_id tc35815_pci_tbl[] = {
80    {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
81    {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
82    {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
83    {0,}
84};
85MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
86
87/* see MODULE_PARM_DESC */
88static struct tc35815_options {
89    int speed;
90    int duplex;
91} options;
92
93/*
94 * Registers
95 */
96struct tc35815_regs {
97    __u32 DMA_Ctl; /* 0x00 */
98    __u32 TxFrmPtr;
99    __u32 TxThrsh;
100    __u32 TxPollCtr;
101    __u32 BLFrmPtr;
102    __u32 RxFragSize;
103    __u32 Int_En;
104    __u32 FDA_Bas;
105    __u32 FDA_Lim; /* 0x20 */
106    __u32 Int_Src;
107    __u32 unused0[2];
108    __u32 PauseCnt;
109    __u32 RemPauCnt;
110    __u32 TxCtlFrmStat;
111    __u32 unused1;
112    __u32 MAC_Ctl; /* 0x40 */
113    __u32 CAM_Ctl;
114    __u32 Tx_Ctl;
115    __u32 Tx_Stat;
116    __u32 Rx_Ctl;
117    __u32 Rx_Stat;
118    __u32 MD_Data;
119    __u32 MD_CA;
120    __u32 CAM_Adr; /* 0x60 */
121    __u32 CAM_Data;
122    __u32 CAM_Ena;
123    __u32 PROM_Ctl;
124    __u32 PROM_Data;
125    __u32 Algn_Cnt;
126    __u32 CRC_Cnt;
127    __u32 Miss_Cnt;
128};
129
130/*
131 * Bit assignments
132 */
133/* DMA_Ctl bit asign ------------------------------------------------------- */
134#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
135#define DMA_RxAlign_1 0x00400000
136#define DMA_RxAlign_2 0x00800000
137#define DMA_RxAlign_3 0x00c00000
138#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
139#define DMA_IntMask 0x00040000 /* 1:Interupt mask */
140#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
141#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
142#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
143#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
144#define DMA_TestMode 0x00002000 /* 1:Test Mode */
145#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
146#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
147
148/* RxFragSize bit asign ---------------------------------------------------- */
149#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
150#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
151
152/* MAC_Ctl bit asign ------------------------------------------------------- */
153#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
154#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
155#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
156#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
157#define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
158#define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
159#define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
160#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
161#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
162#define MAC_Reset 0x00000004 /* 1:Software Reset */
163#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
164#define MAC_HaltReq 0x00000001 /* 1:Halt request */
165
166/* PROM_Ctl bit asign ------------------------------------------------------ */
167#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
168#define PROM_Read 0x00004000 /*10:Read operation */
169#define PROM_Write 0x00002000 /*01:Write operation */
170#define PROM_Erase 0x00006000 /*11:Erase operation */
171                      /*00:Enable or Disable Writting, */
172                      /* as specified in PROM_Addr. */
173#define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
174                      /*00xxxx: disable */
175
176/* CAM_Ctl bit asign ------------------------------------------------------- */
177#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
178#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
179                      /* accept other */
180#define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
181#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
182#define CAM_StationAcc 0x00000001 /* 1:unicast accept */
183
184/* CAM_Ena bit asign ------------------------------------------------------- */
185#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
186#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
187#define CAM_Ena_Bit(index) (1 << (index))
188#define CAM_ENTRY_DESTINATION 0
189#define CAM_ENTRY_SOURCE 1
190#define CAM_ENTRY_MACCTL 20
191
192/* Tx_Ctl bit asign -------------------------------------------------------- */
193#define Tx_En 0x00000001 /* 1:Transmit enable */
194#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
195#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
196#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
197#define Tx_FBack 0x00000010 /* 1:Fast Back-off */
198#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
199#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
200#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
201#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
202#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
203#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
204#define Tx_EnComp 0x00004000 /* 1:Enable Completion */
205
206/* Tx_Stat bit asign ------------------------------------------------------- */
207#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
208#define Tx_ExColl 0x00000010 /* Excessive Collision */
209#define Tx_TXDefer 0x00000020 /* Transmit Defered */
210#define Tx_Paused 0x00000040 /* Transmit Paused */
211#define Tx_IntTx 0x00000080 /* Interrupt on Tx */
212#define Tx_Under 0x00000100 /* Underrun */
213#define Tx_Defer 0x00000200 /* Deferral */
214#define Tx_NCarr 0x00000400 /* No Carrier */
215#define Tx_10Stat 0x00000800 /* 10Mbps Status */
216#define Tx_LateColl 0x00001000 /* Late Collision */
217#define Tx_TxPar 0x00002000 /* Tx Parity Error */
218#define Tx_Comp 0x00004000 /* Completion */
219#define Tx_Halted 0x00008000 /* Tx Halted */
220#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
221
222/* Rx_Ctl bit asign -------------------------------------------------------- */
223#define Rx_EnGood 0x00004000 /* 1:Enable Good */
224#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
225#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
226#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
227#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
228#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
229#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
230#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
231#define Rx_ShortEn 0x00000008 /* 1:Short Enable */
232#define Rx_LongEn 0x00000004 /* 1:Long Enable */
233#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
234#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
235
236/* Rx_Stat bit asign ------------------------------------------------------- */
237#define Rx_Halted 0x00008000 /* Rx Halted */
238#define Rx_Good 0x00004000 /* Rx Good */
239#define Rx_RxPar 0x00002000 /* Rx Parity Error */
240#define Rx_TypePkt 0x00001000 /* Rx Type Packet */
241#define Rx_LongErr 0x00000800 /* Rx Long Error */
242#define Rx_Over 0x00000400 /* Rx Overflow */
243#define Rx_CRCErr 0x00000200 /* Rx CRC Error */
244#define Rx_Align 0x00000100 /* Rx Alignment Error */
245#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
246#define Rx_IntRx 0x00000040 /* Rx Interrupt */
247#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
248#define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
249
250#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
251
252/* Int_En bit asign -------------------------------------------------------- */
253#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
254#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
255#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
256#define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
257#define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
258#define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
259#define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
260#define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
261#define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
262#define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
263#define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
264#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
265                      /* Exhausted Enable */
266
267/* Int_Src bit asign ------------------------------------------------------- */
268#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
269#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
270#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
271#define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
272#define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
273#define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
274#define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
275#define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
276#define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
277#define Int_SWInt 0x00000020 /* 1:Software request & Clear */
278#define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
279#define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
280#define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
281#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
282#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
283
284/* MD_CA bit asign --------------------------------------------------------- */
285#define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
286#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
287#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
288
289
290/*
291 * Descriptors
292 */
293
294/* Frame descripter */
295struct FDesc {
296    volatile __u32 FDNext;
297    volatile __u32 FDSystem;
298    volatile __u32 FDStat;
299    volatile __u32 FDCtl;
300};
301
302/* Buffer descripter */
303struct BDesc {
304    volatile __u32 BuffData;
305    volatile __u32 BDCtl;
306};
307
308#define FD_ALIGN 16
309
310/* Frame Descripter bit asign ---------------------------------------------- */
311#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
312#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
313#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
314#define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
315#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
316#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
317#define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
318#define FD_FrmOpt_Packing 0x04000000 /* Rx only */
319#define FD_CownsFD 0x80000000 /* FD Controller owner bit */
320#define FD_Next_EOL 0x00000001 /* FD EOL indicator */
321#define FD_BDCnt_SHIFT 16
322
323/* Buffer Descripter bit asign --------------------------------------------- */
324#define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
325#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
326#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
327#define BD_CownsBD 0x80000000 /* BD Controller owner bit */
328#define BD_RxBDID_SHIFT 16
329#define BD_RxBDSeqN_SHIFT 24
330
331
332/* Some useful constants. */
333#undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
334
335#ifdef NO_CHECK_CARRIER
336#define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
337    Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
338    Tx_En) /* maybe 0x7b01 */
339#else
340#define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
341    Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
342    Tx_En) /* maybe 0x7b01 */
343#endif
344#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
345    | Rx_EnCRCErr | Rx_EnAlign | Rx_StripCRC | Rx_RxEn) /* maybe 0x6f11 */
346#define INT_EN_CMD (Int_NRAbtEn | \
347    Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
348    Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
349    Int_STargAbtEn | \
350    Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
351#define DMA_CTL_CMD DMA_BURST_SIZE
352#define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
353
354/* Tuning parameters */
355#define DMA_BURST_SIZE 32
356#define TX_THRESHOLD 1024
357/* used threshold with packet max byte for low pci transfer ability.*/
358#define TX_THRESHOLD_MAX 1536
359/* setting threshold max value when overrun error occured this count. */
360#define TX_THRESHOLD_KEEP_LIMIT 10
361
362/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
363#ifdef TC35815_USE_PACKEDBUFFER
364#define FD_PAGE_NUM 2
365#define RX_BUF_NUM 8 /* >= 2 */
366#define RX_FD_NUM 250 /* >= 32 */
367#define TX_FD_NUM 128
368#define RX_BUF_SIZE PAGE_SIZE
369#else /* TC35815_USE_PACKEDBUFFER */
370#define FD_PAGE_NUM 4
371#define RX_BUF_NUM 128 /* < 256 */
372#define RX_FD_NUM 256 /* >= 32 */
373#define TX_FD_NUM 128
374#if RX_CTL_CMD & Rx_LongEn
375#define RX_BUF_SIZE PAGE_SIZE
376#elif RX_CTL_CMD & Rx_StripCRC
377#define RX_BUF_SIZE \
378    L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
379#else
380#define RX_BUF_SIZE \
381    L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
382#endif
383#endif /* TC35815_USE_PACKEDBUFFER */
384#define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
385#define NAPI_WEIGHT 16
386
387struct TxFD {
388    struct FDesc fd;
389    struct BDesc bd;
390    struct BDesc unused;
391};
392
393struct RxFD {
394    struct FDesc fd;
395    struct BDesc bd[0]; /* variable length */
396};
397
398struct FrFD {
399    struct FDesc fd;
400    struct BDesc bd[RX_BUF_NUM];
401};
402
403
404#define tc_readl(addr) ioread32(addr)
405#define tc_writel(d, addr) iowrite32(d, addr)
406
407#define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
408
409/* Information that need to be kept for each controller. */
410struct tc35815_local {
411    struct pci_dev *pci_dev;
412
413    struct net_device *dev;
414    struct napi_struct napi;
415
416    /* statistics */
417    struct {
418        int max_tx_qlen;
419        int tx_ints;
420        int rx_ints;
421        int tx_underrun;
422    } lstats;
423
424    /* Tx control lock. This protects the transmit buffer ring
425     * state along with the "tx full" state of the driver. This
426     * means all netif_queue flow control actions are protected
427     * by this lock as well.
428     */
429    spinlock_t lock;
430
431    struct mii_bus *mii_bus;
432    struct phy_device *phy_dev;
433    int duplex;
434    int speed;
435    int link;
436    struct work_struct restart_work;
437
438    /*
439     * Transmitting: Batch Mode.
440     * 1 BD in 1 TxFD.
441     * Receiving: Packing Mode. (TC35815_USE_PACKEDBUFFER)
442     * 1 circular FD for Free Buffer List.
443     * RX_BUF_NUM BD in Free Buffer FD.
444     * One Free Buffer BD has PAGE_SIZE data buffer.
445     * Or Non-Packing Mode.
446     * 1 circular FD for Free Buffer List.
447     * RX_BUF_NUM BD in Free Buffer FD.
448     * One Free Buffer BD has ETH_FRAME_LEN data buffer.
449     */
450    void *fd_buf; /* for TxFD, RxFD, FrFD */
451    dma_addr_t fd_buf_dma;
452    struct TxFD *tfd_base;
453    unsigned int tfd_start;
454    unsigned int tfd_end;
455    struct RxFD *rfd_base;
456    struct RxFD *rfd_limit;
457    struct RxFD *rfd_cur;
458    struct FrFD *fbl_ptr;
459#ifdef TC35815_USE_PACKEDBUFFER
460    unsigned char fbl_curid;
461    void *data_buf[RX_BUF_NUM]; /* packing */
462    dma_addr_t data_buf_dma[RX_BUF_NUM];
463    struct {
464        struct sk_buff *skb;
465        dma_addr_t skb_dma;
466    } tx_skbs[TX_FD_NUM];
467#else
468    unsigned int fbl_count;
469    struct {
470        struct sk_buff *skb;
471        dma_addr_t skb_dma;
472    } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
473#endif
474    u32 msg_enable;
475    enum tc35815_chiptype chiptype;
476};
477
478static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
479{
480    return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
481}
482#ifdef DEBUG
483static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
484{
485    return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
486}
487#endif
488#ifdef TC35815_USE_PACKEDBUFFER
489static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
490{
491    int i;
492    for (i = 0; i < RX_BUF_NUM; i++) {
493        if (bus >= lp->data_buf_dma[i] &&
494            bus < lp->data_buf_dma[i] + PAGE_SIZE)
495            return (void *)((u8 *)lp->data_buf[i] +
496                    (bus - lp->data_buf_dma[i]));
497    }
498    return NULL;
499}
500
501#define TC35815_DMA_SYNC_ONDEMAND
502static void *alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
503{
504#ifdef TC35815_DMA_SYNC_ONDEMAND
505    void *buf;
506    /* pci_map + pci_dma_sync will be more effective than
507     * pci_alloc_consistent on some archs. */
508    buf = (void *)__get_free_page(GFP_ATOMIC);
509    if (!buf)
510        return NULL;
511    *dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
512                     PCI_DMA_FROMDEVICE);
513    if (pci_dma_mapping_error(hwdev, *dma_handle)) {
514        free_page((unsigned long)buf);
515        return NULL;
516    }
517    return buf;
518#else
519    return pci_alloc_consistent(hwdev, PAGE_SIZE, dma_handle);
520#endif
521}
522
523static void free_rxbuf_page(struct pci_dev *hwdev, void *buf, dma_addr_t dma_handle)
524{
525#ifdef TC35815_DMA_SYNC_ONDEMAND
526    pci_unmap_single(hwdev, dma_handle, PAGE_SIZE, PCI_DMA_FROMDEVICE);
527    free_page((unsigned long)buf);
528#else
529    pci_free_consistent(hwdev, PAGE_SIZE, buf, dma_handle);
530#endif
531}
532#else /* TC35815_USE_PACKEDBUFFER */
533static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
534                       struct pci_dev *hwdev,
535                       dma_addr_t *dma_handle)
536{
537    struct sk_buff *skb;
538    skb = dev_alloc_skb(RX_BUF_SIZE);
539    if (!skb)
540        return NULL;
541    *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
542                     PCI_DMA_FROMDEVICE);
543    if (pci_dma_mapping_error(hwdev, *dma_handle)) {
544        dev_kfree_skb_any(skb);
545        return NULL;
546    }
547    skb_reserve(skb, 2); /* make IP header 4byte aligned */
548    return skb;
549}
550
551static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
552{
553    pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
554             PCI_DMA_FROMDEVICE);
555    dev_kfree_skb_any(skb);
556}
557#endif /* TC35815_USE_PACKEDBUFFER */
558
559/* Index to functions, as function prototypes. */
560
561static int tc35815_open(struct net_device *dev);
562static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
563static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
564#ifdef TC35815_NAPI
565static int tc35815_rx(struct net_device *dev, int limit);
566static int tc35815_poll(struct napi_struct *napi, int budget);
567#else
568static void tc35815_rx(struct net_device *dev);
569#endif
570static void tc35815_txdone(struct net_device *dev);
571static int tc35815_close(struct net_device *dev);
572static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
573static void tc35815_set_multicast_list(struct net_device *dev);
574static void tc35815_tx_timeout(struct net_device *dev);
575static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
576#ifdef CONFIG_NET_POLL_CONTROLLER
577static void tc35815_poll_controller(struct net_device *dev);
578#endif
579static const struct ethtool_ops tc35815_ethtool_ops;
580
581/* Example routines you must write ;->. */
582static void tc35815_chip_reset(struct net_device *dev);
583static void tc35815_chip_init(struct net_device *dev);
584
585#ifdef DEBUG
586static void panic_queues(struct net_device *dev);
587#endif
588
589static void tc35815_restart_work(struct work_struct *work);
590
591static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
592{
593    struct net_device *dev = bus->priv;
594    struct tc35815_regs __iomem *tr =
595        (struct tc35815_regs __iomem *)dev->base_addr;
596    unsigned long timeout = jiffies + 10;
597
598    tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
599    while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
600        if (time_after(jiffies, timeout))
601            return -EIO;
602        cpu_relax();
603    }
604    return tc_readl(&tr->MD_Data) & 0xffff;
605}
606
607static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
608{
609    struct net_device *dev = bus->priv;
610    struct tc35815_regs __iomem *tr =
611        (struct tc35815_regs __iomem *)dev->base_addr;
612    unsigned long timeout = jiffies + 10;
613
614    tc_writel(val, &tr->MD_Data);
615    tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
616          &tr->MD_CA);
617    while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
618        if (time_after(jiffies, timeout))
619            return -EIO;
620        cpu_relax();
621    }
622    return 0;
623}
624
625static void tc_handle_link_change(struct net_device *dev)
626{
627    struct tc35815_local *lp = netdev_priv(dev);
628    struct phy_device *phydev = lp->phy_dev;
629    unsigned long flags;
630    int status_change = 0;
631
632    spin_lock_irqsave(&lp->lock, flags);
633    if (phydev->link &&
634        (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
635        struct tc35815_regs __iomem *tr =
636            (struct tc35815_regs __iomem *)dev->base_addr;
637        u32 reg;
638
639        reg = tc_readl(&tr->MAC_Ctl);
640        reg |= MAC_HaltReq;
641        tc_writel(reg, &tr->MAC_Ctl);
642        if (phydev->duplex == DUPLEX_FULL)
643            reg |= MAC_FullDup;
644        else
645            reg &= ~MAC_FullDup;
646        tc_writel(reg, &tr->MAC_Ctl);
647        reg &= ~MAC_HaltReq;
648        tc_writel(reg, &tr->MAC_Ctl);
649
650        /*
651         * TX4939 PCFG.SPEEDn bit will be changed on
652         * NETDEV_CHANGE event.
653         */
654
655#if !defined(NO_CHECK_CARRIER) && defined(WORKAROUND_LOSTCAR)
656        /*
657         * WORKAROUND: enable LostCrS only if half duplex
658         * operation.
659         * (TX4939 does not have EnLCarr)
660         */
661        if (phydev->duplex == DUPLEX_HALF &&
662            lp->chiptype != TC35815_TX4939)
663            tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
664                  &tr->Tx_Ctl);
665#endif
666
667        lp->speed = phydev->speed;
668        lp->duplex = phydev->duplex;
669        status_change = 1;
670    }
671
672    if (phydev->link != lp->link) {
673        if (phydev->link) {
674#ifdef WORKAROUND_100HALF_PROMISC
675            /* delayed promiscuous enabling */
676            if (dev->flags & IFF_PROMISC)
677                tc35815_set_multicast_list(dev);
678#endif
679        } else {
680            lp->speed = 0;
681            lp->duplex = -1;
682        }
683        lp->link = phydev->link;
684
685        status_change = 1;
686    }
687    spin_unlock_irqrestore(&lp->lock, flags);
688
689    if (status_change && netif_msg_link(lp)) {
690        phy_print_status(phydev);
691        pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
692             dev->name,
693             phy_read(phydev, MII_BMCR),
694             phy_read(phydev, MII_BMSR),
695             phy_read(phydev, MII_LPA));
696    }
697}
698
699static int tc_mii_probe(struct net_device *dev)
700{
701    struct tc35815_local *lp = netdev_priv(dev);
702    struct phy_device *phydev = NULL;
703    int phy_addr;
704    u32 dropmask;
705
706    /* find the first phy */
707    for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
708        if (lp->mii_bus->phy_map[phy_addr]) {
709            if (phydev) {
710                printk(KERN_ERR "%s: multiple PHYs found\n",
711                       dev->name);
712                return -EINVAL;
713            }
714            phydev = lp->mii_bus->phy_map[phy_addr];
715            break;
716        }
717    }
718
719    if (!phydev) {
720        printk(KERN_ERR "%s: no PHY found\n", dev->name);
721        return -ENODEV;
722    }
723
724    /* attach the mac to the phy */
725    phydev = phy_connect(dev, dev_name(&phydev->dev),
726                 &tc_handle_link_change, 0,
727                 lp->chiptype == TC35815_TX4939 ?
728                 PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
729    if (IS_ERR(phydev)) {
730        printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
731        return PTR_ERR(phydev);
732    }
733    printk(KERN_INFO "%s: attached PHY driver [%s] "
734        "(mii_bus:phy_addr=%s, id=%x)\n",
735        dev->name, phydev->drv->name, dev_name(&phydev->dev),
736        phydev->phy_id);
737
738    /* mask with MAC supported features */
739    phydev->supported &= PHY_BASIC_FEATURES;
740    dropmask = 0;
741    if (options.speed == 10)
742        dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
743    else if (options.speed == 100)
744        dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
745    if (options.duplex == 1)
746        dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
747    else if (options.duplex == 2)
748        dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
749    phydev->supported &= ~dropmask;
750    phydev->advertising = phydev->supported;
751
752    lp->link = 0;
753    lp->speed = 0;
754    lp->duplex = -1;
755    lp->phy_dev = phydev;
756
757    return 0;
758}
759
760static int tc_mii_init(struct net_device *dev)
761{
762    struct tc35815_local *lp = netdev_priv(dev);
763    int err;
764    int i;
765
766    lp->mii_bus = mdiobus_alloc();
767    if (lp->mii_bus == NULL) {
768        err = -ENOMEM;
769        goto err_out;
770    }
771
772    lp->mii_bus->name = "tc35815_mii_bus";
773    lp->mii_bus->read = tc_mdio_read;
774    lp->mii_bus->write = tc_mdio_write;
775    snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
776         (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
777    lp->mii_bus->priv = dev;
778    lp->mii_bus->parent = &lp->pci_dev->dev;
779    lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
780    if (!lp->mii_bus->irq) {
781        err = -ENOMEM;
782        goto err_out_free_mii_bus;
783    }
784
785    for (i = 0; i < PHY_MAX_ADDR; i++)
786        lp->mii_bus->irq[i] = PHY_POLL;
787
788    err = mdiobus_register(lp->mii_bus);
789    if (err)
790        goto err_out_free_mdio_irq;
791    err = tc_mii_probe(dev);
792    if (err)
793        goto err_out_unregister_bus;
794    return 0;
795
796err_out_unregister_bus:
797    mdiobus_unregister(lp->mii_bus);
798err_out_free_mdio_irq:
799    kfree(lp->mii_bus->irq);
800err_out_free_mii_bus:
801    mdiobus_free(lp->mii_bus);
802err_out:
803    return err;
804}
805
806#ifdef CONFIG_CPU_TX49XX
807/*
808 * Find a platform_device providing a MAC address. The platform code
809 * should provide a "tc35815-mac" device with a MAC address in its
810 * platform_data.
811 */
812static int __devinit tc35815_mac_match(struct device *dev, void *data)
813{
814    struct platform_device *plat_dev = to_platform_device(dev);
815    struct pci_dev *pci_dev = data;
816    unsigned int id = pci_dev->irq;
817    return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
818}
819
820static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
821{
822    struct tc35815_local *lp = netdev_priv(dev);
823    struct device *pd = bus_find_device(&platform_bus_type, NULL,
824                        lp->pci_dev, tc35815_mac_match);
825    if (pd) {
826        if (pd->platform_data)
827            memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
828        put_device(pd);
829        return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
830    }
831    return -ENODEV;
832}
833#else
834static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
835{
836    return -ENODEV;
837}
838#endif
839
840static int __devinit tc35815_init_dev_addr(struct net_device *dev)
841{
842    struct tc35815_regs __iomem *tr =
843        (struct tc35815_regs __iomem *)dev->base_addr;
844    int i;
845
846    while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
847        ;
848    for (i = 0; i < 6; i += 2) {
849        unsigned short data;
850        tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
851        while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
852            ;
853        data = tc_readl(&tr->PROM_Data);
854        dev->dev_addr[i] = data & 0xff;
855        dev->dev_addr[i+1] = data >> 8;
856    }
857    if (!is_valid_ether_addr(dev->dev_addr))
858        return tc35815_read_plat_dev_addr(dev);
859    return 0;
860}
861
862static const struct net_device_ops tc35815_netdev_ops = {
863    .ndo_open = tc35815_open,
864    .ndo_stop = tc35815_close,
865    .ndo_start_xmit = tc35815_send_packet,
866    .ndo_get_stats = tc35815_get_stats,
867    .ndo_set_multicast_list = tc35815_set_multicast_list,
868    .ndo_tx_timeout = tc35815_tx_timeout,
869    .ndo_do_ioctl = tc35815_ioctl,
870    .ndo_validate_addr = eth_validate_addr,
871    .ndo_change_mtu = eth_change_mtu,
872    .ndo_set_mac_address = eth_mac_addr,
873#ifdef CONFIG_NET_POLL_CONTROLLER
874    .ndo_poll_controller = tc35815_poll_controller,
875#endif
876};
877
878static int __devinit tc35815_init_one(struct pci_dev *pdev,
879                      const struct pci_device_id *ent)
880{
881    void __iomem *ioaddr = NULL;
882    struct net_device *dev;
883    struct tc35815_local *lp;
884    int rc;
885
886    static int printed_version;
887    if (!printed_version++) {
888        printk(version);
889        dev_printk(KERN_DEBUG, &pdev->dev,
890               "speed:%d duplex:%d\n",
891               options.speed, options.duplex);
892    }
893
894    if (!pdev->irq) {
895        dev_warn(&pdev->dev, "no IRQ assigned.\n");
896        return -ENODEV;
897    }
898
899    /* dev zeroed in alloc_etherdev */
900    dev = alloc_etherdev(sizeof(*lp));
901    if (dev == NULL) {
902        dev_err(&pdev->dev, "unable to alloc new ethernet\n");
903        return -ENOMEM;
904    }
905    SET_NETDEV_DEV(dev, &pdev->dev);
906    lp = netdev_priv(dev);
907    lp->dev = dev;
908
909    /* enable device (incl. PCI PM wakeup), and bus-mastering */
910    rc = pcim_enable_device(pdev);
911    if (rc)
912        goto err_out;
913    rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
914    if (rc)
915        goto err_out;
916    pci_set_master(pdev);
917    ioaddr = pcim_iomap_table(pdev)[1];
918
919    /* Initialize the device structure. */
920    dev->netdev_ops = &tc35815_netdev_ops;
921    dev->ethtool_ops = &tc35815_ethtool_ops;
922    dev->watchdog_timeo = TC35815_TX_TIMEOUT;
923#ifdef TC35815_NAPI
924    netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
925#endif
926
927    dev->irq = pdev->irq;
928    dev->base_addr = (unsigned long)ioaddr;
929
930    INIT_WORK(&lp->restart_work, tc35815_restart_work);
931    spin_lock_init(&lp->lock);
932    lp->pci_dev = pdev;
933    lp->chiptype = ent->driver_data;
934
935    lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
936    pci_set_drvdata(pdev, dev);
937
938    /* Soft reset the chip. */
939    tc35815_chip_reset(dev);
940
941    /* Retrieve the ethernet address. */
942    if (tc35815_init_dev_addr(dev)) {
943        dev_warn(&pdev->dev, "not valid ether addr\n");
944        random_ether_addr(dev->dev_addr);
945    }
946
947    rc = register_netdev(dev);
948    if (rc)
949        goto err_out;
950
951    memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
952    printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
953        dev->name,
954        chip_info[ent->driver_data].name,
955        dev->base_addr,
956        dev->dev_addr,
957        dev->irq);
958
959    rc = tc_mii_init(dev);
960    if (rc)
961        goto err_out_unregister;
962
963    return 0;
964
965err_out_unregister:
966    unregister_netdev(dev);
967err_out:
968    free_netdev(dev);
969    return rc;
970}
971
972
973static void __devexit tc35815_remove_one(struct pci_dev *pdev)
974{
975    struct net_device *dev = pci_get_drvdata(pdev);
976    struct tc35815_local *lp = netdev_priv(dev);
977
978    phy_disconnect(lp->phy_dev);
979    mdiobus_unregister(lp->mii_bus);
980    kfree(lp->mii_bus->irq);
981    mdiobus_free(lp->mii_bus);
982    unregister_netdev(dev);
983    free_netdev(dev);
984    pci_set_drvdata(pdev, NULL);
985}
986
987static int
988tc35815_init_queues(struct net_device *dev)
989{
990    struct tc35815_local *lp = netdev_priv(dev);
991    int i;
992    unsigned long fd_addr;
993
994    if (!lp->fd_buf) {
995        BUG_ON(sizeof(struct FDesc) +
996               sizeof(struct BDesc) * RX_BUF_NUM +
997               sizeof(struct FDesc) * RX_FD_NUM +
998               sizeof(struct TxFD) * TX_FD_NUM >
999               PAGE_SIZE * FD_PAGE_NUM);
1000
1001        lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
1002                          PAGE_SIZE * FD_PAGE_NUM,
1003                          &lp->fd_buf_dma);
1004        if (!lp->fd_buf)
1005            return -ENOMEM;
1006        for (i = 0; i < RX_BUF_NUM; i++) {
1007#ifdef TC35815_USE_PACKEDBUFFER
1008            lp->data_buf[i] =
1009                alloc_rxbuf_page(lp->pci_dev,
1010                         &lp->data_buf_dma[i]);
1011            if (!lp->data_buf[i]) {
1012                while (--i >= 0) {
1013                    free_rxbuf_page(lp->pci_dev,
1014                            lp->data_buf[i],
1015                            lp->data_buf_dma[i]);
1016                    lp->data_buf[i] = NULL;
1017                }
1018                pci_free_consistent(lp->pci_dev,
1019                            PAGE_SIZE * FD_PAGE_NUM,
1020                            lp->fd_buf,
1021                            lp->fd_buf_dma);
1022                lp->fd_buf = NULL;
1023                return -ENOMEM;
1024            }
1025#else
1026            lp->rx_skbs[i].skb =
1027                alloc_rxbuf_skb(dev, lp->pci_dev,
1028                        &lp->rx_skbs[i].skb_dma);
1029            if (!lp->rx_skbs[i].skb) {
1030                while (--i >= 0) {
1031                    free_rxbuf_skb(lp->pci_dev,
1032                               lp->rx_skbs[i].skb,
1033                               lp->rx_skbs[i].skb_dma);
1034                    lp->rx_skbs[i].skb = NULL;
1035                }
1036                pci_free_consistent(lp->pci_dev,
1037                            PAGE_SIZE * FD_PAGE_NUM,
1038                            lp->fd_buf,
1039                            lp->fd_buf_dma);
1040                lp->fd_buf = NULL;
1041                return -ENOMEM;
1042            }
1043#endif
1044        }
1045        printk(KERN_DEBUG "%s: FD buf %p DataBuf",
1046               dev->name, lp->fd_buf);
1047#ifdef TC35815_USE_PACKEDBUFFER
1048        printk(" DataBuf");
1049        for (i = 0; i < RX_BUF_NUM; i++)
1050            printk(" %p", lp->data_buf[i]);
1051#endif
1052        printk("\n");
1053    } else {
1054        for (i = 0; i < FD_PAGE_NUM; i++)
1055            clear_page((void *)((unsigned long)lp->fd_buf +
1056                        i * PAGE_SIZE));
1057    }
1058    fd_addr = (unsigned long)lp->fd_buf;
1059
1060    /* Free Descriptors (for Receive) */
1061    lp->rfd_base = (struct RxFD *)fd_addr;
1062    fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
1063    for (i = 0; i < RX_FD_NUM; i++)
1064        lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
1065    lp->rfd_cur = lp->rfd_base;
1066    lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
1067
1068    /* Transmit Descriptors */
1069    lp->tfd_base = (struct TxFD *)fd_addr;
1070    fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
1071    for (i = 0; i < TX_FD_NUM; i++) {
1072        lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
1073        lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1074        lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
1075    }
1076    lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
1077    lp->tfd_start = 0;
1078    lp->tfd_end = 0;
1079
1080    /* Buffer List (for Receive) */
1081    lp->fbl_ptr = (struct FrFD *)fd_addr;
1082    lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
1083    lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
1084#ifndef TC35815_USE_PACKEDBUFFER
1085    /*
1086     * move all allocated skbs to head of rx_skbs[] array.
1087     * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
1088     * tc35815_rx() had failed.
1089     */
1090    lp->fbl_count = 0;
1091    for (i = 0; i < RX_BUF_NUM; i++) {
1092        if (lp->rx_skbs[i].skb) {
1093            if (i != lp->fbl_count) {
1094                lp->rx_skbs[lp->fbl_count].skb =
1095                    lp->rx_skbs[i].skb;
1096                lp->rx_skbs[lp->fbl_count].skb_dma =
1097                    lp->rx_skbs[i].skb_dma;
1098            }
1099            lp->fbl_count++;
1100        }
1101    }
1102#endif
1103    for (i = 0; i < RX_BUF_NUM; i++) {
1104#ifdef TC35815_USE_PACKEDBUFFER
1105        lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(lp->data_buf_dma[i]);
1106#else
1107        if (i >= lp->fbl_count) {
1108            lp->fbl_ptr->bd[i].BuffData = 0;
1109            lp->fbl_ptr->bd[i].BDCtl = 0;
1110            continue;
1111        }
1112        lp->fbl_ptr->bd[i].BuffData =
1113            cpu_to_le32(lp->rx_skbs[i].skb_dma);
1114#endif
1115        /* BDID is index of FrFD.bd[] */
1116        lp->fbl_ptr->bd[i].BDCtl =
1117            cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
1118                    RX_BUF_SIZE);
1119    }
1120#ifdef TC35815_USE_PACKEDBUFFER
1121    lp->fbl_curid = 0;
1122#endif
1123
1124    printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
1125           dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
1126    return 0;
1127}
1128
1129static void
1130tc35815_clear_queues(struct net_device *dev)
1131{
1132    struct tc35815_local *lp = netdev_priv(dev);
1133    int i;
1134
1135    for (i = 0; i < TX_FD_NUM; i++) {
1136        u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1137        struct sk_buff *skb =
1138            fdsystem != 0xffffffff ?
1139            lp->tx_skbs[fdsystem].skb : NULL;
1140#ifdef DEBUG
1141        if (lp->tx_skbs[i].skb != skb) {
1142            printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1143            panic_queues(dev);
1144        }
1145#else
1146        BUG_ON(lp->tx_skbs[i].skb != skb);
1147#endif
1148        if (skb) {
1149            pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1150            lp->tx_skbs[i].skb = NULL;
1151            lp->tx_skbs[i].skb_dma = 0;
1152            dev_kfree_skb_any(skb);
1153        }
1154        lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1155    }
1156
1157    tc35815_init_queues(dev);
1158}
1159
1160static void
1161tc35815_free_queues(struct net_device *dev)
1162{
1163    struct tc35815_local *lp = netdev_priv(dev);
1164    int i;
1165
1166    if (lp->tfd_base) {
1167        for (i = 0; i < TX_FD_NUM; i++) {
1168            u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1169            struct sk_buff *skb =
1170                fdsystem != 0xffffffff ?
1171                lp->tx_skbs[fdsystem].skb : NULL;
1172#ifdef DEBUG
1173            if (lp->tx_skbs[i].skb != skb) {
1174                printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1175                panic_queues(dev);
1176            }
1177#else
1178            BUG_ON(lp->tx_skbs[i].skb != skb);
1179#endif
1180            if (skb) {
1181                dev_kfree_skb(skb);
1182                pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1183                lp->tx_skbs[i].skb = NULL;
1184                lp->tx_skbs[i].skb_dma = 0;
1185            }
1186            lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1187        }
1188    }
1189
1190    lp->rfd_base = NULL;
1191    lp->rfd_limit = NULL;
1192    lp->rfd_cur = NULL;
1193    lp->fbl_ptr = NULL;
1194
1195    for (i = 0; i < RX_BUF_NUM; i++) {
1196#ifdef TC35815_USE_PACKEDBUFFER
1197        if (lp->data_buf[i]) {
1198            free_rxbuf_page(lp->pci_dev,
1199                    lp->data_buf[i], lp->data_buf_dma[i]);
1200            lp->data_buf[i] = NULL;
1201        }
1202#else
1203        if (lp->rx_skbs[i].skb) {
1204            free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1205                       lp->rx_skbs[i].skb_dma);
1206            lp->rx_skbs[i].skb = NULL;
1207        }
1208#endif
1209    }
1210    if (lp->fd_buf) {
1211        pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1212                    lp->fd_buf, lp->fd_buf_dma);
1213        lp->fd_buf = NULL;
1214    }
1215}
1216
1217static void
1218dump_txfd(struct TxFD *fd)
1219{
1220    printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1221           le32_to_cpu(fd->fd.FDNext),
1222           le32_to_cpu(fd->fd.FDSystem),
1223           le32_to_cpu(fd->fd.FDStat),
1224           le32_to_cpu(fd->fd.FDCtl));
1225    printk("BD: ");
1226    printk(" %08x %08x",
1227           le32_to_cpu(fd->bd.BuffData),
1228           le32_to_cpu(fd->bd.BDCtl));
1229    printk("\n");
1230}
1231
1232static int
1233dump_rxfd(struct RxFD *fd)
1234{
1235    int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1236    if (bd_count > 8)
1237        bd_count = 8;
1238    printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1239           le32_to_cpu(fd->fd.FDNext),
1240           le32_to_cpu(fd->fd.FDSystem),
1241           le32_to_cpu(fd->fd.FDStat),
1242           le32_to_cpu(fd->fd.FDCtl));
1243    if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1244        return 0;
1245    printk("BD: ");
1246    for (i = 0; i < bd_count; i++)
1247        printk(" %08x %08x",
1248               le32_to_cpu(fd->bd[i].BuffData),
1249               le32_to_cpu(fd->bd[i].BDCtl));
1250    printk("\n");
1251    return bd_count;
1252}
1253
1254#if defined(DEBUG) || defined(TC35815_USE_PACKEDBUFFER)
1255static void
1256dump_frfd(struct FrFD *fd)
1257{
1258    int i;
1259    printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1260           le32_to_cpu(fd->fd.FDNext),
1261           le32_to_cpu(fd->fd.FDSystem),
1262           le32_to_cpu(fd->fd.FDStat),
1263           le32_to_cpu(fd->fd.FDCtl));
1264    printk("BD: ");
1265    for (i = 0; i < RX_BUF_NUM; i++)
1266        printk(" %08x %08x",
1267               le32_to_cpu(fd->bd[i].BuffData),
1268               le32_to_cpu(fd->bd[i].BDCtl));
1269    printk("\n");
1270}
1271#endif
1272
1273#ifdef DEBUG
1274static void
1275panic_queues(struct net_device *dev)
1276{
1277    struct tc35815_local *lp = netdev_priv(dev);
1278    int i;
1279
1280    printk("TxFD base %p, start %u, end %u\n",
1281           lp->tfd_base, lp->tfd_start, lp->tfd_end);
1282    printk("RxFD base %p limit %p cur %p\n",
1283           lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1284    printk("FrFD %p\n", lp->fbl_ptr);
1285    for (i = 0; i < TX_FD_NUM; i++)
1286        dump_txfd(&lp->tfd_base[i]);
1287    for (i = 0; i < RX_FD_NUM; i++) {
1288        int bd_count = dump_rxfd(&lp->rfd_base[i]);
1289        i += (bd_count + 1) / 2; /* skip BDs */
1290    }
1291    dump_frfd(lp->fbl_ptr);
1292    panic("%s: Illegal queue state.", dev->name);
1293}
1294#endif
1295
1296static void print_eth(const u8 *add)
1297{
1298    printk(KERN_DEBUG "print_eth(%p)\n", add);
1299    printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1300        add + 6, add, add[12], add[13]);
1301}
1302
1303static int tc35815_tx_full(struct net_device *dev)
1304{
1305    struct tc35815_local *lp = netdev_priv(dev);
1306    return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
1307}
1308
1309static void tc35815_restart(struct net_device *dev)
1310{
1311    struct tc35815_local *lp = netdev_priv(dev);
1312
1313    if (lp->phy_dev) {
1314        int timeout;
1315
1316        phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1317        timeout = 100;
1318        while (--timeout) {
1319            if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1320                break;
1321            udelay(1);
1322        }
1323        if (!timeout)
1324            printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1325    }
1326
1327    spin_lock_irq(&lp->lock);
1328    tc35815_chip_reset(dev);
1329    tc35815_clear_queues(dev);
1330    tc35815_chip_init(dev);
1331    /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1332    tc35815_set_multicast_list(dev);
1333    spin_unlock_irq(&lp->lock);
1334
1335    netif_wake_queue(dev);
1336}
1337
1338static void tc35815_restart_work(struct work_struct *work)
1339{
1340    struct tc35815_local *lp =
1341        container_of(work, struct tc35815_local, restart_work);
1342    struct net_device *dev = lp->dev;
1343
1344    tc35815_restart(dev);
1345}
1346
1347static void tc35815_schedule_restart(struct net_device *dev)
1348{
1349    struct tc35815_local *lp = netdev_priv(dev);
1350    struct tc35815_regs __iomem *tr =
1351        (struct tc35815_regs __iomem *)dev->base_addr;
1352
1353    /* disable interrupts */
1354    tc_writel(0, &tr->Int_En);
1355    tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1356    schedule_work(&lp->restart_work);
1357}
1358
1359static void tc35815_tx_timeout(struct net_device *dev)
1360{
1361    struct tc35815_regs __iomem *tr =
1362        (struct tc35815_regs __iomem *)dev->base_addr;
1363
1364    printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1365           dev->name, tc_readl(&tr->Tx_Stat));
1366
1367    /* Try to restart the adaptor. */
1368    tc35815_schedule_restart(dev);
1369    dev->stats.tx_errors++;
1370}
1371
1372/*
1373 * Open/initialize the controller. This is called (in the current kernel)
1374 * sometime after booting when the 'ifconfig' program is run.
1375 *
1376 * This routine should set everything up anew at each open, even
1377 * registers that "should" only need to be set once at boot, so that
1378 * there is non-reboot way to recover if something goes wrong.
1379 */
1380static int
1381tc35815_open(struct net_device *dev)
1382{
1383    struct tc35815_local *lp = netdev_priv(dev);
1384
1385    /*
1386     * This is used if the interrupt line can turned off (shared).
1387     * See 3c503.c for an example of selecting the IRQ at config-time.
1388     */
1389    if (request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED,
1390            dev->name, dev))
1391        return -EAGAIN;
1392
1393    tc35815_chip_reset(dev);
1394
1395    if (tc35815_init_queues(dev) != 0) {
1396        free_irq(dev->irq, dev);
1397        return -EAGAIN;
1398    }
1399
1400#ifdef TC35815_NAPI
1401    napi_enable(&lp->napi);
1402#endif
1403
1404    /* Reset the hardware here. Don't forget to set the station address. */
1405    spin_lock_irq(&lp->lock);
1406    tc35815_chip_init(dev);
1407    spin_unlock_irq(&lp->lock);
1408
1409    netif_carrier_off(dev);
1410    /* schedule a link state check */
1411    phy_start(lp->phy_dev);
1412
1413    /* We are now ready to accept transmit requeusts from
1414     * the queueing layer of the networking.
1415     */
1416    netif_start_queue(dev);
1417
1418    return 0;
1419}
1420
1421/* This will only be invoked if your driver is _not_ in XOFF state.
1422 * What this means is that you need not check it, and that this
1423 * invariant will hold if you make sure that the netif_*_queue()
1424 * calls are done at the proper times.
1425 */
1426static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1427{
1428    struct tc35815_local *lp = netdev_priv(dev);
1429    struct TxFD *txfd;
1430    unsigned long flags;
1431
1432    /* If some error occurs while trying to transmit this
1433     * packet, you should return '1' from this function.
1434     * In such a case you _may not_ do anything to the
1435     * SKB, it is still owned by the network queueing
1436     * layer when an error is returned. This means you
1437     * may not modify any SKB fields, you may not free
1438     * the SKB, etc.
1439     */
1440
1441    /* This is the most common case for modern hardware.
1442     * The spinlock protects this code from the TX complete
1443     * hardware interrupt handler. Queue flow control is
1444     * thus managed under this lock as well.
1445     */
1446    spin_lock_irqsave(&lp->lock, flags);
1447
1448    /* failsafe... (handle txdone now if half of FDs are used) */
1449    if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1450        TX_FD_NUM / 2)
1451        tc35815_txdone(dev);
1452
1453    if (netif_msg_pktdata(lp))
1454        print_eth(skb->data);
1455#ifdef DEBUG
1456    if (lp->tx_skbs[lp->tfd_start].skb) {
1457        printk("%s: tx_skbs conflict.\n", dev->name);
1458        panic_queues(dev);
1459    }
1460#else
1461    BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1462#endif
1463    lp->tx_skbs[lp->tfd_start].skb = skb;
1464    lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1465
1466    /*add to ring */
1467    txfd = &lp->tfd_base[lp->tfd_start];
1468    txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1469    txfd->bd.BDCtl = cpu_to_le32(skb->len);
1470    txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1471    txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1472
1473    if (lp->tfd_start == lp->tfd_end) {
1474        struct tc35815_regs __iomem *tr =
1475            (struct tc35815_regs __iomem *)dev->base_addr;
1476        /* Start DMA Transmitter. */
1477        txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1478#ifdef GATHER_TXINT
1479        txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1480#endif
1481        if (netif_msg_tx_queued(lp)) {
1482            printk("%s: starting TxFD.\n", dev->name);
1483            dump_txfd(txfd);
1484        }
1485        tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1486    } else {
1487        txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1488        if (netif_msg_tx_queued(lp)) {
1489            printk("%s: queueing TxFD.\n", dev->name);
1490            dump_txfd(txfd);
1491        }
1492    }
1493    lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1494
1495    dev->trans_start = jiffies;
1496
1497    /* If we just used up the very last entry in the
1498     * TX ring on this device, tell the queueing
1499     * layer to send no more.
1500     */
1501    if (tc35815_tx_full(dev)) {
1502        if (netif_msg_tx_queued(lp))
1503            printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1504        netif_stop_queue(dev);
1505    }
1506
1507    /* When the TX completion hw interrupt arrives, this
1508     * is when the transmit statistics are updated.
1509     */
1510
1511    spin_unlock_irqrestore(&lp->lock, flags);
1512    return 0;
1513}
1514
1515#define FATAL_ERROR_INT \
1516    (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1517static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1518{
1519    static int count;
1520    printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1521           dev->name, status);
1522    if (status & Int_IntPCI)
1523        printk(" IntPCI");
1524    if (status & Int_DmParErr)
1525        printk(" DmParErr");
1526    if (status & Int_IntNRAbt)
1527        printk(" IntNRAbt");
1528    printk("\n");
1529    if (count++ > 100)
1530        panic("%s: Too many fatal errors.", dev->name);
1531    printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1532    /* Try to restart the adaptor. */
1533    tc35815_schedule_restart(dev);
1534}
1535
1536#ifdef TC35815_NAPI
1537static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1538#else
1539static int tc35815_do_interrupt(struct net_device *dev, u32 status)
1540#endif
1541{
1542    struct tc35815_local *lp = netdev_priv(dev);
1543    struct tc35815_regs __iomem *tr =
1544        (struct tc35815_regs __iomem *)dev->base_addr;
1545    int ret = -1;
1546
1547    /* Fatal errors... */
1548    if (status & FATAL_ERROR_INT) {
1549        tc35815_fatal_error_interrupt(dev, status);
1550        return 0;
1551    }
1552    /* recoverable errors */
1553    if (status & Int_IntFDAEx) {
1554        /* disable FDAEx int. (until we make rooms...) */
1555        tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
1556        printk(KERN_WARNING
1557               "%s: Free Descriptor Area Exhausted (%#x).\n",
1558               dev->name, status);
1559        dev->stats.rx_dropped++;
1560        ret = 0;
1561    }
1562    if (status & Int_IntBLEx) {
1563        /* disable BLEx int. (until we make rooms...) */
1564        tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
1565        printk(KERN_WARNING
1566               "%s: Buffer List Exhausted (%#x).\n",
1567               dev->name, status);
1568        dev->stats.rx_dropped++;
1569        ret = 0;
1570    }
1571    if (status & Int_IntExBD) {
1572        printk(KERN_WARNING
1573               "%s: Excessive Buffer Descriptiors (%#x).\n",
1574               dev->name, status);
1575        dev->stats.rx_length_errors++;
1576        ret = 0;
1577    }
1578
1579    /* normal notification */
1580    if (status & Int_IntMacRx) {
1581        /* Got a packet(s). */
1582#ifdef TC35815_NAPI
1583        ret = tc35815_rx(dev, limit);
1584#else
1585        tc35815_rx(dev);
1586        ret = 0;
1587#endif
1588        lp->lstats.rx_ints++;
1589    }
1590    if (status & Int_IntMacTx) {
1591        /* Transmit complete. */
1592        lp->lstats.tx_ints++;
1593        tc35815_txdone(dev);
1594        netif_wake_queue(dev);
1595        ret = 0;
1596    }
1597    return ret;
1598}
1599
1600/*
1601 * The typical workload of the driver:
1602 * Handle the network interface interrupts.
1603 */
1604static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1605{
1606    struct net_device *dev = dev_id;
1607    struct tc35815_local *lp = netdev_priv(dev);
1608    struct tc35815_regs __iomem *tr =
1609        (struct tc35815_regs __iomem *)dev->base_addr;
1610#ifdef TC35815_NAPI
1611    u32 dmactl = tc_readl(&tr->DMA_Ctl);
1612
1613    if (!(dmactl & DMA_IntMask)) {
1614        /* disable interrupts */
1615        tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1616        if (napi_schedule_prep(&lp->napi))
1617            __napi_schedule(&lp->napi);
1618        else {
1619            printk(KERN_ERR "%s: interrupt taken in poll\n",
1620                   dev->name);
1621            BUG();
1622        }
1623        (void)tc_readl(&tr->Int_Src); /* flush */
1624        return IRQ_HANDLED;
1625    }
1626    return IRQ_NONE;
1627#else
1628    int handled;
1629    u32 status;
1630
1631    spin_lock(&lp->lock);
1632    status = tc_readl(&tr->Int_Src);
1633    tc_writel(status, &tr->Int_Src); /* write to clear */
1634    handled = tc35815_do_interrupt(dev, status);
1635    (void)tc_readl(&tr->Int_Src); /* flush */
1636    spin_unlock(&lp->lock);
1637    return IRQ_RETVAL(handled >= 0);
1638#endif /* TC35815_NAPI */
1639}
1640
1641#ifdef CONFIG_NET_POLL_CONTROLLER
1642static void tc35815_poll_controller(struct net_device *dev)
1643{
1644    disable_irq(dev->irq);
1645    tc35815_interrupt(dev->irq, dev);
1646    enable_irq(dev->irq);
1647}
1648#endif
1649
1650/* We have a good packet(s), get it/them out of the buffers. */
1651#ifdef TC35815_NAPI
1652static int
1653tc35815_rx(struct net_device *dev, int limit)
1654#else
1655static void
1656tc35815_rx(struct net_device *dev)
1657#endif
1658{
1659    struct tc35815_local *lp = netdev_priv(dev);
1660    unsigned int fdctl;
1661    int i;
1662    int buf_free_count = 0;
1663    int fd_free_count = 0;
1664#ifdef TC35815_NAPI
1665    int received = 0;
1666#endif
1667
1668    while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1669        int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1670        int pkt_len = fdctl & FD_FDLength_MASK;
1671        int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1672#ifdef DEBUG
1673        struct RxFD *next_rfd;
1674#endif
1675#if (RX_CTL_CMD & Rx_StripCRC) == 0
1676        pkt_len -= ETH_FCS_LEN;
1677#endif
1678
1679        if (netif_msg_rx_status(lp))
1680            dump_rxfd(lp->rfd_cur);
1681        if (status & Rx_Good) {
1682            struct sk_buff *skb;
1683            unsigned char *data;
1684            int cur_bd;
1685#ifdef TC35815_USE_PACKEDBUFFER
1686            int offset;
1687#endif
1688
1689#ifdef TC35815_NAPI
1690            if (--limit < 0)
1691                break;
1692#endif
1693#ifdef TC35815_USE_PACKEDBUFFER
1694            BUG_ON(bd_count > 2);
1695            skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
1696            if (skb == NULL) {
1697                printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1698                       dev->name);
1699                dev->stats.rx_dropped++;
1700                break;
1701            }
1702            skb_reserve(skb, NET_IP_ALIGN);
1703
1704            data = skb_put(skb, pkt_len);
1705
1706            /* copy from receive buffer */
1707            cur_bd = 0;
1708            offset = 0;
1709            while (offset < pkt_len && cur_bd < bd_count) {
1710                int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1711                    BD_BuffLength_MASK;
1712                dma_addr_t dma = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData);
1713                void *rxbuf = rxbuf_bus_to_virt(lp, dma);
1714                if (offset + len > pkt_len)
1715                    len = pkt_len - offset;
1716#ifdef TC35815_DMA_SYNC_ONDEMAND
1717                pci_dma_sync_single_for_cpu(lp->pci_dev,
1718                                dma, len,
1719                                PCI_DMA_FROMDEVICE);
1720#endif
1721                memcpy(data + offset, rxbuf, len);
1722#ifdef TC35815_DMA_SYNC_ONDEMAND
1723                pci_dma_sync_single_for_device(lp->pci_dev,
1724                                   dma, len,
1725                                   PCI_DMA_FROMDEVICE);
1726#endif
1727                offset += len;
1728                cur_bd++;
1729            }
1730#else /* TC35815_USE_PACKEDBUFFER */
1731            BUG_ON(bd_count > 1);
1732            cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1733                  & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1734#ifdef DEBUG
1735            if (cur_bd >= RX_BUF_NUM) {
1736                printk("%s: invalid BDID.\n", dev->name);
1737                panic_queues(dev);
1738            }
1739            BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1740                   (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1741            if (!lp->rx_skbs[cur_bd].skb) {
1742                printk("%s: NULL skb.\n", dev->name);
1743                panic_queues(dev);
1744            }
1745#else
1746            BUG_ON(cur_bd >= RX_BUF_NUM);
1747#endif
1748            skb = lp->rx_skbs[cur_bd].skb;
1749            prefetch(skb->data);
1750            lp->rx_skbs[cur_bd].skb = NULL;
1751            pci_unmap_single(lp->pci_dev,
1752                     lp->rx_skbs[cur_bd].skb_dma,
1753                     RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1754            if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1755                memmove(skb->data, skb->data - NET_IP_ALIGN,
1756                    pkt_len);
1757            data = skb_put(skb, pkt_len);
1758#endif /* TC35815_USE_PACKEDBUFFER */
1759            if (netif_msg_pktdata(lp))
1760                print_eth(data);
1761            skb->protocol = eth_type_trans(skb, dev);
1762#ifdef TC35815_NAPI
1763            netif_receive_skb(skb);
1764            received++;
1765#else
1766            netif_rx(skb);
1767#endif
1768            dev->stats.rx_packets++;
1769            dev->stats.rx_bytes += pkt_len;
1770        } else {
1771            dev->stats.rx_errors++;
1772            printk(KERN_DEBUG "%s: Rx error (status %x)\n",
1773                   dev->name, status & Rx_Stat_Mask);
1774            /* WORKAROUND: LongErr and CRCErr means Overflow. */
1775            if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1776                status &= ~(Rx_LongErr|Rx_CRCErr);
1777                status |= Rx_Over;
1778            }
1779            if (status & Rx_LongErr)
1780                dev->stats.rx_length_errors++;
1781            if (status & Rx_Over)
1782                dev->stats.rx_fifo_errors++;
1783            if (status & Rx_CRCErr)
1784                dev->stats.rx_crc_errors++;
1785            if (status & Rx_Align)
1786                dev->stats.rx_frame_errors++;
1787        }
1788
1789        if (bd_count > 0) {
1790            /* put Free Buffer back to controller */
1791            int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1792            unsigned char id =
1793                (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1794#ifdef DEBUG
1795            if (id >= RX_BUF_NUM) {
1796                printk("%s: invalid BDID.\n", dev->name);
1797                panic_queues(dev);
1798            }
1799#else
1800            BUG_ON(id >= RX_BUF_NUM);
1801#endif
1802            /* free old buffers */
1803#ifdef TC35815_USE_PACKEDBUFFER
1804            while (lp->fbl_curid != id)
1805#else
1806            lp->fbl_count--;
1807            while (lp->fbl_count < RX_BUF_NUM)
1808#endif
1809            {
1810#ifdef TC35815_USE_PACKEDBUFFER
1811                unsigned char curid = lp->fbl_curid;
1812#else
1813                unsigned char curid =
1814                    (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1815#endif
1816                struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1817#ifdef DEBUG
1818                bdctl = le32_to_cpu(bd->BDCtl);
1819                if (bdctl & BD_CownsBD) {
1820                    printk("%s: Freeing invalid BD.\n",
1821                           dev->name);
1822                    panic_queues(dev);
1823                }
1824#endif
1825                /* pass BD to controller */
1826#ifndef TC35815_USE_PACKEDBUFFER
1827                if (!lp->rx_skbs[curid].skb) {
1828                    lp->rx_skbs[curid].skb =
1829                        alloc_rxbuf_skb(dev,
1830                                lp->pci_dev,
1831                                &lp->rx_skbs[curid].skb_dma);
1832                    if (!lp->rx_skbs[curid].skb)
1833                        break; /* try on next reception */
1834                    bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1835                }
1836#endif /* TC35815_USE_PACKEDBUFFER */
1837                /* Note: BDLength was modified by chip. */
1838                bd->BDCtl = cpu_to_le32(BD_CownsBD |
1839                            (curid << BD_RxBDID_SHIFT) |
1840                            RX_BUF_SIZE);
1841#ifdef TC35815_USE_PACKEDBUFFER
1842                lp->fbl_curid = (curid + 1) % RX_BUF_NUM;
1843                if (netif_msg_rx_status(lp)) {
1844                    printk("%s: Entering new FBD %d\n",
1845                           dev->name, lp->fbl_curid);
1846                    dump_frfd(lp->fbl_ptr);
1847                }
1848#else
1849                lp->fbl_count++;
1850#endif
1851                buf_free_count++;
1852            }
1853        }
1854
1855        /* put RxFD back to controller */
1856#ifdef DEBUG
1857        next_rfd = fd_bus_to_virt(lp,
1858                      le32_to_cpu(lp->rfd_cur->fd.FDNext));
1859        if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1860            printk("%s: RxFD FDNext invalid.\n", dev->name);
1861            panic_queues(dev);
1862        }
1863#endif
1864        for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1865            /* pass FD to controller */
1866#ifdef DEBUG
1867            lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1868#else
1869            lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1870#endif
1871            lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1872            lp->rfd_cur++;
1873            fd_free_count++;
1874        }
1875        if (lp->rfd_cur > lp->rfd_limit)
1876            lp->rfd_cur = lp->rfd_base;
1877#ifdef DEBUG
1878        if (lp->rfd_cur != next_rfd)
1879            printk("rfd_cur = %p, next_rfd %p\n",
1880                   lp->rfd_cur, next_rfd);
1881#endif
1882    }
1883
1884    /* re-enable BL/FDA Exhaust interrupts. */
1885    if (fd_free_count) {
1886        struct tc35815_regs __iomem *tr =
1887            (struct tc35815_regs __iomem *)dev->base_addr;
1888        u32 en, en_old = tc_readl(&tr->Int_En);
1889        en = en_old | Int_FDAExEn;
1890        if (buf_free_count)
1891            en |= Int_BLExEn;
1892        if (en != en_old)
1893            tc_writel(en, &tr->Int_En);
1894    }
1895#ifdef TC35815_NAPI
1896    return received;
1897#endif
1898}
1899
1900#ifdef TC35815_NAPI
1901static int tc35815_poll(struct napi_struct *napi, int budget)
1902{
1903    struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1904    struct net_device *dev = lp->dev;
1905    struct tc35815_regs __iomem *tr =
1906        (struct tc35815_regs __iomem *)dev->base_addr;
1907    int received = 0, handled;
1908    u32 status;
1909
1910    spin_lock(&lp->lock);
1911    status = tc_readl(&tr->Int_Src);
1912    do {
1913        tc_writel(status, &tr->Int_Src); /* write to clear */
1914
1915        handled = tc35815_do_interrupt(dev, status, budget - received);
1916        if (handled >= 0) {
1917            received += handled;
1918            if (received >= budget)
1919                break;
1920        }
1921        status = tc_readl(&tr->Int_Src);
1922    } while (status);
1923    spin_unlock(&lp->lock);
1924
1925    if (received < budget) {
1926        napi_complete(napi);
1927        /* enable interrupts */
1928        tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1929    }
1930    return received;
1931}
1932#endif
1933
1934#ifdef NO_CHECK_CARRIER
1935#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1936#else
1937#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1938#endif
1939
1940static void
1941tc35815_check_tx_stat(struct net_device *dev, int status)
1942{
1943    struct tc35815_local *lp = netdev_priv(dev);
1944    const char *msg = NULL;
1945
1946    /* count collisions */
1947    if (status & Tx_ExColl)
1948        dev->stats.collisions += 16;
1949    if (status & Tx_TxColl_MASK)
1950        dev->stats.collisions += status & Tx_TxColl_MASK;
1951
1952#ifndef NO_CHECK_CARRIER
1953    /* TX4939 does not have NCarr */
1954    if (lp->chiptype == TC35815_TX4939)
1955        status &= ~Tx_NCarr;
1956#ifdef WORKAROUND_LOSTCAR
1957    /* WORKAROUND: ignore LostCrS in full duplex operation */
1958    if (!lp->link || lp->duplex == DUPLEX_FULL)
1959        status &= ~Tx_NCarr;
1960#endif
1961#endif
1962
1963    if (!(status & TX_STA_ERR)) {
1964        /* no error. */
1965        dev->stats.tx_packets++;
1966        return;
1967    }
1968
1969    dev->stats.tx_errors++;
1970    if (status & Tx_ExColl) {
1971        dev->stats.tx_aborted_errors++;
1972        msg = "Excessive Collision.";
1973    }
1974    if (status & Tx_Under) {
1975        dev->stats.tx_fifo_errors++;
1976        msg = "Tx FIFO Underrun.";
1977        if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1978            lp->lstats.tx_underrun++;
1979            if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1980                struct tc35815_regs __iomem *tr =
1981                    (struct tc35815_regs __iomem *)dev->base_addr;
1982                tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1983                msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1984            }
1985        }
1986    }
1987    if (status & Tx_Defer) {
1988        dev->stats.tx_fifo_errors++;
1989        msg = "Excessive Deferral.";
1990    }
1991#ifndef NO_CHECK_CARRIER
1992    if (status & Tx_NCarr) {
1993        dev->stats.tx_carrier_errors++;
1994        msg = "Lost Carrier Sense.";
1995    }
1996#endif
1997    if (status & Tx_LateColl) {
1998        dev->stats.tx_aborted_errors++;
1999        msg = "Late Collision.";
2000    }
2001    if (status & Tx_TxPar) {
2002        dev->stats.tx_fifo_errors++;
2003        msg = "Transmit Parity Error.";
2004    }
2005    if (status & Tx_SQErr) {
2006        dev->stats.tx_heartbeat_errors++;
2007        msg = "Signal Quality Error.";
2008    }
2009    if (msg && netif_msg_tx_err(lp))
2010        printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
2011}
2012
2013/* This handles TX complete events posted by the device
2014 * via interrupts.
2015 */
2016static void
2017tc35815_txdone(struct net_device *dev)
2018{
2019    struct tc35815_local *lp = netdev_priv(dev);
2020    struct TxFD *txfd;
2021    unsigned int fdctl;
2022
2023    txfd = &lp->tfd_base[lp->tfd_end];
2024    while (lp->tfd_start != lp->tfd_end &&
2025           !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
2026        int status = le32_to_cpu(txfd->fd.FDStat);
2027        struct sk_buff *skb;
2028        unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
2029        u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
2030
2031        if (netif_msg_tx_done(lp)) {
2032            printk("%s: complete TxFD.\n", dev->name);
2033            dump_txfd(txfd);
2034        }
2035        tc35815_check_tx_stat(dev, status);
2036
2037        skb = fdsystem != 0xffffffff ?
2038            lp->tx_skbs[fdsystem].skb : NULL;
2039#ifdef DEBUG
2040        if (lp->tx_skbs[lp->tfd_end].skb != skb) {
2041            printk("%s: tx_skbs mismatch.\n", dev->name);
2042            panic_queues(dev);
2043        }
2044#else
2045        BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
2046#endif
2047        if (skb) {
2048            dev->stats.tx_bytes += skb->len;
2049            pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
2050            lp->tx_skbs[lp->tfd_end].skb = NULL;
2051            lp->tx_skbs[lp->tfd_end].skb_dma = 0;
2052#ifdef TC35815_NAPI
2053            dev_kfree_skb_any(skb);
2054#else
2055            dev_kfree_skb_irq(skb);
2056#endif
2057        }
2058        txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
2059
2060        lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
2061        txfd = &lp->tfd_base[lp->tfd_end];
2062#ifdef DEBUG
2063        if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
2064            printk("%s: TxFD FDNext invalid.\n", dev->name);
2065            panic_queues(dev);
2066        }
2067#endif
2068        if (fdnext & FD_Next_EOL) {
2069            /* DMA Transmitter has been stopping... */
2070            if (lp->tfd_end != lp->tfd_start) {
2071                struct tc35815_regs __iomem *tr =
2072                    (struct tc35815_regs __iomem *)dev->base_addr;
2073                int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
2074                struct TxFD *txhead = &lp->tfd_base[head];
2075                int qlen = (lp->tfd_start + TX_FD_NUM
2076                        - lp->tfd_end) % TX_FD_NUM;
2077
2078#ifdef DEBUG
2079                if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
2080                    printk("%s: TxFD FDCtl invalid.\n", dev->name);
2081                    panic_queues(dev);
2082                }
2083#endif
2084                /* log max queue length */
2085                if (lp->lstats.max_tx_qlen < qlen)
2086                    lp->lstats.max_tx_qlen = qlen;
2087
2088
2089                /* start DMA Transmitter again */
2090                txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
2091#ifdef GATHER_TXINT
2092                txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
2093#endif
2094                if (netif_msg_tx_queued(lp)) {
2095                    printk("%s: start TxFD on queue.\n",
2096                           dev->name);
2097                    dump_txfd(txfd);
2098                }
2099                tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
2100            }
2101            break;
2102        }
2103    }
2104
2105    /* If we had stopped the queue due to a "tx full"
2106     * condition, and space has now been made available,
2107     * wake up the queue.
2108     */
2109    if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
2110        netif_wake_queue(dev);
2111}
2112
2113/* The inverse routine to tc35815_open(). */
2114static int
2115tc35815_close(struct net_device *dev)
2116{
2117    struct tc35815_local *lp = netdev_priv(dev);
2118
2119    netif_stop_queue(dev);
2120#ifdef TC35815_NAPI
2121    napi_disable(&lp->napi);
2122#endif
2123    if (lp->phy_dev)
2124        phy_stop(lp->phy_dev);
2125    cancel_work_sync(&lp->restart_work);
2126
2127    /* Flush the Tx and disable Rx here. */
2128    tc35815_chip_reset(dev);
2129    free_irq(dev->irq, dev);
2130
2131    tc35815_free_queues(dev);
2132
2133    return 0;
2134
2135}
2136
2137/*
2138 * Get the current statistics.
2139 * This may be called with the card open or closed.
2140 */
2141static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
2142{
2143    struct tc35815_regs __iomem *tr =
2144        (struct tc35815_regs __iomem *)dev->base_addr;
2145    if (netif_running(dev))
2146        /* Update the statistics from the device registers. */
2147        dev->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
2148
2149    return &dev->stats;
2150}
2151
2152static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
2153{
2154    struct tc35815_local *lp = netdev_priv(dev);
2155    struct tc35815_regs __iomem *tr =
2156        (struct tc35815_regs __iomem *)dev->base_addr;
2157    int cam_index = index * 6;
2158    u32 cam_data;
2159    u32 saved_addr;
2160
2161    saved_addr = tc_readl(&tr->CAM_Adr);
2162
2163    if (netif_msg_hw(lp))
2164        printk(KERN_DEBUG "%s: CAM %d: %pM\n",
2165            dev->name, index, addr);
2166    if (index & 1) {
2167        /* read modify write */
2168        tc_writel(cam_index - 2, &tr->CAM_Adr);
2169        cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
2170        cam_data |= addr[0] << 8 | addr[1];
2171        tc_writel(cam_data, &tr->CAM_Data);
2172        /* write whole word */
2173        tc_writel(cam_index + 2, &tr->CAM_Adr);
2174        cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
2175        tc_writel(cam_data, &tr->CAM_Data);
2176    } else {
2177        /* write whole word */
2178        tc_writel(cam_index, &tr->CAM_Adr);
2179        cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
2180        tc_writel(cam_data, &tr->CAM_Data);
2181        /* read modify write */
2182        tc_writel(cam_index + 4, &tr->CAM_Adr);
2183        cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
2184        cam_data |= addr[4] << 24 | (addr[5] << 16);
2185        tc_writel(cam_data, &tr->CAM_Data);
2186    }
2187
2188    tc_writel(saved_addr, &tr->CAM_Adr);
2189}
2190
2191
2192/*
2193 * Set or clear the multicast filter for this adaptor.
2194 * num_addrs == -1 Promiscuous mode, receive all packets
2195 * num_addrs == 0 Normal mode, clear multicast list
2196 * num_addrs > 0 Multicast mode, receive normal and MC packets,
2197 * and do best-effort filtering.
2198 */
2199static void
2200tc35815_set_multicast_list(struct net_device *dev)
2201{
2202    struct tc35815_regs __iomem *tr =
2203        (struct tc35815_regs __iomem *)dev->base_addr;
2204
2205    if (dev->flags & IFF_PROMISC) {
2206#ifdef WORKAROUND_100HALF_PROMISC
2207        /* With some (all?) 100MHalf HUB, controller will hang
2208         * if we enabled promiscuous mode before linkup... */
2209        struct tc35815_local *lp = netdev_priv(dev);
2210
2211        if (!lp->link)
2212            return;
2213#endif
2214        /* Enable promiscuous mode */
2215        tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
2216    } else if ((dev->flags & IFF_ALLMULTI) ||
2217          dev->mc_count > CAM_ENTRY_MAX - 3) {
2218        /* CAM 0, 1, 20 are reserved. */
2219        /* Disable promiscuous mode, use normal mode. */
2220        tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
2221    } else if (dev->mc_count) {
2222        struct dev_mc_list *cur_addr = dev->mc_list;
2223        int i;
2224        int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
2225
2226        tc_writel(0, &tr->CAM_Ctl);
2227        /* Walk the address list, and load the filter */
2228        for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
2229            if (!cur_addr)
2230                break;
2231            /* entry 0,1 is reserved. */
2232            tc35815_set_cam_entry(dev, i + 2, cur_addr->dmi_addr);
2233            ena_bits |= CAM_Ena_Bit(i + 2);
2234        }
2235        tc_writel(ena_bits, &tr->CAM_Ena);
2236        tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2237    } else {
2238        tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2239        tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2240    }
2241}
2242
2243static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2244{
2245    struct tc35815_local *lp = netdev_priv(dev);
2246    strcpy(info->driver, MODNAME);
2247    strcpy(info->version, DRV_VERSION);
2248    strcpy(info->bus_info, pci_name(lp->pci_dev));
2249}
2250
2251static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2252{
2253    struct tc35815_local *lp = netdev_priv(dev);
2254
2255    if (!lp->phy_dev)
2256        return -ENODEV;
2257    return phy_ethtool_gset(lp->phy_dev, cmd);
2258}
2259
2260static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2261{
2262    struct tc35815_local *lp = netdev_priv(dev);
2263
2264    if (!lp->phy_dev)
2265        return -ENODEV;
2266    return phy_ethtool_sset(lp->phy_dev, cmd);
2267}
2268
2269static u32 tc35815_get_msglevel(struct net_device *dev)
2270{
2271    struct tc35815_local *lp = netdev_priv(dev);
2272    return lp->msg_enable;
2273}
2274
2275static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2276{
2277    struct tc35815_local *lp = netdev_priv(dev);
2278    lp->msg_enable = datum;
2279}
2280
2281static int tc35815_get_sset_count(struct net_device *dev, int sset)
2282{
2283    struct tc35815_local *lp = netdev_priv(dev);
2284
2285    switch (sset) {
2286    case ETH_SS_STATS:
2287        return sizeof(lp->lstats) / sizeof(int);
2288    default:
2289        return -EOPNOTSUPP;
2290    }
2291}
2292
2293static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2294{
2295    struct tc35815_local *lp = netdev_priv(dev);
2296    data[0] = lp->lstats.max_tx_qlen;
2297    data[1] = lp->lstats.tx_ints;
2298    data[2] = lp->lstats.rx_ints;
2299    data[3] = lp->lstats.tx_underrun;
2300}
2301
2302static struct {
2303    const char str[ETH_GSTRING_LEN];
2304} ethtool_stats_keys[] = {
2305    { "max_tx_qlen" },
2306    { "tx_ints" },
2307    { "rx_ints" },
2308    { "tx_underrun" },
2309};
2310
2311static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2312{
2313    memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2314}
2315
2316static const struct ethtool_ops tc35815_ethtool_ops = {
2317    .get_drvinfo = tc35815_get_drvinfo,
2318    .get_settings = tc35815_get_settings,
2319    .set_settings = tc35815_set_settings,
2320    .get_link = ethtool_op_get_link,
2321    .get_msglevel = tc35815_get_msglevel,
2322    .set_msglevel = tc35815_set_msglevel,
2323    .get_strings = tc35815_get_strings,
2324    .get_sset_count = tc35815_get_sset_count,
2325    .get_ethtool_stats = tc35815_get_ethtool_stats,
2326};
2327
2328static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2329{
2330    struct tc35815_local *lp = netdev_priv(dev);
2331
2332    if (!netif_running(dev))
2333        return -EINVAL;
2334    if (!lp->phy_dev)
2335        return -ENODEV;
2336    return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
2337}
2338
2339static void tc35815_chip_reset(struct net_device *dev)
2340{
2341    struct tc35815_regs __iomem *tr =
2342        (struct tc35815_regs __iomem *)dev->base_addr;
2343    int i;
2344    /* reset the controller */
2345    tc_writel(MAC_Reset, &tr->MAC_Ctl);
2346    udelay(4); /* 3200ns */
2347    i = 0;
2348    while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2349        if (i++ > 100) {
2350            printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2351            break;
2352        }
2353        mdelay(1);
2354    }
2355    tc_writel(0, &tr->MAC_Ctl);
2356
2357    /* initialize registers to default value */
2358    tc_writel(0, &tr->DMA_Ctl);
2359    tc_writel(0, &tr->TxThrsh);
2360    tc_writel(0, &tr->TxPollCtr);
2361    tc_writel(0, &tr->RxFragSize);
2362    tc_writel(0, &tr->Int_En);
2363    tc_writel(0, &tr->FDA_Bas);
2364    tc_writel(0, &tr->FDA_Lim);
2365    tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2366    tc_writel(0, &tr->CAM_Ctl);
2367    tc_writel(0, &tr->Tx_Ctl);
2368    tc_writel(0, &tr->Rx_Ctl);
2369    tc_writel(0, &tr->CAM_Ena);
2370    (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2371
2372    /* initialize internal SRAM */
2373    tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2374    for (i = 0; i < 0x1000; i += 4) {
2375        tc_writel(i, &tr->CAM_Adr);
2376        tc_writel(0, &tr->CAM_Data);
2377    }
2378    tc_writel(0, &tr->DMA_Ctl);
2379}
2380
2381static void tc35815_chip_init(struct net_device *dev)
2382{
2383    struct tc35815_local *lp = netdev_priv(dev);
2384    struct tc35815_regs __iomem *tr =
2385        (struct tc35815_regs __iomem *)dev->base_addr;
2386    unsigned long txctl = TX_CTL_CMD;
2387
2388    /* load station address to CAM */
2389    tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2390
2391    /* Enable CAM (broadcast and unicast) */
2392    tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2393    tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2394
2395    /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2396    if (HAVE_DMA_RXALIGN(lp))
2397        tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2398    else
2399        tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2400#ifdef TC35815_USE_PACKEDBUFFER
2401    tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
2402#else
2403    tc_writel(ETH_ZLEN, &tr->RxFragSize);
2404#endif
2405    tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2406    tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2407    tc_writel(INT_EN_CMD, &tr->Int_En);
2408
2409    /* set queues */
2410    tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2411    tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2412          &tr->FDA_Lim);
2413    /*
2414     * Activation method:
2415     * First, enable the MAC Transmitter and the DMA Receive circuits.
2416     * Then enable the DMA Transmitter and the MAC Receive circuits.
2417     */
2418    tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2419    tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2420
2421    /* start MAC transmitter */
2422#ifndef NO_CHECK_CARRIER
2423    /* TX4939 does not have EnLCarr */
2424    if (lp->chiptype == TC35815_TX4939)
2425        txctl &= ~Tx_EnLCarr;
2426#ifdef WORKAROUND_LOSTCAR
2427    /* WORKAROUND: ignore LostCrS in full duplex operation */
2428    if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2429        txctl &= ~Tx_EnLCarr;
2430#endif
2431#endif /* !NO_CHECK_CARRIER */
2432#ifdef GATHER_TXINT
2433    txctl &= ~Tx_EnComp; /* disable global tx completion int. */
2434#endif
2435    tc_writel(txctl, &tr->Tx_Ctl);
2436}
2437
2438#ifdef CONFIG_PM
2439static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2440{
2441    struct net_device *dev = pci_get_drvdata(pdev);
2442    struct tc35815_local *lp = netdev_priv(dev);
2443    unsigned long flags;
2444
2445    pci_save_state(pdev);
2446    if (!netif_running(dev))
2447        return 0;
2448    netif_device_detach(dev);
2449    if (lp->phy_dev)
2450        phy_stop(lp->phy_dev);
2451    spin_lock_irqsave(&lp->lock, flags);
2452    tc35815_chip_reset(dev);
2453    spin_unlock_irqrestore(&lp->lock, flags);
2454    pci_set_power_state(pdev, PCI_D3hot);
2455    return 0;
2456}
2457
2458static int tc35815_resume(struct pci_dev *pdev)
2459{
2460    struct net_device *dev = pci_get_drvdata(pdev);
2461    struct tc35815_local *lp = netdev_priv(dev);
2462
2463    pci_restore_state(pdev);
2464    if (!netif_running(dev))
2465        return 0;
2466    pci_set_power_state(pdev, PCI_D0);
2467    tc35815_restart(dev);
2468    netif_carrier_off(dev);
2469    if (lp->phy_dev)
2470        phy_start(lp->phy_dev);
2471    netif_device_attach(dev);
2472    return 0;
2473}
2474#endif /* CONFIG_PM */
2475
2476static struct pci_driver tc35815_pci_driver = {
2477    .name = MODNAME,
2478    .id_table = tc35815_pci_tbl,
2479    .probe = tc35815_init_one,
2480    .remove = __devexit_p(tc35815_remove_one),
2481#ifdef CONFIG_PM
2482    .suspend = tc35815_suspend,
2483    .resume = tc35815_resume,
2484#endif
2485};
2486
2487module_param_named(speed, options.speed, int, 0);
2488MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2489module_param_named(duplex, options.duplex, int, 0);
2490MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2491
2492static int __init tc35815_init_module(void)
2493{
2494    return pci_register_driver(&tc35815_pci_driver);
2495}
2496
2497static void __exit tc35815_cleanup_module(void)
2498{
2499    pci_unregister_driver(&tc35815_pci_driver);
2500}
2501
2502module_init(tc35815_init_module);
2503module_exit(tc35815_cleanup_module);
2504
2505MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2506MODULE_LICENSE("GPL");
2507

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