drivers/net/ucc_geth.h - Kernel Git Source Tree - This git is only for xburst cpu upstreaming works or co-works. nothing relate to openwrt-xburst.git, please use openwrt-xburst.git/target/linux/xburst/ for the last NanoNote kernel

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/*

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*

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* Author: Shlomi Gridish <gridish@freescale.com>

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*

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* Description:

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* Internal header file for UCC Gigabit Ethernet unit routines.

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*

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* Changelog:

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* Jun 28, 2006 Li Yang <LeoLi@freescale.com>

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* - Rearrange code and style fixes

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*

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* This program is free software; you can redistribute it and/or modify it

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* under the terms of the GNU General Public License as published by the

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* Free Software Foundation; either version 2 of the License, or (at your

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* option) any later version.

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*/

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#ifndef __UCC_GETH_H__

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#define __UCC_GETH_H__

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#include <linux/kernel.h>

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#include <linux/list.h>

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#include <asm/immap_qe.h>

#include <asm/qe.h>

#include <asm/ucc.h>

#include <asm/ucc_fast.h>

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#define DRV_DESC "QE UCC Gigabit Ethernet Controller"

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#define DRV_NAME "ucc_geth"

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#define DRV_VERSION "1.1"

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#define NUM_TX_QUEUES 8

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#define NUM_RX_QUEUES 8

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#define NUM_BDS_IN_PREFETCHED_BDS 4

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#define TX_IP_OFFSET_ENTRY_MAX 8

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#define NUM_OF_PADDRS 4

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#define ENET_INIT_PARAM_MAX_ENTRIES_RX 9

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#define ENET_INIT_PARAM_MAX_ENTRIES_TX 8

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struct ucc_geth {

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struct ucc_fast uccf;

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u8 res0[0x100 - sizeof(struct ucc_fast)];

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u32 maccfg1; /* mac configuration reg. 1 */

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u32 maccfg2; /* mac configuration reg. 2 */

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u32 ipgifg; /* interframe gap reg. */

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u32 hafdup; /* half-duplex reg. */

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u8 res1[0x10];

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u8 miimng[0x18]; /* MII management structure moved to _mii.h */

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u32 ifctl; /* interface control reg */

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u32 ifstat; /* interface statux reg */

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u32 macstnaddr1; /* mac station address part 1 reg */

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u32 macstnaddr2; /* mac station address part 2 reg */

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u8 res2[0x8];

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u32 uempr; /* UCC Ethernet Mac parameter reg */

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u32 utbipar; /* UCC tbi address reg */

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u16 uescr; /* UCC Ethernet statistics control reg */

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u8 res3[0x180 - 0x15A];

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u32 tx64; /* Total number of frames (including bad

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frames) transmitted that were exactly of the

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minimal length (64 for un tagged, 68 for

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tagged, or with length exactly equal to the

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parameter MINLength */

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u32 tx127; /* Total number of frames (including bad

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frames) transmitted that were between

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MINLength (Including FCS length==4) and 127

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octets */

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u32 tx255; /* Total number of frames (including bad

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frames) transmitted that were between 128

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(Including FCS length==4) and 255 octets */

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u32 rx64; /* Total number of frames received including

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bad frames that were exactly of the mninimal

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length (64 bytes) */

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u32 rx127; /* Total number of frames (including bad

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frames) received that were between MINLength

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(Including FCS length==4) and 127 octets */

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u32 rx255; /* Total number of frames (including bad

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frames) received that were between 128

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(Including FCS length==4) and 255 octets */

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u32 txok; /* Total number of octets residing in frames

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that where involved in succesfull

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transmission */

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u16 txcf; /* Total number of PAUSE control frames

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transmitted by this MAC */

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u8 res4[0x2];

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u32 tmca; /* Total number of frames that were transmitted

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succesfully with the group address bit set

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that are not broadcast frames */

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u32 tbca; /* Total number of frames transmitted

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succesfully that had destination address

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field equal to the broadcast address */

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u32 rxfok; /* Total number of frames received OK */

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u32 rxbok; /* Total number of octets received OK */

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u32 rbyt; /* Total number of octets received including

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octets in bad frames. Must be implemented in

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HW because it includes octets in frames that

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never even reach the UCC */

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u32 rmca; /* Total number of frames that were received

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succesfully with the group address bit set

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that are not broadcast frames */

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u32 rbca; /* Total number of frames received succesfully

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that had destination address equal to the

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broadcast address */

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u32 scar; /* Statistics carry register */

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u32 scam; /* Statistics caryy mask register */

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u8 res5[0x200 - 0x1c4];

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} __attribute__ ((packed));

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/* UCC GETH TEMODR Register */

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#define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics

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*/

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#define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */

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#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4

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checksums */

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#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance

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optimization

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enhancement (mode1) */

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#define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics

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*/

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#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues <<

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shift */

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/* UCC GETH TEMODR Register */

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#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx

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statistics */

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#define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable

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extended

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features */

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#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation

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tagged << shift */

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#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non

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tagged << shift */

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#define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift

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*/

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#define REMODER_RMON_STATISTICS 0x00001000 /* enable rx

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statistics */

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#define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended

filtering

vs.

mpc82xx-like

filtering */

#define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues <<

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shift */

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#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable

dynamic max

frame length

*/

#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable

dynamic min

frame length

*/

#define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4

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checksums */

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#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip

address to

4-byte

boundary */

/* UCC GETH Event Register */

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#define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \

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UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \

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UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \

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UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)

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#define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \

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UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \

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UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \

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UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)

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#define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \

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UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \

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UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \

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UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)

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#define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \

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UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \

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UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)

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#define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY)

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#define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE)

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/* TBI defines */

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#define ENET_TBI_MII_CR 0x00 /* Control */

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#define ENET_TBI_MII_SR 0x01 /* Status */

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#define ENET_TBI_MII_ANA 0x04 /* AN advertisement */

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#define ENET_TBI_MII_ANLPBPA 0x05 /* AN link partner base page ability */

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#define ENET_TBI_MII_ANEX 0x06 /* AN expansion */

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#define ENET_TBI_MII_ANNPT 0x07 /* AN next page transmit */

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#define ENET_TBI_MII_ANLPANP 0x08 /* AN link partner ability next page */

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#define ENET_TBI_MII_EXST 0x0F /* Extended status */

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#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */

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#define ENET_TBI_MII_TBICON 0x11 /* TBI control */

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/* TBI MDIO register bit fields*/

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#define TBISR_LSTATUS 0x0004

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#define TBICON_CLK_SELECT 0x0020

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#define TBIANA_ASYMMETRIC_PAUSE 0x0100

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#define TBIANA_SYMMETRIC_PAUSE 0x0080

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#define TBIANA_HALF_DUPLEX 0x0040

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#define TBIANA_FULL_DUPLEX 0x0020

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#define TBICR_PHY_RESET 0x8000

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#define TBICR_ANEG_ENABLE 0x1000

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#define TBICR_RESTART_ANEG 0x0200

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#define TBICR_FULL_DUPLEX 0x0100

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#define TBICR_SPEED1_SET 0x0040

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#define TBIANA_SETTINGS ( \

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TBIANA_ASYMMETRIC_PAUSE \

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| TBIANA_SYMMETRIC_PAUSE \

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| TBIANA_FULL_DUPLEX \

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)

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#define TBICR_SETTINGS ( \

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TBICR_PHY_RESET \

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| TBICR_ANEG_ENABLE \

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| TBICR_FULL_DUPLEX \

| TBICR_SPEED1_SET \

)

/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */

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#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control

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Rx */

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#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control

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Tx */

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#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable

synchronized

to Rx stream

*/

#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */

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#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable

synchronized

to Tx stream

*/

#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */

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/* UCC GETH MACCFG2 (MAC Configuration 2 Register) */

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#define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble

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Length <<

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shift */

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#define MACCFG2_PREL_MASK 0x0000f000 /* Preamble

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Length mask */

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#define MACCFG2_SRP 0x00000080 /* Soft Receive

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Preamble */

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#define MACCFG2_STP 0x00000040 /* Soft

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Transmit

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Preamble */

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#define MACCFG2_RESERVED_1 0x00000020 /* Reserved -

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must be set

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to 1 */

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#define MACCFG2_LC 0x00000010 /* Length Check

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*/

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#define MACCFG2_MPE 0x00000008 /* Magic packet

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detect */

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#define MACCFG2_FDX 0x00000001 /* Full Duplex */

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#define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex

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mask */

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#define MACCFG2_PAD_CRC 0x00000004

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#define MACCFG2_CRC_EN 0x00000002

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#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither

Padding

short frames

nor CRC */

#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC

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only */

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#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004

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#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode

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(MII/RMII/RGMII

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10/100bps) */

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#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode

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(GMII/TBI/RTB/RGMII

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1000bps ) */

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#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask

covering all

relevant

bits */

/* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */

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#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non

back-to-back

inter frame

gap part 1.

<< shift */

#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non

back-to-back

inter frame

gap part 2.

<< shift */

#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG

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Enforcement

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<< shift */

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#define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back

inter frame

gap << shift

*/

#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back

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inter frame gap part

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1. max val */

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#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back

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inter frame gap part

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2. max val */

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#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG

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Enforcement max val */

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#define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter

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frame gap max val */

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#define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000

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#define IPGIFG_NBTB_IPG_MASK 0x007F0000

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#define IPGIFG_MIN_IFG_MASK 0x0000FF00

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#define IPGIFG_BTB_IPG_MASK 0x0000007F

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/* UCC GETH HAFDUP (Half Duplex Register) */

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#define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate

Binary

Exponential

Backoff

Truncation

<< shift */

#define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary

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Exponential Backoff

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Truncation max val */

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#define HALFDUP_ALT_BEB 0x00080000 /* Alternate

Binary

Exponential

Backoff */

#define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back

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pressure no

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backoff */

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#define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */

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#define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive

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Defer */

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#define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum

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Retransmission

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<< shift */

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#define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum

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Retransmission max

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val */

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#define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision

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Window <<

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shift */

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#define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max

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val */

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#define HALFDUP_ALT_BEB_TR_MASK 0x00F00000

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#define HALFDUP_RETRANS_MASK 0x0000F000

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#define HALFDUP_COL_WINDOW_MASK 0x0000003F

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/* UCC GETH UCCS (Ethernet Status Register) */

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#define UCCS_BPR 0x02 /* Back pressure (in

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half duplex mode) */

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#define UCCS_PAU 0x02 /* Pause state (in full

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duplex mode) */

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#define UCCS_MPD 0x01 /* Magic Packet

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Detected */

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/* UCC GETH IFSTAT (Interface Status Register) */

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#define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive

transmission

defer */

/* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */

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#define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station

address 6th

octet <<

shift */

#define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station

address 5th

octet <<

shift */

#define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station

address 4th

octet <<

shift */

#define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station

address 3rd

octet <<

shift */

/* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */

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#define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station

address 2nd

octet <<

shift */

#define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station

address 1st

octet <<

shift */

/* UCC GETH UEMPR (Ethernet Mac Parameter Register) */

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#define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time

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value <<

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shift */

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#define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended

pause time

value <<

shift */

/* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */

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#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address

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<< shift */

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#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address

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mask */

401

402

/* UCC GETH UESCR (Ethernet Statistics Control Register) */

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#define UESCR_AUTOZ 0x8000 /* Automatically zero

addressed

statistical counter

values */

#define UESCR_CLRCNT 0x4000 /* Clear all statistics

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counters */

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#define UESCR_MAXCOV_SHIFT (15 - 7) /* Max

Coalescing

Value <<

shift */

#define UESCR_SCOV_SHIFT (15 - 15) /* Status

Coalescing

Value <<

shift */

/* UCC GETH UDSR (Data Synchronization Register) */

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#define UDSR_MAGIC 0x067E

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struct ucc_geth_thread_data_tx {

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u8 res0[104];

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} __attribute__ ((packed));

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struct ucc_geth_thread_data_rx {

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u8 res0[40];

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} __attribute__ ((packed));

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/* Send Queue Queue-Descriptor */

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struct ucc_geth_send_queue_qd {

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u32 bd_ring_base; /* pointer to BD ring base address */

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u8 res0[0x8];

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u32 last_bd_completed_address;/* initialize to last entry in BD ring */

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u8 res1[0x30];

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} __attribute__ ((packed));

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struct ucc_geth_send_queue_mem_region {

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struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];

439

} __attribute__ ((packed));

440

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struct ucc_geth_thread_tx_pram {

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u8 res0[64];

443

} __attribute__ ((packed));

444

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struct ucc_geth_thread_rx_pram {

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u8 res0[128];

447

} __attribute__ ((packed));

448

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#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64

450

#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64

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#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96

452

453

struct ucc_geth_scheduler {

454

u16 cpucount0; /* CPU packet counter */

455

u16 cpucount1; /* CPU packet counter */

456

u16 cecount0; /* QE packet counter */

457

u16 cecount1; /* QE packet counter */

458

u16 cpucount2; /* CPU packet counter */

459

u16 cpucount3; /* CPU packet counter */

460

u16 cecount2; /* QE packet counter */

461

u16 cecount3; /* QE packet counter */

462

u16 cpucount4; /* CPU packet counter */

463

u16 cpucount5; /* CPU packet counter */

464

u16 cecount4; /* QE packet counter */

465

u16 cecount5; /* QE packet counter */

466

u16 cpucount6; /* CPU packet counter */

467

u16 cpucount7; /* CPU packet counter */

468

u16 cecount6; /* QE packet counter */

469

u16 cecount7; /* QE packet counter */

470

u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */

471

u32 rtsrshadow; /* temporary variable handled by QE */

472

u32 time; /* temporary variable handled by QE */

473

u32 ttl; /* temporary variable handled by QE */

474

u32 mblinterval; /* max burst length interval */

475

u16 nortsrbytetime; /* normalized value of byte time in tsr units */

476

u8 fracsiz; /* radix 2 log value of denom. of

477

NorTSRByteTime */

478

u8 res0[1];

479

u8 strictpriorityq; /* Strict Priority Mask register */

480

u8 txasap; /* Transmit ASAP register */

481

u8 extrabw; /* Extra BandWidth register */

482

u8 oldwfqmask; /* temporary variable handled by QE */

483

u8 weightfactor[NUM_TX_QUEUES];

484

/**< weight factor for queues */

485

u32 minw; /* temporary variable handled by QE */

486

u8 res1[0x70 - 0x64];

487

} __attribute__ ((packed));

488

489

struct ucc_geth_tx_firmware_statistics_pram {

490

u32 sicoltx; /* single collision */

491

u32 mulcoltx; /* multiple collision */

492

u32 latecoltxfr; /* late collision */

493

u32 frabortduecol; /* frames aborted due to transmit collision */

494

u32 frlostinmactxer; /* frames lost due to internal MAC error

495

transmission that are not counted on any

496

other counter */

497

u32 carriersenseertx; /* carrier sense error */

498

u32 frtxok; /* frames transmitted OK */

499

u32 txfrexcessivedefer; /* frames with defferal time greater than

500

specified threshold */

501

u32 txpkts256; /* total packets (including bad) between 256

502

and 511 octets */

503

u32 txpkts512; /* total packets (including bad) between 512

504

and 1023 octets */

505

u32 txpkts1024; /* total packets (including bad) between 1024

506

and 1518 octets */

507

u32 txpktsjumbo; /* total packets (including bad) between 1024

508

and MAXLength octets */

509

} __attribute__ ((packed));

510

511

struct ucc_geth_rx_firmware_statistics_pram {

512

u32 frrxfcser; /* frames with crc error */

513

u32 fraligner; /* frames with alignment error */

514

u32 inrangelenrxer; /* in range length error */

515

u32 outrangelenrxer; /* out of range length error */

516

u32 frtoolong; /* frame too long */

517

u32 runt; /* runt */

518

u32 verylongevent; /* very long event */

519

u32 symbolerror; /* symbol error */

520

u32 dropbsy; /* drop because of BD not ready */

521

u8 res0[0x8];

522

u32 mismatchdrop; /* drop because of MAC filtering (e.g. address

523

or type mismatch) */

524

u32 underpkts; /* total frames less than 64 octets */

525

u32 pkts256; /* total frames (including bad) between 256 and

526

511 octets */

527

u32 pkts512; /* total frames (including bad) between 512 and

528

1023 octets */

529

u32 pkts1024; /* total frames (including bad) between 1024

530

and 1518 octets */

531

u32 pktsjumbo; /* total frames (including bad) between 1024

532

and MAXLength octets */

533

u32 frlossinmacer; /* frames lost because of internal MAC error

534

that is not counted in any other counter */

535

u32 pausefr; /* pause frames */

536

u8 res1[0x4];

537

u32 removevlan; /* total frames that had their VLAN tag removed

538

*/

539

u32 replacevlan; /* total frames that had their VLAN tag

540

replaced */

541

u32 insertvlan; /* total frames that had their VLAN tag

542

inserted */

543

} __attribute__ ((packed));

544

545

struct ucc_geth_rx_interrupt_coalescing_entry {

546

u32 interruptcoalescingmaxvalue; /* interrupt coalescing max

547

value */

548

u32 interruptcoalescingcounter; /* interrupt coalescing counter,

549

initialize to

550

interruptcoalescingmaxvalue */

551

} __attribute__ ((packed));

552

553

struct ucc_geth_rx_interrupt_coalescing_table {

554

struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];

555

/**< interrupt coalescing entry */

556

} __attribute__ ((packed));

557

558

struct ucc_geth_rx_prefetched_bds {

559

struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */

560

} __attribute__ ((packed));

561

562

struct ucc_geth_rx_bd_queues_entry {

563

u32 bdbaseptr; /* BD base pointer */

564

u32 bdptr; /* BD pointer */

565

u32 externalbdbaseptr; /* external BD base pointer */

566

u32 externalbdptr; /* external BD pointer */

567

} __attribute__ ((packed));

568

569

struct ucc_geth_tx_global_pram {

570

u16 temoder;

571

u8 res0[0x38 - 0x02];

572

u32 sqptr; /* a base pointer to send queue memory region */

573

u32 schedulerbasepointer; /* a base pointer to scheduler memory

574

region */

575

u32 txrmonbaseptr; /* base pointer to Tx RMON statistics counter */

576

u32 tstate; /* tx internal state. High byte contains

577

function code */

578

u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];

579

u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */

580

u32 tqptr; /* a base pointer to the Tx Queues Memory

581

Region */

582

u8 res2[0x80 - 0x74];

583

} __attribute__ ((packed));

584

585

/* structure representing Extended Filtering Global Parameters in PRAM */

586

struct ucc_geth_exf_global_pram {

587

u32 l2pcdptr; /* individual address filter, high */

588

u8 res0[0x10 - 0x04];

589

} __attribute__ ((packed));

590

591

struct ucc_geth_rx_global_pram {

592

u32 remoder; /* ethernet mode reg. */

593

u32 rqptr; /* base pointer to the Rx Queues Memory Region*/

594

u32 res0[0x1];

595

u8 res1[0x20 - 0xC];

596

u16 typeorlen; /* cutoff point less than which, type/len field

597

is considered length */

598

u8 res2[0x1];

599

u8 rxgstpack; /* acknowledgement on GRACEFUL STOP RX command*/

600

u32 rxrmonbaseptr; /* base pointer to Rx RMON statistics counter */

601

u8 res3[0x30 - 0x28];

602

u32 intcoalescingptr; /* Interrupt coalescing table pointer */

603

u8 res4[0x36 - 0x34];

604

u8 rstate; /* rx internal state. High byte contains

605

function code */

606

u8 res5[0x46 - 0x37];

607

u16 mrblr; /* max receive buffer length reg. */

608

u32 rbdqptr; /* base pointer to RxBD parameter table

609

description */

610

u16 mflr; /* max frame length reg. */

611

u16 minflr; /* min frame length reg. */

612

u16 maxd1; /* max dma1 length reg. */

613

u16 maxd2; /* max dma2 length reg. */

614

u32 ecamptr; /* external CAM address */

615

u32 l2qt; /* VLAN priority mapping table. */

616

u32 l3qt[0x8]; /* IP priority mapping table. */

617

u16 vlantype; /* vlan type */

618

u16 vlantci; /* default vlan tci */

619

u8 addressfiltering[64]; /* address filtering data structure */

620

u32 exfGlobalParam; /* base address for extended filtering global

621

parameters */

622

u8 res6[0x100 - 0xC4]; /* Initialize to zero */

623

} __attribute__ ((packed));

624

625

#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01

626

627

/* structure representing InitEnet command */

628

struct ucc_geth_init_pram {

u8 resinit1;

u8 resinit2;

u8 resinit3;

u8 resinit4;

u16 resinit5;

u8 res1[0x1];

u8 largestexternallookupkeysize;

636

u32 rgftgfrxglobal;

637

u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX]; /* rx threads */

638

u8 res2[0x38 - 0x30];

639

u32 txglobal; /* tx global */

640

u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */

641

u8 res3[0x1];

642

} __attribute__ ((packed));

643

644

#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)

645

#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)

646

647

#define ENET_INIT_PARAM_RISC_MASK 0x0000003f

648

#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0

649

#define ENET_INIT_PARAM_SNUM_MASK 0xff000000

650

#define ENET_INIT_PARAM_SNUM_SHIFT 24

651

652

#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06

653

#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30

654

#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff

655

#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00

656

#define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400

657

658

/* structure representing 82xx Address Filtering Enet Address in PRAM */

659

struct ucc_geth_82xx_enet_address {

660

u8 res1[0x2];

661

u16 h; /* address (MSB) */

662

u16 m; /* address */

663

u16 l; /* address (LSB) */

664

} __attribute__ ((packed));

665

666

/* structure representing 82xx Address Filtering PRAM */

667

struct ucc_geth_82xx_address_filtering_pram {

668

u32 iaddr_h; /* individual address filter, high */

669

u32 iaddr_l; /* individual address filter, low */

670

u32 gaddr_h; /* group address filter, high */

671

u32 gaddr_l; /* group address filter, low */

672

struct ucc_geth_82xx_enet_address __iomem taddr;

673

struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];

674

u8 res0[0x40 - 0x38];

675

} __attribute__ ((packed));

676

677

/* GETH Tx firmware statistics structure, used when calling

678

UCC_GETH_GetStatistics. */

679

struct ucc_geth_tx_firmware_statistics {

680

u32 sicoltx; /* single collision */

681

u32 mulcoltx; /* multiple collision */

682

u32 latecoltxfr; /* late collision */

683

u32 frabortduecol; /* frames aborted due to transmit collision */

684

u32 frlostinmactxer; /* frames lost due to internal MAC error

685

transmission that are not counted on any

686

other counter */

687

u32 carriersenseertx; /* carrier sense error */

688

u32 frtxok; /* frames transmitted OK */

689

u32 txfrexcessivedefer; /* frames with defferal time greater than

690

specified threshold */

691

u32 txpkts256; /* total packets (including bad) between 256

692

and 511 octets */

693

u32 txpkts512; /* total packets (including bad) between 512

694

and 1023 octets */

695

u32 txpkts1024; /* total packets (including bad) between 1024

696

and 1518 octets */

697

u32 txpktsjumbo; /* total packets (including bad) between 1024

698

and MAXLength octets */

699

} __attribute__ ((packed));

700

701

/* GETH Rx firmware statistics structure, used when calling

702

UCC_GETH_GetStatistics. */

703

struct ucc_geth_rx_firmware_statistics {

704

u32 frrxfcser; /* frames with crc error */

705

u32 fraligner; /* frames with alignment error */

706

u32 inrangelenrxer; /* in range length error */

707

u32 outrangelenrxer; /* out of range length error */

708

u32 frtoolong; /* frame too long */

709

u32 runt; /* runt */

710

u32 verylongevent; /* very long event */

711

u32 symbolerror; /* symbol error */

712

u32 dropbsy; /* drop because of BD not ready */

713

u8 res0[0x8];

714

u32 mismatchdrop; /* drop because of MAC filtering (e.g. address

715

or type mismatch) */

716

u32 underpkts; /* total frames less than 64 octets */

717

u32 pkts256; /* total frames (including bad) between 256 and

718

511 octets */

719

u32 pkts512; /* total frames (including bad) between 512 and

720

1023 octets */

721

u32 pkts1024; /* total frames (including bad) between 1024

722

and 1518 octets */

723

u32 pktsjumbo; /* total frames (including bad) between 1024

724

and MAXLength octets */

725

u32 frlossinmacer; /* frames lost because of internal MAC error

726

that is not counted in any other counter */

727

u32 pausefr; /* pause frames */

728

u8 res1[0x4];

729

u32 removevlan; /* total frames that had their VLAN tag removed

730

*/

731

u32 replacevlan; /* total frames that had their VLAN tag

732

replaced */

733

u32 insertvlan; /* total frames that had their VLAN tag

734

inserted */

735

} __attribute__ ((packed));

736

737

/* GETH hardware statistics structure, used when calling

738

UCC_GETH_GetStatistics. */

739

struct ucc_geth_hardware_statistics {

740

u32 tx64; /* Total number of frames (including bad

741

frames) transmitted that were exactly of the

742

minimal length (64 for un tagged, 68 for

743

tagged, or with length exactly equal to the

744

parameter MINLength */

745

u32 tx127; /* Total number of frames (including bad

746

frames) transmitted that were between

747

MINLength (Including FCS length==4) and 127

748

octets */

749

u32 tx255; /* Total number of frames (including bad

750

frames) transmitted that were between 128

751

(Including FCS length==4) and 255 octets */

752

u32 rx64; /* Total number of frames received including

753

bad frames that were exactly of the mninimal

754

length (64 bytes) */

755

u32 rx127; /* Total number of frames (including bad

756

frames) received that were between MINLength

757

(Including FCS length==4) and 127 octets */

758

u32 rx255; /* Total number of frames (including bad

759

frames) received that were between 128

760

(Including FCS length==4) and 255 octets */

761

u32 txok; /* Total number of octets residing in frames

762

that where involved in succesfull

763

transmission */

764

u16 txcf; /* Total number of PAUSE control frames

765

transmitted by this MAC */

766

u32 tmca; /* Total number of frames that were transmitted

767

succesfully with the group address bit set

768

that are not broadcast frames */

769

u32 tbca; /* Total number of frames transmitted

770

succesfully that had destination address

771

field equal to the broadcast address */

772

u32 rxfok; /* Total number of frames received OK */

773

u32 rxbok; /* Total number of octets received OK */

774

u32 rbyt; /* Total number of octets received including

775

octets in bad frames. Must be implemented in

776

HW because it includes octets in frames that

777

never even reach the UCC */

778

u32 rmca; /* Total number of frames that were received

779

succesfully with the group address bit set

780

that are not broadcast frames */

781

u32 rbca; /* Total number of frames received succesfully

782

that had destination address equal to the

783

broadcast address */

784

} __attribute__ ((packed));

785

786

/* UCC GETH Tx errors returned via TxConf callback */

787

#define TX_ERRORS_DEF 0x0200

788

#define TX_ERRORS_EXDEF 0x0100

789

#define TX_ERRORS_LC 0x0080

790

#define TX_ERRORS_RL 0x0040

791

#define TX_ERRORS_RC_MASK 0x003C

792

#define TX_ERRORS_RC_SHIFT 2

793

#define TX_ERRORS_UN 0x0002

794

#define TX_ERRORS_CSL 0x0001

795

796

/* UCC GETH Rx errors returned via RxStore callback */

797

#define RX_ERRORS_CMR 0x0200

798

#define RX_ERRORS_M 0x0100

799

#define RX_ERRORS_BC 0x0080

800

#define RX_ERRORS_MC 0x0040

801

802

/* Transmit BD. These are in addition to values defined in uccf. */

803

#define T_VID 0x003c0000 /* insert VLAN id index mask. */

804

#define T_DEF (((u32) TX_ERRORS_DEF ) << 16)

805

#define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16)

806

#define T_LC (((u32) TX_ERRORS_LC ) << 16)

807

#define T_RL (((u32) TX_ERRORS_RL ) << 16)

808

#define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16)

809

#define T_UN (((u32) TX_ERRORS_UN ) << 16)

810

#define T_CSL (((u32) TX_ERRORS_CSL ) << 16)

811

#define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \

812

| T_UN | T_CSL) /* transmit errors to report */

813

814

/* Receive BD. These are in addition to values defined in uccf. */

815

#define R_LG 0x00200000 /* Frame length violation. */

816

#define R_NO 0x00100000 /* Non-octet aligned frame. */

817

#define R_SH 0x00080000 /* Short frame. */

818

#define R_CR 0x00040000 /* CRC error. */

819

#define R_OV 0x00020000 /* Overrun. */

820

#define R_IPCH 0x00010000 /* IP checksum check failed. */

821

#define R_CMR (((u32) RX_ERRORS_CMR ) << 16)

822

#define R_M (((u32) RX_ERRORS_M ) << 16)

823

#define R_BC (((u32) RX_ERRORS_BC ) << 16)

824

#define R_MC (((u32) RX_ERRORS_MC ) << 16)

825

#define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to

826

report */

827

#define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \

828

R_OV | R_IPCH) /* receive errors to discard */

829

830

/* Alignments */

831

#define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256

832

#define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128

833

#define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128

834

#define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64

835

#define UCC_GETH_THREAD_DATA_ALIGNMENT 256 /* spec gives values

based on num of

threads, but always

using the maximum is

easier */

#define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32

841

#define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */

842

#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */

843

#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */

844

#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64

845

#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */

846

#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */

847

#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This

is a

guess

*/

#define UCC_GETH_RX_BD_RING_ALIGNMENT 32

852

#define UCC_GETH_TX_BD_RING_ALIGNMENT 32

853

#define UCC_GETH_MRBLR_ALIGNMENT 128

854

#define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4

855

#define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32

856

#define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64

857

858

#define UCC_GETH_TAD_EF 0x80

859

#define UCC_GETH_TAD_V 0x40

860

#define UCC_GETH_TAD_REJ 0x20

861

#define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2

862

#define UCC_GETH_TAD_VTAG_OP_SHIFT 6

863

#define UCC_GETH_TAD_V_NON_VTAG_OP 0x20

864

#define UCC_GETH_TAD_RQOS_SHIFT 0

865

#define UCC_GETH_TAD_V_PRIORITY_SHIFT 5

866

#define UCC_GETH_TAD_CFI 0x10

867

868

#define UCC_GETH_VLAN_PRIORITY_MAX 8

869

#define UCC_GETH_IP_PRIORITY_MAX 64

870

#define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8

871

#define UCC_GETH_RX_BD_RING_SIZE_MIN 8

872

#define UCC_GETH_TX_BD_RING_SIZE_MIN 2

873

#define UCC_GETH_BD_RING_SIZE_MAX 0xffff

874

875

#define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD

876

877

/* Driver definitions */

878

#define TX_BD_RING_LEN 0x10

879

#define RX_BD_RING_LEN 0x10

880

881

#define TX_RING_MOD_MASK(size) (size-1)

882

#define RX_RING_MOD_MASK(size) (size-1)

883

884

#define ENET_NUM_OCTETS_PER_ADDRESS 6

885

#define ENET_GROUP_ADDR 0x01 /* Group address mask

for ethernet

addresses */

#define TX_TIMEOUT (1*HZ)

890

#define SKB_ALLOC_TIMEOUT 100000

891

#define PHY_INIT_TIMEOUT 100000

892

#define PHY_CHANGE_TIME 2

893

894

/* Fast Ethernet (10/100 Mbps) */

895

#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size

896

*/

897

#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */

898

#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */

899

#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size

900

*/

901

#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */

902

#define UCC_GETH_UTFTT_INIT 128

903

/* Gigabit Ethernet (1000 Mbps) */

904

#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual

905

FIFO size */

906

#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */

907

#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */

908

#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual

909

FIFO size */

910

#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */

911

#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */

912

913

#define UCC_GETH_REMODER_INIT 0 /* bits that must be

914

set */

915

#define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */

916

917

/* Initial value for UPSMR */

918

#define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1

919

920

#define UCC_GETH_MACCFG1_INIT 0

921

#define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1)

922

923

/* Ethernet Address Type. */

924

enum enet_addr_type {

925

ENET_ADDR_TYPE_INDIVIDUAL,

926

ENET_ADDR_TYPE_GROUP,

927

ENET_ADDR_TYPE_BROADCAST

928

};

929

930

/* UCC GETH 82xx Ethernet Address Recognition Location */

931

enum ucc_geth_enet_address_recognition_location {

932

UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station

933

address */

934

UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional

station

address

paddr1 */

UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2, /* additional

station

address

paddr2 */

UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3, /* additional

station

address

paddr3 */

UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST, /* additional

station

address

paddr4 */

UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */

951

UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual

hash */

};

/* UCC GETH vlan operation tagged */

956

enum ucc_geth_vlan_operation_tagged {

957

UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */

958

UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG

959

= 0x1, /* Tagged - replace vid portion of q tag */

960

UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE

961

= 0x2, /* Tagged - if vid0 replace vid with default value */

962

UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME

963

= 0x3 /* Tagged - extract q tag from frame */

964

};

965

966

/* UCC GETH vlan operation non-tagged */

967

enum ucc_geth_vlan_operation_non_tagged {

968

UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */

969

UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged -

q tag insert

*/

};

/* UCC GETH Rx Quality of Service Mode */

975

enum ucc_geth_qos_mode {

976

UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */

977

UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue

determined

by L2

criteria */

UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2 /* queue

determined

by L3

criteria */

};

/* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together

988

for combined functionality */

989

enum ucc_geth_statistics_gathering_mode {

990

UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No

991

statistics

992

gathering */

993

UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable

hardware

statistics

gathering

*/

UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable

firmware

tx

statistics

gathering

*/

UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable

firmware

rx

statistics

gathering

*/

};

/* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */

1013

enum ucc_geth_maccfg2_pad_and_crc_mode {

1014

UCC_GETH_PAD_AND_CRC_MODE_NONE

1015

= MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding

1016

short frames

1017

nor CRC */

1018

UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY

1019

= MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY, /* Append

1020

CRC only */

1021

UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =

1022

MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC

1023

};

1024

1025

/* UCC GETH upsmr Flow Control Mode */

1026

enum ucc_geth_flow_control_mode {

1027

UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic

1028

flow control

1029

*/

1030

UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY

1031

= 0x00004000 /* Send pause frame when RxFIFO reaches its

1032

emergency threshold */

1033

};

1034

1035

/* UCC GETH number of threads */

1036

enum ucc_geth_num_of_threads {

1037

UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */

1038

UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */

1039

UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */

1040

UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */

1041

UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */

1042

};

1043

1044

/* UCC GETH number of station addresses */

1045

enum ucc_geth_num_of_station_addresses {

1046

UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */

1047

UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */

1048

};

1049

1050

/* UCC GETH 82xx Ethernet Address Container */

1051

struct enet_addr_container {

1052

u8 address[ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */

1053

enum ucc_geth_enet_address_recognition_location location; /* location in

82xx address

recognition

hardware */

struct list_head node;

1058

};

1059

1060

#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)

1061

1062

/* UCC GETH Termination Action Descriptor (TAD) structure. */

1063

struct ucc_geth_tad_params {

1064

int rx_non_dynamic_extended_features_mode;

1065

int reject_frame;

1066

enum ucc_geth_vlan_operation_tagged vtag_op;

1067

enum ucc_geth_vlan_operation_non_tagged vnontag_op;

1068

enum ucc_geth_qos_mode rqos;

u8 vpri;

u16 vid;

};

/* GETH protocol initialization structure */

1074

struct ucc_geth_info {

1075

struct ucc_fast_info uf_info;

u8 numQueuesTx;

u8 numQueuesRx;

int ipCheckSumCheck;

int ipCheckSumGenerate;

1080

int rxExtendedFiltering;

1081

u32 extendedFilteringChainPointer;

1082

u16 typeorlen;

1083

int dynamicMaxFrameLength;

1084

int dynamicMinFrameLength;

1085

u8 nonBackToBackIfgPart1;

1086

u8 nonBackToBackIfgPart2;

1087

u8 miminumInterFrameGapEnforcement;

1088

u8 backToBackInterFrameGap;

1089

int ipAddressAlignment;

int lengthCheckRx;

u32 mblinterval;

u16 nortsrbytetime;

u8 fracsiz;

u8 strictpriorityq;

u8 txasap;

u8 extrabw;

int miiPreambleSupress;

1098

u8 altBebTruncation;

1099

int altBeb;

1100

int backPressureNoBackoff;

1101

int noBackoff;

1102

int excessDefer;

1103

u8 maxRetransmission;

u8 collisionWindow;

int pro;

int cap;

int rsh;

int rlpb;

int cam;

int bro;

int ecm;

int receiveFlowControl;

1113

int transmitFlowControl;

1114

u8 maxGroupAddrInHash;

u8 maxIndAddrInHash;

u8 prel;

u16 maxFrameLength;

u16 minFrameLength;

u16 maxD1Length;

u16 maxD2Length;

u16 vlantype;

u16 vlantci;

u32 ecamptr;

u32 eventRegMask;

u16 pausePeriod;

u16 extensionField;

struct device_node *phy_node;

1128

struct device_node *tbi_node;

1129

u8 weightfactor[NUM_TX_QUEUES];

1130

u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];

1131

u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];

1132

u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];

1133

u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];

1134

u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];

1135

u16 bdRingLenTx[NUM_TX_QUEUES];

1136

u16 bdRingLenRx[NUM_RX_QUEUES];

1137

enum ucc_geth_num_of_station_addresses numStationAddresses;

1138

enum qe_fltr_largest_external_tbl_lookup_key_size

1139

largestexternallookupkeysize;

1140

enum ucc_geth_statistics_gathering_mode statisticsMode;

1141

enum ucc_geth_vlan_operation_tagged vlanOperationTagged;

1142

enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;

1143

enum ucc_geth_qos_mode rxQoSMode;

1144

enum ucc_geth_flow_control_mode aufc;

1145

enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;

1146

enum ucc_geth_num_of_threads numThreadsTx;

1147

enum ucc_geth_num_of_threads numThreadsRx;

unsigned int riscTx;

unsigned int riscRx;

};

/* structure representing UCC GETH */

1153

struct ucc_geth_private {

1154

struct ucc_geth_info *ug_info;

1155

struct ucc_fast_private *uccf;

1156

struct device *dev;

1157

struct net_device *ndev;

1158

struct napi_struct napi;

1159

struct work_struct timeout_work;

1160

struct ucc_geth __iomem *ug_regs;

1161

struct ucc_geth_init_pram *p_init_enet_param_shadow;

1162

struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;

1163

u32 exf_glbl_param_offset;

1164

struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;

1165

u32 rx_glbl_pram_offset;

1166

struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;

1167

u32 tx_glbl_pram_offset;

1168

struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;

1169

u32 send_q_mem_reg_offset;

1170

struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;

1171

u32 thread_dat_tx_offset;

1172

struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;

1173

u32 thread_dat_rx_offset;

1174

struct ucc_geth_scheduler __iomem *p_scheduler;

1175

u32 scheduler_offset;

1176

struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;

1177

u32 tx_fw_statistics_pram_offset;

1178

struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;

1179

u32 rx_fw_statistics_pram_offset;

1180

struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;

1181

u32 rx_irq_coalescing_tbl_offset;

1182

struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;

1183

u32 rx_bd_qs_tbl_offset;

1184

u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];

1185

u32 tx_bd_ring_offset[NUM_TX_QUEUES];

1186

u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];

1187

u32 rx_bd_ring_offset[NUM_RX_QUEUES];

1188

u8 __iomem *confBd[NUM_TX_QUEUES];

1189

u8 __iomem *txBd[NUM_TX_QUEUES];

1190

u8 __iomem *rxBd[NUM_RX_QUEUES];

1191

int badFrame[NUM_RX_QUEUES];

1192

u16 cpucount[NUM_TX_QUEUES];

1193

u16 __iomem *p_cpucount[NUM_TX_QUEUES];

1194

int indAddrRegUsed[NUM_OF_PADDRS];

1195

u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */

1196

u8 numGroupAddrInHash;

1197

u8 numIndAddrInHash;

1198

u8 numIndAddrInReg;

1199

int rx_extended_features;

1200

int rx_non_dynamic_extended_features;

1201

struct list_head conf_skbs;

1202

struct list_head group_hash_q;

1203

struct list_head ind_hash_q;

1204

u32 saved_uccm;

1205

spinlock_t lock;

1206

/* pointers to arrays of skbuffs for tx and rx */

1207

struct sk_buff **tx_skbuff[NUM_TX_QUEUES];

1208

struct sk_buff **rx_skbuff[NUM_RX_QUEUES];

1209

/* indices pointing to the next free sbk in skb arrays */

1210

u16 skb_curtx[NUM_TX_QUEUES];

1211

u16 skb_currx[NUM_RX_QUEUES];

1212

/* index of the first skb which hasn't been transmitted yet. */

1213

u16 skb_dirtytx[NUM_TX_QUEUES];

1214

1215

struct ugeth_mii_info *mii_info;

1216

struct phy_device *phydev;

1217

phy_interface_t phy_interface;

int max_speed;

uint32_t msg_enable;

int oldspeed;

int oldduplex;

int oldlink;

struct device_node *node;

1225

};

1226

1227

void uec_set_ethtool_ops(struct net_device *netdev);

1228

int init_flow_control_params(u32 automatic_flow_control_mode,

1229

int rx_flow_control_enable, int tx_flow_control_enable,

1230

u16 pause_period, u16 extension_field,

1231

u32 __iomem *upsmr_register, u32 __iomem *uempr_register,

1232

u32 __iomem *maccfg1_register);

1233

1234

1235

#endif /* __UCC_GETH_H__ */

1236

Kernel

Kernel Git Source Tree

Root/drivers/net/ucc_geth.h

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