Root/drivers/net/via-rhine.c

1/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3    Written 1998-2001 by Donald Becker.
4
5    Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7    This software may be used and distributed according to the terms of
8    the GNU General Public License (GPL), incorporated herein by reference.
9    Drivers based on or derived from this code fall under the GPL and must
10    retain the authorship, copyright and license notice. This file is not
11    a complete program and may only be used when the entire operating
12    system is licensed under the GPL.
13
14    This driver is designed for the VIA VT86C100A Rhine-I.
15    It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16    and management NIC 6105M).
17
18    The author may be reached as becker@scyld.com, or C/O
19    Scyld Computing Corporation
20    410 Severn Ave., Suite 210
21    Annapolis MD 21403
22
23
24    This driver contains some changes from the original Donald Becker
25    version. He may or may not be interested in bug reports on this
26    code. You can find his versions at:
27    http://www.scyld.com/network/via-rhine.html
28    [link no longer provides useful info -jgarzik]
29
30*/
31
32#define DRV_NAME "via-rhine"
33#define DRV_VERSION "1.4.3"
34#define DRV_RELDATE "2007-03-06"
35
36
37/* A few user-configurable values.
38   These may be modified when a driver module is loaded. */
39
40static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41static int max_interrupt_work = 20;
42
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44   Setting to > 1518 effectively disables this feature. */
45#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
46       || defined(CONFIG_SPARC) || defined(__ia64__) \
47       || defined(__sh__) || defined(__mips__)
48static int rx_copybreak = 1518;
49#else
50static int rx_copybreak;
51#endif
52
53/* Work-around for broken BIOSes: they are unable to get the chip back out of
54   power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
55static int avoid_D3;
56
57/*
58 * In case you are looking for 'options[]' or 'full_duplex[]', they
59 * are gone. Use ethtool(8) instead.
60 */
61
62/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63   The Rhine has a 64 element 8390-like hash table. */
64static const int multicast_filter_limit = 32;
65
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for compile efficiency.
70   The compiler will convert <unsigned>'%'<2^N> into a bit mask.
71   Making the Tx ring too large decreases the effectiveness of channel
72   bonding and packet priority.
73   There are no ill effects from too-large receive rings. */
74#define TX_RING_SIZE 16
75#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
76#define RX_RING_SIZE 64
77
78/* Operational parameters that usually are not changed. */
79
80/* Time in jiffies before concluding the transmitter is hung. */
81#define TX_TIMEOUT (2*HZ)
82
83#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85#include <linux/module.h>
86#include <linux/moduleparam.h>
87#include <linux/kernel.h>
88#include <linux/string.h>
89#include <linux/timer.h>
90#include <linux/errno.h>
91#include <linux/ioport.h>
92#include <linux/slab.h>
93#include <linux/interrupt.h>
94#include <linux/pci.h>
95#include <linux/dma-mapping.h>
96#include <linux/netdevice.h>
97#include <linux/etherdevice.h>
98#include <linux/skbuff.h>
99#include <linux/init.h>
100#include <linux/delay.h>
101#include <linux/mii.h>
102#include <linux/ethtool.h>
103#include <linux/crc32.h>
104#include <linux/bitops.h>
105#include <asm/processor.h> /* Processor type for cache alignment. */
106#include <asm/io.h>
107#include <asm/irq.h>
108#include <asm/uaccess.h>
109#include <linux/dmi.h>
110
111/* These identify the driver base version and may not be removed. */
112static const char version[] __devinitconst =
113    KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE
114    " Written by Donald Becker\n";
115
116/* This driver was written to use PCI memory space. Some early versions
117   of the Rhine may only work correctly with I/O space accesses. */
118#ifdef CONFIG_VIA_RHINE_MMIO
119#define USE_MMIO
120#else
121#endif
122
123MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
124MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
125MODULE_LICENSE("GPL");
126
127module_param(max_interrupt_work, int, 0);
128module_param(debug, int, 0);
129module_param(rx_copybreak, int, 0);
130module_param(avoid_D3, bool, 0);
131MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
132MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
133MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
134MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
135
136/*
137        Theory of Operation
138
139I. Board Compatibility
140
141This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
142controller.
143
144II. Board-specific settings
145
146Boards with this chip are functional only in a bus-master PCI slot.
147
148Many operational settings are loaded from the EEPROM to the Config word at
149offset 0x78. For most of these settings, this driver assumes that they are
150correct.
151If this driver is compiled to use PCI memory space operations the EEPROM
152must be configured to enable memory ops.
153
154III. Driver operation
155
156IIIa. Ring buffers
157
158This driver uses two statically allocated fixed-size descriptor lists
159formed into rings by a branch from the final descriptor to the beginning of
160the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
161
162IIIb/c. Transmit/Receive Structure
163
164This driver attempts to use a zero-copy receive and transmit scheme.
165
166Alas, all data buffers are required to start on a 32 bit boundary, so
167the driver must often copy transmit packets into bounce buffers.
168
169The driver allocates full frame size skbuffs for the Rx ring buffers at
170open() time and passes the skb->data field to the chip as receive data
171buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
172a fresh skbuff is allocated and the frame is copied to the new skbuff.
173When the incoming frame is larger, the skbuff is passed directly up the
174protocol stack. Buffers consumed this way are replaced by newly allocated
175skbuffs in the last phase of rhine_rx().
176
177The RX_COPYBREAK value is chosen to trade-off the memory wasted by
178using a full-sized skbuff for small frames vs. the copying costs of larger
179frames. New boards are typically used in generously configured machines
180and the underfilled buffers have negligible impact compared to the benefit of
181a single allocation size, so the default value of zero results in never
182copying packets. When copying is done, the cost is usually mitigated by using
183a combined copy/checksum routine. Copying also preloads the cache, which is
184most useful with small frames.
185
186Since the VIA chips are only able to transfer data to buffers on 32 bit
187boundaries, the IP header at offset 14 in an ethernet frame isn't
188longword aligned for further processing. Copying these unaligned buffers
189has the beneficial effect of 16-byte aligning the IP header.
190
191IIId. Synchronization
192
193The driver runs as two independent, single-threaded flows of control. One
194is the send-packet routine, which enforces single-threaded use by the
195netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
196which is single threaded by the hardware and interrupt handling software.
197
198The send packet thread has partial control over the Tx ring. It locks the
199netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
200the ring is not available it stops the transmit queue by
201calling netif_stop_queue.
202
203The interrupt handler has exclusive control over the Rx ring and records stats
204from the Tx ring. After reaping the stats, it marks the Tx queue entry as
205empty by incrementing the dirty_tx mark. If at least half of the entries in
206the Rx ring are available the transmit queue is woken up if it was stopped.
207
208IV. Notes
209
210IVb. References
211
212Preliminary VT86C100A manual from http://www.via.com.tw/
213http://www.scyld.com/expert/100mbps.html
214http://www.scyld.com/expert/NWay.html
215ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
216ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
217
218
219IVc. Errata
220
221The VT86C100A manual is not reliable information.
222The 3043 chip does not handle unaligned transmit or receive buffers, resulting
223in significant performance degradation for bounce buffer copies on transmit
224and unaligned IP headers on receive.
225The chip does not pad to minimum transmit length.
226
227*/
228
229
230/* This table drives the PCI probe routines. It's mostly boilerplate in all
231   of the drivers, and will likely be provided by some future kernel.
232   Note the matching code -- the first table entry matchs all 56** cards but
233   second only the 1234 card.
234*/
235
236enum rhine_revs {
237    VT86C100A = 0x00,
238    VTunknown0 = 0x20,
239    VT6102 = 0x40,
240    VT8231 = 0x50, /* Integrated MAC */
241    VT8233 = 0x60, /* Integrated MAC */
242    VT8235 = 0x74, /* Integrated MAC */
243    VT8237 = 0x78, /* Integrated MAC */
244    VTunknown1 = 0x7C,
245    VT6105 = 0x80,
246    VT6105_B0 = 0x83,
247    VT6105L = 0x8A,
248    VT6107 = 0x8C,
249    VTunknown2 = 0x8E,
250    VT6105M = 0x90, /* Management adapter */
251};
252
253enum rhine_quirks {
254    rqWOL = 0x0001, /* Wake-On-LAN support */
255    rqForceReset = 0x0002,
256    rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
257    rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
258    rqRhineI = 0x0100, /* See comment below */
259};
260/*
261 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
262 * MMIO as well as for the collision counter and the Tx FIFO underflow
263 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
264 */
265
266/* Beware of PCI posted writes */
267#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
268
269static const struct pci_device_id rhine_pci_tbl[] = {
270    { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
271    { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
272    { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
273    { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
274    { } /* terminate list */
275};
276MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
277
278
279/* Offsets to the device registers. */
280enum register_offsets {
281    StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
282    ChipCmd1=0x09,
283    IntrStatus=0x0C, IntrEnable=0x0E,
284    MulticastFilter0=0x10, MulticastFilter1=0x14,
285    RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
286    MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
287    MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
288    ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
289    RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
290    StickyHW=0x83, IntrStatus2=0x84,
291    WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
292    WOLcrClr1=0xA6, WOLcgClr=0xA7,
293    PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
294};
295
296/* Bits in ConfigD */
297enum backoff_bits {
298    BackOptional=0x01, BackModify=0x02,
299    BackCaptureEffect=0x04, BackRandom=0x08
300};
301
302#ifdef USE_MMIO
303/* Registers we check that mmio and reg are the same. */
304static const int mmio_verify_registers[] = {
305    RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
306    0
307};
308#endif
309
310/* Bits in the interrupt status/mask registers. */
311enum intr_status_bits {
312    IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
313    IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
314    IntrPCIErr=0x0040,
315    IntrStatsMax=0x0080, IntrRxEarly=0x0100,
316    IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
317    IntrTxAborted=0x2000, IntrLinkChange=0x4000,
318    IntrRxWakeUp=0x8000,
319    IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
320    IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
321    IntrTxErrSummary=0x082218,
322};
323
324/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
325enum wol_bits {
326    WOLucast = 0x10,
327    WOLmagic = 0x20,
328    WOLbmcast = 0x30,
329    WOLlnkon = 0x40,
330    WOLlnkoff = 0x80,
331};
332
333/* The Rx and Tx buffer descriptors. */
334struct rx_desc {
335    __le32 rx_status;
336    __le32 desc_length; /* Chain flag, Buffer/frame length */
337    __le32 addr;
338    __le32 next_desc;
339};
340struct tx_desc {
341    __le32 tx_status;
342    __le32 desc_length; /* Chain flag, Tx Config, Frame length */
343    __le32 addr;
344    __le32 next_desc;
345};
346
347/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
348#define TXDESC 0x00e08000
349
350enum rx_status_bits {
351    RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
352};
353
354/* Bits in *_desc.*_status */
355enum desc_status_bits {
356    DescOwn=0x80000000
357};
358
359/* Bits in ChipCmd. */
360enum chip_cmd_bits {
361    CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
362    CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
363    Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
364    Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
365};
366
367struct rhine_private {
368    /* Descriptor rings */
369    struct rx_desc *rx_ring;
370    struct tx_desc *tx_ring;
371    dma_addr_t rx_ring_dma;
372    dma_addr_t tx_ring_dma;
373
374    /* The addresses of receive-in-place skbuffs. */
375    struct sk_buff *rx_skbuff[RX_RING_SIZE];
376    dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
377
378    /* The saved address of a sent-in-place packet/buffer, for later free(). */
379    struct sk_buff *tx_skbuff[TX_RING_SIZE];
380    dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
381
382    /* Tx bounce buffers (Rhine-I only) */
383    unsigned char *tx_buf[TX_RING_SIZE];
384    unsigned char *tx_bufs;
385    dma_addr_t tx_bufs_dma;
386
387    struct pci_dev *pdev;
388    long pioaddr;
389    struct net_device *dev;
390    struct napi_struct napi;
391    spinlock_t lock;
392
393    /* Frequently used values: keep some adjacent for cache effect. */
394    u32 quirks;
395    struct rx_desc *rx_head_desc;
396    unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
397    unsigned int cur_tx, dirty_tx;
398    unsigned int rx_buf_sz; /* Based on MTU+slack. */
399    u8 wolopts;
400
401    u8 tx_thresh, rx_thresh;
402
403    struct mii_if_info mii_if;
404    void __iomem *base;
405};
406
407static int mdio_read(struct net_device *dev, int phy_id, int location);
408static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
409static int rhine_open(struct net_device *dev);
410static void rhine_tx_timeout(struct net_device *dev);
411static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
412static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
413static void rhine_tx(struct net_device *dev);
414static int rhine_rx(struct net_device *dev, int limit);
415static void rhine_error(struct net_device *dev, int intr_status);
416static void rhine_set_rx_mode(struct net_device *dev);
417static struct net_device_stats *rhine_get_stats(struct net_device *dev);
418static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
419static const struct ethtool_ops netdev_ethtool_ops;
420static int rhine_close(struct net_device *dev);
421static void rhine_shutdown (struct pci_dev *pdev);
422
423#define RHINE_WAIT_FOR(condition) do { \
424    int i=1024; \
425    while (!(condition) && --i) \
426        ; \
427    if (debug > 1 && i < 512) \
428        printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
429                DRV_NAME, 1024-i, __func__, __LINE__); \
430} while(0)
431
432static inline u32 get_intr_status(struct net_device *dev)
433{
434    struct rhine_private *rp = netdev_priv(dev);
435    void __iomem *ioaddr = rp->base;
436    u32 intr_status;
437
438    intr_status = ioread16(ioaddr + IntrStatus);
439    /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
440    if (rp->quirks & rqStatusWBRace)
441        intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
442    return intr_status;
443}
444
445/*
446 * Get power related registers into sane state.
447 * Notify user about past WOL event.
448 */
449static void rhine_power_init(struct net_device *dev)
450{
451    struct rhine_private *rp = netdev_priv(dev);
452    void __iomem *ioaddr = rp->base;
453    u16 wolstat;
454
455    if (rp->quirks & rqWOL) {
456        /* Make sure chip is in power state D0 */
457        iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
458
459        /* Disable "force PME-enable" */
460        iowrite8(0x80, ioaddr + WOLcgClr);
461
462        /* Clear power-event config bits (WOL) */
463        iowrite8(0xFF, ioaddr + WOLcrClr);
464        /* More recent cards can manage two additional patterns */
465        if (rp->quirks & rq6patterns)
466            iowrite8(0x03, ioaddr + WOLcrClr1);
467
468        /* Save power-event status bits */
469        wolstat = ioread8(ioaddr + PwrcsrSet);
470        if (rp->quirks & rq6patterns)
471            wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
472
473        /* Clear power-event status bits */
474        iowrite8(0xFF, ioaddr + PwrcsrClr);
475        if (rp->quirks & rq6patterns)
476            iowrite8(0x03, ioaddr + PwrcsrClr1);
477
478        if (wolstat) {
479            char *reason;
480            switch (wolstat) {
481            case WOLmagic:
482                reason = "Magic packet";
483                break;
484            case WOLlnkon:
485                reason = "Link went up";
486                break;
487            case WOLlnkoff:
488                reason = "Link went down";
489                break;
490            case WOLucast:
491                reason = "Unicast packet";
492                break;
493            case WOLbmcast:
494                reason = "Multicast/broadcast packet";
495                break;
496            default:
497                reason = "Unknown";
498            }
499            printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
500                   DRV_NAME, reason);
501        }
502    }
503}
504
505static void rhine_chip_reset(struct net_device *dev)
506{
507    struct rhine_private *rp = netdev_priv(dev);
508    void __iomem *ioaddr = rp->base;
509
510    iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
511    IOSYNC;
512
513    if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
514        printk(KERN_INFO "%s: Reset not complete yet. "
515            "Trying harder.\n", DRV_NAME);
516
517        /* Force reset */
518        if (rp->quirks & rqForceReset)
519            iowrite8(0x40, ioaddr + MiscCmd);
520
521        /* Reset can take somewhat longer (rare) */
522        RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
523    }
524
525    if (debug > 1)
526        printk(KERN_INFO "%s: Reset %s.\n", dev->name,
527            (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
528            "failed" : "succeeded");
529}
530
531#ifdef USE_MMIO
532static void enable_mmio(long pioaddr, u32 quirks)
533{
534    int n;
535    if (quirks & rqRhineI) {
536        /* More recent docs say that this bit is reserved ... */
537        n = inb(pioaddr + ConfigA) | 0x20;
538        outb(n, pioaddr + ConfigA);
539    } else {
540        n = inb(pioaddr + ConfigD) | 0x80;
541        outb(n, pioaddr + ConfigD);
542    }
543}
544#endif
545
546/*
547 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
548 * (plus 0x6C for Rhine-I/II)
549 */
550static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
551{
552    struct rhine_private *rp = netdev_priv(dev);
553    void __iomem *ioaddr = rp->base;
554
555    outb(0x20, pioaddr + MACRegEEcsr);
556    RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
557
558#ifdef USE_MMIO
559    /*
560     * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
561     * MMIO. If reloading EEPROM was done first this could be avoided, but
562     * it is not known if that still works with the "win98-reboot" problem.
563     */
564    enable_mmio(pioaddr, rp->quirks);
565#endif
566
567    /* Turn off EEPROM-controlled wake-up (magic packet) */
568    if (rp->quirks & rqWOL)
569        iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
570
571}
572
573#ifdef CONFIG_NET_POLL_CONTROLLER
574static void rhine_poll(struct net_device *dev)
575{
576    disable_irq(dev->irq);
577    rhine_interrupt(dev->irq, (void *)dev);
578    enable_irq(dev->irq);
579}
580#endif
581
582static int rhine_napipoll(struct napi_struct *napi, int budget)
583{
584    struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
585    struct net_device *dev = rp->dev;
586    void __iomem *ioaddr = rp->base;
587    int work_done;
588
589    work_done = rhine_rx(dev, budget);
590
591    if (work_done < budget) {
592        napi_complete(napi);
593
594        iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
595              IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
596              IntrTxDone | IntrTxError | IntrTxUnderrun |
597              IntrPCIErr | IntrStatsMax | IntrLinkChange,
598              ioaddr + IntrEnable);
599    }
600    return work_done;
601}
602
603static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
604{
605    struct rhine_private *rp = netdev_priv(dev);
606
607    /* Reset the chip to erase previous misconfiguration. */
608    rhine_chip_reset(dev);
609
610    /* Rhine-I needs extra time to recuperate before EEPROM reload */
611    if (rp->quirks & rqRhineI)
612        msleep(5);
613
614    /* Reload EEPROM controlled bytes cleared by soft reset */
615    rhine_reload_eeprom(pioaddr, dev);
616}
617
618static const struct net_device_ops rhine_netdev_ops = {
619    .ndo_open = rhine_open,
620    .ndo_stop = rhine_close,
621    .ndo_start_xmit = rhine_start_tx,
622    .ndo_get_stats = rhine_get_stats,
623    .ndo_set_multicast_list = rhine_set_rx_mode,
624    .ndo_change_mtu = eth_change_mtu,
625    .ndo_validate_addr = eth_validate_addr,
626    .ndo_set_mac_address = eth_mac_addr,
627    .ndo_do_ioctl = netdev_ioctl,
628    .ndo_tx_timeout = rhine_tx_timeout,
629#ifdef CONFIG_NET_POLL_CONTROLLER
630    .ndo_poll_controller = rhine_poll,
631#endif
632};
633
634static int __devinit rhine_init_one(struct pci_dev *pdev,
635                    const struct pci_device_id *ent)
636{
637    struct net_device *dev;
638    struct rhine_private *rp;
639    int i, rc;
640    u32 quirks;
641    long pioaddr;
642    long memaddr;
643    void __iomem *ioaddr;
644    int io_size, phy_id;
645    const char *name;
646#ifdef USE_MMIO
647    int bar = 1;
648#else
649    int bar = 0;
650#endif
651
652/* when built into the kernel, we only print version if device is found */
653#ifndef MODULE
654    static int printed_version;
655    if (!printed_version++)
656        printk(version);
657#endif
658
659    io_size = 256;
660    phy_id = 0;
661    quirks = 0;
662    name = "Rhine";
663    if (pdev->revision < VTunknown0) {
664        quirks = rqRhineI;
665        io_size = 128;
666    }
667    else if (pdev->revision >= VT6102) {
668        quirks = rqWOL | rqForceReset;
669        if (pdev->revision < VT6105) {
670            name = "Rhine II";
671            quirks |= rqStatusWBRace; /* Rhine-II exclusive */
672        }
673        else {
674            phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
675            if (pdev->revision >= VT6105_B0)
676                quirks |= rq6patterns;
677            if (pdev->revision < VT6105M)
678                name = "Rhine III";
679            else
680                name = "Rhine III (Management Adapter)";
681        }
682    }
683
684    rc = pci_enable_device(pdev);
685    if (rc)
686        goto err_out;
687
688    /* this should always be supported */
689    rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
690    if (rc) {
691        printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
692               "the card!?\n");
693        goto err_out;
694    }
695
696    /* sanity check */
697    if ((pci_resource_len(pdev, 0) < io_size) ||
698        (pci_resource_len(pdev, 1) < io_size)) {
699        rc = -EIO;
700        printk(KERN_ERR "Insufficient PCI resources, aborting\n");
701        goto err_out;
702    }
703
704    pioaddr = pci_resource_start(pdev, 0);
705    memaddr = pci_resource_start(pdev, 1);
706
707    pci_set_master(pdev);
708
709    dev = alloc_etherdev(sizeof(struct rhine_private));
710    if (!dev) {
711        rc = -ENOMEM;
712        printk(KERN_ERR "alloc_etherdev failed\n");
713        goto err_out;
714    }
715    SET_NETDEV_DEV(dev, &pdev->dev);
716
717    rp = netdev_priv(dev);
718    rp->dev = dev;
719    rp->quirks = quirks;
720    rp->pioaddr = pioaddr;
721    rp->pdev = pdev;
722
723    rc = pci_request_regions(pdev, DRV_NAME);
724    if (rc)
725        goto err_out_free_netdev;
726
727    ioaddr = pci_iomap(pdev, bar, io_size);
728    if (!ioaddr) {
729        rc = -EIO;
730        printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
731               "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
732        goto err_out_free_res;
733    }
734
735#ifdef USE_MMIO
736    enable_mmio(pioaddr, quirks);
737
738    /* Check that selected MMIO registers match the PIO ones */
739    i = 0;
740    while (mmio_verify_registers[i]) {
741        int reg = mmio_verify_registers[i++];
742        unsigned char a = inb(pioaddr+reg);
743        unsigned char b = readb(ioaddr+reg);
744        if (a != b) {
745            rc = -EIO;
746            printk(KERN_ERR "MMIO do not match PIO [%02x] "
747                   "(%02x != %02x)\n", reg, a, b);
748            goto err_out_unmap;
749        }
750    }
751#endif /* USE_MMIO */
752
753    dev->base_addr = (unsigned long)ioaddr;
754    rp->base = ioaddr;
755
756    /* Get chip registers into a sane state */
757    rhine_power_init(dev);
758    rhine_hw_init(dev, pioaddr);
759
760    for (i = 0; i < 6; i++)
761        dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
762    memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
763
764    if (!is_valid_ether_addr(dev->perm_addr)) {
765        rc = -EIO;
766        printk(KERN_ERR "Invalid MAC address\n");
767        goto err_out_unmap;
768    }
769
770    /* For Rhine-I/II, phy_id is loaded from EEPROM */
771    if (!phy_id)
772        phy_id = ioread8(ioaddr + 0x6C);
773
774    dev->irq = pdev->irq;
775
776    spin_lock_init(&rp->lock);
777    rp->mii_if.dev = dev;
778    rp->mii_if.mdio_read = mdio_read;
779    rp->mii_if.mdio_write = mdio_write;
780    rp->mii_if.phy_id_mask = 0x1f;
781    rp->mii_if.reg_num_mask = 0x1f;
782
783    /* The chip-specific entries in the device structure. */
784    dev->netdev_ops = &rhine_netdev_ops;
785    dev->ethtool_ops = &netdev_ethtool_ops,
786    dev->watchdog_timeo = TX_TIMEOUT;
787
788    netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
789
790    if (rp->quirks & rqRhineI)
791        dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
792
793    /* dev->name not defined before register_netdev()! */
794    rc = register_netdev(dev);
795    if (rc)
796        goto err_out_unmap;
797
798    printk(KERN_INFO "%s: VIA %s at 0x%lx, %pM, IRQ %d.\n",
799           dev->name, name,
800#ifdef USE_MMIO
801           memaddr,
802#else
803           (long)ioaddr,
804#endif
805           dev->dev_addr, pdev->irq);
806
807    pci_set_drvdata(pdev, dev);
808
809    {
810        u16 mii_cmd;
811        int mii_status = mdio_read(dev, phy_id, 1);
812        mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
813        mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
814        if (mii_status != 0xffff && mii_status != 0x0000) {
815            rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
816            printk(KERN_INFO "%s: MII PHY found at address "
817                   "%d, status 0x%4.4x advertising %4.4x "
818                   "Link %4.4x.\n", dev->name, phy_id,
819                   mii_status, rp->mii_if.advertising,
820                   mdio_read(dev, phy_id, 5));
821
822            /* set IFF_RUNNING */
823            if (mii_status & BMSR_LSTATUS)
824                netif_carrier_on(dev);
825            else
826                netif_carrier_off(dev);
827
828        }
829    }
830    rp->mii_if.phy_id = phy_id;
831    if (debug > 1 && avoid_D3)
832        printk(KERN_INFO "%s: No D3 power state at shutdown.\n",
833               dev->name);
834
835    return 0;
836
837err_out_unmap:
838    pci_iounmap(pdev, ioaddr);
839err_out_free_res:
840    pci_release_regions(pdev);
841err_out_free_netdev:
842    free_netdev(dev);
843err_out:
844    return rc;
845}
846
847static int alloc_ring(struct net_device* dev)
848{
849    struct rhine_private *rp = netdev_priv(dev);
850    void *ring;
851    dma_addr_t ring_dma;
852
853    ring = pci_alloc_consistent(rp->pdev,
854                    RX_RING_SIZE * sizeof(struct rx_desc) +
855                    TX_RING_SIZE * sizeof(struct tx_desc),
856                    &ring_dma);
857    if (!ring) {
858        printk(KERN_ERR "Could not allocate DMA memory.\n");
859        return -ENOMEM;
860    }
861    if (rp->quirks & rqRhineI) {
862        rp->tx_bufs = pci_alloc_consistent(rp->pdev,
863                           PKT_BUF_SZ * TX_RING_SIZE,
864                           &rp->tx_bufs_dma);
865        if (rp->tx_bufs == NULL) {
866            pci_free_consistent(rp->pdev,
867                    RX_RING_SIZE * sizeof(struct rx_desc) +
868                    TX_RING_SIZE * sizeof(struct tx_desc),
869                    ring, ring_dma);
870            return -ENOMEM;
871        }
872    }
873
874    rp->rx_ring = ring;
875    rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
876    rp->rx_ring_dma = ring_dma;
877    rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
878
879    return 0;
880}
881
882static void free_ring(struct net_device* dev)
883{
884    struct rhine_private *rp = netdev_priv(dev);
885
886    pci_free_consistent(rp->pdev,
887                RX_RING_SIZE * sizeof(struct rx_desc) +
888                TX_RING_SIZE * sizeof(struct tx_desc),
889                rp->rx_ring, rp->rx_ring_dma);
890    rp->tx_ring = NULL;
891
892    if (rp->tx_bufs)
893        pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
894                    rp->tx_bufs, rp->tx_bufs_dma);
895
896    rp->tx_bufs = NULL;
897
898}
899
900static void alloc_rbufs(struct net_device *dev)
901{
902    struct rhine_private *rp = netdev_priv(dev);
903    dma_addr_t next;
904    int i;
905
906    rp->dirty_rx = rp->cur_rx = 0;
907
908    rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
909    rp->rx_head_desc = &rp->rx_ring[0];
910    next = rp->rx_ring_dma;
911
912    /* Init the ring entries */
913    for (i = 0; i < RX_RING_SIZE; i++) {
914        rp->rx_ring[i].rx_status = 0;
915        rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
916        next += sizeof(struct rx_desc);
917        rp->rx_ring[i].next_desc = cpu_to_le32(next);
918        rp->rx_skbuff[i] = NULL;
919    }
920    /* Mark the last entry as wrapping the ring. */
921    rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
922
923    /* Fill in the Rx buffers. Handle allocation failure gracefully. */
924    for (i = 0; i < RX_RING_SIZE; i++) {
925        struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
926        rp->rx_skbuff[i] = skb;
927        if (skb == NULL)
928            break;
929        skb->dev = dev; /* Mark as being used by this device. */
930
931        rp->rx_skbuff_dma[i] =
932            pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
933                       PCI_DMA_FROMDEVICE);
934
935        rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
936        rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
937    }
938    rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
939}
940
941static void free_rbufs(struct net_device* dev)
942{
943    struct rhine_private *rp = netdev_priv(dev);
944    int i;
945
946    /* Free all the skbuffs in the Rx queue. */
947    for (i = 0; i < RX_RING_SIZE; i++) {
948        rp->rx_ring[i].rx_status = 0;
949        rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
950        if (rp->rx_skbuff[i]) {
951            pci_unmap_single(rp->pdev,
952                     rp->rx_skbuff_dma[i],
953                     rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
954            dev_kfree_skb(rp->rx_skbuff[i]);
955        }
956        rp->rx_skbuff[i] = NULL;
957    }
958}
959
960static void alloc_tbufs(struct net_device* dev)
961{
962    struct rhine_private *rp = netdev_priv(dev);
963    dma_addr_t next;
964    int i;
965
966    rp->dirty_tx = rp->cur_tx = 0;
967    next = rp->tx_ring_dma;
968    for (i = 0; i < TX_RING_SIZE; i++) {
969        rp->tx_skbuff[i] = NULL;
970        rp->tx_ring[i].tx_status = 0;
971        rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
972        next += sizeof(struct tx_desc);
973        rp->tx_ring[i].next_desc = cpu_to_le32(next);
974        if (rp->quirks & rqRhineI)
975            rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
976    }
977    rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
978
979}
980
981static void free_tbufs(struct net_device* dev)
982{
983    struct rhine_private *rp = netdev_priv(dev);
984    int i;
985
986    for (i = 0; i < TX_RING_SIZE; i++) {
987        rp->tx_ring[i].tx_status = 0;
988        rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
989        rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
990        if (rp->tx_skbuff[i]) {
991            if (rp->tx_skbuff_dma[i]) {
992                pci_unmap_single(rp->pdev,
993                         rp->tx_skbuff_dma[i],
994                         rp->tx_skbuff[i]->len,
995                         PCI_DMA_TODEVICE);
996            }
997            dev_kfree_skb(rp->tx_skbuff[i]);
998        }
999        rp->tx_skbuff[i] = NULL;
1000        rp->tx_buf[i] = NULL;
1001    }
1002}
1003
1004static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1005{
1006    struct rhine_private *rp = netdev_priv(dev);
1007    void __iomem *ioaddr = rp->base;
1008
1009    mii_check_media(&rp->mii_if, debug, init_media);
1010
1011    if (rp->mii_if.full_duplex)
1012        iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1013           ioaddr + ChipCmd1);
1014    else
1015        iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1016           ioaddr + ChipCmd1);
1017    if (debug > 1)
1018        printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1019            rp->mii_if.force_media, netif_carrier_ok(dev));
1020}
1021
1022/* Called after status of force_media possibly changed */
1023static void rhine_set_carrier(struct mii_if_info *mii)
1024{
1025    if (mii->force_media) {
1026        /* autoneg is off: Link is always assumed to be up */
1027        if (!netif_carrier_ok(mii->dev))
1028            netif_carrier_on(mii->dev);
1029    }
1030    else /* Let MMI library update carrier status */
1031        rhine_check_media(mii->dev, 0);
1032    if (debug > 1)
1033        printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1034               mii->dev->name, mii->force_media,
1035               netif_carrier_ok(mii->dev));
1036}
1037
1038static void init_registers(struct net_device *dev)
1039{
1040    struct rhine_private *rp = netdev_priv(dev);
1041    void __iomem *ioaddr = rp->base;
1042    int i;
1043
1044    for (i = 0; i < 6; i++)
1045        iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1046
1047    /* Initialize other registers. */
1048    iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1049    /* Configure initial FIFO thresholds. */
1050    iowrite8(0x20, ioaddr + TxConfig);
1051    rp->tx_thresh = 0x20;
1052    rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1053
1054    iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1055    iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1056
1057    rhine_set_rx_mode(dev);
1058
1059    napi_enable(&rp->napi);
1060
1061    /* Enable interrupts by setting the interrupt mask. */
1062    iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1063           IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1064           IntrTxDone | IntrTxError | IntrTxUnderrun |
1065           IntrPCIErr | IntrStatsMax | IntrLinkChange,
1066           ioaddr + IntrEnable);
1067
1068    iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1069           ioaddr + ChipCmd);
1070    rhine_check_media(dev, 1);
1071}
1072
1073/* Enable MII link status auto-polling (required for IntrLinkChange) */
1074static void rhine_enable_linkmon(void __iomem *ioaddr)
1075{
1076    iowrite8(0, ioaddr + MIICmd);
1077    iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1078    iowrite8(0x80, ioaddr + MIICmd);
1079
1080    RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1081
1082    iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1083}
1084
1085/* Disable MII link status auto-polling (required for MDIO access) */
1086static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1087{
1088    iowrite8(0, ioaddr + MIICmd);
1089
1090    if (quirks & rqRhineI) {
1091        iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1092
1093        /* Can be called from ISR. Evil. */
1094        mdelay(1);
1095
1096        /* 0x80 must be set immediately before turning it off */
1097        iowrite8(0x80, ioaddr + MIICmd);
1098
1099        RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1100
1101        /* Heh. Now clear 0x80 again. */
1102        iowrite8(0, ioaddr + MIICmd);
1103    }
1104    else
1105        RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1106}
1107
1108/* Read and write over the MII Management Data I/O (MDIO) interface. */
1109
1110static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1111{
1112    struct rhine_private *rp = netdev_priv(dev);
1113    void __iomem *ioaddr = rp->base;
1114    int result;
1115
1116    rhine_disable_linkmon(ioaddr, rp->quirks);
1117
1118    /* rhine_disable_linkmon already cleared MIICmd */
1119    iowrite8(phy_id, ioaddr + MIIPhyAddr);
1120    iowrite8(regnum, ioaddr + MIIRegAddr);
1121    iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1122    RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1123    result = ioread16(ioaddr + MIIData);
1124
1125    rhine_enable_linkmon(ioaddr);
1126    return result;
1127}
1128
1129static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1130{
1131    struct rhine_private *rp = netdev_priv(dev);
1132    void __iomem *ioaddr = rp->base;
1133
1134    rhine_disable_linkmon(ioaddr, rp->quirks);
1135
1136    /* rhine_disable_linkmon already cleared MIICmd */
1137    iowrite8(phy_id, ioaddr + MIIPhyAddr);
1138    iowrite8(regnum, ioaddr + MIIRegAddr);
1139    iowrite16(value, ioaddr + MIIData);
1140    iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1141    RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1142
1143    rhine_enable_linkmon(ioaddr);
1144}
1145
1146static int rhine_open(struct net_device *dev)
1147{
1148    struct rhine_private *rp = netdev_priv(dev);
1149    void __iomem *ioaddr = rp->base;
1150    int rc;
1151
1152    rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name,
1153            dev);
1154    if (rc)
1155        return rc;
1156
1157    if (debug > 1)
1158        printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1159               dev->name, rp->pdev->irq);
1160
1161    rc = alloc_ring(dev);
1162    if (rc) {
1163        free_irq(rp->pdev->irq, dev);
1164        return rc;
1165    }
1166    alloc_rbufs(dev);
1167    alloc_tbufs(dev);
1168    rhine_chip_reset(dev);
1169    init_registers(dev);
1170    if (debug > 2)
1171        printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1172               "MII status: %4.4x.\n",
1173               dev->name, ioread16(ioaddr + ChipCmd),
1174               mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1175
1176    netif_start_queue(dev);
1177
1178    return 0;
1179}
1180
1181static void rhine_tx_timeout(struct net_device *dev)
1182{
1183    struct rhine_private *rp = netdev_priv(dev);
1184    void __iomem *ioaddr = rp->base;
1185
1186    printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1187           "%4.4x, resetting...\n",
1188           dev->name, ioread16(ioaddr + IntrStatus),
1189           mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1190
1191    /* protect against concurrent rx interrupts */
1192    disable_irq(rp->pdev->irq);
1193
1194    napi_disable(&rp->napi);
1195
1196    spin_lock(&rp->lock);
1197
1198    /* clear all descriptors */
1199    free_tbufs(dev);
1200    free_rbufs(dev);
1201    alloc_tbufs(dev);
1202    alloc_rbufs(dev);
1203
1204    /* Reinitialize the hardware. */
1205    rhine_chip_reset(dev);
1206    init_registers(dev);
1207
1208    spin_unlock(&rp->lock);
1209    enable_irq(rp->pdev->irq);
1210
1211    dev->trans_start = jiffies;
1212    dev->stats.tx_errors++;
1213    netif_wake_queue(dev);
1214}
1215
1216static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1217{
1218    struct rhine_private *rp = netdev_priv(dev);
1219    void __iomem *ioaddr = rp->base;
1220    unsigned entry;
1221    unsigned long flags;
1222
1223    /* Caution: the write order is important here, set the field
1224       with the "ownership" bits last. */
1225
1226    /* Calculate the next Tx descriptor entry. */
1227    entry = rp->cur_tx % TX_RING_SIZE;
1228
1229    if (skb_padto(skb, ETH_ZLEN))
1230        return 0;
1231
1232    rp->tx_skbuff[entry] = skb;
1233
1234    if ((rp->quirks & rqRhineI) &&
1235        (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1236        /* Must use alignment buffer. */
1237        if (skb->len > PKT_BUF_SZ) {
1238            /* packet too long, drop it */
1239            dev_kfree_skb(skb);
1240            rp->tx_skbuff[entry] = NULL;
1241            dev->stats.tx_dropped++;
1242            return 0;
1243        }
1244
1245        /* Padding is not copied and so must be redone. */
1246        skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1247        if (skb->len < ETH_ZLEN)
1248            memset(rp->tx_buf[entry] + skb->len, 0,
1249                   ETH_ZLEN - skb->len);
1250        rp->tx_skbuff_dma[entry] = 0;
1251        rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1252                              (rp->tx_buf[entry] -
1253                               rp->tx_bufs));
1254    } else {
1255        rp->tx_skbuff_dma[entry] =
1256            pci_map_single(rp->pdev, skb->data, skb->len,
1257                       PCI_DMA_TODEVICE);
1258        rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1259    }
1260
1261    rp->tx_ring[entry].desc_length =
1262        cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1263
1264    /* lock eth irq */
1265    spin_lock_irqsave(&rp->lock, flags);
1266    wmb();
1267    rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1268    wmb();
1269
1270    rp->cur_tx++;
1271
1272    /* Non-x86 Todo: explicitly flush cache lines here. */
1273
1274    /* Wake the potentially-idle transmit channel */
1275    iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1276           ioaddr + ChipCmd1);
1277    IOSYNC;
1278
1279    if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1280        netif_stop_queue(dev);
1281
1282    dev->trans_start = jiffies;
1283
1284    spin_unlock_irqrestore(&rp->lock, flags);
1285
1286    if (debug > 4) {
1287        printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1288               dev->name, rp->cur_tx-1, entry);
1289    }
1290    return 0;
1291}
1292
1293/* The interrupt handler does all of the Rx thread work and cleans up
1294   after the Tx thread. */
1295static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1296{
1297    struct net_device *dev = dev_instance;
1298    struct rhine_private *rp = netdev_priv(dev);
1299    void __iomem *ioaddr = rp->base;
1300    u32 intr_status;
1301    int boguscnt = max_interrupt_work;
1302    int handled = 0;
1303
1304    while ((intr_status = get_intr_status(dev))) {
1305        handled = 1;
1306
1307        /* Acknowledge all of the current interrupt sources ASAP. */
1308        if (intr_status & IntrTxDescRace)
1309            iowrite8(0x08, ioaddr + IntrStatus2);
1310        iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1311        IOSYNC;
1312
1313        if (debug > 4)
1314            printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1315                   dev->name, intr_status);
1316
1317        if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1318                   IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
1319            iowrite16(IntrTxAborted |
1320                  IntrTxDone | IntrTxError | IntrTxUnderrun |
1321                  IntrPCIErr | IntrStatsMax | IntrLinkChange,
1322                  ioaddr + IntrEnable);
1323
1324            napi_schedule(&rp->napi);
1325        }
1326
1327        if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1328            if (intr_status & IntrTxErrSummary) {
1329                /* Avoid scavenging before Tx engine turned off */
1330                RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1331                if (debug > 2 &&
1332                    ioread8(ioaddr+ChipCmd) & CmdTxOn)
1333                    printk(KERN_WARNING "%s: "
1334                           "rhine_interrupt() Tx engine "
1335                           "still on.\n", dev->name);
1336            }
1337            rhine_tx(dev);
1338        }
1339
1340        /* Abnormal error summary/uncommon events handlers. */
1341        if (intr_status & (IntrPCIErr | IntrLinkChange |
1342                   IntrStatsMax | IntrTxError | IntrTxAborted |
1343                   IntrTxUnderrun | IntrTxDescRace))
1344            rhine_error(dev, intr_status);
1345
1346        if (--boguscnt < 0) {
1347            printk(KERN_WARNING "%s: Too much work at interrupt, "
1348                   "status=%#8.8x.\n",
1349                   dev->name, intr_status);
1350            break;
1351        }
1352    }
1353
1354    if (debug > 3)
1355        printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1356               dev->name, ioread16(ioaddr + IntrStatus));
1357    return IRQ_RETVAL(handled);
1358}
1359
1360/* This routine is logically part of the interrupt handler, but isolated
1361   for clarity. */
1362static void rhine_tx(struct net_device *dev)
1363{
1364    struct rhine_private *rp = netdev_priv(dev);
1365    int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1366
1367    spin_lock(&rp->lock);
1368
1369    /* find and cleanup dirty tx descriptors */
1370    while (rp->dirty_tx != rp->cur_tx) {
1371        txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1372        if (debug > 6)
1373            printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
1374                   entry, txstatus);
1375        if (txstatus & DescOwn)
1376            break;
1377        if (txstatus & 0x8000) {
1378            if (debug > 1)
1379                printk(KERN_DEBUG "%s: Transmit error, "
1380                       "Tx status %8.8x.\n",
1381                       dev->name, txstatus);
1382            dev->stats.tx_errors++;
1383            if (txstatus & 0x0400)
1384                dev->stats.tx_carrier_errors++;
1385            if (txstatus & 0x0200)
1386                dev->stats.tx_window_errors++;
1387            if (txstatus & 0x0100)
1388                dev->stats.tx_aborted_errors++;
1389            if (txstatus & 0x0080)
1390                dev->stats.tx_heartbeat_errors++;
1391            if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1392                (txstatus & 0x0800) || (txstatus & 0x1000)) {
1393                dev->stats.tx_fifo_errors++;
1394                rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1395                break; /* Keep the skb - we try again */
1396            }
1397            /* Transmitter restarted in 'abnormal' handler. */
1398        } else {
1399            if (rp->quirks & rqRhineI)
1400                dev->stats.collisions += (txstatus >> 3) & 0x0F;
1401            else
1402                dev->stats.collisions += txstatus & 0x0F;
1403            if (debug > 6)
1404                printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1405                       (txstatus >> 3) & 0xF,
1406                       txstatus & 0xF);
1407            dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1408            dev->stats.tx_packets++;
1409        }
1410        /* Free the original skb. */
1411        if (rp->tx_skbuff_dma[entry]) {
1412            pci_unmap_single(rp->pdev,
1413                     rp->tx_skbuff_dma[entry],
1414                     rp->tx_skbuff[entry]->len,
1415                     PCI_DMA_TODEVICE);
1416        }
1417        dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1418        rp->tx_skbuff[entry] = NULL;
1419        entry = (++rp->dirty_tx) % TX_RING_SIZE;
1420    }
1421    if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1422        netif_wake_queue(dev);
1423
1424    spin_unlock(&rp->lock);
1425}
1426
1427/* Process up to limit frames from receive ring */
1428static int rhine_rx(struct net_device *dev, int limit)
1429{
1430    struct rhine_private *rp = netdev_priv(dev);
1431    int count;
1432    int entry = rp->cur_rx % RX_RING_SIZE;
1433
1434    if (debug > 4) {
1435        printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1436               dev->name, entry,
1437               le32_to_cpu(rp->rx_head_desc->rx_status));
1438    }
1439
1440    /* If EOP is set on the next entry, it's a new packet. Send it up. */
1441    for (count = 0; count < limit; ++count) {
1442        struct rx_desc *desc = rp->rx_head_desc;
1443        u32 desc_status = le32_to_cpu(desc->rx_status);
1444        int data_size = desc_status >> 16;
1445
1446        if (desc_status & DescOwn)
1447            break;
1448
1449        if (debug > 4)
1450            printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
1451                   desc_status);
1452
1453        if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1454            if ((desc_status & RxWholePkt) != RxWholePkt) {
1455                printk(KERN_WARNING "%s: Oversized Ethernet "
1456                       "frame spanned multiple buffers, entry "
1457                       "%#x length %d status %8.8x!\n",
1458                       dev->name, entry, data_size,
1459                       desc_status);
1460                printk(KERN_WARNING "%s: Oversized Ethernet "
1461                       "frame %p vs %p.\n", dev->name,
1462                       rp->rx_head_desc, &rp->rx_ring[entry]);
1463                dev->stats.rx_length_errors++;
1464            } else if (desc_status & RxErr) {
1465                /* There was a error. */
1466                if (debug > 2)
1467                    printk(KERN_DEBUG "rhine_rx() Rx "
1468                           "error was %8.8x.\n",
1469                           desc_status);
1470                dev->stats.rx_errors++;
1471                if (desc_status & 0x0030)
1472                    dev->stats.rx_length_errors++;
1473                if (desc_status & 0x0048)
1474                    dev->stats.rx_fifo_errors++;
1475                if (desc_status & 0x0004)
1476                    dev->stats.rx_frame_errors++;
1477                if (desc_status & 0x0002) {
1478                    /* this can also be updated outside the interrupt handler */
1479                    spin_lock(&rp->lock);
1480                    dev->stats.rx_crc_errors++;
1481                    spin_unlock(&rp->lock);
1482                }
1483            }
1484        } else {
1485            struct sk_buff *skb;
1486            /* Length should omit the CRC */
1487            int pkt_len = data_size - 4;
1488
1489            /* Check if the packet is long enough to accept without
1490               copying to a minimally-sized skbuff. */
1491            if (pkt_len < rx_copybreak &&
1492                (skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN)) != NULL) {
1493                skb_reserve(skb, NET_IP_ALIGN); /* 16 byte align the IP header */
1494                pci_dma_sync_single_for_cpu(rp->pdev,
1495                                rp->rx_skbuff_dma[entry],
1496                                rp->rx_buf_sz,
1497                                PCI_DMA_FROMDEVICE);
1498
1499                skb_copy_to_linear_data(skb,
1500                         rp->rx_skbuff[entry]->data,
1501                         pkt_len);
1502                skb_put(skb, pkt_len);
1503                pci_dma_sync_single_for_device(rp->pdev,
1504                                   rp->rx_skbuff_dma[entry],
1505                                   rp->rx_buf_sz,
1506                                   PCI_DMA_FROMDEVICE);
1507            } else {
1508                skb = rp->rx_skbuff[entry];
1509                if (skb == NULL) {
1510                    printk(KERN_ERR "%s: Inconsistent Rx "
1511                           "descriptor chain.\n",
1512                           dev->name);
1513                    break;
1514                }
1515                rp->rx_skbuff[entry] = NULL;
1516                skb_put(skb, pkt_len);
1517                pci_unmap_single(rp->pdev,
1518                         rp->rx_skbuff_dma[entry],
1519                         rp->rx_buf_sz,
1520                         PCI_DMA_FROMDEVICE);
1521            }
1522            skb->protocol = eth_type_trans(skb, dev);
1523            netif_receive_skb(skb);
1524            dev->stats.rx_bytes += pkt_len;
1525            dev->stats.rx_packets++;
1526        }
1527        entry = (++rp->cur_rx) % RX_RING_SIZE;
1528        rp->rx_head_desc = &rp->rx_ring[entry];
1529    }
1530
1531    /* Refill the Rx ring buffers. */
1532    for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1533        struct sk_buff *skb;
1534        entry = rp->dirty_rx % RX_RING_SIZE;
1535        if (rp->rx_skbuff[entry] == NULL) {
1536            skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1537            rp->rx_skbuff[entry] = skb;
1538            if (skb == NULL)
1539                break; /* Better luck next round. */
1540            skb->dev = dev; /* Mark as being used by this device. */
1541            rp->rx_skbuff_dma[entry] =
1542                pci_map_single(rp->pdev, skb->data,
1543                           rp->rx_buf_sz,
1544                           PCI_DMA_FROMDEVICE);
1545            rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1546        }
1547        rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1548    }
1549
1550    return count;
1551}
1552
1553/*
1554 * Clears the "tally counters" for CRC errors and missed frames(?).
1555 * It has been reported that some chips need a write of 0 to clear
1556 * these, for others the counters are set to 1 when written to and
1557 * instead cleared when read. So we clear them both ways ...
1558 */
1559static inline void clear_tally_counters(void __iomem *ioaddr)
1560{
1561    iowrite32(0, ioaddr + RxMissed);
1562    ioread16(ioaddr + RxCRCErrs);
1563    ioread16(ioaddr + RxMissed);
1564}
1565
1566static void rhine_restart_tx(struct net_device *dev) {
1567    struct rhine_private *rp = netdev_priv(dev);
1568    void __iomem *ioaddr = rp->base;
1569    int entry = rp->dirty_tx % TX_RING_SIZE;
1570    u32 intr_status;
1571
1572    /*
1573     * If new errors occured, we need to sort them out before doing Tx.
1574     * In that case the ISR will be back here RSN anyway.
1575     */
1576    intr_status = get_intr_status(dev);
1577
1578    if ((intr_status & IntrTxErrSummary) == 0) {
1579
1580        /* We know better than the chip where it should continue. */
1581        iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1582               ioaddr + TxRingPtr);
1583
1584        iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1585               ioaddr + ChipCmd);
1586        iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1587               ioaddr + ChipCmd1);
1588        IOSYNC;
1589    }
1590    else {
1591        /* This should never happen */
1592        if (debug > 1)
1593            printk(KERN_WARNING "%s: rhine_restart_tx() "
1594                   "Another error occured %8.8x.\n",
1595                   dev->name, intr_status);
1596    }
1597
1598}
1599
1600static void rhine_error(struct net_device *dev, int intr_status)
1601{
1602    struct rhine_private *rp = netdev_priv(dev);
1603    void __iomem *ioaddr = rp->base;
1604
1605    spin_lock(&rp->lock);
1606
1607    if (intr_status & IntrLinkChange)
1608        rhine_check_media(dev, 0);
1609    if (intr_status & IntrStatsMax) {
1610        dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1611        dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1612        clear_tally_counters(ioaddr);
1613    }
1614    if (intr_status & IntrTxAborted) {
1615        if (debug > 1)
1616            printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1617                   dev->name, intr_status);
1618    }
1619    if (intr_status & IntrTxUnderrun) {
1620        if (rp->tx_thresh < 0xE0)
1621            iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1622        if (debug > 1)
1623            printk(KERN_INFO "%s: Transmitter underrun, Tx "
1624                   "threshold now %2.2x.\n",
1625                   dev->name, rp->tx_thresh);
1626    }
1627    if (intr_status & IntrTxDescRace) {
1628        if (debug > 2)
1629            printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1630                   dev->name);
1631    }
1632    if ((intr_status & IntrTxError) &&
1633        (intr_status & (IntrTxAborted |
1634         IntrTxUnderrun | IntrTxDescRace)) == 0) {
1635        if (rp->tx_thresh < 0xE0) {
1636            iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1637        }
1638        if (debug > 1)
1639            printk(KERN_INFO "%s: Unspecified error. Tx "
1640                   "threshold now %2.2x.\n",
1641                   dev->name, rp->tx_thresh);
1642    }
1643    if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1644               IntrTxError))
1645        rhine_restart_tx(dev);
1646
1647    if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1648                IntrTxError | IntrTxAborted | IntrNormalSummary |
1649                IntrTxDescRace)) {
1650        if (debug > 1)
1651            printk(KERN_ERR "%s: Something Wicked happened! "
1652                   "%8.8x.\n", dev->name, intr_status);
1653    }
1654
1655    spin_unlock(&rp->lock);
1656}
1657
1658static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1659{
1660    struct rhine_private *rp = netdev_priv(dev);
1661    void __iomem *ioaddr = rp->base;
1662    unsigned long flags;
1663
1664    spin_lock_irqsave(&rp->lock, flags);
1665    dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1666    dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1667    clear_tally_counters(ioaddr);
1668    spin_unlock_irqrestore(&rp->lock, flags);
1669
1670    return &dev->stats;
1671}
1672
1673static void rhine_set_rx_mode(struct net_device *dev)
1674{
1675    struct rhine_private *rp = netdev_priv(dev);
1676    void __iomem *ioaddr = rp->base;
1677    u32 mc_filter[2]; /* Multicast hash filter */
1678    u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1679
1680    if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1681        rx_mode = 0x1C;
1682        iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1683        iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1684    } else if ((dev->mc_count > multicast_filter_limit)
1685           || (dev->flags & IFF_ALLMULTI)) {
1686        /* Too many to match, or accept all multicasts. */
1687        iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1688        iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1689        rx_mode = 0x0C;
1690    } else {
1691        struct dev_mc_list *mclist;
1692        int i;
1693        memset(mc_filter, 0, sizeof(mc_filter));
1694        for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1695             i++, mclist = mclist->next) {
1696            int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1697
1698            mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1699        }
1700        iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1701        iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1702        rx_mode = 0x0C;
1703    }
1704    iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1705}
1706
1707static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1708{
1709    struct rhine_private *rp = netdev_priv(dev);
1710
1711    strcpy(info->driver, DRV_NAME);
1712    strcpy(info->version, DRV_VERSION);
1713    strcpy(info->bus_info, pci_name(rp->pdev));
1714}
1715
1716static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1717{
1718    struct rhine_private *rp = netdev_priv(dev);
1719    int rc;
1720
1721    spin_lock_irq(&rp->lock);
1722    rc = mii_ethtool_gset(&rp->mii_if, cmd);
1723    spin_unlock_irq(&rp->lock);
1724
1725    return rc;
1726}
1727
1728static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1729{
1730    struct rhine_private *rp = netdev_priv(dev);
1731    int rc;
1732
1733    spin_lock_irq(&rp->lock);
1734    rc = mii_ethtool_sset(&rp->mii_if, cmd);
1735    spin_unlock_irq(&rp->lock);
1736    rhine_set_carrier(&rp->mii_if);
1737
1738    return rc;
1739}
1740
1741static int netdev_nway_reset(struct net_device *dev)
1742{
1743    struct rhine_private *rp = netdev_priv(dev);
1744
1745    return mii_nway_restart(&rp->mii_if);
1746}
1747
1748static u32 netdev_get_link(struct net_device *dev)
1749{
1750    struct rhine_private *rp = netdev_priv(dev);
1751
1752    return mii_link_ok(&rp->mii_if);
1753}
1754
1755static u32 netdev_get_msglevel(struct net_device *dev)
1756{
1757    return debug;
1758}
1759
1760static void netdev_set_msglevel(struct net_device *dev, u32 value)
1761{
1762    debug = value;
1763}
1764
1765static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1766{
1767    struct rhine_private *rp = netdev_priv(dev);
1768
1769    if (!(rp->quirks & rqWOL))
1770        return;
1771
1772    spin_lock_irq(&rp->lock);
1773    wol->supported = WAKE_PHY | WAKE_MAGIC |
1774             WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1775    wol->wolopts = rp->wolopts;
1776    spin_unlock_irq(&rp->lock);
1777}
1778
1779static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1780{
1781    struct rhine_private *rp = netdev_priv(dev);
1782    u32 support = WAKE_PHY | WAKE_MAGIC |
1783              WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1784
1785    if (!(rp->quirks & rqWOL))
1786        return -EINVAL;
1787
1788    if (wol->wolopts & ~support)
1789        return -EINVAL;
1790
1791    spin_lock_irq(&rp->lock);
1792    rp->wolopts = wol->wolopts;
1793    spin_unlock_irq(&rp->lock);
1794
1795    return 0;
1796}
1797
1798static const struct ethtool_ops netdev_ethtool_ops = {
1799    .get_drvinfo = netdev_get_drvinfo,
1800    .get_settings = netdev_get_settings,
1801    .set_settings = netdev_set_settings,
1802    .nway_reset = netdev_nway_reset,
1803    .get_link = netdev_get_link,
1804    .get_msglevel = netdev_get_msglevel,
1805    .set_msglevel = netdev_set_msglevel,
1806    .get_wol = rhine_get_wol,
1807    .set_wol = rhine_set_wol,
1808};
1809
1810static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1811{
1812    struct rhine_private *rp = netdev_priv(dev);
1813    int rc;
1814
1815    if (!netif_running(dev))
1816        return -EINVAL;
1817
1818    spin_lock_irq(&rp->lock);
1819    rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1820    spin_unlock_irq(&rp->lock);
1821    rhine_set_carrier(&rp->mii_if);
1822
1823    return rc;
1824}
1825
1826static int rhine_close(struct net_device *dev)
1827{
1828    struct rhine_private *rp = netdev_priv(dev);
1829    void __iomem *ioaddr = rp->base;
1830
1831    spin_lock_irq(&rp->lock);
1832
1833    netif_stop_queue(dev);
1834    napi_disable(&rp->napi);
1835
1836    if (debug > 1)
1837        printk(KERN_DEBUG "%s: Shutting down ethercard, "
1838               "status was %4.4x.\n",
1839               dev->name, ioread16(ioaddr + ChipCmd));
1840
1841    /* Switch to loopback mode to avoid hardware races. */
1842    iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1843
1844    /* Disable interrupts by clearing the interrupt mask. */
1845    iowrite16(0x0000, ioaddr + IntrEnable);
1846
1847    /* Stop the chip's Tx and Rx processes. */
1848    iowrite16(CmdStop, ioaddr + ChipCmd);
1849
1850    spin_unlock_irq(&rp->lock);
1851
1852    free_irq(rp->pdev->irq, dev);
1853    free_rbufs(dev);
1854    free_tbufs(dev);
1855    free_ring(dev);
1856
1857    return 0;
1858}
1859
1860
1861static void __devexit rhine_remove_one(struct pci_dev *pdev)
1862{
1863    struct net_device *dev = pci_get_drvdata(pdev);
1864    struct rhine_private *rp = netdev_priv(dev);
1865
1866    unregister_netdev(dev);
1867
1868    pci_iounmap(pdev, rp->base);
1869    pci_release_regions(pdev);
1870
1871    free_netdev(dev);
1872    pci_disable_device(pdev);
1873    pci_set_drvdata(pdev, NULL);
1874}
1875
1876static void rhine_shutdown (struct pci_dev *pdev)
1877{
1878    struct net_device *dev = pci_get_drvdata(pdev);
1879    struct rhine_private *rp = netdev_priv(dev);
1880    void __iomem *ioaddr = rp->base;
1881
1882    if (!(rp->quirks & rqWOL))
1883        return; /* Nothing to do for non-WOL adapters */
1884
1885    rhine_power_init(dev);
1886
1887    /* Make sure we use pattern 0, 1 and not 4, 5 */
1888    if (rp->quirks & rq6patterns)
1889        iowrite8(0x04, ioaddr + WOLcgClr);
1890
1891    if (rp->wolopts & WAKE_MAGIC) {
1892        iowrite8(WOLmagic, ioaddr + WOLcrSet);
1893        /*
1894         * Turn EEPROM-controlled wake-up back on -- some hardware may
1895         * not cooperate otherwise.
1896         */
1897        iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1898    }
1899
1900    if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1901        iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1902
1903    if (rp->wolopts & WAKE_PHY)
1904        iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1905
1906    if (rp->wolopts & WAKE_UCAST)
1907        iowrite8(WOLucast, ioaddr + WOLcrSet);
1908
1909    if (rp->wolopts) {
1910        /* Enable legacy WOL (for old motherboards) */
1911        iowrite8(0x01, ioaddr + PwcfgSet);
1912        iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1913    }
1914
1915    /* Hit power state D3 (sleep) */
1916    if (!avoid_D3)
1917        iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
1918
1919    /* TODO: Check use of pci_enable_wake() */
1920
1921}
1922
1923#ifdef CONFIG_PM
1924static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1925{
1926    struct net_device *dev = pci_get_drvdata(pdev);
1927    struct rhine_private *rp = netdev_priv(dev);
1928    unsigned long flags;
1929
1930    if (!netif_running(dev))
1931        return 0;
1932
1933    napi_disable(&rp->napi);
1934
1935    netif_device_detach(dev);
1936    pci_save_state(pdev);
1937
1938    spin_lock_irqsave(&rp->lock, flags);
1939    rhine_shutdown(pdev);
1940    spin_unlock_irqrestore(&rp->lock, flags);
1941
1942    free_irq(dev->irq, dev);
1943    return 0;
1944}
1945
1946static int rhine_resume(struct pci_dev *pdev)
1947{
1948    struct net_device *dev = pci_get_drvdata(pdev);
1949    struct rhine_private *rp = netdev_priv(dev);
1950    unsigned long flags;
1951    int ret;
1952
1953    if (!netif_running(dev))
1954        return 0;
1955
1956        if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
1957        printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
1958
1959    ret = pci_set_power_state(pdev, PCI_D0);
1960    if (debug > 1)
1961        printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
1962            dev->name, ret ? "failed" : "succeeded", ret);
1963
1964    pci_restore_state(pdev);
1965
1966    spin_lock_irqsave(&rp->lock, flags);
1967#ifdef USE_MMIO
1968    enable_mmio(rp->pioaddr, rp->quirks);
1969#endif
1970    rhine_power_init(dev);
1971    free_tbufs(dev);
1972    free_rbufs(dev);
1973    alloc_tbufs(dev);
1974    alloc_rbufs(dev);
1975    init_registers(dev);
1976    spin_unlock_irqrestore(&rp->lock, flags);
1977
1978    netif_device_attach(dev);
1979
1980    return 0;
1981}
1982#endif /* CONFIG_PM */
1983
1984static struct pci_driver rhine_driver = {
1985    .name = DRV_NAME,
1986    .id_table = rhine_pci_tbl,
1987    .probe = rhine_init_one,
1988    .remove = __devexit_p(rhine_remove_one),
1989#ifdef CONFIG_PM
1990    .suspend = rhine_suspend,
1991    .resume = rhine_resume,
1992#endif /* CONFIG_PM */
1993    .shutdown = rhine_shutdown,
1994};
1995
1996static struct dmi_system_id __initdata rhine_dmi_table[] = {
1997    {
1998        .ident = "EPIA-M",
1999        .matches = {
2000            DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
2001            DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2002        },
2003    },
2004    {
2005        .ident = "KV7",
2006        .matches = {
2007            DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2008            DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2009        },
2010    },
2011    { NULL }
2012};
2013
2014static int __init rhine_init(void)
2015{
2016/* when a module, this is printed whether or not devices are found in probe */
2017#ifdef MODULE
2018    printk(version);
2019#endif
2020    if (dmi_check_system(rhine_dmi_table)) {
2021        /* these BIOSes fail at PXE boot if chip is in D3 */
2022        avoid_D3 = 1;
2023        printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 "
2024                    "enabled.\n",
2025               DRV_NAME);
2026    }
2027    else if (avoid_D3)
2028        printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME);
2029
2030    return pci_register_driver(&rhine_driver);
2031}
2032
2033
2034static void __exit rhine_cleanup(void)
2035{
2036    pci_unregister_driver(&rhine_driver);
2037}
2038
2039
2040module_init(rhine_init);
2041module_exit(rhine_cleanup);
2042

Archive Download this file

Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.2
jz-3.3
jz-3.4
jz47xx
jz47xx-2.6.38
master
xiangfu/openwrt/v3.0.0
xiangfu/openwrt/v3.2.1

Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7



interactive