Kernel

Kernel Git Source Tree

Root/drivers/net/yellowfin.c

1	/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2	/*
3	Written 1997-2001 by Donald Becker.
4
5	This software may be used and distributed according to the terms of
6	the GNU General Public License (GPL), incorporated herein by reference.
7	Drivers based on or derived from this code fall under the GPL and must
8	retain the authorship, copyright and license notice. This file is not
9	a complete program and may only be used when the entire operating
10	system is licensed under the GPL.
11
12	This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13	It also supports the Symbios Logic version of the same chip core.
14
15	The author may be reached as becker@scyld.com, or C/O
16	Scyld Computing Corporation
17	410 Severn Ave., Suite 210
18	Annapolis MD 21403
19
20	Support and updates available at
21	http://www.scyld.com/network/yellowfin.html
22	[link no longer provides useful info -jgarzik]
23
24	*/
25
26	#define DRV_NAME "yellowfin"
27	#define DRV_VERSION "2.1"
28	#define DRV_RELDATE "Sep 11, 2006"
29
30	#define PFX DRV_NAME ": "
31
32	/* The user-configurable values.
33	These may be modified when a driver module is loaded.*/
34
35	static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36	/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37	static int max_interrupt_work = 20;
38	static int mtu;
39	#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40	/* System-wide count of bogus-rx frames. */
41	static int bogus_rx;
42	static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43	static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44	#elif defined(YF_NEW) /* A future perfect board :->. */
45	static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46	static int fifo_cfg = 0x0028;
47	#else
48	static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49	static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
50	#endif
51
52	/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53	Setting to > 1514 effectively disables this feature. */
54	static int rx_copybreak;
55
56	/* Used to pass the media type, etc.
57	No media types are currently defined. These exist for driver
58	interoperability.
59	*/
60	#define MAX_UNITS 8 /* More are supported, limit only on options */
61	static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62	static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
63
64	/* Do ugly workaround for GX server chipset errata. */
65	static int gx_fix;
66
67	/* Operational parameters that are set at compile time. */
68
69	/* Keep the ring sizes a power of two for efficiency.
70	Making the Tx ring too long decreases the effectiveness of channel
71	bonding and packet priority.
72	There are no ill effects from too-large receive rings. */
73	#define TX_RING_SIZE 16
74	#define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75	#define RX_RING_SIZE 64
76	#define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77	#define TX_TOTAL_SIZE 2TX_RING_SIZEsizeof(struct yellowfin_desc)
78	#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
79
80	/* Operational parameters that usually are not changed. */
81	/* Time in jiffies before concluding the transmitter is hung. */
82	#define TX_TIMEOUT (2*HZ)
83	#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85	#define yellowfin_debug debug
86
87	#include <linux/module.h>
88	#include <linux/kernel.h>
89	#include <linux/string.h>
90	#include <linux/timer.h>
91	#include <linux/errno.h>
92	#include <linux/ioport.h>
93	#include <linux/slab.h>
94	#include <linux/interrupt.h>
95	#include <linux/pci.h>
96	#include <linux/init.h>
97	#include <linux/mii.h>
98	#include <linux/netdevice.h>
99	#include <linux/etherdevice.h>
100	#include <linux/skbuff.h>
101	#include <linux/ethtool.h>
102	#include <linux/crc32.h>
103	#include <linux/bitops.h>
104	#include <asm/uaccess.h>
105	#include <asm/processor.h> /* Processor type for cache alignment. */
106	#include <asm/unaligned.h>
107	#include <asm/io.h>
108
109	/* These identify the driver base version and may not be removed. */
110	static const char version[] __devinitconst =
111	KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
112	" (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
113
114	MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
115	MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
116	MODULE_LICENSE("GPL");
117
118	module_param(max_interrupt_work, int, 0);
119	module_param(mtu, int, 0);
120	module_param(debug, int, 0);
121	module_param(rx_copybreak, int, 0);
122	module_param_array(options, int, NULL, 0);
123	module_param_array(full_duplex, int, NULL, 0);
124	module_param(gx_fix, int, 0);
125	MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
126	MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
127	MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
128	MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
129	MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
130	MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
131	MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
132
133	/*
134	Theory of Operation
135
136	I. Board Compatibility
137
138	This device driver is designed for the Packet Engines "Yellowfin" Gigabit
139	Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
140	Symbios 53C885E dual function chip.
141
142	II. Board-specific settings
143
144	PCI bus devices are configured by the system at boot time, so no jumpers
145	need to be set on the board. The system BIOS preferably should assign the
146	PCI INTA signal to an otherwise unused system IRQ line.
147	Note: Kernel versions earlier than 1.3.73 do not support shared PCI
148	interrupt lines.
149
150	III. Driver operation
151
152	IIIa. Ring buffers
153
154	The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
155	This is a descriptor list scheme similar to that used by the EEPro100 and
156	Tulip. This driver uses two statically allocated fixed-size descriptor lists
157	formed into rings by a branch from the final descriptor to the beginning of
158	the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
159
160	The driver allocates full frame size skbuffs for the Rx ring buffers at
161	open() time and passes the skb->data field to the Yellowfin as receive data
162	buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
163	a fresh skbuff is allocated and the frame is copied to the new skbuff.
164	When the incoming frame is larger, the skbuff is passed directly up the
165	protocol stack and replaced by a newly allocated skbuff.
166
167	The RX_COPYBREAK value is chosen to trade-off the memory wasted by
168	using a full-sized skbuff for small frames vs. the copying costs of larger
169	frames. For small frames the copying cost is negligible (esp. considering
170	that we are pre-loading the cache with immediately useful header
171	information). For large frames the copying cost is non-trivial, and the
172	larger copy might flush the cache of useful data.
173
174	IIIC. Synchronization
175
176	The driver runs as two independent, single-threaded flows of control. One
177	is the send-packet routine, which enforces single-threaded use by the
178	dev->tbusy flag. The other thread is the interrupt handler, which is single
179	threaded by the hardware and other software.
180
181	The send packet thread has partial control over the Tx ring and 'dev->tbusy'
182	flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
183	queue slot is empty, it clears the tbusy flag when finished otherwise it sets
184	the 'yp->tx_full' flag.
185
186	The interrupt handler has exclusive control over the Rx ring and records stats
187	from the Tx ring. After reaping the stats, it marks the Tx queue entry as
188	empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
189	clears both the tx_full and tbusy flags.
190
191	IV. Notes
192
193	Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
194	Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
195	and an AlphaStation to verifty the Alpha port!
196
197	IVb. References
198
199	Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
200	Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
201	Data Manual v3.0
202	http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
203	http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
204
205	IVc. Errata
206
207	See Packet Engines confidential appendix (prototype chips only).
208	*/
209
210
211
212	enum capability_flags {
213	HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
214	HasMACAddrBug=32, /* Only on early revs. */
215	DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
216	};
217
218	/* The PCI I/O space extent. */
219	enum {
220	YELLOWFIN_SIZE = 0x100,
221	};
222
223	struct pci_id_info {
224	const char *name;
225	struct match_info {
226	int pci, pci_mask, subsystem, subsystem_mask;
227	int revision, revision_mask; /* Only 8 bits. */
228	} id;
229	int drv_flags; /* Driver use, intended as capability flags. */
230	};
231
232	static const struct pci_id_info pci_id_tbl[] = {
233	{"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
234	FullTxStatus \| IsGigabit \| HasMulticastBug \| HasMACAddrBug \| DontUseEeprom},
235	{"Symbios SYM83C885", { 0x07011000, 0xffffffff},
236	HasMII \| DontUseEeprom },
237	{ }
238	};
239
240	static const struct pci_device_id yellowfin_pci_tbl[] = {
241	{ 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
242	{ 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
243	{ }
244	};
245	MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
246
247
248	/* Offsets to the Yellowfin registers. Various sizes and alignments. */
249	enum yellowfin_offsets {
250	TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
251	TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
252	RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
253	RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
254	EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
255	ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
256	Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
257	MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
258	MII_Status=0xAE,
259	RxDepth=0xB8, FlowCtrl=0xBC,
260	AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
261	EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
262	EEFeature=0xF5,
263	};
264
265	/* The Yellowfin Rx and Tx buffer descriptors.
266	Elements are written as 32 bit for endian portability. */
267	struct yellowfin_desc {
268	__le32 dbdma_cmd;
269	__le32 addr;
270	__le32 branch_addr;
271	__le32 result_status;
272	};
273
274	struct tx_status_words {
275	#ifdef __BIG_ENDIAN
276	u16 tx_errs;
277	u16 tx_cnt;
278	u16 paused;
279	u16 total_tx_cnt;
280	#else /* Little endian chips. */
281	u16 tx_cnt;
282	u16 tx_errs;
283	u16 total_tx_cnt;
284	u16 paused;
285	#endif /* __BIG_ENDIAN */
286	};
287
288	/* Bits in yellowfin_desc.cmd */
289	enum desc_cmd_bits {
290	CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
291	CMD_NOP=0x60000000, CMD_STOP=0x70000000,
292	BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
293	BRANCH_IFTRUE=0x040000,
294	};
295
296	/* Bits in yellowfin_desc.status */
297	enum desc_status_bits { RX_EOP=0x0040, };
298
299	/* Bits in the interrupt status/mask registers. */
300	enum intr_status_bits {
301	IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
302	IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
303	IntrEarlyRx=0x100, IntrWakeup=0x200, };
304
305	#define PRIV_ALIGN 31 /* Required alignment mask */
306	#define MII_CNT 4
307	struct yellowfin_private {
308	/* Descriptor rings first for alignment.
309	Tx requires a second descriptor for status. */
310	struct yellowfin_desc *rx_ring;
311	struct yellowfin_desc *tx_ring;
312	struct sk_buff* rx_skbuff[RX_RING_SIZE];
313	struct sk_buff* tx_skbuff[TX_RING_SIZE];
314	dma_addr_t rx_ring_dma;
315	dma_addr_t tx_ring_dma;
316
317	struct tx_status_words *tx_status;
318	dma_addr_t tx_status_dma;
319
320	struct timer_list timer; /* Media selection timer. */
321	/* Frequently used and paired value: keep adjacent for cache effect. */
322	int chip_id, drv_flags;
323	struct pci_dev *pci_dev;
324	unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
325	unsigned int rx_buf_sz; /* Based on MTU+slack. */
326	struct tx_status_words *tx_tail_desc;
327	unsigned int cur_tx, dirty_tx;
328	int tx_threshold;
329	unsigned int tx_full:1; /* The Tx queue is full. */
330	unsigned int full_duplex:1; /* Full-duplex operation requested. */
331	unsigned int duplex_lock:1;
332	unsigned int medialock:1; /* Do not sense media. */
333	unsigned int default_port:4; /* Last dev->if_port value. */
334	/* MII transceiver section. */
335	int mii_cnt; /* MII device addresses. */
336	u16 advertising; /* NWay media advertisement */
337	unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
338	spinlock_t lock;
339	void __iomem *base;
340	};
341
342	static int read_eeprom(void __iomem *ioaddr, int location);
343	static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
344	static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
345	static int netdev_ioctl(struct net_device dev, struct ifreq rq, int cmd);
346	static int yellowfin_open(struct net_device *dev);
347	static void yellowfin_timer(unsigned long data);
348	static void yellowfin_tx_timeout(struct net_device *dev);
349	static int yellowfin_init_ring(struct net_device *dev);
350	static int yellowfin_start_xmit(struct sk_buff skb, struct net_device dev);
351	static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
352	static int yellowfin_rx(struct net_device *dev);
353	static void yellowfin_error(struct net_device *dev, int intr_status);
354	static int yellowfin_close(struct net_device *dev);
355	static void set_rx_mode(struct net_device *dev);
356	static const struct ethtool_ops ethtool_ops;
357
358	static const struct net_device_ops netdev_ops = {
359	.ndo_open = yellowfin_open,
360	.ndo_stop = yellowfin_close,
361	.ndo_start_xmit = yellowfin_start_xmit,
362	.ndo_set_multicast_list = set_rx_mode,
363	.ndo_change_mtu = eth_change_mtu,
364	.ndo_validate_addr = eth_validate_addr,
365	.ndo_set_mac_address = eth_mac_addr,
366	.ndo_do_ioctl = netdev_ioctl,
367	.ndo_tx_timeout = yellowfin_tx_timeout,
368	};
369
370	static int __devinit yellowfin_init_one(struct pci_dev *pdev,
371	const struct pci_device_id *ent)
372	{
373	struct net_device *dev;
374	struct yellowfin_private *np;
375	int irq;
376	int chip_idx = ent->driver_data;
377	static int find_cnt;
378	void __iomem *ioaddr;
379	int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
380	int drv_flags = pci_id_tbl[chip_idx].drv_flags;
381	void *ring_space;
382	dma_addr_t ring_dma;
383	#ifdef USE_IO_OPS
384	int bar = 0;
385	#else
386	int bar = 1;
387	#endif
388
389	/* when built into the kernel, we only print version if device is found */
390	#ifndef MODULE
391	static int printed_version;
392	if (!printed_version++)
393	printk(version);
394	#endif
395
396	i = pci_enable_device(pdev);
397	if (i) return i;
398
399	dev = alloc_etherdev(sizeof(*np));
400	if (!dev) {
401	printk (KERN_ERR PFX "cannot allocate ethernet device\n");
402	return -ENOMEM;
403	}
404	SET_NETDEV_DEV(dev, &pdev->dev);
405
406	np = netdev_priv(dev);
407
408	if (pci_request_regions(pdev, DRV_NAME))
409	goto err_out_free_netdev;
410
411	pci_set_master (pdev);
412
413	ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
414	if (!ioaddr)
415	goto err_out_free_res;
416
417	irq = pdev->irq;
418
419	if (drv_flags & DontUseEeprom)
420	for (i = 0; i < 6; i++)
421	dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
422	else {
423	int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
424	for (i = 0; i < 6; i++)
425	dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
426	}
427
428	/* Reset the chip. */
429	iowrite32(0x80000000, ioaddr + DMACtrl);
430
431	dev->base_addr = (unsigned long)ioaddr;
432	dev->irq = irq;
433
434	pci_set_drvdata(pdev, dev);
435	spin_lock_init(&np->lock);
436
437	np->pci_dev = pdev;
438	np->chip_id = chip_idx;
439	np->drv_flags = drv_flags;
440	np->base = ioaddr;
441
442	ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
443	if (!ring_space)
444	goto err_out_cleardev;
445	np->tx_ring = (struct yellowfin_desc *)ring_space;
446	np->tx_ring_dma = ring_dma;
447
448	ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
449	if (!ring_space)
450	goto err_out_unmap_tx;
451	np->rx_ring = (struct yellowfin_desc *)ring_space;
452	np->rx_ring_dma = ring_dma;
453
454	ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
455	if (!ring_space)
456	goto err_out_unmap_rx;
457	np->tx_status = (struct tx_status_words *)ring_space;
458	np->tx_status_dma = ring_dma;
459
460	if (dev->mem_start)
461	option = dev->mem_start;
462
463	/* The lower four bits are the media type. */
464	if (option > 0) {
465	if (option & 0x200)
466	np->full_duplex = 1;
467	np->default_port = option & 15;
468	if (np->default_port)
469	np->medialock = 1;
470	}
471	if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
472	np->full_duplex = 1;
473
474	if (np->full_duplex)
475	np->duplex_lock = 1;
476
477	/* The Yellowfin-specific entries in the device structure. */
478	dev->netdev_ops = &netdev_ops;
479	SET_ETHTOOL_OPS(dev, &ethtool_ops);
480	dev->watchdog_timeo = TX_TIMEOUT;
481
482	if (mtu)
483	dev->mtu = mtu;
484
485	i = register_netdev(dev);
486	if (i)
487	goto err_out_unmap_status;
488
489	printk(KERN_INFO "%s: %s type %8x at %p, %pM, IRQ %d.\n",
490	dev->name, pci_id_tbl[chip_idx].name,
491	ioread32(ioaddr + ChipRev), ioaddr,
492	dev->dev_addr, irq);
493
494	if (np->drv_flags & HasMII) {
495	int phy, phy_idx = 0;
496	for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
497	int mii_status = mdio_read(ioaddr, phy, 1);
498	if (mii_status != 0xffff && mii_status != 0x0000) {
499	np->phys[phy_idx++] = phy;
500	np->advertising = mdio_read(ioaddr, phy, 4);
501	printk(KERN_INFO "%s: MII PHY found at address %d, status "
502	"0x%4.4x advertising %4.4x.\n",
503	dev->name, phy, mii_status, np->advertising);
504	}
505	}
506	np->mii_cnt = phy_idx;
507	}
508
509	find_cnt++;
510
511	return 0;
512
513	err_out_unmap_status:
514	pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
515	np->tx_status_dma);
516	err_out_unmap_rx:
517	pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
518	err_out_unmap_tx:
519	pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
520	err_out_cleardev:
521	pci_set_drvdata(pdev, NULL);
522	pci_iounmap(pdev, ioaddr);
523	err_out_free_res:
524	pci_release_regions(pdev);
525	err_out_free_netdev:
526	free_netdev (dev);
527	return -ENODEV;
528	}
529
530	static int __devinit read_eeprom(void __iomem *ioaddr, int location)
531	{
532	int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
533
534	iowrite8(location, ioaddr + EEAddr);
535	iowrite8(0x30 \| ((location >> 8) & 7), ioaddr + EECtrl);
536	while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
537	;
538	return ioread8(ioaddr + EERead);
539	}
540
541	/* MII Managemen Data I/O accesses.
542	These routines assume the MDIO controller is idle, and do not exit until
543	the command is finished. */
544
545	static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
546	{
547	int i;
548
549	iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
550	iowrite16(1, ioaddr + MII_Cmd);
551	for (i = 10000; i >= 0; i--)
552	if ((ioread16(ioaddr + MII_Status) & 1) == 0)
553	break;
554	return ioread16(ioaddr + MII_Rd_Data);
555	}
556
557	static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
558	{
559	int i;
560
561	iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
562	iowrite16(value, ioaddr + MII_Wr_Data);
563
564	/* Wait for the command to finish. */
565	for (i = 10000; i >= 0; i--)
566	if ((ioread16(ioaddr + MII_Status) & 1) == 0)
567	break;
568	return;
569	}
570
571
572	static int yellowfin_open(struct net_device *dev)
573	{
574	struct yellowfin_private *yp = netdev_priv(dev);
575	void __iomem *ioaddr = yp->base;
576	int i, ret;
577
578	/* Reset the chip. */
579	iowrite32(0x80000000, ioaddr + DMACtrl);
580
581	ret = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
582	if (ret)
583	return ret;
584
585	if (yellowfin_debug > 1)
586	printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
587	dev->name, dev->irq);
588
589	ret = yellowfin_init_ring(dev);
590	if (ret) {
591	free_irq(dev->irq, dev);
592	return ret;
593	}
594
595	iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
596	iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
597
598	for (i = 0; i < 6; i++)
599	iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
600
601	/* Set up various condition 'select' registers.
602	There are no options here. */
603	iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
604	iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
605	iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
606	iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
607	iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
608	iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
609
610	/* Initialize other registers: with so many this eventually this will
611	converted to an offset/value list. */
612	iowrite32(dma_ctrl, ioaddr + DMACtrl);
613	iowrite16(fifo_cfg, ioaddr + FIFOcfg);
614	/* Enable automatic generation of flow control frames, period 0xffff. */
615	iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
616
617	yp->tx_threshold = 32;
618	iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
619
620	if (dev->if_port == 0)
621	dev->if_port = yp->default_port;
622
623	netif_start_queue(dev);
624
625	/* Setting the Rx mode will start the Rx process. */
626	if (yp->drv_flags & IsGigabit) {
627	/* We are always in full-duplex mode with gigabit! */
628	yp->full_duplex = 1;
629	iowrite16(0x01CF, ioaddr + Cnfg);
630	} else {
631	iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
632	iowrite16(0x1018, ioaddr + FrameGap1);
633	iowrite16(0x101C \| (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
634	}
635	set_rx_mode(dev);
636
637	/* Enable interrupts by setting the interrupt mask. */
638	iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
639	iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
640	iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
641	iowrite32(0x80008000, ioaddr + TxCtrl);
642
643	if (yellowfin_debug > 2) {
644	printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
645	dev->name);
646	}
647
648	/* Set the timer to check for link beat. */
649	init_timer(&yp->timer);
650	yp->timer.expires = jiffies + 3*HZ;
651	yp->timer.data = (unsigned long)dev;
652	yp->timer.function = &yellowfin_timer; /* timer handler */
653	add_timer(&yp->timer);
654
655	return 0;
656	}
657
658	static void yellowfin_timer(unsigned long data)
659	{
660	struct net_device dev = (struct net_device )data;
661	struct yellowfin_private *yp = netdev_priv(dev);
662	void __iomem *ioaddr = yp->base;
663	int next_tick = 60*HZ;
664
665	if (yellowfin_debug > 3) {
666	printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
667	dev->name, ioread16(ioaddr + IntrStatus));
668	}
669
670	if (yp->mii_cnt) {
671	int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
672	int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
673	int negotiated = lpa & yp->advertising;
674	if (yellowfin_debug > 1)
675	printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
676	"link partner capability %4.4x.\n",
677	dev->name, yp->phys[0], bmsr, lpa);
678
679	yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
680
681	iowrite16(0x101C \| (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
682
683	if (bmsr & BMSR_LSTATUS)
684	next_tick = 60*HZ;
685	else
686	next_tick = 3*HZ;
687	}
688
689	yp->timer.expires = jiffies + next_tick;
690	add_timer(&yp->timer);
691	}
692
693	static void yellowfin_tx_timeout(struct net_device *dev)
694	{
695	struct yellowfin_private *yp = netdev_priv(dev);
696	void __iomem *ioaddr = yp->base;
697
698	printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
699	"status %4.4x, Rx status %4.4x, resetting...\n",
700	dev->name, yp->cur_tx, yp->dirty_tx,
701	ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
702
703	/* Note: these should be KERN_DEBUG. */
704	if (yellowfin_debug) {
705	int i;
706	printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring);
707	for (i = 0; i < RX_RING_SIZE; i++)
708	printk(KERN_CONT " %8.8x",
709	yp->rx_ring[i].result_status);
710	printk(KERN_CONT "\n");
711	printk(KERN_WARNING" Tx ring %p: ", yp->tx_ring);
712	for (i = 0; i < TX_RING_SIZE; i++)
713	printk(KERN_CONT " %4.4x /%8.8x",
714	yp->tx_status[i].tx_errs,
715	yp->tx_ring[i].result_status);
716	printk(KERN_CONT "\n");
717	}
718
719	/* If the hardware is found to hang regularly, we will update the code
720	to reinitialize the chip here. */
721	dev->if_port = 0;
722
723	/* Wake the potentially-idle transmit channel. */
724	iowrite32(0x10001000, yp->base + TxCtrl);
725	if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
726	netif_wake_queue (dev); /* Typical path */
727
728	dev->trans_start = jiffies; /* prevent tx timeout */
729	dev->stats.tx_errors++;
730	}
731
732	/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
733	static int yellowfin_init_ring(struct net_device *dev)
734	{
735	struct yellowfin_private *yp = netdev_priv(dev);
736	int i, j;
737
738	yp->tx_full = 0;
739	yp->cur_rx = yp->cur_tx = 0;
740	yp->dirty_tx = 0;
741
742	yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
743
744	for (i = 0; i < RX_RING_SIZE; i++) {
745	yp->rx_ring[i].dbdma_cmd =
746	cpu_to_le32(CMD_RX_BUF \| INTR_ALWAYS \| yp->rx_buf_sz);
747	yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
748	((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
749	}
750
751	for (i = 0; i < RX_RING_SIZE; i++) {
752	struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
753	yp->rx_skbuff[i] = skb;
754	if (skb == NULL)
755	break;
756	skb->dev = dev; /* Mark as being used by this device. */
757	skb_reserve(skb, 2); /* 16 byte align the IP header. */
758	yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
759	skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
760	}
761	if (i != RX_RING_SIZE) {
762	for (j = 0; j < i; j++)
763	dev_kfree_skb(yp->rx_skbuff[j]);
764	return -ENOMEM;
765	}
766	yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
767	yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
768
769	#define NO_TXSTATS
770	#ifdef NO_TXSTATS
771	/* In this mode the Tx ring needs only a single descriptor. */
772	for (i = 0; i < TX_RING_SIZE; i++) {
773	yp->tx_skbuff[i] = NULL;
774	yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
775	yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
776	((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
777	}
778	/* Wrap ring */
779	yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP \| BRANCH_ALWAYS);
780	#else
781	{
782	/* Tx ring needs a pair of descriptors, the second for the status. */
783	for (i = 0; i < TX_RING_SIZE; i++) {
784	j = 2*i;
785	yp->tx_skbuff[i] = 0;
786	/* Branch on Tx error. */
787	yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
788	yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
789	(j+1)*sizeof(struct yellowfin_desc));
790	j++;
791	if (yp->flags & FullTxStatus) {
792	yp->tx_ring[j].dbdma_cmd =
793	cpu_to_le32(CMD_TXSTATUS \| sizeof(*yp->tx_status));
794	yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
795	yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
796	i*sizeof(struct tx_status_words));
797	} else {
798	/* Symbios chips write only tx_errs word. */
799	yp->tx_ring[j].dbdma_cmd =
800	cpu_to_le32(CMD_TXSTATUS \| INTR_ALWAYS \| 2);
801	yp->tx_ring[j].request_cnt = 2;
802	/* Om pade ummmmm... */
803	yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
804	i*sizeof(struct tx_status_words) +
805	&(yp->tx_status[0].tx_errs) -
806	&(yp->tx_status[0]));
807	}
808	yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
809	((j+1)%(2TX_RING_SIZE))sizeof(struct yellowfin_desc));
810	}
811	/* Wrap ring */
812	yp->tx_ring[++j].dbdma_cmd \|= cpu_to_le32(BRANCH_ALWAYS \| INTR_ALWAYS);
813	}
814	#endif
815	yp->tx_tail_desc = &yp->tx_status[0];
816	return 0;
817	}
818
819	static int yellowfin_start_xmit(struct sk_buff skb, struct net_device dev)
820	{
821	struct yellowfin_private *yp = netdev_priv(dev);
822	unsigned entry;
823	int len = skb->len;
824
825	netif_stop_queue (dev);
826
827	/* Note: Ordering is important here, set the field with the
828	"ownership" bit last, and only then increment cur_tx. */
829
830	/* Calculate the next Tx descriptor entry. */
831	entry = yp->cur_tx % TX_RING_SIZE;
832
833	if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
834	int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
835	/* Fix GX chipset errata. */
836	if (cacheline_end > 24 \|\| cacheline_end == 0) {
837	len = skb->len + 32 - cacheline_end + 1;
838	if (skb_padto(skb, len)) {
839	yp->tx_skbuff[entry] = NULL;
840	netif_wake_queue(dev);
841	return 0;
842	}
843	}
844	}
845	yp->tx_skbuff[entry] = skb;
846
847	#ifdef NO_TXSTATS
848	yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
849	skb->data, len, PCI_DMA_TODEVICE));
850	yp->tx_ring[entry].result_status = 0;
851	if (entry >= TX_RING_SIZE-1) {
852	/* New stop command. */
853	yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
854	yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
855	cpu_to_le32(CMD_TX_PKT\|BRANCH_ALWAYS \| len);
856	} else {
857	yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
858	yp->tx_ring[entry].dbdma_cmd =
859	cpu_to_le32(CMD_TX_PKT \| BRANCH_IFTRUE \| len);
860	}
861	yp->cur_tx++;
862	#else
863	yp->tx_ring[entry<<1].request_cnt = len;
864	yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
865	skb->data, len, PCI_DMA_TODEVICE));
866	/* The input_last (status-write) command is constant, but we must
867	rewrite the subsequent 'stop' command. */
868
869	yp->cur_tx++;
870	{
871	unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
872	yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
873	}
874	/* Final step -- overwrite the old 'stop' command. */
875
876	yp->tx_ring[entry<<1].dbdma_cmd =
877	cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT\|INTR_ALWAYS\|BRANCH_IFTRUE :
878	CMD_TX_PKT \| BRANCH_IFTRUE) \| len);
879	#endif
880
881	/* Non-x86 Todo: explicitly flush cache lines here. */
882
883	/* Wake the potentially-idle transmit channel. */
884	iowrite32(0x10001000, yp->base + TxCtrl);
885
886	if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
887	netif_start_queue (dev); /* Typical path */
888	else
889	yp->tx_full = 1;
890
891	if (yellowfin_debug > 4) {
892	printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
893	dev->name, yp->cur_tx, entry);
894	}
895	return 0;
896	}
897
898	/* The interrupt handler does all of the Rx thread work and cleans up
899	after the Tx thread. */
900	static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
901	{
902	struct net_device *dev = dev_instance;
903	struct yellowfin_private *yp;
904	void __iomem *ioaddr;
905	int boguscnt = max_interrupt_work;
906	unsigned int handled = 0;
907
908	yp = netdev_priv(dev);
909	ioaddr = yp->base;
910
911	spin_lock (&yp->lock);
912
913	do {
914	u16 intr_status = ioread16(ioaddr + IntrClear);
915
916	if (yellowfin_debug > 4)
917	printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
918	dev->name, intr_status);
919
920	if (intr_status == 0)
921	break;
922	handled = 1;
923
924	if (intr_status & (IntrRxDone \| IntrEarlyRx)) {
925	yellowfin_rx(dev);
926	iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
927	}
928
929	#ifdef NO_TXSTATS
930	for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
931	int entry = yp->dirty_tx % TX_RING_SIZE;
932	struct sk_buff *skb;
933
934	if (yp->tx_ring[entry].result_status == 0)
935	break;
936	skb = yp->tx_skbuff[entry];
937	dev->stats.tx_packets++;
938	dev->stats.tx_bytes += skb->len;
939	/* Free the original skb. */
940	pci_unmap_single(yp->pci_dev, le32_to_cpu(yp->tx_ring[entry].addr),
941	skb->len, PCI_DMA_TODEVICE);
942	dev_kfree_skb_irq(skb);
943	yp->tx_skbuff[entry] = NULL;
944	}
945	if (yp->tx_full
946	&& yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
947	/* The ring is no longer full, clear tbusy. */
948	yp->tx_full = 0;
949	netif_wake_queue(dev);
950	}
951	#else
952	if ((intr_status & IntrTxDone) \|\| (yp->tx_tail_desc->tx_errs)) {
953	unsigned dirty_tx = yp->dirty_tx;
954
955	for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
956	dirty_tx++) {
957	/* Todo: optimize this. */
958	int entry = dirty_tx % TX_RING_SIZE;
959	u16 tx_errs = yp->tx_status[entry].tx_errs;
960	struct sk_buff *skb;
961
962	#ifndef final_version
963	if (yellowfin_debug > 5)
964	printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
965	"%4.4x %4.4x %4.4x %4.4x.\n",
966	dev->name, entry,
967	yp->tx_status[entry].tx_cnt,
968	yp->tx_status[entry].tx_errs,
969	yp->tx_status[entry].total_tx_cnt,
970	yp->tx_status[entry].paused);
971	#endif
972	if (tx_errs == 0)
973	break; /* It still hasn't been Txed */
974	skb = yp->tx_skbuff[entry];
975	if (tx_errs & 0xF810) {
976	/* There was an major error, log it. */
977	#ifndef final_version
978	if (yellowfin_debug > 1)
979	printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
980	dev->name, tx_errs);
981	#endif
982	dev->stats.tx_errors++;
983	if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
984	if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
985	if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
986	if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
987	} else {
988	#ifndef final_version
989	if (yellowfin_debug > 4)
990	printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
991	dev->name, tx_errs);
992	#endif
993	dev->stats.tx_bytes += skb->len;
994	dev->stats.collisions += tx_errs & 15;
995	dev->stats.tx_packets++;
996	}
997	/* Free the original skb. */
998	pci_unmap_single(yp->pci_dev,
999	yp->tx_ring[entry<<1].addr, skb->len,
1000	PCI_DMA_TODEVICE);
1001	dev_kfree_skb_irq(skb);
1002	yp->tx_skbuff[entry] = 0;
1003	/* Mark status as empty. */
1004	yp->tx_status[entry].tx_errs = 0;
1005	}
1006
1007	#ifndef final_version
1008	if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1009	printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1010	dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
1011	dirty_tx += TX_RING_SIZE;
1012	}
1013	#endif
1014
1015	if (yp->tx_full
1016	&& yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1017	/* The ring is no longer full, clear tbusy. */
1018	yp->tx_full = 0;
1019	netif_wake_queue(dev);
1020	}
1021
1022	yp->dirty_tx = dirty_tx;
1023	yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1024	}
1025	#endif
1026
1027	/* Log errors and other uncommon events. */
1028	if (intr_status & 0x2ee) /* Abnormal error summary. */
1029	yellowfin_error(dev, intr_status);
1030
1031	if (--boguscnt < 0) {
1032	printk(KERN_WARNING "%s: Too much work at interrupt, "
1033	"status=0x%4.4x.\n",
1034	dev->name, intr_status);
1035	break;
1036	}
1037	} while (1);
1038
1039	if (yellowfin_debug > 3)
1040	printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1041	dev->name, ioread16(ioaddr + IntrStatus));
1042
1043	spin_unlock (&yp->lock);
1044	return IRQ_RETVAL(handled);
1045	}
1046
1047	/* This routine is logically part of the interrupt handler, but separated
1048	for clarity and better register allocation. */
1049	static int yellowfin_rx(struct net_device *dev)
1050	{
1051	struct yellowfin_private *yp = netdev_priv(dev);
1052	int entry = yp->cur_rx % RX_RING_SIZE;
1053	int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1054
1055	if (yellowfin_debug > 4) {
1056	printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1057	entry, yp->rx_ring[entry].result_status);
1058	printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
1059	entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1060	yp->rx_ring[entry].result_status);
1061	}
1062
1063	/* If EOP is set on the next entry, it's a new packet. Send it up. */
1064	while (1) {
1065	struct yellowfin_desc *desc = &yp->rx_ring[entry];
1066	struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1067	s16 frame_status;
1068	u16 desc_status;
1069	int data_size;
1070	u8 *buf_addr;
1071
1072	if(!desc->result_status)
1073	break;
1074	pci_dma_sync_single_for_cpu(yp->pci_dev, le32_to_cpu(desc->addr),
1075	yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1076	desc_status = le32_to_cpu(desc->result_status) >> 16;
1077	buf_addr = rx_skb->data;
1078	data_size = (le32_to_cpu(desc->dbdma_cmd) -
1079	le32_to_cpu(desc->result_status)) & 0xffff;
1080	frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1081	if (yellowfin_debug > 4)
1082	printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n",
1083	frame_status);
1084	if (--boguscnt < 0)
1085	break;
1086	if ( ! (desc_status & RX_EOP)) {
1087	if (data_size != 0)
1088	printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1089	" status %4.4x, data_size %d!\n", dev->name, desc_status, data_size);
1090	dev->stats.rx_length_errors++;
1091	} else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1092	/* There was a error. */
1093	if (yellowfin_debug > 3)
1094	printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n",
1095	frame_status);
1096	dev->stats.rx_errors++;
1097	if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1098	if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1099	if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1100	if (frame_status < 0) dev->stats.rx_dropped++;
1101	} else if ( !(yp->drv_flags & IsGigabit) &&
1102	((buf_addr[data_size-1] & 0x85) \|\| buf_addr[data_size-2] & 0xC0)) {
1103	u8 status1 = buf_addr[data_size-2];
1104	u8 status2 = buf_addr[data_size-1];
1105	dev->stats.rx_errors++;
1106	if (status1 & 0xC0) dev->stats.rx_length_errors++;
1107	if (status2 & 0x03) dev->stats.rx_frame_errors++;
1108	if (status2 & 0x04) dev->stats.rx_crc_errors++;
1109	if (status2 & 0x80) dev->stats.rx_dropped++;
1110	#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1111	} else if ((yp->flags & HasMACAddrBug) &&
1112	memcmp(le32_to_cpu(yp->rx_ring_dma +
1113	entry*sizeof(struct yellowfin_desc)),
1114	dev->dev_addr, 6) != 0 &&
1115	memcmp(le32_to_cpu(yp->rx_ring_dma +
1116	entry*sizeof(struct yellowfin_desc)),
1117	"\377\377\377\377\377\377", 6) != 0) {
1118	if (bogus_rx++ == 0)
1119	printk(KERN_WARNING "%s: Bad frame to %pM\n",
1120	dev->name, buf_addr);
1121	#endif
1122	} else {
1123	struct sk_buff *skb;
1124	int pkt_len = data_size -
1125	(yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1126	/* To verify: Yellowfin Length should omit the CRC! */
1127
1128	#ifndef final_version
1129	if (yellowfin_debug > 4)
1130	printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d"
1131	" of %d, bogus_cnt %d.\n",
1132	pkt_len, data_size, boguscnt);
1133	#endif
1134	/* Check if the packet is long enough to just pass up the skbuff
1135	without copying to a properly sized skbuff. */
1136	if (pkt_len > rx_copybreak) {
1137	skb_put(skb = rx_skb, pkt_len);
1138	pci_unmap_single(yp->pci_dev,
1139	le32_to_cpu(yp->rx_ring[entry].addr),
1140	yp->rx_buf_sz,
1141	PCI_DMA_FROMDEVICE);
1142	yp->rx_skbuff[entry] = NULL;
1143	} else {
1144	skb = dev_alloc_skb(pkt_len + 2);
1145	if (skb == NULL)
1146	break;
1147	skb_reserve(skb, 2); /* 16 byte align the IP header */
1148	skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1149	skb_put(skb, pkt_len);
1150	pci_dma_sync_single_for_device(yp->pci_dev,
1151	le32_to_cpu(desc->addr),
1152	yp->rx_buf_sz,
1153	PCI_DMA_FROMDEVICE);
1154	}
1155	skb->protocol = eth_type_trans(skb, dev);
1156	netif_rx(skb);
1157	dev->stats.rx_packets++;
1158	dev->stats.rx_bytes += pkt_len;
1159	}
1160	entry = (++yp->cur_rx) % RX_RING_SIZE;
1161	}
1162
1163	/* Refill the Rx ring buffers. */
1164	for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1165	entry = yp->dirty_rx % RX_RING_SIZE;
1166	if (yp->rx_skbuff[entry] == NULL) {
1167	struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1168	if (skb == NULL)
1169	break; /* Better luck next round. */
1170	yp->rx_skbuff[entry] = skb;
1171	skb->dev = dev; /* Mark as being used by this device. */
1172	skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1173	yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1174	skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1175	}
1176	yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1177	yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1178	if (entry != 0)
1179	yp->rx_ring[entry - 1].dbdma_cmd =
1180	cpu_to_le32(CMD_RX_BUF \| INTR_ALWAYS \| yp->rx_buf_sz);
1181	else
1182	yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1183	cpu_to_le32(CMD_RX_BUF \| INTR_ALWAYS \| BRANCH_ALWAYS
1184	\| yp->rx_buf_sz);
1185	}
1186
1187	return 0;
1188	}
1189
1190	static void yellowfin_error(struct net_device *dev, int intr_status)
1191	{
1192	printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1193	dev->name, intr_status);
1194	/* Hmmmmm, it's not clear what to do here. */
1195	if (intr_status & (IntrTxPCIErr \| IntrTxPCIFault))
1196	dev->stats.tx_errors++;
1197	if (intr_status & (IntrRxPCIErr \| IntrRxPCIFault))
1198	dev->stats.rx_errors++;
1199	}
1200
1201	static int yellowfin_close(struct net_device *dev)
1202	{
1203	struct yellowfin_private *yp = netdev_priv(dev);
1204	void __iomem *ioaddr = yp->base;
1205	int i;
1206
1207	netif_stop_queue (dev);
1208
1209	if (yellowfin_debug > 1) {
1210	printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1211	"Rx %4.4x Int %2.2x.\n",
1212	dev->name, ioread16(ioaddr + TxStatus),
1213	ioread16(ioaddr + RxStatus),
1214	ioread16(ioaddr + IntrStatus));
1215	printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1216	dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1217	}
1218
1219	/* Disable interrupts by clearing the interrupt mask. */
1220	iowrite16(0x0000, ioaddr + IntrEnb);
1221
1222	/* Stop the chip's Tx and Rx processes. */
1223	iowrite32(0x80000000, ioaddr + RxCtrl);
1224	iowrite32(0x80000000, ioaddr + TxCtrl);
1225
1226	del_timer(&yp->timer);
1227
1228	#if defined(__i386__)
1229	if (yellowfin_debug > 2) {
1230	printk(KERN_DEBUG" Tx ring at %8.8llx:\n",
1231	(unsigned long long)yp->tx_ring_dma);
1232	for (i = 0; i < TX_RING_SIZE*2; i++)
1233	printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1234	ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1235	i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1236	yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1237	printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1238	for (i = 0; i < TX_RING_SIZE; i++)
1239	printk(KERN_DEBUG " #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1240	i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1241	yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1242
1243	printk(KERN_DEBUG " Rx ring %8.8llx:\n",
1244	(unsigned long long)yp->rx_ring_dma);
1245	for (i = 0; i < RX_RING_SIZE; i++) {
1246	printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1247	ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1248	i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1249	yp->rx_ring[i].result_status);
1250	if (yellowfin_debug > 6) {
1251	if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1252	int j;
1253	for (j = 0; j < 0x50; j++)
1254	printk(" %4.4x",
1255	get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1256	printk("\n");
1257	}
1258	}
1259	}
1260	}
1261	#endif /* __i386__ debugging only */
1262
1263	free_irq(dev->irq, dev);
1264
1265	/* Free all the skbuffs in the Rx queue. */
1266	for (i = 0; i < RX_RING_SIZE; i++) {
1267	yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1268	yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1269	if (yp->rx_skbuff[i]) {
1270	dev_kfree_skb(yp->rx_skbuff[i]);
1271	}
1272	yp->rx_skbuff[i] = NULL;
1273	}
1274	for (i = 0; i < TX_RING_SIZE; i++) {
1275	if (yp->tx_skbuff[i])
1276	dev_kfree_skb(yp->tx_skbuff[i]);
1277	yp->tx_skbuff[i] = NULL;
1278	}
1279
1280	#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1281	if (yellowfin_debug > 0) {
1282	printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1283	dev->name, bogus_rx);
1284	}
1285	#endif
1286
1287	return 0;
1288	}
1289
1290	/* Set or clear the multicast filter for this adaptor. */
1291
1292	static void set_rx_mode(struct net_device *dev)
1293	{
1294	struct yellowfin_private *yp = netdev_priv(dev);
1295	void __iomem *ioaddr = yp->base;
1296	u16 cfg_value = ioread16(ioaddr + Cnfg);
1297
1298	/* Stop the Rx process to change any value. */
1299	iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1300	if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1301	iowrite16(0x000F, ioaddr + AddrMode);
1302	} else if ((dev->mc_count > 64) \|\| (dev->flags & IFF_ALLMULTI)) {
1303	/* Too many to filter well, or accept all multicasts. */
1304	iowrite16(0x000B, ioaddr + AddrMode);
1305	} else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1306	struct dev_mc_list *mclist;
1307	u16 hash_table[4];
1308	int i;
1309	memset(hash_table, 0, sizeof(hash_table));
1310	for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1311	i++, mclist = mclist->next) {
1312	unsigned int bit;
1313
1314	/* Due to a bug in the early chip versions, multiple filter
1315	slots must be set for each address. */
1316	if (yp->drv_flags & HasMulticastBug) {
1317	bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1318	hash_table[bit >> 4] \|= (1 << bit);
1319	bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1320	hash_table[bit >> 4] \|= (1 << bit);
1321	bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1322	hash_table[bit >> 4] \|= (1 << bit);
1323	}
1324	bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1325	hash_table[bit >> 4] \|= (1 << bit);
1326	}
1327	/* Copy the hash table to the chip. */
1328	for (i = 0; i < 4; i++)
1329	iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1330	iowrite16(0x0003, ioaddr + AddrMode);
1331	} else { /* Normal, unicast/broadcast-only mode. */
1332	iowrite16(0x0001, ioaddr + AddrMode);
1333	}
1334	/* Restart the Rx process. */
1335	iowrite16(cfg_value \| 0x1000, ioaddr + Cnfg);
1336	}
1337
1338	static void yellowfin_get_drvinfo(struct net_device dev, struct ethtool_drvinfo info)
1339	{
1340	struct yellowfin_private *np = netdev_priv(dev);
1341	strcpy(info->driver, DRV_NAME);
1342	strcpy(info->version, DRV_VERSION);
1343	strcpy(info->bus_info, pci_name(np->pci_dev));
1344	}
1345
1346	static const struct ethtool_ops ethtool_ops = {
1347	.get_drvinfo = yellowfin_get_drvinfo
1348	};
1349
1350	static int netdev_ioctl(struct net_device dev, struct ifreq rq, int cmd)
1351	{
1352	struct yellowfin_private *np = netdev_priv(dev);
1353	void __iomem *ioaddr = np->base;
1354	struct mii_ioctl_data *data = if_mii(rq);
1355
1356	switch(cmd) {
1357	case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1358	data->phy_id = np->phys[0] & 0x1f;
1359	/* Fall Through */
1360
1361	case SIOCGMIIREG: /* Read MII PHY register. */
1362	data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1363	return 0;
1364
1365	case SIOCSMIIREG: /* Write MII PHY register. */
1366	if (!capable(CAP_NET_ADMIN))
1367	return -EPERM;
1368	if (data->phy_id == np->phys[0]) {
1369	u16 value = data->val_in;
1370	switch (data->reg_num) {
1371	case 0:
1372	/* Check for autonegotiation on or reset. */
1373	np->medialock = (value & 0x9000) ? 0 : 1;
1374	if (np->medialock)
1375	np->full_duplex = (value & 0x0100) ? 1 : 0;
1376	break;
1377	case 4: np->advertising = value; break;
1378	}
1379	/* Perhaps check_duplex(dev), depending on chip semantics. */
1380	}
1381	mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1382	return 0;
1383	default:
1384	return -EOPNOTSUPP;
1385	}
1386	}
1387
1388
1389	static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1390	{
1391	struct net_device *dev = pci_get_drvdata(pdev);
1392	struct yellowfin_private *np;
1393
1394	BUG_ON(!dev);
1395	np = netdev_priv(dev);
1396
1397	pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1398	np->tx_status_dma);
1399	pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1400	pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1401	unregister_netdev (dev);
1402
1403	pci_iounmap(pdev, np->base);
1404
1405	pci_release_regions (pdev);
1406
1407	free_netdev (dev);
1408	pci_set_drvdata(pdev, NULL);
1409	}
1410
1411
1412	static struct pci_driver yellowfin_driver = {
1413	.name = DRV_NAME,
1414	.id_table = yellowfin_pci_tbl,
1415	.probe = yellowfin_init_one,
1416	.remove = __devexit_p(yellowfin_remove_one),
1417	};
1418
1419
1420	static int __init yellowfin_init (void)
1421	{
1422	/* when a module, this is printed whether or not devices are found in probe */
1423	#ifdef MODULE
1424	printk(version);
1425	#endif
1426	return pci_register_driver(&yellowfin_driver);
1427	}
1428
1429
1430	static void __exit yellowfin_cleanup (void)
1431	{
1432	pci_unregister_driver (&yellowfin_driver);
1433	}
1434
1435
1436	module_init(yellowfin_init);
1437	module_exit(yellowfin_cleanup);
1438

Download this file

Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.2
jz-3.3
jz-3.4
jz47xx
jz47xx-2.6.38
master
xiangfu/openwrt/v3.0.0
xiangfu/openwrt/v3.2.1

Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7

Kernel

Kernel Git Source Tree

Root/drivers/net/yellowfin.c

interactive