Root/arch/mips/jz4740/platform.c

Source at commit 65b33a24c1039156c0f4c0f0dbe043a41ce5a177 created 9 years 11 months ago.
By Lars-Peter Clausen, usb: musb-jz4740: Move musb_hdrc_config to the glue driver
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform devices
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/device.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/resource.h>
21
22#include <linux/dma-mapping.h>
23
24#include <linux/usb/musb.h>
25
26#include <asm/mach-jz4740/platform.h>
27#include <asm/mach-jz4740/base.h>
28#include <asm/mach-jz4740/irq.h>
29
30#include <linux/serial_core.h>
31#include <linux/serial_8250.h>
32
33#include "serial.h"
34#include "clock.h"
35
36/* OHCI controller */
37static struct resource jz4740_usb_ohci_resources[] = {
38    {
39        .start = JZ4740_UHC_BASE_ADDR,
40        .end = JZ4740_UHC_BASE_ADDR + 0x1000 - 1,
41        .flags = IORESOURCE_MEM,
42    },
43    {
44        .start = JZ4740_IRQ_UHC,
45        .end = JZ4740_IRQ_UHC,
46        .flags = IORESOURCE_IRQ,
47    },
48};
49
50struct platform_device jz4740_usb_ohci_device = {
51    .name = "jz4740-ohci",
52    .id = -1,
53    .dev = {
54        .dma_mask = &jz4740_usb_ohci_device.dev.coherent_dma_mask,
55        .coherent_dma_mask = DMA_BIT_MASK(32),
56    },
57    .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources),
58    .resource = jz4740_usb_ohci_resources,
59};
60
61/* USB Device Controller */
62struct platform_device jz4740_udc_xceiv_device = {
63    .name = "usb_phy_gen_xceiv",
64    .id = 0,
65};
66
67static struct resource jz4740_udc_resources[] = {
68    [0] = {
69        .start = JZ4740_UDC_BASE_ADDR,
70        .end = JZ4740_UDC_BASE_ADDR + 0x10000 - 1,
71        .flags = IORESOURCE_MEM,
72    },
73    [1] = {
74        .start = JZ4740_IRQ_UDC,
75        .end = JZ4740_IRQ_UDC,
76        .flags = IORESOURCE_IRQ,
77        .name = "mc",
78    },
79};
80
81struct platform_device jz4740_udc_device = {
82    .name = "musb-jz4740",
83    .id = -1,
84    .dev = {
85        .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
86        .coherent_dma_mask = DMA_BIT_MASK(32),
87    },
88    .num_resources = ARRAY_SIZE(jz4740_udc_resources),
89    .resource = jz4740_udc_resources,
90};
91
92/* MMC/SD controller */
93static struct resource jz4740_mmc_resources[] = {
94    {
95        .start = JZ4740_MSC_BASE_ADDR,
96        .end = JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
97        .flags = IORESOURCE_MEM,
98    },
99    {
100        .start = JZ4740_IRQ_MSC,
101        .end = JZ4740_IRQ_MSC,
102        .flags = IORESOURCE_IRQ,
103    }
104};
105
106struct platform_device jz4740_mmc_device = {
107    .name = "jz4740-mmc",
108    .id = 0,
109    .dev = {
110        .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
111        .coherent_dma_mask = DMA_BIT_MASK(32),
112    },
113    .num_resources = ARRAY_SIZE(jz4740_mmc_resources),
114    .resource = jz4740_mmc_resources,
115};
116
117/* RTC controller */
118static struct resource jz4740_rtc_resources[] = {
119    {
120        .start = JZ4740_RTC_BASE_ADDR,
121        .end = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
122        .flags = IORESOURCE_MEM,
123    },
124    {
125        .start = JZ4740_IRQ_RTC,
126        .end = JZ4740_IRQ_RTC,
127        .flags = IORESOURCE_IRQ,
128    },
129};
130
131struct platform_device jz4740_rtc_device = {
132    .name = "jz4740-rtc",
133    .id = -1,
134    .num_resources = ARRAY_SIZE(jz4740_rtc_resources),
135    .resource = jz4740_rtc_resources,
136};
137
138/* I2C controller */
139static struct resource jz4740_i2c_resources[] = {
140    {
141        .start = JZ4740_I2C_BASE_ADDR,
142        .end = JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
143        .flags = IORESOURCE_MEM,
144    },
145    {
146        .start = JZ4740_IRQ_I2C,
147        .end = JZ4740_IRQ_I2C,
148        .flags = IORESOURCE_IRQ,
149    }
150};
151
152struct platform_device jz4740_i2c_device = {
153    .name = "jz4740-i2c",
154    .id = 0,
155    .num_resources = ARRAY_SIZE(jz4740_i2c_resources),
156    .resource = jz4740_i2c_resources,
157};
158
159/* NAND controller */
160static struct resource jz4740_nand_resources[] = {
161    {
162        .name = "mmio",
163        .start = JZ4740_EMC_BASE_ADDR,
164        .end = JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
165        .flags = IORESOURCE_MEM,
166    },
167    {
168        .name = "bank1",
169        .start = 0x18000000,
170        .end = 0x180C0000 - 1,
171        .flags = IORESOURCE_MEM,
172    },
173    {
174        .name = "bank2",
175        .start = 0x14000000,
176        .end = 0x140C0000 - 1,
177        .flags = IORESOURCE_MEM,
178    },
179    {
180        .name = "bank3",
181        .start = 0x0C000000,
182        .end = 0x0C0C0000 - 1,
183        .flags = IORESOURCE_MEM,
184    },
185    {
186        .name = "bank4",
187        .start = 0x08000000,
188        .end = 0x080C0000 - 1,
189        .flags = IORESOURCE_MEM,
190    },
191};
192
193struct platform_device jz4740_nand_device = {
194    .name = "jz4740-nand",
195    .num_resources = ARRAY_SIZE(jz4740_nand_resources),
196    .resource = jz4740_nand_resources,
197};
198
199/* LCD controller */
200static struct resource jz4740_framebuffer_resources[] = {
201    {
202        .start = JZ4740_LCD_BASE_ADDR,
203        .end = JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
204        .flags = IORESOURCE_MEM,
205    },
206};
207
208struct platform_device jz4740_framebuffer_device = {
209    .name = "jz4740-fb",
210    .id = -1,
211    .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
212    .resource = jz4740_framebuffer_resources,
213    .dev = {
214        .dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
215        .coherent_dma_mask = DMA_BIT_MASK(32),
216    },
217};
218
219/* I2S controller */
220static struct resource jz4740_i2s_resources[] = {
221    {
222        .start = JZ4740_AIC_BASE_ADDR,
223        .end = JZ4740_AIC_BASE_ADDR + 0x38 - 1,
224        .flags = IORESOURCE_MEM,
225    },
226};
227
228struct platform_device jz4740_i2s_device = {
229    .name = "jz4740-i2s",
230    .id = -1,
231    .num_resources = ARRAY_SIZE(jz4740_i2s_resources),
232    .resource = jz4740_i2s_resources,
233};
234
235/* PCM */
236struct platform_device jz4740_pcm_device = {
237    .name = "jz4740-pcm-audio",
238    .id = -1,
239};
240
241/* Codec */
242static struct resource jz4740_codec_resources[] = {
243    {
244        .start = JZ4740_AIC_BASE_ADDR + 0x80,
245        .end = JZ4740_AIC_BASE_ADDR + 0x88 - 1,
246        .flags = IORESOURCE_MEM,
247    },
248};
249
250struct platform_device jz4740_codec_device = {
251    .name = "jz4740-codec",
252    .id = -1,
253    .num_resources = ARRAY_SIZE(jz4740_codec_resources),
254    .resource = jz4740_codec_resources,
255};
256
257/* ADC controller */
258static struct resource jz4740_adc_resources[] = {
259    {
260        .start = JZ4740_SADC_BASE_ADDR,
261        .end = JZ4740_SADC_BASE_ADDR + 0x30,
262        .flags = IORESOURCE_MEM,
263    },
264    {
265        .start = JZ4740_IRQ_SADC,
266        .end = JZ4740_IRQ_SADC,
267        .flags = IORESOURCE_IRQ,
268    },
269    {
270        .start = JZ4740_IRQ_ADC_BASE,
271        .end = JZ4740_IRQ_ADC_BASE,
272        .flags = IORESOURCE_IRQ,
273    },
274};
275
276struct platform_device jz4740_adc_device = {
277    .name = "jz4740-adc",
278    .id = -1,
279    .num_resources = ARRAY_SIZE(jz4740_adc_resources),
280    .resource = jz4740_adc_resources,
281};
282
283/* Serial */
284#define JZ4740_UART_DATA(_id) \
285    { \
286        .flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \
287        .iotype = UPIO_MEM, \
288        .regshift = 2, \
289        .serial_out = jz4740_serial_out, \
290        .type = PORT_16550, \
291        .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
292        .irq = JZ4740_IRQ_UART ## _id, \
293    }
294
295static struct plat_serial8250_port jz4740_uart_data[] = {
296    JZ4740_UART_DATA(0),
297    JZ4740_UART_DATA(1),
298    {},
299};
300
301static struct platform_device jz4740_uart_device = {
302    .name = "serial8250",
303    .id = 0,
304    .dev = {
305        .platform_data = jz4740_uart_data,
306    },
307};
308
309void jz4740_serial_device_register(void)
310{
311    struct plat_serial8250_port *p;
312
313    for (p = jz4740_uart_data; p->flags != 0; ++p)
314        p->uartclk = jz4740_clock_bdata.ext_rate;
315
316    platform_device_register(&jz4740_uart_device);
317}
318
319/* Watchdog */
320static struct resource jz4740_wdt_resources[] = {
321    {
322        .start = JZ4740_WDT_BASE_ADDR,
323        .end = JZ4740_WDT_BASE_ADDR + 0x10 - 1,
324        .flags = IORESOURCE_MEM,
325    },
326};
327
328struct platform_device jz4740_wdt_device = {
329    .name = "jz4740-wdt",
330    .id = -1,
331    .num_resources = ARRAY_SIZE(jz4740_wdt_resources),
332    .resource = jz4740_wdt_resources,
333};
334
335/* PWM */
336struct platform_device jz4740_pwm_device = {
337    .name = "jz4740-pwm",
338    .id = -1,
339};
340
341/* DMA */
342static struct resource jz4740_dma_resources[] = {
343    {
344        .start = JZ4740_DMAC_BASE_ADDR,
345        .end = JZ4740_DMAC_BASE_ADDR + 0x400 - 1,
346        .flags = IORESOURCE_MEM,
347    },
348    {
349        .start = JZ4740_IRQ_DMAC,
350        .end = JZ4740_IRQ_DMAC,
351        .flags = IORESOURCE_IRQ,
352    },
353};
354
355struct platform_device jz4740_dma_device = {
356    .name = "jz4740-dma",
357    .id = -1,
358    .num_resources = ARRAY_SIZE(jz4740_dma_resources),
359    .resource = jz4740_dma_resources,
360};
361

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