Root/arch/mips/jz4740/irq.c

Source at commit 694c7fbe86b8a9c91392e505afcb9fcfc91deccc created 12 years 6 months ago.
By Maarten ter Huurne, MIPS: JZ4740: Add cpufreq support
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform IRQ support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/errno.h>
17#include <linux/init.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/timex.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24
25#include <linux/debugfs.h>
26#include <linux/seq_file.h>
27
28#include <asm/io.h>
29#include <asm/mipsregs.h>
30#include <asm/irq_cpu.h>
31
32#include <asm/mach-jz4740/base.h>
33
34static void __iomem *jz_intc_base;
35
36#define JZ_REG_INTC_STATUS 0x00
37#define JZ_REG_INTC_MASK 0x04
38#define JZ_REG_INTC_SET_MASK 0x08
39#define JZ_REG_INTC_CLEAR_MASK 0x0c
40#define JZ_REG_INTC_PENDING 0x10
41
42static irqreturn_t jz4740_cascade(int irq, void *data)
43{
44    uint32_t irq_reg;
45
46    irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
47
48    if (irq_reg)
49        generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
50
51    return IRQ_HANDLED;
52}
53
54static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
55{
56    struct irq_chip_regs *regs = &gc->chip_types->regs;
57
58    writel(mask, gc->reg_base + regs->enable);
59    writel(~mask, gc->reg_base + regs->disable);
60}
61
62void jz4740_irq_suspend(struct irq_data *data)
63{
64    struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
65    jz4740_irq_set_mask(gc, gc->wake_active);
66}
67
68void jz4740_irq_resume(struct irq_data *data)
69{
70    struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
71    jz4740_irq_set_mask(gc, gc->mask_cache);
72}
73
74static struct irqaction jz4740_cascade_action = {
75    .handler = jz4740_cascade,
76    .name = "JZ4740 cascade interrupt",
77};
78
79void __init arch_init_irq(void)
80{
81    struct irq_chip_generic *gc;
82    struct irq_chip_type *ct;
83
84    mips_cpu_irq_init();
85
86    jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
87
88    /* Mask all irqs */
89    writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
90
91    gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base,
92        handle_level_irq);
93
94    gc->wake_enabled = IRQ_MSK(32);
95
96    ct = gc->chip_types;
97    ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
98    ct->regs.disable = JZ_REG_INTC_SET_MASK;
99    ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
100    ct->chip.irq_mask = irq_gc_mask_disable_reg;
101    ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
102    ct->chip.irq_set_wake = irq_gc_set_wake;
103    ct->chip.irq_suspend = jz4740_irq_suspend;
104    ct->chip.irq_resume = jz4740_irq_resume;
105
106    irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
107
108    setup_irq(2, &jz4740_cascade_action);
109}
110
111asmlinkage void plat_irq_dispatch(void)
112{
113    unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
114    if (pending & STATUSF_IP2)
115        do_IRQ(2);
116    else if (pending & STATUSF_IP3)
117        do_IRQ(3);
118    else
119        spurious_interrupt();
120}
121
122#ifdef CONFIG_DEBUG_FS
123
124static inline void intc_seq_reg(struct seq_file *s, const char *name,
125    unsigned int reg)
126{
127    seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
128}
129
130static int intc_regs_show(struct seq_file *s, void *unused)
131{
132    intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
133    intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
134    intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
135
136    return 0;
137}
138
139static int intc_regs_open(struct inode *inode, struct file *file)
140{
141    return single_open(file, intc_regs_show, NULL);
142}
143
144static const struct file_operations intc_regs_operations = {
145    .open = intc_regs_open,
146    .read = seq_read,
147    .llseek = seq_lseek,
148    .release = single_release,
149};
150
151static int __init intc_debugfs_init(void)
152{
153    (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
154                NULL, NULL, &intc_regs_operations);
155    return 0;
156}
157subsys_initcall(intc_debugfs_init);
158
159#endif
160

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