Root/arch/mips/mm/cex-gen.S

Source at commit 694c7fbe86b8a9c91392e505afcb9fcfc91deccc created 13 years 12 days ago.
By Maarten ter Huurne, MIPS: JZ4740: Add cpufreq support
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995 - 1999 Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics, Inc.
8 *
9 * Cache error handler
10 */
11#include <asm/asm.h>
12#include <asm/regdef.h>
13#include <asm/mipsregs.h>
14#include <asm/stackframe.h>
15
16/*
17 * Game over. Go to the button. Press gently. Swear where allowed by
18 * legislation.
19 */
20    LEAF(except_vec2_generic)
21    .set noreorder
22    .set noat
23    .set mips0
24    /*
25     * This is a very bad place to be. Our cache error
26     * detection has triggered. If we have write-back data
27     * in the cache, we may not be able to recover. As a
28     * first-order desperate measure, turn off KSEG0 cacheing.
29     */
30    mfc0 k0,CP0_CONFIG
31    li k1,~CONF_CM_CMASK
32    and k0,k0,k1
33    ori k0,k0,CONF_CM_UNCACHED
34    mtc0 k0,CP0_CONFIG
35    /* Give it a few cycles to sink in... */
36    nop
37    nop
38    nop
39
40    j cache_parity_error
41    nop
42    END(except_vec2_generic)
43

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