Root/arch/mips/mm/cex-sb1.S

Source at commit 694c7fbe86b8a9c91392e505afcb9fcfc91deccc created 12 years 8 months ago.
By Maarten ter Huurne, MIPS: JZ4740: Add cpufreq support
1/*
2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/init.h>
19
20#include <asm/asm.h>
21#include <asm/regdef.h>
22#include <asm/mipsregs.h>
23#include <asm/stackframe.h>
24#include <asm/cacheops.h>
25#include <asm/sibyte/board.h>
26
27#define C0_ERRCTL $26 /* CP0: Error info */
28#define C0_CERR_I $27 /* CP0: Icache error */
29#define C0_CERR_D $27,1 /* CP0: Dcache error */
30
31    /*
32     * Based on SiByte sample software cache-err/cerr.S
33     * CVS revision 1.8. Only the 'unrecoverable' case
34     * is changed.
35     */
36
37    .set mips64
38    .set noreorder
39    .set noat
40
41    /*
42     * sb1_cerr_vec: code to be copied to the Cache Error
43     * Exception vector. The code must be pushed out to memory
44     * (either by copying to Kseg0 and Kseg1 both, or by flushing
45     * the L1 and L2) since it is fetched as 0xa0000100.
46     *
47     * NOTE: Be sure this handler is at most 28 instructions long
48     * since the final 16 bytes of the exception vector memory
49     * (0x170-0x17f) are used to preserve k0, k1, and ra.
50     */
51
52LEAF(except_vec2_sb1)
53    /*
54     * If this error is recoverable, we need to exit the handler
55     * without having dirtied any registers. To do this,
56     * save/restore k0 and k1 from low memory (Useg is direct
57     * mapped while ERL=1). Note that we can't save to a
58     * CPU-specific location without ruining a register in the
59     * process. This means we are vulnerable to data corruption
60     * whenever the handler is reentered by a second CPU.
61     */
62    sd k0,0x170($0)
63    sd k1,0x178($0)
64
65#ifdef CONFIG_SB1_CEX_ALWAYS_FATAL
66    j handle_vec2_sb1
67     nop
68#else
69    /*
70     * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
71     * if we can fast-path out of here for a h/w-recovered error.
72     */
73    mfc0 k1,C0_ERRCTL
74    bgtz k1,attempt_recovery
75     sll k0,k1,1
76
77recovered_dcache:
78    /*
79     * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
80     * Ought to log the occurrence of this recovered dcache error.
81     */
82    b recovered
83     mtc0 $0,C0_CERR_D
84
85attempt_recovery:
86    /*
87     * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31. Any
88     * Dcache errors we can recover from will take more extensive
89     * processing. For now, they are considered "unrecoverable".
90     * Note that 'DC' becoming set (outside of ERL mode) will
91     * cause 'IC' to clear; so if there's an Icache error, we'll
92     * only find out about it if we recover from this error and
93     * continue executing.
94     */
95    bltz k0,unrecoverable
96     sll k0,1
97
98    /*
99     * k0 has C0_ERRCTL << 2, which puts 'IC' at bit 31. If an
100     * Icache error isn't indicated, I'm not sure why we got here.
101     * Consider that case "unrecoverable" for now.
102     */
103    bgez k0,unrecoverable
104
105attempt_icache_recovery:
106    /*
107     * External icache errors are due to uncorrectable ECC errors
108     * in the L2 cache or Memory Controller and cannot be
109     * recovered here.
110     */
111     mfc0 k0,C0_CERR_I /* delay slot */
112    li k1,1 << 26 /* ICACHE_EXTERNAL */
113    and k1,k0
114    bnez k1,unrecoverable
115     andi k0,0x1fe0
116
117    /*
118     * Since the error is internal, the 'IDX' field from
119     * CacheErr-I is valid and we can just invalidate all blocks
120     * in that set.
121     */
122    cache Index_Invalidate_I,(0<<13)(k0)
123    cache Index_Invalidate_I,(1<<13)(k0)
124    cache Index_Invalidate_I,(2<<13)(k0)
125    cache Index_Invalidate_I,(3<<13)(k0)
126
127    /* Ought to log this recovered icache error */
128
129recovered:
130    /* Restore the saved registers */
131    ld k0,0x170($0)
132    ld k1,0x178($0)
133    eret
134
135unrecoverable:
136    /* Unrecoverable Icache or Dcache error; log it and/or fail */
137    j handle_vec2_sb1
138     nop
139#endif
140
141END(except_vec2_sb1)
142
143    LEAF(handle_vec2_sb1)
144    mfc0 k0,CP0_CONFIG
145    li k1,~CONF_CM_CMASK
146    and k0,k0,k1
147    ori k0,k0,CONF_CM_UNCACHED
148    mtc0 k0,CP0_CONFIG
149
150    SSNOP
151    SSNOP
152    SSNOP
153    SSNOP
154    bnezl $0, 1f
1551:
156    mfc0 k0, CP0_STATUS
157    sll k0, k0, 3 # check CU0 (kernel?)
158    bltz k0, 2f
159     nop
160
161    /* Get a valid Kseg0 stack pointer. Any task's stack pointer
162     * will do, although if we ever want to resume execution we
163     * better not have corrupted any state. */
164    get_saved_sp
165    move sp, k1
166
1672:
168    j sb1_cache_error
169     nop
170
171    END(handle_vec2_sb1)
172

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