Root/arch/mips/mm/uasm-micromips.c

Source at commit 694c7fbe86b8a9c91392e505afcb9fcfc91deccc created 12 years 8 months ago.
By Maarten ter Huurne, MIPS: JZ4740: Add cpufreq support
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/init.h>
19
20#include <asm/inst.h>
21#include <asm/elf.h>
22#include <asm/bugs.h>
23#define UASM_ISA _UASM_ISA_MICROMIPS
24#include <asm/uasm.h>
25
26#define RS_MASK 0x1f
27#define RS_SH 16
28#define RT_MASK 0x1f
29#define RT_SH 21
30#define SCIMM_MASK 0x3ff
31#define SCIMM_SH 16
32
33/* This macro sets the non-variable bits of an instruction. */
34#define M(a, b, c, d, e, f) \
35    ((a) << OP_SH \
36     | (b) << RT_SH \
37     | (c) << RS_SH \
38     | (d) << RD_SH \
39     | (e) << RE_SH \
40     | (f) << FUNC_SH)
41
42/* Define these when we are not the ISA the kernel is being compiled with. */
43#ifndef CONFIG_CPU_MICROMIPS
44#define MM_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off)
45#define MM_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off)
46#define MM_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off)
47#define MM_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off)
48#endif
49
50#include "uasm.c"
51
52static struct insn insn_table_MM[] = {
53    { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
54    { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
55    { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
56    { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
57    { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
58    { insn_beql, 0, 0 },
59    { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
60    { insn_bgezl, 0, 0 },
61    { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
62    { insn_bltzl, 0, 0 },
63    { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
64    { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
65    { insn_daddu, 0, 0 },
66    { insn_daddiu, 0, 0 },
67    { insn_dmfc0, 0, 0 },
68    { insn_dmtc0, 0, 0 },
69    { insn_dsll, 0, 0 },
70    { insn_dsll32, 0, 0 },
71    { insn_dsra, 0, 0 },
72    { insn_dsrl, 0, 0 },
73    { insn_dsrl32, 0, 0 },
74    { insn_drotr, 0, 0 },
75    { insn_drotr32, 0, 0 },
76    { insn_dsubu, 0, 0 },
77    { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 },
78    { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE },
79    { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE },
80    { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM },
81    { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM },
82    { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS },
83    { insn_ld, 0, 0 },
84    { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM },
85    { insn_lld, 0, 0 },
86    { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM },
87    { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
88    { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
89    { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
90    { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
91    { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
92    { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM },
93    { insn_rfe, 0, 0 },
94    { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM },
95    { insn_scd, 0, 0 },
96    { insn_sd, 0, 0 },
97    { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
98    { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
99    { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },
100    { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
101    { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
102    { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
103    { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 },
104    { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },
105    { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },
106    { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },
107    { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },
108    { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
109    { insn_dins, 0, 0 },
110    { insn_dinsm, 0, 0 },
111    { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
112    { insn_bbit0, 0, 0 },
113    { insn_bbit1, 0, 0 },
114    { insn_lwx, 0, 0 },
115    { insn_ldx, 0, 0 },
116    { insn_invalid, 0, 0 }
117};
118
119#undef M
120
121static inline u32 build_bimm(s32 arg)
122{
123    WARN(arg > 0xffff || arg < -0x10000,
124         KERN_WARNING "Micro-assembler field overflow\n");
125
126    WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
127
128    return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff);
129}
130
131static inline u32 build_jimm(u32 arg)
132{
133
134    WARN(arg & ~((JIMM_MASK << 2) | 1),
135         KERN_WARNING "Micro-assembler field overflow\n");
136
137    return (arg >> 1) & JIMM_MASK;
138}
139
140/*
141 * The order of opcode arguments is implicitly left to right,
142 * starting with RS and ending with FUNC or IMM.
143 */
144static void build_insn(u32 **buf, enum opcode opc, ...)
145{
146    struct insn *ip = NULL;
147    unsigned int i;
148    va_list ap;
149    u32 op;
150
151    for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++)
152        if (insn_table_MM[i].opcode == opc) {
153            ip = &insn_table_MM[i];
154            break;
155        }
156
157    if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
158        panic("Unsupported Micro-assembler instruction %d", opc);
159
160    op = ip->match;
161    va_start(ap, opc);
162    if (ip->fields & RS) {
163        if (opc == insn_mfc0 || opc == insn_mtc0)
164            op |= build_rt(va_arg(ap, u32));
165        else
166            op |= build_rs(va_arg(ap, u32));
167    }
168    if (ip->fields & RT) {
169        if (opc == insn_mfc0 || opc == insn_mtc0)
170            op |= build_rs(va_arg(ap, u32));
171        else
172            op |= build_rt(va_arg(ap, u32));
173    }
174    if (ip->fields & RD)
175        op |= build_rd(va_arg(ap, u32));
176    if (ip->fields & RE)
177        op |= build_re(va_arg(ap, u32));
178    if (ip->fields & SIMM)
179        op |= build_simm(va_arg(ap, s32));
180    if (ip->fields & UIMM)
181        op |= build_uimm(va_arg(ap, u32));
182    if (ip->fields & BIMM)
183        op |= build_bimm(va_arg(ap, s32));
184    if (ip->fields & JIMM)
185        op |= build_jimm(va_arg(ap, u32));
186    if (ip->fields & FUNC)
187        op |= build_func(va_arg(ap, u32));
188    if (ip->fields & SET)
189        op |= build_set(va_arg(ap, u32));
190    if (ip->fields & SCIMM)
191        op |= build_scimm(va_arg(ap, u32));
192    va_end(ap);
193
194#ifdef CONFIG_CPU_LITTLE_ENDIAN
195    **buf = ((op & 0xffff) << 16) | (op >> 16);
196#else
197    **buf = op;
198#endif
199    (*buf)++;
200}
201
202static inline void
203__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
204{
205    long laddr = (long)lab->addr;
206    long raddr = (long)rel->addr;
207
208    switch (rel->type) {
209    case R_MIPS_PC16:
210#ifdef CONFIG_CPU_LITTLE_ENDIAN
211        *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16);
212#else
213        *rel->addr |= build_bimm(laddr - (raddr + 4));
214#endif
215        break;
216
217    default:
218        panic("Unsupported Micro-assembler relocation %d",
219              rel->type);
220    }
221}
222

Archive Download this file



interactive