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| Source at commit 694c7fbe86b8a9c91392e505afcb9fcfc91deccc created 12 years 8 months ago. By Maarten ter Huurne, MIPS: JZ4740: Add cpufreq support | |
|---|---|
| 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * A small micro-assembler. It is intentionally kept simple, does only |
| 7 | * support a subset of instructions, and does not try to hide pipeline |
| 8 | * effects like branch delay slots. |
| 9 | * |
| 10 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
| 11 | * Copyright (C) 2005, 2007 Maciej W. Rozycki |
| 12 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
| 13 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/init.h> |
| 19 | |
| 20 | #include <asm/inst.h> |
| 21 | #include <asm/elf.h> |
| 22 | #include <asm/bugs.h> |
| 23 | #define UASM_ISA _UASM_ISA_CLASSIC |
| 24 | #include <asm/uasm.h> |
| 25 | |
| 26 | #define RS_MASK 0x1f |
| 27 | #define RS_SH 21 |
| 28 | #define RT_MASK 0x1f |
| 29 | #define RT_SH 16 |
| 30 | #define SCIMM_MASK 0xfffff |
| 31 | #define SCIMM_SH 6 |
| 32 | |
| 33 | /* This macro sets the non-variable bits of an instruction. */ |
| 34 | #define M(a, b, c, d, e, f) \ |
| 35 | ((a) << OP_SH \ |
| 36 | | (b) << RS_SH \ |
| 37 | | (c) << RT_SH \ |
| 38 | | (d) << RD_SH \ |
| 39 | | (e) << RE_SH \ |
| 40 | | (f) << FUNC_SH) |
| 41 | |
| 42 | /* Define these when we are not the ISA the kernel is being compiled with. */ |
| 43 | #ifdef CONFIG_CPU_MICROMIPS |
| 44 | #define CL_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off) |
| 45 | #define CL_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off) |
| 46 | #define CL_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off) |
| 47 | #define CL_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off) |
| 48 | #endif |
| 49 | |
| 50 | #include "uasm.c" |
| 51 | |
| 52 | static struct insn insn_table[] = { |
| 53 | { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 54 | { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, |
| 55 | { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, |
| 56 | { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, |
| 57 | { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, |
| 58 | { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, |
| 59 | { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, |
| 60 | { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, |
| 61 | { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, |
| 62 | { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, |
| 63 | { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, |
| 64 | { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, |
| 65 | { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, |
| 66 | { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 67 | { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 68 | { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, |
| 69 | { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, |
| 70 | { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, |
| 71 | { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, |
| 72 | { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, |
| 73 | { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, |
| 74 | { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, |
| 75 | { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, |
| 76 | { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, |
| 77 | { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, |
| 78 | { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, |
| 79 | { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, |
| 80 | { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, |
| 81 | { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, |
| 82 | { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE }, |
| 83 | { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, |
| 84 | { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, |
| 85 | { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, |
| 86 | { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, |
| 87 | { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, |
| 88 | { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 89 | { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, |
| 90 | { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 91 | { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 92 | { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, |
| 93 | { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 94 | { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, |
| 95 | { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, |
| 96 | { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, |
| 97 | { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, |
| 98 | { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, |
| 99 | { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 100 | { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, |
| 101 | { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, |
| 102 | { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 103 | { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 104 | { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 105 | { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, |
| 106 | { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, |
| 107 | { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, |
| 108 | { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, |
| 109 | { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 110 | { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, |
| 111 | { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, |
| 112 | { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, |
| 113 | { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, |
| 114 | { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, |
| 115 | { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, |
| 116 | { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, |
| 117 | { insn_invalid, 0, 0 } |
| 118 | }; |
| 119 | |
| 120 | #undef M |
| 121 | |
| 122 | static inline u32 build_bimm(s32 arg) |
| 123 | { |
| 124 | WARN(arg > 0x1ffff || arg < -0x20000, |
| 125 | KERN_WARNING "Micro-assembler field overflow\n"); |
| 126 | |
| 127 | WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); |
| 128 | |
| 129 | return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); |
| 130 | } |
| 131 | |
| 132 | static inline u32 build_jimm(u32 arg) |
| 133 | { |
| 134 | WARN(arg & ~(JIMM_MASK << 2), |
| 135 | KERN_WARNING "Micro-assembler field overflow\n"); |
| 136 | |
| 137 | return (arg >> 2) & JIMM_MASK; |
| 138 | } |
| 139 | |
| 140 | /* |
| 141 | * The order of opcode arguments is implicitly left to right, |
| 142 | * starting with RS and ending with FUNC or IMM. |
| 143 | */ |
| 144 | static void build_insn(u32 **buf, enum opcode opc, ...) |
| 145 | { |
| 146 | struct insn *ip = NULL; |
| 147 | unsigned int i; |
| 148 | va_list ap; |
| 149 | u32 op; |
| 150 | |
| 151 | for (i = 0; insn_table[i].opcode != insn_invalid; i++) |
| 152 | if (insn_table[i].opcode == opc) { |
| 153 | ip = &insn_table[i]; |
| 154 | break; |
| 155 | } |
| 156 | |
| 157 | if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) |
| 158 | panic("Unsupported Micro-assembler instruction %d", opc); |
| 159 | |
| 160 | op = ip->match; |
| 161 | va_start(ap, opc); |
| 162 | if (ip->fields & RS) |
| 163 | op |= build_rs(va_arg(ap, u32)); |
| 164 | if (ip->fields & RT) |
| 165 | op |= build_rt(va_arg(ap, u32)); |
| 166 | if (ip->fields & RD) |
| 167 | op |= build_rd(va_arg(ap, u32)); |
| 168 | if (ip->fields & RE) |
| 169 | op |= build_re(va_arg(ap, u32)); |
| 170 | if (ip->fields & SIMM) |
| 171 | op |= build_simm(va_arg(ap, s32)); |
| 172 | if (ip->fields & UIMM) |
| 173 | op |= build_uimm(va_arg(ap, u32)); |
| 174 | if (ip->fields & BIMM) |
| 175 | op |= build_bimm(va_arg(ap, s32)); |
| 176 | if (ip->fields & JIMM) |
| 177 | op |= build_jimm(va_arg(ap, u32)); |
| 178 | if (ip->fields & FUNC) |
| 179 | op |= build_func(va_arg(ap, u32)); |
| 180 | if (ip->fields & SET) |
| 181 | op |= build_set(va_arg(ap, u32)); |
| 182 | if (ip->fields & SCIMM) |
| 183 | op |= build_scimm(va_arg(ap, u32)); |
| 184 | va_end(ap); |
| 185 | |
| 186 | **buf = op; |
| 187 | (*buf)++; |
| 188 | } |
| 189 | |
| 190 | static inline void |
| 191 | __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) |
| 192 | { |
| 193 | long laddr = (long)lab->addr; |
| 194 | long raddr = (long)rel->addr; |
| 195 | |
| 196 | switch (rel->type) { |
| 197 | case R_MIPS_PC16: |
| 198 | *rel->addr |= build_bimm(laddr - (raddr + 4)); |
| 199 | break; |
| 200 | |
| 201 | default: |
| 202 | panic("Unsupported Micro-assembler relocation %d", |
| 203 | rel->type); |
| 204 | } |
| 205 | } |
| 206 | |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
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jz-3.11
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master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9
