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Source at commit 6c17a31f1fc515425221067cb3ece599c09dbc5d created 12 years 8 months ago. By Werner Almesberger, atusb, atben: moved from spi/ to ieee802154/; renamed atusb to spi_atusb | |
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1 | /* |
2 | * drivers/spi/amba-pl022.c |
3 | * |
4 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
5 | * |
6 | * Copyright (C) 2008-2009 ST-Ericsson AB |
7 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
8 | * |
9 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
10 | * |
11 | * Initial version inspired by: |
12 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c |
13 | * Initial adoption to PL022 by: |
14 | * Sachin Verma <sachin.verma@st.com> |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify |
17 | * it under the terms of the GNU General Public License as published by |
18 | * the Free Software Foundation; either version 2 of the License, or |
19 | * (at your option) any later version. |
20 | * |
21 | * This program is distributed in the hope that it will be useful, |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
24 | * GNU General Public License for more details. |
25 | */ |
26 | |
27 | /* |
28 | * TODO: |
29 | * - add timeout on polled transfers |
30 | */ |
31 | |
32 | #include <linux/init.h> |
33 | #include <linux/module.h> |
34 | #include <linux/device.h> |
35 | #include <linux/ioport.h> |
36 | #include <linux/errno.h> |
37 | #include <linux/interrupt.h> |
38 | #include <linux/spi/spi.h> |
39 | #include <linux/workqueue.h> |
40 | #include <linux/delay.h> |
41 | #include <linux/clk.h> |
42 | #include <linux/err.h> |
43 | #include <linux/amba/bus.h> |
44 | #include <linux/amba/pl022.h> |
45 | #include <linux/io.h> |
46 | #include <linux/slab.h> |
47 | #include <linux/dmaengine.h> |
48 | #include <linux/dma-mapping.h> |
49 | #include <linux/scatterlist.h> |
50 | |
51 | /* |
52 | * This macro is used to define some register default values. |
53 | * reg is masked with mask, the OR:ed with an (again masked) |
54 | * val shifted sb steps to the left. |
55 | */ |
56 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ |
57 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) |
58 | |
59 | /* |
60 | * This macro is also used to define some default values. |
61 | * It will just shift val by sb steps to the left and mask |
62 | * the result with mask. |
63 | */ |
64 | #define GEN_MASK_BITS(val, mask, sb) \ |
65 | (((val)<<(sb)) & (mask)) |
66 | |
67 | #define DRIVE_TX 0 |
68 | #define DO_NOT_DRIVE_TX 1 |
69 | |
70 | #define DO_NOT_QUEUE_DMA 0 |
71 | #define QUEUE_DMA 1 |
72 | |
73 | #define RX_TRANSFER 1 |
74 | #define TX_TRANSFER 2 |
75 | |
76 | /* |
77 | * Macros to access SSP Registers with their offsets |
78 | */ |
79 | #define SSP_CR0(r) (r + 0x000) |
80 | #define SSP_CR1(r) (r + 0x004) |
81 | #define SSP_DR(r) (r + 0x008) |
82 | #define SSP_SR(r) (r + 0x00C) |
83 | #define SSP_CPSR(r) (r + 0x010) |
84 | #define SSP_IMSC(r) (r + 0x014) |
85 | #define SSP_RIS(r) (r + 0x018) |
86 | #define SSP_MIS(r) (r + 0x01C) |
87 | #define SSP_ICR(r) (r + 0x020) |
88 | #define SSP_DMACR(r) (r + 0x024) |
89 | #define SSP_ITCR(r) (r + 0x080) |
90 | #define SSP_ITIP(r) (r + 0x084) |
91 | #define SSP_ITOP(r) (r + 0x088) |
92 | #define SSP_TDR(r) (r + 0x08C) |
93 | |
94 | #define SSP_PID0(r) (r + 0xFE0) |
95 | #define SSP_PID1(r) (r + 0xFE4) |
96 | #define SSP_PID2(r) (r + 0xFE8) |
97 | #define SSP_PID3(r) (r + 0xFEC) |
98 | |
99 | #define SSP_CID0(r) (r + 0xFF0) |
100 | #define SSP_CID1(r) (r + 0xFF4) |
101 | #define SSP_CID2(r) (r + 0xFF8) |
102 | #define SSP_CID3(r) (r + 0xFFC) |
103 | |
104 | /* |
105 | * SSP Control Register 0 - SSP_CR0 |
106 | */ |
107 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
108 | #define SSP_CR0_MASK_FRF (0x3UL << 4) |
109 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
110 | #define SSP_CR0_MASK_SPH (0x1UL << 7) |
111 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) |
112 | |
113 | /* |
114 | * The ST version of this block moves som bits |
115 | * in SSP_CR0 and extends it to 32 bits |
116 | */ |
117 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) |
118 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) |
119 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) |
120 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) |
121 | |
122 | |
123 | /* |
124 | * SSP Control Register 0 - SSP_CR1 |
125 | */ |
126 | #define SSP_CR1_MASK_LBM (0x1UL << 0) |
127 | #define SSP_CR1_MASK_SSE (0x1UL << 1) |
128 | #define SSP_CR1_MASK_MS (0x1UL << 2) |
129 | #define SSP_CR1_MASK_SOD (0x1UL << 3) |
130 | |
131 | /* |
132 | * The ST version of this block adds some bits |
133 | * in SSP_CR1 |
134 | */ |
135 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
136 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) |
137 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) |
138 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) |
139 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) |
140 | /* This one is only in the PL023 variant */ |
141 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) |
142 | |
143 | /* |
144 | * SSP Status Register - SSP_SR |
145 | */ |
146 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ |
147 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ |
148 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ |
149 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
150 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
151 | |
152 | /* |
153 | * SSP Clock Prescale Register - SSP_CPSR |
154 | */ |
155 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) |
156 | |
157 | /* |
158 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC |
159 | */ |
160 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ |
161 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ |
162 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ |
163 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ |
164 | |
165 | /* |
166 | * SSP Raw Interrupt Status Register - SSP_RIS |
167 | */ |
168 | /* Receive Overrun Raw Interrupt status */ |
169 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) |
170 | /* Receive Timeout Raw Interrupt status */ |
171 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) |
172 | /* Receive FIFO Raw Interrupt status */ |
173 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) |
174 | /* Transmit FIFO Raw Interrupt status */ |
175 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) |
176 | |
177 | /* |
178 | * SSP Masked Interrupt Status Register - SSP_MIS |
179 | */ |
180 | /* Receive Overrun Masked Interrupt status */ |
181 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) |
182 | /* Receive Timeout Masked Interrupt status */ |
183 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) |
184 | /* Receive FIFO Masked Interrupt status */ |
185 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) |
186 | /* Transmit FIFO Masked Interrupt status */ |
187 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) |
188 | |
189 | /* |
190 | * SSP Interrupt Clear Register - SSP_ICR |
191 | */ |
192 | /* Receive Overrun Raw Clear Interrupt bit */ |
193 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) |
194 | /* Receive Timeout Clear Interrupt bit */ |
195 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) |
196 | |
197 | /* |
198 | * SSP DMA Control Register - SSP_DMACR |
199 | */ |
200 | /* Receive DMA Enable bit */ |
201 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) |
202 | /* Transmit DMA Enable bit */ |
203 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) |
204 | |
205 | /* |
206 | * SSP Integration Test control Register - SSP_ITCR |
207 | */ |
208 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) |
209 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) |
210 | |
211 | /* |
212 | * SSP Integration Test Input Register - SSP_ITIP |
213 | */ |
214 | #define ITIP_MASK_SSPRXD (0x1UL << 0) |
215 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) |
216 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) |
217 | #define ITIP_MASK_RXDMAC (0x1UL << 3) |
218 | #define ITIP_MASK_TXDMAC (0x1UL << 4) |
219 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) |
220 | |
221 | /* |
222 | * SSP Integration Test output Register - SSP_ITOP |
223 | */ |
224 | #define ITOP_MASK_SSPTXD (0x1UL << 0) |
225 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) |
226 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) |
227 | #define ITOP_MASK_SSPOEn (0x1UL << 3) |
228 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) |
229 | #define ITOP_MASK_RORINTR (0x1UL << 5) |
230 | #define ITOP_MASK_RTINTR (0x1UL << 6) |
231 | #define ITOP_MASK_RXINTR (0x1UL << 7) |
232 | #define ITOP_MASK_TXINTR (0x1UL << 8) |
233 | #define ITOP_MASK_INTR (0x1UL << 9) |
234 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) |
235 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) |
236 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) |
237 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) |
238 | |
239 | /* |
240 | * SSP Test Data Register - SSP_TDR |
241 | */ |
242 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
243 | |
244 | /* |
245 | * Message State |
246 | * we use the spi_message.state (void *) pointer to |
247 | * hold a single state value, that's why all this |
248 | * (void *) casting is done here. |
249 | */ |
250 | #define STATE_START ((void *) 0) |
251 | #define STATE_RUNNING ((void *) 1) |
252 | #define STATE_DONE ((void *) 2) |
253 | #define STATE_ERROR ((void *) -1) |
254 | |
255 | /* |
256 | * SSP State - Whether Enabled or Disabled |
257 | */ |
258 | #define SSP_DISABLED (0) |
259 | #define SSP_ENABLED (1) |
260 | |
261 | /* |
262 | * SSP DMA State - Whether DMA Enabled or Disabled |
263 | */ |
264 | #define SSP_DMA_DISABLED (0) |
265 | #define SSP_DMA_ENABLED (1) |
266 | |
267 | /* |
268 | * SSP Clock Defaults |
269 | */ |
270 | #define SSP_DEFAULT_CLKRATE 0x2 |
271 | #define SSP_DEFAULT_PRESCALE 0x40 |
272 | |
273 | /* |
274 | * SSP Clock Parameter ranges |
275 | */ |
276 | #define CPSDVR_MIN 0x02 |
277 | #define CPSDVR_MAX 0xFE |
278 | #define SCR_MIN 0x00 |
279 | #define SCR_MAX 0xFF |
280 | |
281 | /* |
282 | * SSP Interrupt related Macros |
283 | */ |
284 | #define DEFAULT_SSP_REG_IMSC 0x0UL |
285 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC |
286 | #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) |
287 | |
288 | #define CLEAR_ALL_INTERRUPTS 0x3 |
289 | |
290 | |
291 | /* |
292 | * The type of reading going on on this chip |
293 | */ |
294 | enum ssp_reading { |
295 | READING_NULL, |
296 | READING_U8, |
297 | READING_U16, |
298 | READING_U32 |
299 | }; |
300 | |
301 | /** |
302 | * The type of writing going on on this chip |
303 | */ |
304 | enum ssp_writing { |
305 | WRITING_NULL, |
306 | WRITING_U8, |
307 | WRITING_U16, |
308 | WRITING_U32 |
309 | }; |
310 | |
311 | /** |
312 | * struct vendor_data - vendor-specific config parameters |
313 | * for PL022 derivates |
314 | * @fifodepth: depth of FIFOs (both) |
315 | * @max_bpw: maximum number of bits per word |
316 | * @unidir: supports unidirection transfers |
317 | * @extended_cr: 32 bit wide control register 0 with extra |
318 | * features and extra features in CR1 as found in the ST variants |
319 | * @pl023: supports a subset of the ST extensions called "PL023" |
320 | */ |
321 | struct vendor_data { |
322 | int fifodepth; |
323 | int max_bpw; |
324 | bool unidir; |
325 | bool extended_cr; |
326 | bool pl023; |
327 | }; |
328 | |
329 | /** |
330 | * struct pl022 - This is the private SSP driver data structure |
331 | * @adev: AMBA device model hookup |
332 | * @vendor: Vendor data for the IP block |
333 | * @phybase: The physical memory where the SSP device resides |
334 | * @virtbase: The virtual memory where the SSP is mapped |
335 | * @master: SPI framework hookup |
336 | * @master_info: controller-specific data from machine setup |
337 | * @regs: SSP controller register's virtual address |
338 | * @pump_messages: Work struct for scheduling work to the workqueue |
339 | * @lock: spinlock to syncronise access to driver data |
340 | * @workqueue: a workqueue on which any spi_message request is queued |
341 | * @busy: workqueue is busy |
342 | * @running: workqueue is running |
343 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
344 | * @cur_msg: Pointer to current spi_message being processed |
345 | * @cur_transfer: Pointer to current spi_transfer |
346 | * @cur_chip: pointer to current clients chip(assigned from controller_state) |
347 | * @tx: current position in TX buffer to be read |
348 | * @tx_end: end position in TX buffer to be read |
349 | * @rx: current position in RX buffer to be written |
350 | * @rx_end: end position in RX buffer to be written |
351 | * @readingtype: the type of read currently going on |
352 | * @writingtype: the type or write currently going on |
353 | */ |
354 | struct pl022 { |
355 | struct amba_device *adev; |
356 | struct vendor_data *vendor; |
357 | resource_size_t phybase; |
358 | void __iomem *virtbase; |
359 | struct clk *clk; |
360 | struct spi_master *master; |
361 | struct pl022_ssp_controller *master_info; |
362 | /* Driver message queue */ |
363 | struct workqueue_struct *workqueue; |
364 | struct work_struct pump_messages; |
365 | spinlock_t queue_lock; |
366 | struct list_head queue; |
367 | bool busy; |
368 | bool running; |
369 | /* Message transfer pump */ |
370 | struct tasklet_struct pump_transfers; |
371 | struct spi_message *cur_msg; |
372 | struct spi_transfer *cur_transfer; |
373 | struct chip_data *cur_chip; |
374 | void *tx; |
375 | void *tx_end; |
376 | void *rx; |
377 | void *rx_end; |
378 | enum ssp_reading read; |
379 | enum ssp_writing write; |
380 | u32 exp_fifo_level; |
381 | /* DMA settings */ |
382 | #ifdef CONFIG_DMA_ENGINE |
383 | struct dma_chan *dma_rx_channel; |
384 | struct dma_chan *dma_tx_channel; |
385 | struct sg_table sgt_rx; |
386 | struct sg_table sgt_tx; |
387 | char *dummypage; |
388 | #endif |
389 | }; |
390 | |
391 | /** |
392 | * struct chip_data - To maintain runtime state of SSP for each client chip |
393 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
394 | * register is 32 bits wide rather than just 16 |
395 | * @cr1: Value of control register CR1 of SSP |
396 | * @dmacr: Value of DMA control Register of SSP |
397 | * @cpsr: Value of Clock prescale register |
398 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client |
399 | * @enable_dma: Whether to enable DMA or not |
400 | * @write: function ptr to be used to write when doing xfer for this chip |
401 | * @read: function ptr to be used to read when doing xfer for this chip |
402 | * @cs_control: chip select callback provided by chip |
403 | * @xfer_type: polling/interrupt/DMA |
404 | * |
405 | * Runtime state of the SSP controller, maintained per chip, |
406 | * This would be set according to the current message that would be served |
407 | */ |
408 | struct chip_data { |
409 | u32 cr0; |
410 | u16 cr1; |
411 | u16 dmacr; |
412 | u16 cpsr; |
413 | u8 n_bytes; |
414 | bool enable_dma; |
415 | enum ssp_reading read; |
416 | enum ssp_writing write; |
417 | void (*cs_control) (u32 command); |
418 | int xfer_type; |
419 | }; |
420 | |
421 | /** |
422 | * null_cs_control - Dummy chip select function |
423 | * @command: select/delect the chip |
424 | * |
425 | * If no chip select function is provided by client this is used as dummy |
426 | * chip select |
427 | */ |
428 | static void null_cs_control(u32 command) |
429 | { |
430 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); |
431 | } |
432 | |
433 | /** |
434 | * giveback - current spi_message is over, schedule next message and call |
435 | * callback of this message. Assumes that caller already |
436 | * set message->status; dma and pio irqs are blocked |
437 | * @pl022: SSP driver private data structure |
438 | */ |
439 | static void giveback(struct pl022 *pl022) |
440 | { |
441 | struct spi_transfer *last_transfer; |
442 | unsigned long flags; |
443 | struct spi_message *msg; |
444 | void (*curr_cs_control) (u32 command); |
445 | |
446 | /* |
447 | * This local reference to the chip select function |
448 | * is needed because we set curr_chip to NULL |
449 | * as a step toward termininating the message. |
450 | */ |
451 | curr_cs_control = pl022->cur_chip->cs_control; |
452 | spin_lock_irqsave(&pl022->queue_lock, flags); |
453 | msg = pl022->cur_msg; |
454 | pl022->cur_msg = NULL; |
455 | pl022->cur_transfer = NULL; |
456 | pl022->cur_chip = NULL; |
457 | queue_work(pl022->workqueue, &pl022->pump_messages); |
458 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
459 | |
460 | last_transfer = list_entry(msg->transfers.prev, |
461 | struct spi_transfer, |
462 | transfer_list); |
463 | |
464 | /* Delay if requested before any change in chip select */ |
465 | if (last_transfer->delay_usecs) |
466 | /* |
467 | * FIXME: This runs in interrupt context. |
468 | * Is this really smart? |
469 | */ |
470 | udelay(last_transfer->delay_usecs); |
471 | |
472 | /* |
473 | * Drop chip select UNLESS cs_change is true or we are returning |
474 | * a message with an error, or next message is for another chip |
475 | */ |
476 | if (!last_transfer->cs_change) |
477 | curr_cs_control(SSP_CHIP_DESELECT); |
478 | else { |
479 | struct spi_message *next_msg; |
480 | |
481 | /* Holding of cs was hinted, but we need to make sure |
482 | * the next message is for the same chip. Don't waste |
483 | * time with the following tests unless this was hinted. |
484 | * |
485 | * We cannot postpone this until pump_messages, because |
486 | * after calling msg->complete (below) the driver that |
487 | * sent the current message could be unloaded, which |
488 | * could invalidate the cs_control() callback... |
489 | */ |
490 | |
491 | /* get a pointer to the next message, if any */ |
492 | spin_lock_irqsave(&pl022->queue_lock, flags); |
493 | if (list_empty(&pl022->queue)) |
494 | next_msg = NULL; |
495 | else |
496 | next_msg = list_entry(pl022->queue.next, |
497 | struct spi_message, queue); |
498 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
499 | |
500 | /* see if the next and current messages point |
501 | * to the same chip |
502 | */ |
503 | if (next_msg && next_msg->spi != msg->spi) |
504 | next_msg = NULL; |
505 | if (!next_msg || msg->state == STATE_ERROR) |
506 | curr_cs_control(SSP_CHIP_DESELECT); |
507 | } |
508 | msg->state = NULL; |
509 | if (msg->complete) |
510 | msg->complete(msg->context); |
511 | /* This message is completed, so let's turn off the clocks! */ |
512 | clk_disable(pl022->clk); |
513 | amba_pclk_disable(pl022->adev); |
514 | } |
515 | |
516 | /** |
517 | * flush - flush the FIFO to reach a clean state |
518 | * @pl022: SSP driver private data structure |
519 | */ |
520 | static int flush(struct pl022 *pl022) |
521 | { |
522 | unsigned long limit = loops_per_jiffy << 1; |
523 | |
524 | dev_dbg(&pl022->adev->dev, "flush\n"); |
525 | do { |
526 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
527 | readw(SSP_DR(pl022->virtbase)); |
528 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); |
529 | |
530 | pl022->exp_fifo_level = 0; |
531 | |
532 | return limit; |
533 | } |
534 | |
535 | /** |
536 | * restore_state - Load configuration of current chip |
537 | * @pl022: SSP driver private data structure |
538 | */ |
539 | static void restore_state(struct pl022 *pl022) |
540 | { |
541 | struct chip_data *chip = pl022->cur_chip; |
542 | |
543 | if (pl022->vendor->extended_cr) |
544 | writel(chip->cr0, SSP_CR0(pl022->virtbase)); |
545 | else |
546 | writew(chip->cr0, SSP_CR0(pl022->virtbase)); |
547 | writew(chip->cr1, SSP_CR1(pl022->virtbase)); |
548 | writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); |
549 | writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); |
550 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
551 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
552 | } |
553 | |
554 | /* |
555 | * Default SSP Register Values |
556 | */ |
557 | #define DEFAULT_SSP_REG_CR0 ( \ |
558 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ |
559 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
560 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
561 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
562 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ |
563 | ) |
564 | |
565 | /* ST versions have slightly different bit layout */ |
566 | #define DEFAULT_SSP_REG_CR0_ST ( \ |
567 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ |
568 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ |
569 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
570 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
571 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
572 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ |
573 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ |
574 | ) |
575 | |
576 | /* The PL023 version is slightly different again */ |
577 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ |
578 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ |
579 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
580 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
581 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ |
582 | ) |
583 | |
584 | #define DEFAULT_SSP_REG_CR1 ( \ |
585 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ |
586 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ |
587 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ |
588 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
589 | ) |
590 | |
591 | /* ST versions extend this register to use all 16 bits */ |
592 | #define DEFAULT_SSP_REG_CR1_ST ( \ |
593 | DEFAULT_SSP_REG_CR1 | \ |
594 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ |
595 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ |
596 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ |
597 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ |
598 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ |
599 | ) |
600 | |
601 | /* |
602 | * The PL023 variant has further differences: no loopback mode, no microwire |
603 | * support, and a new clock feedback delay setting. |
604 | */ |
605 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ |
606 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ |
607 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ |
608 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ |
609 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ |
610 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ |
611 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ |
612 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ |
613 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ |
614 | ) |
615 | |
616 | #define DEFAULT_SSP_REG_CPSR ( \ |
617 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
618 | ) |
619 | |
620 | #define DEFAULT_SSP_REG_DMACR (\ |
621 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ |
622 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ |
623 | ) |
624 | |
625 | /** |
626 | * load_ssp_default_config - Load default configuration for SSP |
627 | * @pl022: SSP driver private data structure |
628 | */ |
629 | static void load_ssp_default_config(struct pl022 *pl022) |
630 | { |
631 | if (pl022->vendor->pl023) { |
632 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); |
633 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); |
634 | } else if (pl022->vendor->extended_cr) { |
635 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
636 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); |
637 | } else { |
638 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); |
639 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); |
640 | } |
641 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
642 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); |
643 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
644 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
645 | } |
646 | |
647 | /** |
648 | * This will write to TX and read from RX according to the parameters |
649 | * set in pl022. |
650 | */ |
651 | static void readwriter(struct pl022 *pl022) |
652 | { |
653 | |
654 | /* |
655 | * The FIFO depth is different inbetween primecell variants. |
656 | * I believe filling in too much in the FIFO might cause |
657 | * errons in 8bit wide transfers on ARM variants (just 8 words |
658 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. |
659 | * |
660 | * To prevent this issue, the TX FIFO is only filled to the |
661 | * unused RX FIFO fill length, regardless of what the TX |
662 | * FIFO status flag indicates. |
663 | */ |
664 | dev_dbg(&pl022->adev->dev, |
665 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", |
666 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); |
667 | |
668 | /* Read as much as you can */ |
669 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
670 | && (pl022->rx < pl022->rx_end)) { |
671 | switch (pl022->read) { |
672 | case READING_NULL: |
673 | readw(SSP_DR(pl022->virtbase)); |
674 | break; |
675 | case READING_U8: |
676 | *(u8 *) (pl022->rx) = |
677 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; |
678 | break; |
679 | case READING_U16: |
680 | *(u16 *) (pl022->rx) = |
681 | (u16) readw(SSP_DR(pl022->virtbase)); |
682 | break; |
683 | case READING_U32: |
684 | *(u32 *) (pl022->rx) = |
685 | readl(SSP_DR(pl022->virtbase)); |
686 | break; |
687 | } |
688 | pl022->rx += (pl022->cur_chip->n_bytes); |
689 | pl022->exp_fifo_level--; |
690 | } |
691 | /* |
692 | * Write as much as possible up to the RX FIFO size |
693 | */ |
694 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
695 | && (pl022->tx < pl022->tx_end)) { |
696 | switch (pl022->write) { |
697 | case WRITING_NULL: |
698 | writew(0x0, SSP_DR(pl022->virtbase)); |
699 | break; |
700 | case WRITING_U8: |
701 | writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); |
702 | break; |
703 | case WRITING_U16: |
704 | writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); |
705 | break; |
706 | case WRITING_U32: |
707 | writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); |
708 | break; |
709 | } |
710 | pl022->tx += (pl022->cur_chip->n_bytes); |
711 | pl022->exp_fifo_level++; |
712 | /* |
713 | * This inner reader takes care of things appearing in the RX |
714 | * FIFO as we're transmitting. This will happen a lot since the |
715 | * clock starts running when you put things into the TX FIFO, |
716 | * and then things are continously clocked into the RX FIFO. |
717 | */ |
718 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
719 | && (pl022->rx < pl022->rx_end)) { |
720 | switch (pl022->read) { |
721 | case READING_NULL: |
722 | readw(SSP_DR(pl022->virtbase)); |
723 | break; |
724 | case READING_U8: |
725 | *(u8 *) (pl022->rx) = |
726 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; |
727 | break; |
728 | case READING_U16: |
729 | *(u16 *) (pl022->rx) = |
730 | (u16) readw(SSP_DR(pl022->virtbase)); |
731 | break; |
732 | case READING_U32: |
733 | *(u32 *) (pl022->rx) = |
734 | readl(SSP_DR(pl022->virtbase)); |
735 | break; |
736 | } |
737 | pl022->rx += (pl022->cur_chip->n_bytes); |
738 | pl022->exp_fifo_level--; |
739 | } |
740 | } |
741 | /* |
742 | * When we exit here the TX FIFO should be full and the RX FIFO |
743 | * should be empty |
744 | */ |
745 | } |
746 | |
747 | |
748 | /** |
749 | * next_transfer - Move to the Next transfer in the current spi message |
750 | * @pl022: SSP driver private data structure |
751 | * |
752 | * This function moves though the linked list of spi transfers in the |
753 | * current spi message and returns with the state of current spi |
754 | * message i.e whether its last transfer is done(STATE_DONE) or |
755 | * Next transfer is ready(STATE_RUNNING) |
756 | */ |
757 | static void *next_transfer(struct pl022 *pl022) |
758 | { |
759 | struct spi_message *msg = pl022->cur_msg; |
760 | struct spi_transfer *trans = pl022->cur_transfer; |
761 | |
762 | /* Move to next transfer */ |
763 | if (trans->transfer_list.next != &msg->transfers) { |
764 | pl022->cur_transfer = |
765 | list_entry(trans->transfer_list.next, |
766 | struct spi_transfer, transfer_list); |
767 | return STATE_RUNNING; |
768 | } |
769 | return STATE_DONE; |
770 | } |
771 | |
772 | /* |
773 | * This DMA functionality is only compiled in if we have |
774 | * access to the generic DMA devices/DMA engine. |
775 | */ |
776 | #ifdef CONFIG_DMA_ENGINE |
777 | static void unmap_free_dma_scatter(struct pl022 *pl022) |
778 | { |
779 | /* Unmap and free the SG tables */ |
780 | dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, |
781 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
782 | dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, |
783 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
784 | sg_free_table(&pl022->sgt_rx); |
785 | sg_free_table(&pl022->sgt_tx); |
786 | } |
787 | |
788 | static void dma_callback(void *data) |
789 | { |
790 | struct pl022 *pl022 = data; |
791 | struct spi_message *msg = pl022->cur_msg; |
792 | |
793 | BUG_ON(!pl022->sgt_rx.sgl); |
794 | |
795 | #ifdef VERBOSE_DEBUG |
796 | /* |
797 | * Optionally dump out buffers to inspect contents, this is |
798 | * good if you want to convince yourself that the loopback |
799 | * read/write contents are the same, when adopting to a new |
800 | * DMA engine. |
801 | */ |
802 | { |
803 | struct scatterlist *sg; |
804 | unsigned int i; |
805 | |
806 | dma_sync_sg_for_cpu(&pl022->adev->dev, |
807 | pl022->sgt_rx.sgl, |
808 | pl022->sgt_rx.nents, |
809 | DMA_FROM_DEVICE); |
810 | |
811 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { |
812 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); |
813 | print_hex_dump(KERN_ERR, "SPI RX: ", |
814 | DUMP_PREFIX_OFFSET, |
815 | 16, |
816 | 1, |
817 | sg_virt(sg), |
818 | sg_dma_len(sg), |
819 | 1); |
820 | } |
821 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { |
822 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); |
823 | print_hex_dump(KERN_ERR, "SPI TX: ", |
824 | DUMP_PREFIX_OFFSET, |
825 | 16, |
826 | 1, |
827 | sg_virt(sg), |
828 | sg_dma_len(sg), |
829 | 1); |
830 | } |
831 | } |
832 | #endif |
833 | |
834 | unmap_free_dma_scatter(pl022); |
835 | |
836 | /* Update total bytes transfered */ |
837 | msg->actual_length += pl022->cur_transfer->len; |
838 | if (pl022->cur_transfer->cs_change) |
839 | pl022->cur_chip-> |
840 | cs_control(SSP_CHIP_DESELECT); |
841 | |
842 | /* Move to next transfer */ |
843 | msg->state = next_transfer(pl022); |
844 | tasklet_schedule(&pl022->pump_transfers); |
845 | } |
846 | |
847 | static void setup_dma_scatter(struct pl022 *pl022, |
848 | void *buffer, |
849 | unsigned int length, |
850 | struct sg_table *sgtab) |
851 | { |
852 | struct scatterlist *sg; |
853 | int bytesleft = length; |
854 | void *bufp = buffer; |
855 | int mapbytes; |
856 | int i; |
857 | |
858 | if (buffer) { |
859 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
860 | /* |
861 | * If there are less bytes left than what fits |
862 | * in the current page (plus page alignment offset) |
863 | * we just feed in this, else we stuff in as much |
864 | * as we can. |
865 | */ |
866 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) |
867 | mapbytes = bytesleft; |
868 | else |
869 | mapbytes = PAGE_SIZE - offset_in_page(bufp); |
870 | sg_set_page(sg, virt_to_page(bufp), |
871 | mapbytes, offset_in_page(bufp)); |
872 | bufp += mapbytes; |
873 | bytesleft -= mapbytes; |
874 | dev_dbg(&pl022->adev->dev, |
875 | "set RX/TX target page @ %p, %d bytes, %d left\n", |
876 | bufp, mapbytes, bytesleft); |
877 | } |
878 | } else { |
879 | /* Map the dummy buffer on every page */ |
880 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
881 | if (bytesleft < PAGE_SIZE) |
882 | mapbytes = bytesleft; |
883 | else |
884 | mapbytes = PAGE_SIZE; |
885 | sg_set_page(sg, virt_to_page(pl022->dummypage), |
886 | mapbytes, 0); |
887 | bytesleft -= mapbytes; |
888 | dev_dbg(&pl022->adev->dev, |
889 | "set RX/TX to dummy page %d bytes, %d left\n", |
890 | mapbytes, bytesleft); |
891 | |
892 | } |
893 | } |
894 | BUG_ON(bytesleft); |
895 | } |
896 | |
897 | /** |
898 | * configure_dma - configures the channels for the next transfer |
899 | * @pl022: SSP driver's private data structure |
900 | */ |
901 | static int configure_dma(struct pl022 *pl022) |
902 | { |
903 | struct dma_slave_config rx_conf = { |
904 | .src_addr = SSP_DR(pl022->phybase), |
905 | .direction = DMA_FROM_DEVICE, |
906 | .src_maxburst = pl022->vendor->fifodepth >> 1, |
907 | }; |
908 | struct dma_slave_config tx_conf = { |
909 | .dst_addr = SSP_DR(pl022->phybase), |
910 | .direction = DMA_TO_DEVICE, |
911 | .dst_maxburst = pl022->vendor->fifodepth >> 1, |
912 | }; |
913 | unsigned int pages; |
914 | int ret; |
915 | int rx_sglen, tx_sglen; |
916 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
917 | struct dma_chan *txchan = pl022->dma_tx_channel; |
918 | struct dma_async_tx_descriptor *rxdesc; |
919 | struct dma_async_tx_descriptor *txdesc; |
920 | dma_cookie_t cookie; |
921 | |
922 | /* Check that the channels are available */ |
923 | if (!rxchan || !txchan) |
924 | return -ENODEV; |
925 | |
926 | switch (pl022->read) { |
927 | case READING_NULL: |
928 | /* Use the same as for writing */ |
929 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
930 | break; |
931 | case READING_U8: |
932 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
933 | break; |
934 | case READING_U16: |
935 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
936 | break; |
937 | case READING_U32: |
938 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
939 | break; |
940 | } |
941 | |
942 | switch (pl022->write) { |
943 | case WRITING_NULL: |
944 | /* Use the same as for reading */ |
945 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
946 | break; |
947 | case WRITING_U8: |
948 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
949 | break; |
950 | case WRITING_U16: |
951 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
952 | break; |
953 | case WRITING_U32: |
954 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
955 | break; |
956 | } |
957 | |
958 | /* SPI pecularity: we need to read and write the same width */ |
959 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
960 | rx_conf.src_addr_width = tx_conf.dst_addr_width; |
961 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
962 | tx_conf.dst_addr_width = rx_conf.src_addr_width; |
963 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); |
964 | |
965 | rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG, |
966 | (unsigned long) &rx_conf); |
967 | txchan->device->device_control(txchan, DMA_SLAVE_CONFIG, |
968 | (unsigned long) &tx_conf); |
969 | |
970 | /* Create sglists for the transfers */ |
971 | pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1; |
972 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); |
973 | |
974 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL); |
975 | if (ret) |
976 | goto err_alloc_rx_sg; |
977 | |
978 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL); |
979 | if (ret) |
980 | goto err_alloc_tx_sg; |
981 | |
982 | /* Fill in the scatterlists for the RX+TX buffers */ |
983 | setup_dma_scatter(pl022, pl022->rx, |
984 | pl022->cur_transfer->len, &pl022->sgt_rx); |
985 | setup_dma_scatter(pl022, pl022->tx, |
986 | pl022->cur_transfer->len, &pl022->sgt_tx); |
987 | |
988 | /* Map DMA buffers */ |
989 | rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
990 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
991 | if (!rx_sglen) |
992 | goto err_rx_sgmap; |
993 | |
994 | tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
995 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
996 | if (!tx_sglen) |
997 | goto err_tx_sgmap; |
998 | |
999 | /* Send both scatterlists */ |
1000 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, |
1001 | pl022->sgt_rx.sgl, |
1002 | rx_sglen, |
1003 | DMA_FROM_DEVICE, |
1004 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1005 | if (!rxdesc) |
1006 | goto err_rxdesc; |
1007 | |
1008 | txdesc = txchan->device->device_prep_slave_sg(txchan, |
1009 | pl022->sgt_tx.sgl, |
1010 | tx_sglen, |
1011 | DMA_TO_DEVICE, |
1012 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1013 | if (!txdesc) |
1014 | goto err_txdesc; |
1015 | |
1016 | /* Put the callback on the RX transfer only, that should finish last */ |
1017 | rxdesc->callback = dma_callback; |
1018 | rxdesc->callback_param = pl022; |
1019 | |
1020 | /* Submit and fire RX and TX with TX last so we're ready to read! */ |
1021 | cookie = rxdesc->tx_submit(rxdesc); |
1022 | if (dma_submit_error(cookie)) |
1023 | goto err_submit_rx; |
1024 | cookie = txdesc->tx_submit(txdesc); |
1025 | if (dma_submit_error(cookie)) |
1026 | goto err_submit_tx; |
1027 | rxchan->device->device_issue_pending(rxchan); |
1028 | txchan->device->device_issue_pending(txchan); |
1029 | |
1030 | return 0; |
1031 | |
1032 | err_submit_tx: |
1033 | err_submit_rx: |
1034 | err_txdesc: |
1035 | txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0); |
1036 | err_rxdesc: |
1037 | rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0); |
1038 | dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
1039 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
1040 | err_tx_sgmap: |
1041 | dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
1042 | pl022->sgt_tx.nents, DMA_FROM_DEVICE); |
1043 | err_rx_sgmap: |
1044 | sg_free_table(&pl022->sgt_tx); |
1045 | err_alloc_tx_sg: |
1046 | sg_free_table(&pl022->sgt_rx); |
1047 | err_alloc_rx_sg: |
1048 | return -ENOMEM; |
1049 | } |
1050 | |
1051 | static int __init pl022_dma_probe(struct pl022 *pl022) |
1052 | { |
1053 | dma_cap_mask_t mask; |
1054 | |
1055 | /* Try to acquire a generic DMA engine slave channel */ |
1056 | dma_cap_zero(mask); |
1057 | dma_cap_set(DMA_SLAVE, mask); |
1058 | /* |
1059 | * We need both RX and TX channels to do DMA, else do none |
1060 | * of them. |
1061 | */ |
1062 | pl022->dma_rx_channel = dma_request_channel(mask, |
1063 | pl022->master_info->dma_filter, |
1064 | pl022->master_info->dma_rx_param); |
1065 | if (!pl022->dma_rx_channel) { |
1066 | dev_err(&pl022->adev->dev, "no RX DMA channel!\n"); |
1067 | goto err_no_rxchan; |
1068 | } |
1069 | |
1070 | pl022->dma_tx_channel = dma_request_channel(mask, |
1071 | pl022->master_info->dma_filter, |
1072 | pl022->master_info->dma_tx_param); |
1073 | if (!pl022->dma_tx_channel) { |
1074 | dev_err(&pl022->adev->dev, "no TX DMA channel!\n"); |
1075 | goto err_no_txchan; |
1076 | } |
1077 | |
1078 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); |
1079 | if (!pl022->dummypage) { |
1080 | dev_err(&pl022->adev->dev, "no DMA dummypage!\n"); |
1081 | goto err_no_dummypage; |
1082 | } |
1083 | |
1084 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", |
1085 | dma_chan_name(pl022->dma_rx_channel), |
1086 | dma_chan_name(pl022->dma_tx_channel)); |
1087 | |
1088 | return 0; |
1089 | |
1090 | err_no_dummypage: |
1091 | dma_release_channel(pl022->dma_tx_channel); |
1092 | err_no_txchan: |
1093 | dma_release_channel(pl022->dma_rx_channel); |
1094 | pl022->dma_rx_channel = NULL; |
1095 | err_no_rxchan: |
1096 | return -ENODEV; |
1097 | } |
1098 | |
1099 | static void terminate_dma(struct pl022 *pl022) |
1100 | { |
1101 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
1102 | struct dma_chan *txchan = pl022->dma_tx_channel; |
1103 | |
1104 | rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0); |
1105 | txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0); |
1106 | unmap_free_dma_scatter(pl022); |
1107 | } |
1108 | |
1109 | static void pl022_dma_remove(struct pl022 *pl022) |
1110 | { |
1111 | if (pl022->busy) |
1112 | terminate_dma(pl022); |
1113 | if (pl022->dma_tx_channel) |
1114 | dma_release_channel(pl022->dma_tx_channel); |
1115 | if (pl022->dma_rx_channel) |
1116 | dma_release_channel(pl022->dma_rx_channel); |
1117 | kfree(pl022->dummypage); |
1118 | } |
1119 | |
1120 | #else |
1121 | static inline int configure_dma(struct pl022 *pl022) |
1122 | { |
1123 | return -ENODEV; |
1124 | } |
1125 | |
1126 | static inline int pl022_dma_probe(struct pl022 *pl022) |
1127 | { |
1128 | return 0; |
1129 | } |
1130 | |
1131 | static inline void pl022_dma_remove(struct pl022 *pl022) |
1132 | { |
1133 | } |
1134 | #endif |
1135 | |
1136 | /** |
1137 | * pl022_interrupt_handler - Interrupt handler for SSP controller |
1138 | * |
1139 | * This function handles interrupts generated for an interrupt based transfer. |
1140 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the |
1141 | * current message's state as STATE_ERROR and schedule the tasklet |
1142 | * pump_transfers which will do the postprocessing of the current message by |
1143 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no |
1144 | * more data, and writes data in TX FIFO till it is not full. If we complete |
1145 | * the transfer we move to the next transfer and schedule the tasklet. |
1146 | */ |
1147 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) |
1148 | { |
1149 | struct pl022 *pl022 = dev_id; |
1150 | struct spi_message *msg = pl022->cur_msg; |
1151 | u16 irq_status = 0; |
1152 | u16 flag = 0; |
1153 | |
1154 | if (unlikely(!msg)) { |
1155 | dev_err(&pl022->adev->dev, |
1156 | "bad message state in interrupt handler"); |
1157 | /* Never fail */ |
1158 | return IRQ_HANDLED; |
1159 | } |
1160 | |
1161 | /* Read the Interrupt Status Register */ |
1162 | irq_status = readw(SSP_MIS(pl022->virtbase)); |
1163 | |
1164 | if (unlikely(!irq_status)) |
1165 | return IRQ_NONE; |
1166 | |
1167 | /* |
1168 | * This handles the FIFO interrupts, the timeout |
1169 | * interrupts are flatly ignored, they cannot be |
1170 | * trusted. |
1171 | */ |
1172 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
1173 | /* |
1174 | * Overrun interrupt - bail out since our Data has been |
1175 | * corrupted |
1176 | */ |
1177 | dev_err(&pl022->adev->dev, "FIFO overrun\n"); |
1178 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
1179 | dev_err(&pl022->adev->dev, |
1180 | "RXFIFO is full\n"); |
1181 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) |
1182 | dev_err(&pl022->adev->dev, |
1183 | "TXFIFO is full\n"); |
1184 | |
1185 | /* |
1186 | * Disable and clear interrupts, disable SSP, |
1187 | * mark message with bad status so it can be |
1188 | * retried. |
1189 | */ |
1190 | writew(DISABLE_ALL_INTERRUPTS, |
1191 | SSP_IMSC(pl022->virtbase)); |
1192 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
1193 | writew((readw(SSP_CR1(pl022->virtbase)) & |
1194 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); |
1195 | msg->state = STATE_ERROR; |
1196 | |
1197 | /* Schedule message queue handler */ |
1198 | tasklet_schedule(&pl022->pump_transfers); |
1199 | return IRQ_HANDLED; |
1200 | } |
1201 | |
1202 | readwriter(pl022); |
1203 | |
1204 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { |
1205 | flag = 1; |
1206 | /* Disable Transmit interrupt */ |
1207 | writew(readw(SSP_IMSC(pl022->virtbase)) & |
1208 | (~SSP_IMSC_MASK_TXIM), |
1209 | SSP_IMSC(pl022->virtbase)); |
1210 | } |
1211 | |
1212 | /* |
1213 | * Since all transactions must write as much as shall be read, |
1214 | * we can conclude the entire transaction once RX is complete. |
1215 | * At this point, all TX will always be finished. |
1216 | */ |
1217 | if (pl022->rx >= pl022->rx_end) { |
1218 | writew(DISABLE_ALL_INTERRUPTS, |
1219 | SSP_IMSC(pl022->virtbase)); |
1220 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
1221 | if (unlikely(pl022->rx > pl022->rx_end)) { |
1222 | dev_warn(&pl022->adev->dev, "read %u surplus " |
1223 | "bytes (did you request an odd " |
1224 | "number of bytes on a 16bit bus?)\n", |
1225 | (u32) (pl022->rx - pl022->rx_end)); |
1226 | } |
1227 | /* Update total bytes transfered */ |
1228 | msg->actual_length += pl022->cur_transfer->len; |
1229 | if (pl022->cur_transfer->cs_change) |
1230 | pl022->cur_chip-> |
1231 | cs_control(SSP_CHIP_DESELECT); |
1232 | /* Move to next transfer */ |
1233 | msg->state = next_transfer(pl022); |
1234 | tasklet_schedule(&pl022->pump_transfers); |
1235 | return IRQ_HANDLED; |
1236 | } |
1237 | |
1238 | return IRQ_HANDLED; |
1239 | } |
1240 | |
1241 | /** |
1242 | * This sets up the pointers to memory for the next message to |
1243 | * send out on the SPI bus. |
1244 | */ |
1245 | static int set_up_next_transfer(struct pl022 *pl022, |
1246 | struct spi_transfer *transfer) |
1247 | { |
1248 | int residue; |
1249 | |
1250 | /* Sanity check the message for this bus width */ |
1251 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; |
1252 | if (unlikely(residue != 0)) { |
1253 | dev_err(&pl022->adev->dev, |
1254 | "message of %u bytes to transmit but the current " |
1255 | "chip bus has a data width of %u bytes!\n", |
1256 | pl022->cur_transfer->len, |
1257 | pl022->cur_chip->n_bytes); |
1258 | dev_err(&pl022->adev->dev, "skipping this message\n"); |
1259 | return -EIO; |
1260 | } |
1261 | pl022->tx = (void *)transfer->tx_buf; |
1262 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; |
1263 | pl022->rx = (void *)transfer->rx_buf; |
1264 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; |
1265 | pl022->write = |
1266 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; |
1267 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; |
1268 | return 0; |
1269 | } |
1270 | |
1271 | /** |
1272 | * pump_transfers - Tasklet function which schedules next transfer |
1273 | * when running in interrupt or DMA transfer mode. |
1274 | * @data: SSP driver private data structure |
1275 | * |
1276 | */ |
1277 | static void pump_transfers(unsigned long data) |
1278 | { |
1279 | struct pl022 *pl022 = (struct pl022 *) data; |
1280 | struct spi_message *message = NULL; |
1281 | struct spi_transfer *transfer = NULL; |
1282 | struct spi_transfer *previous = NULL; |
1283 | |
1284 | /* Get current state information */ |
1285 | message = pl022->cur_msg; |
1286 | transfer = pl022->cur_transfer; |
1287 | |
1288 | /* Handle for abort */ |
1289 | if (message->state == STATE_ERROR) { |
1290 | message->status = -EIO; |
1291 | giveback(pl022); |
1292 | return; |
1293 | } |
1294 | |
1295 | /* Handle end of message */ |
1296 | if (message->state == STATE_DONE) { |
1297 | message->status = 0; |
1298 | giveback(pl022); |
1299 | return; |
1300 | } |
1301 | |
1302 | /* Delay if requested at end of transfer before CS change */ |
1303 | if (message->state == STATE_RUNNING) { |
1304 | previous = list_entry(transfer->transfer_list.prev, |
1305 | struct spi_transfer, |
1306 | transfer_list); |
1307 | if (previous->delay_usecs) |
1308 | /* |
1309 | * FIXME: This runs in interrupt context. |
1310 | * Is this really smart? |
1311 | */ |
1312 | udelay(previous->delay_usecs); |
1313 | |
1314 | /* Drop chip select only if cs_change is requested */ |
1315 | if (previous->cs_change) |
1316 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
1317 | } else { |
1318 | /* STATE_START */ |
1319 | message->state = STATE_RUNNING; |
1320 | } |
1321 | |
1322 | if (set_up_next_transfer(pl022, transfer)) { |
1323 | message->state = STATE_ERROR; |
1324 | message->status = -EIO; |
1325 | giveback(pl022); |
1326 | return; |
1327 | } |
1328 | /* Flush the FIFOs and let's go! */ |
1329 | flush(pl022); |
1330 | |
1331 | if (pl022->cur_chip->enable_dma) { |
1332 | if (configure_dma(pl022)) { |
1333 | dev_dbg(&pl022->adev->dev, |
1334 | "configuration of DMA failed, fall back to interrupt mode\n"); |
1335 | goto err_config_dma; |
1336 | } |
1337 | return; |
1338 | } |
1339 | |
1340 | err_config_dma: |
1341 | writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
1342 | } |
1343 | |
1344 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
1345 | { |
1346 | u32 irqflags = ENABLE_ALL_INTERRUPTS; |
1347 | |
1348 | /* Enable target chip */ |
1349 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
1350 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { |
1351 | /* Error path */ |
1352 | pl022->cur_msg->state = STATE_ERROR; |
1353 | pl022->cur_msg->status = -EIO; |
1354 | giveback(pl022); |
1355 | return; |
1356 | } |
1357 | /* If we're using DMA, set up DMA here */ |
1358 | if (pl022->cur_chip->enable_dma) { |
1359 | /* Configure DMA transfer */ |
1360 | if (configure_dma(pl022)) { |
1361 | dev_dbg(&pl022->adev->dev, |
1362 | "configuration of DMA failed, fall back to interrupt mode\n"); |
1363 | goto err_config_dma; |
1364 | } |
1365 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ |
1366 | irqflags = DISABLE_ALL_INTERRUPTS; |
1367 | } |
1368 | err_config_dma: |
1369 | /* Enable SSP, turn on interrupts */ |
1370 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), |
1371 | SSP_CR1(pl022->virtbase)); |
1372 | writew(irqflags, SSP_IMSC(pl022->virtbase)); |
1373 | } |
1374 | |
1375 | static void do_polling_transfer(struct pl022 *pl022) |
1376 | { |
1377 | struct spi_message *message = NULL; |
1378 | struct spi_transfer *transfer = NULL; |
1379 | struct spi_transfer *previous = NULL; |
1380 | struct chip_data *chip; |
1381 | |
1382 | chip = pl022->cur_chip; |
1383 | message = pl022->cur_msg; |
1384 | |
1385 | while (message->state != STATE_DONE) { |
1386 | /* Handle for abort */ |
1387 | if (message->state == STATE_ERROR) |
1388 | break; |
1389 | transfer = pl022->cur_transfer; |
1390 | |
1391 | /* Delay if requested at end of transfer */ |
1392 | if (message->state == STATE_RUNNING) { |
1393 | previous = |
1394 | list_entry(transfer->transfer_list.prev, |
1395 | struct spi_transfer, transfer_list); |
1396 | if (previous->delay_usecs) |
1397 | udelay(previous->delay_usecs); |
1398 | if (previous->cs_change) |
1399 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
1400 | } else { |
1401 | /* STATE_START */ |
1402 | message->state = STATE_RUNNING; |
1403 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
1404 | } |
1405 | |
1406 | /* Configuration Changing Per Transfer */ |
1407 | if (set_up_next_transfer(pl022, transfer)) { |
1408 | /* Error path */ |
1409 | message->state = STATE_ERROR; |
1410 | break; |
1411 | } |
1412 | /* Flush FIFOs and enable SSP */ |
1413 | flush(pl022); |
1414 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), |
1415 | SSP_CR1(pl022->virtbase)); |
1416 | |
1417 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); |
1418 | /* FIXME: insert a timeout so we don't hang here indefinately */ |
1419 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) |
1420 | readwriter(pl022); |
1421 | |
1422 | /* Update total byte transfered */ |
1423 | message->actual_length += pl022->cur_transfer->len; |
1424 | if (pl022->cur_transfer->cs_change) |
1425 | pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); |
1426 | /* Move to next transfer */ |
1427 | message->state = next_transfer(pl022); |
1428 | } |
1429 | |
1430 | /* Handle end of message */ |
1431 | if (message->state == STATE_DONE) |
1432 | message->status = 0; |
1433 | else |
1434 | message->status = -EIO; |
1435 | |
1436 | giveback(pl022); |
1437 | return; |
1438 | } |
1439 | |
1440 | /** |
1441 | * pump_messages - Workqueue function which processes spi message queue |
1442 | * @data: pointer to private data of SSP driver |
1443 | * |
1444 | * This function checks if there is any spi message in the queue that |
1445 | * needs processing and delegate control to appropriate function |
1446 | * do_polling_transfer()/do_interrupt_dma_transfer() |
1447 | * based on the kind of the transfer |
1448 | * |
1449 | */ |
1450 | static void pump_messages(struct work_struct *work) |
1451 | { |
1452 | struct pl022 *pl022 = |
1453 | container_of(work, struct pl022, pump_messages); |
1454 | unsigned long flags; |
1455 | |
1456 | /* Lock queue and check for queue work */ |
1457 | spin_lock_irqsave(&pl022->queue_lock, flags); |
1458 | if (list_empty(&pl022->queue) || !pl022->running) { |
1459 | pl022->busy = false; |
1460 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1461 | return; |
1462 | } |
1463 | /* Make sure we are not already running a message */ |
1464 | if (pl022->cur_msg) { |
1465 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1466 | return; |
1467 | } |
1468 | /* Extract head of queue */ |
1469 | pl022->cur_msg = |
1470 | list_entry(pl022->queue.next, struct spi_message, queue); |
1471 | |
1472 | list_del_init(&pl022->cur_msg->queue); |
1473 | pl022->busy = true; |
1474 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1475 | |
1476 | /* Initial message state */ |
1477 | pl022->cur_msg->state = STATE_START; |
1478 | pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, |
1479 | struct spi_transfer, |
1480 | transfer_list); |
1481 | |
1482 | /* Setup the SPI using the per chip configuration */ |
1483 | pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); |
1484 | /* |
1485 | * We enable the clocks here, then the clocks will be disabled when |
1486 | * giveback() is called in each method (poll/interrupt/DMA) |
1487 | */ |
1488 | amba_pclk_enable(pl022->adev); |
1489 | clk_enable(pl022->clk); |
1490 | restore_state(pl022); |
1491 | flush(pl022); |
1492 | |
1493 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) |
1494 | do_polling_transfer(pl022); |
1495 | else |
1496 | do_interrupt_dma_transfer(pl022); |
1497 | } |
1498 | |
1499 | |
1500 | static int __init init_queue(struct pl022 *pl022) |
1501 | { |
1502 | INIT_LIST_HEAD(&pl022->queue); |
1503 | spin_lock_init(&pl022->queue_lock); |
1504 | |
1505 | pl022->running = false; |
1506 | pl022->busy = false; |
1507 | |
1508 | tasklet_init(&pl022->pump_transfers, |
1509 | pump_transfers, (unsigned long)pl022); |
1510 | |
1511 | INIT_WORK(&pl022->pump_messages, pump_messages); |
1512 | pl022->workqueue = create_singlethread_workqueue( |
1513 | dev_name(pl022->master->dev.parent)); |
1514 | if (pl022->workqueue == NULL) |
1515 | return -EBUSY; |
1516 | |
1517 | return 0; |
1518 | } |
1519 | |
1520 | |
1521 | static int start_queue(struct pl022 *pl022) |
1522 | { |
1523 | unsigned long flags; |
1524 | |
1525 | spin_lock_irqsave(&pl022->queue_lock, flags); |
1526 | |
1527 | if (pl022->running || pl022->busy) { |
1528 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1529 | return -EBUSY; |
1530 | } |
1531 | |
1532 | pl022->running = true; |
1533 | pl022->cur_msg = NULL; |
1534 | pl022->cur_transfer = NULL; |
1535 | pl022->cur_chip = NULL; |
1536 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1537 | |
1538 | queue_work(pl022->workqueue, &pl022->pump_messages); |
1539 | |
1540 | return 0; |
1541 | } |
1542 | |
1543 | |
1544 | static int stop_queue(struct pl022 *pl022) |
1545 | { |
1546 | unsigned long flags; |
1547 | unsigned limit = 500; |
1548 | int status = 0; |
1549 | |
1550 | spin_lock_irqsave(&pl022->queue_lock, flags); |
1551 | |
1552 | /* This is a bit lame, but is optimized for the common execution path. |
1553 | * A wait_queue on the pl022->busy could be used, but then the common |
1554 | * execution path (pump_messages) would be required to call wake_up or |
1555 | * friends on every SPI message. Do this instead */ |
1556 | while (!list_empty(&pl022->queue) && pl022->busy && limit--) { |
1557 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1558 | msleep(10); |
1559 | spin_lock_irqsave(&pl022->queue_lock, flags); |
1560 | } |
1561 | |
1562 | if (!list_empty(&pl022->queue) || pl022->busy) |
1563 | status = -EBUSY; |
1564 | else |
1565 | pl022->running = false; |
1566 | |
1567 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1568 | |
1569 | return status; |
1570 | } |
1571 | |
1572 | static int destroy_queue(struct pl022 *pl022) |
1573 | { |
1574 | int status; |
1575 | |
1576 | status = stop_queue(pl022); |
1577 | /* we are unloading the module or failing to load (only two calls |
1578 | * to this routine), and neither call can handle a return value. |
1579 | * However, destroy_workqueue calls flush_workqueue, and that will |
1580 | * block until all work is done. If the reason that stop_queue |
1581 | * timed out is that the work will never finish, then it does no |
1582 | * good to call destroy_workqueue, so return anyway. */ |
1583 | if (status != 0) |
1584 | return status; |
1585 | |
1586 | destroy_workqueue(pl022->workqueue); |
1587 | |
1588 | return 0; |
1589 | } |
1590 | |
1591 | static int verify_controller_parameters(struct pl022 *pl022, |
1592 | struct pl022_config_chip const *chip_info) |
1593 | { |
1594 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
1595 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { |
1596 | dev_err(&pl022->adev->dev, |
1597 | "interface is configured incorrectly\n"); |
1598 | return -EINVAL; |
1599 | } |
1600 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && |
1601 | (!pl022->vendor->unidir)) { |
1602 | dev_err(&pl022->adev->dev, |
1603 | "unidirectional mode not supported in this " |
1604 | "hardware version\n"); |
1605 | return -EINVAL; |
1606 | } |
1607 | if ((chip_info->hierarchy != SSP_MASTER) |
1608 | && (chip_info->hierarchy != SSP_SLAVE)) { |
1609 | dev_err(&pl022->adev->dev, |
1610 | "hierarchy is configured incorrectly\n"); |
1611 | return -EINVAL; |
1612 | } |
1613 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
1614 | && (chip_info->com_mode != DMA_TRANSFER) |
1615 | && (chip_info->com_mode != POLLING_TRANSFER)) { |
1616 | dev_err(&pl022->adev->dev, |
1617 | "Communication mode is configured incorrectly\n"); |
1618 | return -EINVAL; |
1619 | } |
1620 | if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM) |
1621 | || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) { |
1622 | dev_err(&pl022->adev->dev, |
1623 | "RX FIFO Trigger Level is configured incorrectly\n"); |
1624 | return -EINVAL; |
1625 | } |
1626 | if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC) |
1627 | || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) { |
1628 | dev_err(&pl022->adev->dev, |
1629 | "TX FIFO Trigger Level is configured incorrectly\n"); |
1630 | return -EINVAL; |
1631 | } |
1632 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
1633 | if ((chip_info->ctrl_len < SSP_BITS_4) |
1634 | || (chip_info->ctrl_len > SSP_BITS_32)) { |
1635 | dev_err(&pl022->adev->dev, |
1636 | "CTRL LEN is configured incorrectly\n"); |
1637 | return -EINVAL; |
1638 | } |
1639 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) |
1640 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { |
1641 | dev_err(&pl022->adev->dev, |
1642 | "Wait State is configured incorrectly\n"); |
1643 | return -EINVAL; |
1644 | } |
1645 | /* Half duplex is only available in the ST Micro version */ |
1646 | if (pl022->vendor->extended_cr) { |
1647 | if ((chip_info->duplex != |
1648 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) |
1649 | && (chip_info->duplex != |
1650 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
1651 | dev_err(&pl022->adev->dev, |
1652 | "Microwire duplex mode is configured incorrectly\n"); |
1653 | return -EINVAL; |
1654 | } |
1655 | } else { |
1656 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) |
1657 | dev_err(&pl022->adev->dev, |
1658 | "Microwire half duplex mode requested," |
1659 | " but this is only available in the" |
1660 | " ST version of PL022\n"); |
1661 | return -EINVAL; |
1662 | } |
1663 | } |
1664 | return 0; |
1665 | } |
1666 | |
1667 | /** |
1668 | * pl022_transfer - transfer function registered to SPI master framework |
1669 | * @spi: spi device which is requesting transfer |
1670 | * @msg: spi message which is to handled is queued to driver queue |
1671 | * |
1672 | * This function is registered to the SPI framework for this SPI master |
1673 | * controller. It will queue the spi_message in the queue of driver if |
1674 | * the queue is not stopped and return. |
1675 | */ |
1676 | static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) |
1677 | { |
1678 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); |
1679 | unsigned long flags; |
1680 | |
1681 | spin_lock_irqsave(&pl022->queue_lock, flags); |
1682 | |
1683 | if (!pl022->running) { |
1684 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1685 | return -ESHUTDOWN; |
1686 | } |
1687 | msg->actual_length = 0; |
1688 | msg->status = -EINPROGRESS; |
1689 | msg->state = STATE_START; |
1690 | |
1691 | list_add_tail(&msg->queue, &pl022->queue); |
1692 | if (pl022->running && !pl022->busy) |
1693 | queue_work(pl022->workqueue, &pl022->pump_messages); |
1694 | |
1695 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1696 | return 0; |
1697 | } |
1698 | |
1699 | static int calculate_effective_freq(struct pl022 *pl022, |
1700 | int freq, |
1701 | struct ssp_clock_params *clk_freq) |
1702 | { |
1703 | /* Lets calculate the frequency parameters */ |
1704 | u16 cpsdvsr = 2; |
1705 | u16 scr = 0; |
1706 | bool freq_found = false; |
1707 | u32 rate; |
1708 | u32 max_tclk; |
1709 | u32 min_tclk; |
1710 | |
1711 | rate = clk_get_rate(pl022->clk); |
1712 | /* cpsdvscr = 2 & scr 0 */ |
1713 | max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN))); |
1714 | /* cpsdvsr = 254 & scr = 255 */ |
1715 | min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX))); |
1716 | |
1717 | if ((freq <= max_tclk) && (freq >= min_tclk)) { |
1718 | while (cpsdvsr <= CPSDVR_MAX && !freq_found) { |
1719 | while (scr <= SCR_MAX && !freq_found) { |
1720 | if ((rate / |
1721 | (cpsdvsr * (1 + scr))) > freq) |
1722 | scr += 1; |
1723 | else { |
1724 | /* |
1725 | * This bool is made true when |
1726 | * effective frequency >= |
1727 | * target frequency is found |
1728 | */ |
1729 | freq_found = true; |
1730 | if ((rate / |
1731 | (cpsdvsr * (1 + scr))) != freq) { |
1732 | if (scr == SCR_MIN) { |
1733 | cpsdvsr -= 2; |
1734 | scr = SCR_MAX; |
1735 | } else |
1736 | scr -= 1; |
1737 | } |
1738 | } |
1739 | } |
1740 | if (!freq_found) { |
1741 | cpsdvsr += 2; |
1742 | scr = SCR_MIN; |
1743 | } |
1744 | } |
1745 | if (cpsdvsr != 0) { |
1746 | dev_dbg(&pl022->adev->dev, |
1747 | "SSP Effective Frequency is %u\n", |
1748 | (rate / (cpsdvsr * (1 + scr)))); |
1749 | clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF); |
1750 | clk_freq->scr = (u8) (scr & 0xFF); |
1751 | dev_dbg(&pl022->adev->dev, |
1752 | "SSP cpsdvsr = %d, scr = %d\n", |
1753 | clk_freq->cpsdvsr, clk_freq->scr); |
1754 | } |
1755 | } else { |
1756 | dev_err(&pl022->adev->dev, |
1757 | "controller data is incorrect: out of range frequency"); |
1758 | return -EINVAL; |
1759 | } |
1760 | return 0; |
1761 | } |
1762 | |
1763 | |
1764 | /* |
1765 | * A piece of default chip info unless the platform |
1766 | * supplies it. |
1767 | */ |
1768 | static const struct pl022_config_chip pl022_default_chip_info = { |
1769 | .com_mode = POLLING_TRANSFER, |
1770 | .iface = SSP_INTERFACE_MOTOROLA_SPI, |
1771 | .hierarchy = SSP_SLAVE, |
1772 | .slave_tx_disable = DO_NOT_DRIVE_TX, |
1773 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, |
1774 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, |
1775 | .ctrl_len = SSP_BITS_8, |
1776 | .wait_state = SSP_MWIRE_WAIT_ZERO, |
1777 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
1778 | .cs_control = null_cs_control, |
1779 | }; |
1780 | |
1781 | |
1782 | /** |
1783 | * pl022_setup - setup function registered to SPI master framework |
1784 | * @spi: spi device which is requesting setup |
1785 | * |
1786 | * This function is registered to the SPI framework for this SPI master |
1787 | * controller. If it is the first time when setup is called by this device, |
1788 | * this function will initialize the runtime state for this chip and save |
1789 | * the same in the device structure. Else it will update the runtime info |
1790 | * with the updated chip info. Nothing is really being written to the |
1791 | * controller hardware here, that is not done until the actual transfer |
1792 | * commence. |
1793 | */ |
1794 | static int pl022_setup(struct spi_device *spi) |
1795 | { |
1796 | struct pl022_config_chip const *chip_info; |
1797 | struct chip_data *chip; |
1798 | struct ssp_clock_params clk_freq = {0, }; |
1799 | int status = 0; |
1800 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); |
1801 | unsigned int bits = spi->bits_per_word; |
1802 | u32 tmp; |
1803 | |
1804 | if (!spi->max_speed_hz) |
1805 | return -EINVAL; |
1806 | |
1807 | /* Get controller_state if one is supplied */ |
1808 | chip = spi_get_ctldata(spi); |
1809 | |
1810 | if (chip == NULL) { |
1811 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
1812 | if (!chip) { |
1813 | dev_err(&spi->dev, |
1814 | "cannot allocate controller state\n"); |
1815 | return -ENOMEM; |
1816 | } |
1817 | dev_dbg(&spi->dev, |
1818 | "allocated memory for controller's runtime state\n"); |
1819 | } |
1820 | |
1821 | /* Get controller data if one is supplied */ |
1822 | chip_info = spi->controller_data; |
1823 | |
1824 | if (chip_info == NULL) { |
1825 | chip_info = &pl022_default_chip_info; |
1826 | /* spi_board_info.controller_data not is supplied */ |
1827 | dev_dbg(&spi->dev, |
1828 | "using default controller_data settings\n"); |
1829 | } else |
1830 | dev_dbg(&spi->dev, |
1831 | "using user supplied controller_data settings\n"); |
1832 | |
1833 | /* |
1834 | * We can override with custom divisors, else we use the board |
1835 | * frequency setting |
1836 | */ |
1837 | if ((0 == chip_info->clk_freq.cpsdvsr) |
1838 | && (0 == chip_info->clk_freq.scr)) { |
1839 | status = calculate_effective_freq(pl022, |
1840 | spi->max_speed_hz, |
1841 | &clk_freq); |
1842 | if (status < 0) |
1843 | goto err_config_params; |
1844 | } else { |
1845 | memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); |
1846 | if ((clk_freq.cpsdvsr % 2) != 0) |
1847 | clk_freq.cpsdvsr = |
1848 | clk_freq.cpsdvsr - 1; |
1849 | } |
1850 | if ((clk_freq.cpsdvsr < CPSDVR_MIN) |
1851 | || (clk_freq.cpsdvsr > CPSDVR_MAX)) { |
1852 | dev_err(&spi->dev, |
1853 | "cpsdvsr is configured incorrectly\n"); |
1854 | goto err_config_params; |
1855 | } |
1856 | |
1857 | |
1858 | status = verify_controller_parameters(pl022, chip_info); |
1859 | if (status) { |
1860 | dev_err(&spi->dev, "controller data is incorrect"); |
1861 | goto err_config_params; |
1862 | } |
1863 | |
1864 | /* Now set controller state based on controller data */ |
1865 | chip->xfer_type = chip_info->com_mode; |
1866 | if (!chip_info->cs_control) { |
1867 | chip->cs_control = null_cs_control; |
1868 | dev_warn(&spi->dev, |
1869 | "chip select function is NULL for this chip\n"); |
1870 | } else |
1871 | chip->cs_control = chip_info->cs_control; |
1872 | |
1873 | if (bits <= 3) { |
1874 | /* PL022 doesn't support less than 4-bits */ |
1875 | status = -ENOTSUPP; |
1876 | goto err_config_params; |
1877 | } else if (bits <= 8) { |
1878 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); |
1879 | chip->n_bytes = 1; |
1880 | chip->read = READING_U8; |
1881 | chip->write = WRITING_U8; |
1882 | } else if (bits <= 16) { |
1883 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
1884 | chip->n_bytes = 2; |
1885 | chip->read = READING_U16; |
1886 | chip->write = WRITING_U16; |
1887 | } else { |
1888 | if (pl022->vendor->max_bpw >= 32) { |
1889 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); |
1890 | chip->n_bytes = 4; |
1891 | chip->read = READING_U32; |
1892 | chip->write = WRITING_U32; |
1893 | } else { |
1894 | dev_err(&spi->dev, |
1895 | "illegal data size for this controller!\n"); |
1896 | dev_err(&spi->dev, |
1897 | "a standard pl022 can only handle " |
1898 | "1 <= n <= 16 bit words\n"); |
1899 | status = -ENOTSUPP; |
1900 | goto err_config_params; |
1901 | } |
1902 | } |
1903 | |
1904 | /* Now Initialize all register settings required for this chip */ |
1905 | chip->cr0 = 0; |
1906 | chip->cr1 = 0; |
1907 | chip->dmacr = 0; |
1908 | chip->cpsr = 0; |
1909 | if ((chip_info->com_mode == DMA_TRANSFER) |
1910 | && ((pl022->master_info)->enable_dma)) { |
1911 | chip->enable_dma = true; |
1912 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
1913 | if (status < 0) |
1914 | goto err_config_params; |
1915 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
1916 | SSP_DMACR_MASK_RXDMAE, 0); |
1917 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
1918 | SSP_DMACR_MASK_TXDMAE, 1); |
1919 | } else { |
1920 | chip->enable_dma = false; |
1921 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
1922 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, |
1923 | SSP_DMACR_MASK_RXDMAE, 0); |
1924 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, |
1925 | SSP_DMACR_MASK_TXDMAE, 1); |
1926 | } |
1927 | |
1928 | chip->cpsr = clk_freq.cpsdvsr; |
1929 | |
1930 | /* Special setup for the ST micro extended control registers */ |
1931 | if (pl022->vendor->extended_cr) { |
1932 | u32 etx; |
1933 | |
1934 | if (pl022->vendor->pl023) { |
1935 | /* These bits are only in the PL023 */ |
1936 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, |
1937 | SSP_CR1_MASK_FBCLKDEL_ST, 13); |
1938 | } else { |
1939 | /* These bits are in the PL022 but not PL023 */ |
1940 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, |
1941 | SSP_CR0_MASK_HALFDUP_ST, 5); |
1942 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, |
1943 | SSP_CR0_MASK_CSS_ST, 16); |
1944 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, |
1945 | SSP_CR0_MASK_FRF_ST, 21); |
1946 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, |
1947 | SSP_CR1_MASK_MWAIT_ST, 6); |
1948 | } |
1949 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
1950 | SSP_CR0_MASK_DSS_ST, 0); |
1951 | |
1952 | if (spi->mode & SPI_LSB_FIRST) { |
1953 | tmp = SSP_RX_LSB; |
1954 | etx = SSP_TX_LSB; |
1955 | } else { |
1956 | tmp = SSP_RX_MSB; |
1957 | etx = SSP_TX_MSB; |
1958 | } |
1959 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); |
1960 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); |
1961 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
1962 | SSP_CR1_MASK_RXIFLSEL_ST, 7); |
1963 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, |
1964 | SSP_CR1_MASK_TXIFLSEL_ST, 10); |
1965 | } else { |
1966 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
1967 | SSP_CR0_MASK_DSS, 0); |
1968 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, |
1969 | SSP_CR0_MASK_FRF, 4); |
1970 | } |
1971 | |
1972 | /* Stuff that is common for all versions */ |
1973 | if (spi->mode & SPI_CPOL) |
1974 | tmp = SSP_CLK_POL_IDLE_HIGH; |
1975 | else |
1976 | tmp = SSP_CLK_POL_IDLE_LOW; |
1977 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); |
1978 | |
1979 | if (spi->mode & SPI_CPHA) |
1980 | tmp = SSP_CLK_SECOND_EDGE; |
1981 | else |
1982 | tmp = SSP_CLK_FIRST_EDGE; |
1983 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); |
1984 | |
1985 | SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
1986 | /* Loopback is available on all versions except PL023 */ |
1987 | if (!pl022->vendor->pl023) { |
1988 | if (spi->mode & SPI_LOOP) |
1989 | tmp = LOOPBACK_ENABLED; |
1990 | else |
1991 | tmp = LOOPBACK_DISABLED; |
1992 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); |
1993 | } |
1994 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
1995 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); |
1996 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3); |
1997 | |
1998 | /* Save controller_state */ |
1999 | spi_set_ctldata(spi, chip); |
2000 | return status; |
2001 | err_config_params: |
2002 | spi_set_ctldata(spi, NULL); |
2003 | kfree(chip); |
2004 | return status; |
2005 | } |
2006 | |
2007 | /** |
2008 | * pl022_cleanup - cleanup function registered to SPI master framework |
2009 | * @spi: spi device which is requesting cleanup |
2010 | * |
2011 | * This function is registered to the SPI framework for this SPI master |
2012 | * controller. It will free the runtime state of chip. |
2013 | */ |
2014 | static void pl022_cleanup(struct spi_device *spi) |
2015 | { |
2016 | struct chip_data *chip = spi_get_ctldata(spi); |
2017 | |
2018 | spi_set_ctldata(spi, NULL); |
2019 | kfree(chip); |
2020 | } |
2021 | |
2022 | |
2023 | static int __devinit |
2024 | pl022_probe(struct amba_device *adev, struct amba_id *id) |
2025 | { |
2026 | struct device *dev = &adev->dev; |
2027 | struct pl022_ssp_controller *platform_info = adev->dev.platform_data; |
2028 | struct spi_master *master; |
2029 | struct pl022 *pl022 = NULL; /*Data for this driver */ |
2030 | int status = 0; |
2031 | |
2032 | dev_info(&adev->dev, |
2033 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); |
2034 | if (platform_info == NULL) { |
2035 | dev_err(&adev->dev, "probe - no platform data supplied\n"); |
2036 | status = -ENODEV; |
2037 | goto err_no_pdata; |
2038 | } |
2039 | |
2040 | /* Allocate master with space for data */ |
2041 | master = spi_alloc_master(dev, sizeof(struct pl022)); |
2042 | if (master == NULL) { |
2043 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); |
2044 | status = -ENOMEM; |
2045 | goto err_no_master; |
2046 | } |
2047 | |
2048 | pl022 = spi_master_get_devdata(master); |
2049 | pl022->master = master; |
2050 | pl022->master_info = platform_info; |
2051 | pl022->adev = adev; |
2052 | pl022->vendor = id->data; |
2053 | |
2054 | /* |
2055 | * Bus Number Which has been Assigned to this SSP controller |
2056 | * on this board |
2057 | */ |
2058 | master->bus_num = platform_info->bus_id; |
2059 | master->num_chipselect = platform_info->num_chipselect; |
2060 | master->cleanup = pl022_cleanup; |
2061 | master->setup = pl022_setup; |
2062 | master->transfer = pl022_transfer; |
2063 | |
2064 | /* |
2065 | * Supports mode 0-3, loopback, and active low CS. Transfers are |
2066 | * always MS bit first on the original pl022. |
2067 | */ |
2068 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
2069 | if (pl022->vendor->extended_cr) |
2070 | master->mode_bits |= SPI_LSB_FIRST; |
2071 | |
2072 | dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); |
2073 | |
2074 | status = amba_request_regions(adev, NULL); |
2075 | if (status) |
2076 | goto err_no_ioregion; |
2077 | |
2078 | pl022->phybase = adev->res.start; |
2079 | pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
2080 | if (pl022->virtbase == NULL) { |
2081 | status = -ENOMEM; |
2082 | goto err_no_ioremap; |
2083 | } |
2084 | printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", |
2085 | adev->res.start, pl022->virtbase); |
2086 | |
2087 | pl022->clk = clk_get(&adev->dev, NULL); |
2088 | if (IS_ERR(pl022->clk)) { |
2089 | status = PTR_ERR(pl022->clk); |
2090 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); |
2091 | goto err_no_clk; |
2092 | } |
2093 | |
2094 | /* Disable SSP */ |
2095 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
2096 | SSP_CR1(pl022->virtbase)); |
2097 | load_ssp_default_config(pl022); |
2098 | |
2099 | status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", |
2100 | pl022); |
2101 | if (status < 0) { |
2102 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); |
2103 | goto err_no_irq; |
2104 | } |
2105 | |
2106 | /* Get DMA channels */ |
2107 | if (platform_info->enable_dma) { |
2108 | status = pl022_dma_probe(pl022); |
2109 | if (status != 0) |
2110 | goto err_no_dma; |
2111 | } |
2112 | |
2113 | /* Initialize and start queue */ |
2114 | status = init_queue(pl022); |
2115 | if (status != 0) { |
2116 | dev_err(&adev->dev, "probe - problem initializing queue\n"); |
2117 | goto err_init_queue; |
2118 | } |
2119 | status = start_queue(pl022); |
2120 | if (status != 0) { |
2121 | dev_err(&adev->dev, "probe - problem starting queue\n"); |
2122 | goto err_start_queue; |
2123 | } |
2124 | /* Register with the SPI framework */ |
2125 | amba_set_drvdata(adev, pl022); |
2126 | status = spi_register_master(master); |
2127 | if (status != 0) { |
2128 | dev_err(&adev->dev, |
2129 | "probe - problem registering spi master\n"); |
2130 | goto err_spi_register; |
2131 | } |
2132 | dev_dbg(dev, "probe succeded\n"); |
2133 | /* Disable the silicon block pclk and clock it when needed */ |
2134 | amba_pclk_disable(adev); |
2135 | return 0; |
2136 | |
2137 | err_spi_register: |
2138 | err_start_queue: |
2139 | err_init_queue: |
2140 | destroy_queue(pl022); |
2141 | pl022_dma_remove(pl022); |
2142 | err_no_dma: |
2143 | free_irq(adev->irq[0], pl022); |
2144 | err_no_irq: |
2145 | clk_put(pl022->clk); |
2146 | err_no_clk: |
2147 | iounmap(pl022->virtbase); |
2148 | err_no_ioremap: |
2149 | amba_release_regions(adev); |
2150 | err_no_ioregion: |
2151 | spi_master_put(master); |
2152 | err_no_master: |
2153 | err_no_pdata: |
2154 | return status; |
2155 | } |
2156 | |
2157 | static int __devexit |
2158 | pl022_remove(struct amba_device *adev) |
2159 | { |
2160 | struct pl022 *pl022 = amba_get_drvdata(adev); |
2161 | int status = 0; |
2162 | if (!pl022) |
2163 | return 0; |
2164 | |
2165 | /* Remove the queue */ |
2166 | status = destroy_queue(pl022); |
2167 | if (status != 0) { |
2168 | dev_err(&adev->dev, |
2169 | "queue remove failed (%d)\n", status); |
2170 | return status; |
2171 | } |
2172 | load_ssp_default_config(pl022); |
2173 | pl022_dma_remove(pl022); |
2174 | free_irq(adev->irq[0], pl022); |
2175 | clk_disable(pl022->clk); |
2176 | clk_put(pl022->clk); |
2177 | iounmap(pl022->virtbase); |
2178 | amba_release_regions(adev); |
2179 | tasklet_disable(&pl022->pump_transfers); |
2180 | spi_unregister_master(pl022->master); |
2181 | spi_master_put(pl022->master); |
2182 | amba_set_drvdata(adev, NULL); |
2183 | dev_dbg(&adev->dev, "remove succeded\n"); |
2184 | return 0; |
2185 | } |
2186 | |
2187 | #ifdef CONFIG_PM |
2188 | static int pl022_suspend(struct amba_device *adev, pm_message_t state) |
2189 | { |
2190 | struct pl022 *pl022 = amba_get_drvdata(adev); |
2191 | int status = 0; |
2192 | |
2193 | status = stop_queue(pl022); |
2194 | if (status) { |
2195 | dev_warn(&adev->dev, "suspend cannot stop queue\n"); |
2196 | return status; |
2197 | } |
2198 | |
2199 | amba_pclk_enable(adev); |
2200 | load_ssp_default_config(pl022); |
2201 | amba_pclk_disable(adev); |
2202 | dev_dbg(&adev->dev, "suspended\n"); |
2203 | return 0; |
2204 | } |
2205 | |
2206 | static int pl022_resume(struct amba_device *adev) |
2207 | { |
2208 | struct pl022 *pl022 = amba_get_drvdata(adev); |
2209 | int status = 0; |
2210 | |
2211 | /* Start the queue running */ |
2212 | status = start_queue(pl022); |
2213 | if (status) |
2214 | dev_err(&adev->dev, "problem starting queue (%d)\n", status); |
2215 | else |
2216 | dev_dbg(&adev->dev, "resumed\n"); |
2217 | |
2218 | return status; |
2219 | } |
2220 | #else |
2221 | #define pl022_suspend NULL |
2222 | #define pl022_resume NULL |
2223 | #endif /* CONFIG_PM */ |
2224 | |
2225 | static struct vendor_data vendor_arm = { |
2226 | .fifodepth = 8, |
2227 | .max_bpw = 16, |
2228 | .unidir = false, |
2229 | .extended_cr = false, |
2230 | .pl023 = false, |
2231 | }; |
2232 | |
2233 | |
2234 | static struct vendor_data vendor_st = { |
2235 | .fifodepth = 32, |
2236 | .max_bpw = 32, |
2237 | .unidir = false, |
2238 | .extended_cr = true, |
2239 | .pl023 = false, |
2240 | }; |
2241 | |
2242 | static struct vendor_data vendor_st_pl023 = { |
2243 | .fifodepth = 32, |
2244 | .max_bpw = 32, |
2245 | .unidir = false, |
2246 | .extended_cr = true, |
2247 | .pl023 = true, |
2248 | }; |
2249 | |
2250 | static struct amba_id pl022_ids[] = { |
2251 | { |
2252 | /* |
2253 | * ARM PL022 variant, this has a 16bit wide |
2254 | * and 8 locations deep TX/RX FIFO |
2255 | */ |
2256 | .id = 0x00041022, |
2257 | .mask = 0x000fffff, |
2258 | .data = &vendor_arm, |
2259 | }, |
2260 | { |
2261 | /* |
2262 | * ST Micro derivative, this has 32bit wide |
2263 | * and 32 locations deep TX/RX FIFO |
2264 | */ |
2265 | .id = 0x01080022, |
2266 | .mask = 0xffffffff, |
2267 | .data = &vendor_st, |
2268 | }, |
2269 | { |
2270 | /* |
2271 | * ST-Ericsson derivative "PL023" (this is not |
2272 | * an official ARM number), this is a PL022 SSP block |
2273 | * stripped to SPI mode only, it has 32bit wide |
2274 | * and 32 locations deep TX/RX FIFO but no extended |
2275 | * CR0/CR1 register |
2276 | */ |
2277 | .id = 0x00080023, |
2278 | .mask = 0xffffffff, |
2279 | .data = &vendor_st_pl023, |
2280 | }, |
2281 | { 0, 0 }, |
2282 | }; |
2283 | |
2284 | static struct amba_driver pl022_driver = { |
2285 | .drv = { |
2286 | .name = "ssp-pl022", |
2287 | }, |
2288 | .id_table = pl022_ids, |
2289 | .probe = pl022_probe, |
2290 | .remove = __devexit_p(pl022_remove), |
2291 | .suspend = pl022_suspend, |
2292 | .resume = pl022_resume, |
2293 | }; |
2294 | |
2295 | |
2296 | static int __init pl022_init(void) |
2297 | { |
2298 | return amba_driver_register(&pl022_driver); |
2299 | } |
2300 | |
2301 | subsys_initcall(pl022_init); |
2302 | |
2303 | static void __exit pl022_exit(void) |
2304 | { |
2305 | amba_driver_unregister(&pl022_driver); |
2306 | } |
2307 | |
2308 | module_exit(pl022_exit); |
2309 | |
2310 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); |
2311 | MODULE_DESCRIPTION("PL022 SSP Controller Driver"); |
2312 | MODULE_LICENSE("GPL"); |
2313 |
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