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Source at commit 6c17a31f1fc515425221067cb3ece599c09dbc5d created 12 years 8 months ago. By Werner Almesberger, atusb, atben: moved from spi/ to ieee802154/; renamed atusb to spi_atusb | |
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1 | /* |
2 | * MPC512x PSC in SPI mode driver. |
3 | * |
4 | * Copyright (C) 2007,2008 Freescale Semiconductor Inc. |
5 | * Original port from 52xx driver: |
6 | * Hongjun Chen <hong-jun.chen@freescale.com> |
7 | * |
8 | * Fork of mpc52xx_psc_spi.c: |
9 | * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify it |
12 | * under the terms of the GNU General Public License as published by the |
13 | * Free Software Foundation; either version 2 of the License, or (at your |
14 | * option) any later version. |
15 | */ |
16 | |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> |
20 | #include <linux/errno.h> |
21 | #include <linux/interrupt.h> |
22 | #include <linux/of_address.h> |
23 | #include <linux/of_platform.h> |
24 | #include <linux/workqueue.h> |
25 | #include <linux/completion.h> |
26 | #include <linux/io.h> |
27 | #include <linux/delay.h> |
28 | #include <linux/clk.h> |
29 | #include <linux/spi/spi.h> |
30 | #include <linux/fsl_devices.h> |
31 | #include <asm/mpc52xx_psc.h> |
32 | |
33 | struct mpc512x_psc_spi { |
34 | void (*cs_control)(struct spi_device *spi, bool on); |
35 | u32 sysclk; |
36 | |
37 | /* driver internal data */ |
38 | struct mpc52xx_psc __iomem *psc; |
39 | struct mpc512x_psc_fifo __iomem *fifo; |
40 | unsigned int irq; |
41 | u8 bits_per_word; |
42 | u8 busy; |
43 | u32 mclk; |
44 | u8 eofbyte; |
45 | |
46 | struct workqueue_struct *workqueue; |
47 | struct work_struct work; |
48 | |
49 | struct list_head queue; |
50 | spinlock_t lock; /* Message queue lock */ |
51 | |
52 | struct completion done; |
53 | }; |
54 | |
55 | /* controller state */ |
56 | struct mpc512x_psc_spi_cs { |
57 | int bits_per_word; |
58 | int speed_hz; |
59 | }; |
60 | |
61 | /* set clock freq, clock ramp, bits per work |
62 | * if t is NULL then reset the values to the default values |
63 | */ |
64 | static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi, |
65 | struct spi_transfer *t) |
66 | { |
67 | struct mpc512x_psc_spi_cs *cs = spi->controller_state; |
68 | |
69 | cs->speed_hz = (t && t->speed_hz) |
70 | ? t->speed_hz : spi->max_speed_hz; |
71 | cs->bits_per_word = (t && t->bits_per_word) |
72 | ? t->bits_per_word : spi->bits_per_word; |
73 | cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; |
74 | return 0; |
75 | } |
76 | |
77 | static void mpc512x_psc_spi_activate_cs(struct spi_device *spi) |
78 | { |
79 | struct mpc512x_psc_spi_cs *cs = spi->controller_state; |
80 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); |
81 | struct mpc52xx_psc __iomem *psc = mps->psc; |
82 | u32 sicr; |
83 | u32 ccr; |
84 | u16 bclkdiv; |
85 | |
86 | sicr = in_be32(&psc->sicr); |
87 | |
88 | /* Set clock phase and polarity */ |
89 | if (spi->mode & SPI_CPHA) |
90 | sicr |= 0x00001000; |
91 | else |
92 | sicr &= ~0x00001000; |
93 | |
94 | if (spi->mode & SPI_CPOL) |
95 | sicr |= 0x00002000; |
96 | else |
97 | sicr &= ~0x00002000; |
98 | |
99 | if (spi->mode & SPI_LSB_FIRST) |
100 | sicr |= 0x10000000; |
101 | else |
102 | sicr &= ~0x10000000; |
103 | out_be32(&psc->sicr, sicr); |
104 | |
105 | ccr = in_be32(&psc->ccr); |
106 | ccr &= 0xFF000000; |
107 | if (cs->speed_hz) |
108 | bclkdiv = (mps->mclk / cs->speed_hz) - 1; |
109 | else |
110 | bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */ |
111 | |
112 | ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); |
113 | out_be32(&psc->ccr, ccr); |
114 | mps->bits_per_word = cs->bits_per_word; |
115 | |
116 | if (mps->cs_control) |
117 | mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0); |
118 | } |
119 | |
120 | static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi) |
121 | { |
122 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); |
123 | |
124 | if (mps->cs_control) |
125 | mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1); |
126 | |
127 | } |
128 | |
129 | /* extract and scale size field in txsz or rxsz */ |
130 | #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2); |
131 | |
132 | #define EOFBYTE 1 |
133 | |
134 | static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, |
135 | struct spi_transfer *t) |
136 | { |
137 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); |
138 | struct mpc52xx_psc __iomem *psc = mps->psc; |
139 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; |
140 | size_t len = t->len; |
141 | u8 *tx_buf = (u8 *)t->tx_buf; |
142 | u8 *rx_buf = (u8 *)t->rx_buf; |
143 | |
144 | if (!tx_buf && !rx_buf && t->len) |
145 | return -EINVAL; |
146 | |
147 | /* Zero MR2 */ |
148 | in_8(&psc->mode); |
149 | out_8(&psc->mode, 0x0); |
150 | |
151 | while (len) { |
152 | int count; |
153 | int i; |
154 | u8 data; |
155 | size_t fifosz; |
156 | int rxcount; |
157 | |
158 | /* |
159 | * The number of bytes that can be sent at a time |
160 | * depends on the fifo size. |
161 | */ |
162 | fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); |
163 | count = min(fifosz, len); |
164 | |
165 | for (i = count; i > 0; i--) { |
166 | data = tx_buf ? *tx_buf++ : 0; |
167 | if (len == EOFBYTE) |
168 | setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF); |
169 | out_8(&fifo->txdata_8, data); |
170 | len--; |
171 | } |
172 | |
173 | INIT_COMPLETION(mps->done); |
174 | |
175 | /* interrupt on tx fifo empty */ |
176 | out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); |
177 | out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY); |
178 | |
179 | /* enable transmiter/receiver */ |
180 | out_8(&psc->command, |
181 | MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); |
182 | |
183 | wait_for_completion(&mps->done); |
184 | |
185 | mdelay(1); |
186 | |
187 | /* rx fifo should have count bytes in it */ |
188 | rxcount = in_be32(&fifo->rxcnt); |
189 | if (rxcount != count) |
190 | mdelay(1); |
191 | |
192 | rxcount = in_be32(&fifo->rxcnt); |
193 | if (rxcount != count) { |
194 | dev_warn(&spi->dev, "expected %d bytes in rx fifo " |
195 | "but got %d\n", count, rxcount); |
196 | } |
197 | |
198 | rxcount = min(rxcount, count); |
199 | for (i = rxcount; i > 0; i--) { |
200 | data = in_8(&fifo->rxdata_8); |
201 | if (rx_buf) |
202 | *rx_buf++ = data; |
203 | } |
204 | while (in_be32(&fifo->rxcnt)) { |
205 | in_8(&fifo->rxdata_8); |
206 | } |
207 | |
208 | out_8(&psc->command, |
209 | MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); |
210 | } |
211 | /* disable transmiter/receiver and fifo interrupt */ |
212 | out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); |
213 | out_be32(&fifo->tximr, 0); |
214 | return 0; |
215 | } |
216 | |
217 | static void mpc512x_psc_spi_work(struct work_struct *work) |
218 | { |
219 | struct mpc512x_psc_spi *mps = container_of(work, |
220 | struct mpc512x_psc_spi, |
221 | work); |
222 | |
223 | spin_lock_irq(&mps->lock); |
224 | mps->busy = 1; |
225 | while (!list_empty(&mps->queue)) { |
226 | struct spi_message *m; |
227 | struct spi_device *spi; |
228 | struct spi_transfer *t = NULL; |
229 | unsigned cs_change; |
230 | int status; |
231 | |
232 | m = container_of(mps->queue.next, struct spi_message, queue); |
233 | list_del_init(&m->queue); |
234 | spin_unlock_irq(&mps->lock); |
235 | |
236 | spi = m->spi; |
237 | cs_change = 1; |
238 | status = 0; |
239 | list_for_each_entry(t, &m->transfers, transfer_list) { |
240 | if (t->bits_per_word || t->speed_hz) { |
241 | status = mpc512x_psc_spi_transfer_setup(spi, t); |
242 | if (status < 0) |
243 | break; |
244 | } |
245 | |
246 | if (cs_change) |
247 | mpc512x_psc_spi_activate_cs(spi); |
248 | cs_change = t->cs_change; |
249 | |
250 | status = mpc512x_psc_spi_transfer_rxtx(spi, t); |
251 | if (status) |
252 | break; |
253 | m->actual_length += t->len; |
254 | |
255 | if (t->delay_usecs) |
256 | udelay(t->delay_usecs); |
257 | |
258 | if (cs_change) |
259 | mpc512x_psc_spi_deactivate_cs(spi); |
260 | } |
261 | |
262 | m->status = status; |
263 | m->complete(m->context); |
264 | |
265 | if (status || !cs_change) |
266 | mpc512x_psc_spi_deactivate_cs(spi); |
267 | |
268 | mpc512x_psc_spi_transfer_setup(spi, NULL); |
269 | |
270 | spin_lock_irq(&mps->lock); |
271 | } |
272 | mps->busy = 0; |
273 | spin_unlock_irq(&mps->lock); |
274 | } |
275 | |
276 | static int mpc512x_psc_spi_setup(struct spi_device *spi) |
277 | { |
278 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); |
279 | struct mpc512x_psc_spi_cs *cs = spi->controller_state; |
280 | unsigned long flags; |
281 | |
282 | if (spi->bits_per_word % 8) |
283 | return -EINVAL; |
284 | |
285 | if (!cs) { |
286 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
287 | if (!cs) |
288 | return -ENOMEM; |
289 | spi->controller_state = cs; |
290 | } |
291 | |
292 | cs->bits_per_word = spi->bits_per_word; |
293 | cs->speed_hz = spi->max_speed_hz; |
294 | |
295 | spin_lock_irqsave(&mps->lock, flags); |
296 | if (!mps->busy) |
297 | mpc512x_psc_spi_deactivate_cs(spi); |
298 | spin_unlock_irqrestore(&mps->lock, flags); |
299 | |
300 | return 0; |
301 | } |
302 | |
303 | static int mpc512x_psc_spi_transfer(struct spi_device *spi, |
304 | struct spi_message *m) |
305 | { |
306 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); |
307 | unsigned long flags; |
308 | |
309 | m->actual_length = 0; |
310 | m->status = -EINPROGRESS; |
311 | |
312 | spin_lock_irqsave(&mps->lock, flags); |
313 | list_add_tail(&m->queue, &mps->queue); |
314 | queue_work(mps->workqueue, &mps->work); |
315 | spin_unlock_irqrestore(&mps->lock, flags); |
316 | |
317 | return 0; |
318 | } |
319 | |
320 | static void mpc512x_psc_spi_cleanup(struct spi_device *spi) |
321 | { |
322 | kfree(spi->controller_state); |
323 | } |
324 | |
325 | static int mpc512x_psc_spi_port_config(struct spi_master *master, |
326 | struct mpc512x_psc_spi *mps) |
327 | { |
328 | struct mpc52xx_psc __iomem *psc = mps->psc; |
329 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; |
330 | struct clk *spiclk; |
331 | int ret = 0; |
332 | char name[32]; |
333 | u32 sicr; |
334 | u32 ccr; |
335 | u16 bclkdiv; |
336 | |
337 | sprintf(name, "psc%d_mclk", master->bus_num); |
338 | spiclk = clk_get(&master->dev, name); |
339 | clk_enable(spiclk); |
340 | mps->mclk = clk_get_rate(spiclk); |
341 | clk_put(spiclk); |
342 | |
343 | /* Reset the PSC into a known state */ |
344 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
345 | out_8(&psc->command, MPC52xx_PSC_RST_TX); |
346 | out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); |
347 | |
348 | /* Disable psc interrupts all useful interrupts are in fifo */ |
349 | out_be16(&psc->isr_imr.imr, 0); |
350 | |
351 | /* Disable fifo interrupts, will be enabled later */ |
352 | out_be32(&fifo->tximr, 0); |
353 | out_be32(&fifo->rximr, 0); |
354 | |
355 | /* Setup fifo slice address and size */ |
356 | /*out_be32(&fifo->txsz, 0x0fe00004);*/ |
357 | /*out_be32(&fifo->rxsz, 0x0ff00004);*/ |
358 | |
359 | sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */ |
360 | 0x00800000 | /* GenClk = 1 -- internal clk */ |
361 | 0x00008000 | /* SPI = 1 */ |
362 | 0x00004000 | /* MSTR = 1 -- SPI master */ |
363 | 0x00000800; /* UseEOF = 1 -- SS low until EOF */ |
364 | |
365 | out_be32(&psc->sicr, sicr); |
366 | |
367 | ccr = in_be32(&psc->ccr); |
368 | ccr &= 0xFF000000; |
369 | bclkdiv = (mps->mclk / 1000000) - 1; /* default 1MHz */ |
370 | ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); |
371 | out_be32(&psc->ccr, ccr); |
372 | |
373 | /* Set 2ms DTL delay */ |
374 | out_8(&psc->ctur, 0x00); |
375 | out_8(&psc->ctlr, 0x82); |
376 | |
377 | /* we don't use the alarms */ |
378 | out_be32(&fifo->rxalarm, 0xfff); |
379 | out_be32(&fifo->txalarm, 0); |
380 | |
381 | /* Enable FIFO slices for Rx/Tx */ |
382 | out_be32(&fifo->rxcmd, |
383 | MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); |
384 | out_be32(&fifo->txcmd, |
385 | MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); |
386 | |
387 | mps->bits_per_word = 8; |
388 | |
389 | return ret; |
390 | } |
391 | |
392 | static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id) |
393 | { |
394 | struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id; |
395 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; |
396 | |
397 | /* clear interrupt and wake up the work queue */ |
398 | if (in_be32(&fifo->txisr) & |
399 | in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) { |
400 | out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); |
401 | out_be32(&fifo->tximr, 0); |
402 | complete(&mps->done); |
403 | return IRQ_HANDLED; |
404 | } |
405 | return IRQ_NONE; |
406 | } |
407 | |
408 | /* bus_num is used only for the case dev->platform_data == NULL */ |
409 | static int __devinit mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, |
410 | u32 size, unsigned int irq, |
411 | s16 bus_num) |
412 | { |
413 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
414 | struct mpc512x_psc_spi *mps; |
415 | struct spi_master *master; |
416 | int ret; |
417 | void *tempp; |
418 | |
419 | master = spi_alloc_master(dev, sizeof *mps); |
420 | if (master == NULL) |
421 | return -ENOMEM; |
422 | |
423 | dev_set_drvdata(dev, master); |
424 | mps = spi_master_get_devdata(master); |
425 | mps->irq = irq; |
426 | |
427 | if (pdata == NULL) { |
428 | dev_err(dev, "probe called without platform data, no " |
429 | "cs_control function will be called\n"); |
430 | mps->cs_control = NULL; |
431 | mps->sysclk = 0; |
432 | master->bus_num = bus_num; |
433 | master->num_chipselect = 255; |
434 | } else { |
435 | mps->cs_control = pdata->cs_control; |
436 | mps->sysclk = pdata->sysclk; |
437 | master->bus_num = pdata->bus_num; |
438 | master->num_chipselect = pdata->max_chipselect; |
439 | } |
440 | |
441 | master->setup = mpc512x_psc_spi_setup; |
442 | master->transfer = mpc512x_psc_spi_transfer; |
443 | master->cleanup = mpc512x_psc_spi_cleanup; |
444 | master->dev.of_node = dev->of_node; |
445 | |
446 | tempp = ioremap(regaddr, size); |
447 | if (!tempp) { |
448 | dev_err(dev, "could not ioremap I/O port range\n"); |
449 | ret = -EFAULT; |
450 | goto free_master; |
451 | } |
452 | mps->psc = tempp; |
453 | mps->fifo = |
454 | (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc)); |
455 | |
456 | ret = request_irq(mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED, |
457 | "mpc512x-psc-spi", mps); |
458 | if (ret) |
459 | goto free_master; |
460 | |
461 | ret = mpc512x_psc_spi_port_config(master, mps); |
462 | if (ret < 0) |
463 | goto free_irq; |
464 | |
465 | spin_lock_init(&mps->lock); |
466 | init_completion(&mps->done); |
467 | INIT_WORK(&mps->work, mpc512x_psc_spi_work); |
468 | INIT_LIST_HEAD(&mps->queue); |
469 | |
470 | mps->workqueue = |
471 | create_singlethread_workqueue(dev_name(master->dev.parent)); |
472 | if (mps->workqueue == NULL) { |
473 | ret = -EBUSY; |
474 | goto free_irq; |
475 | } |
476 | |
477 | ret = spi_register_master(master); |
478 | if (ret < 0) |
479 | goto unreg_master; |
480 | |
481 | return ret; |
482 | |
483 | unreg_master: |
484 | destroy_workqueue(mps->workqueue); |
485 | free_irq: |
486 | free_irq(mps->irq, mps); |
487 | free_master: |
488 | if (mps->psc) |
489 | iounmap(mps->psc); |
490 | spi_master_put(master); |
491 | |
492 | return ret; |
493 | } |
494 | |
495 | static int __devexit mpc512x_psc_spi_do_remove(struct device *dev) |
496 | { |
497 | struct spi_master *master = dev_get_drvdata(dev); |
498 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); |
499 | |
500 | flush_workqueue(mps->workqueue); |
501 | destroy_workqueue(mps->workqueue); |
502 | spi_unregister_master(master); |
503 | free_irq(mps->irq, mps); |
504 | if (mps->psc) |
505 | iounmap(mps->psc); |
506 | |
507 | return 0; |
508 | } |
509 | |
510 | static int __devinit mpc512x_psc_spi_of_probe(struct platform_device *op, |
511 | const struct of_device_id *match) |
512 | { |
513 | const u32 *regaddr_p; |
514 | u64 regaddr64, size64; |
515 | s16 id = -1; |
516 | |
517 | regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL); |
518 | if (!regaddr_p) { |
519 | dev_err(&op->dev, "Invalid PSC address\n"); |
520 | return -EINVAL; |
521 | } |
522 | regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); |
523 | |
524 | /* get PSC id (0..11, used by port_config) */ |
525 | if (op->dev.platform_data == NULL) { |
526 | const u32 *psc_nump; |
527 | |
528 | psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL); |
529 | if (!psc_nump || *psc_nump > 11) { |
530 | dev_err(&op->dev, "mpc512x_psc_spi: Device node %s " |
531 | "has invalid cell-index property\n", |
532 | op->dev.of_node->full_name); |
533 | return -EINVAL; |
534 | } |
535 | id = *psc_nump; |
536 | } |
537 | |
538 | return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64, |
539 | irq_of_parse_and_map(op->dev.of_node, 0), id); |
540 | } |
541 | |
542 | static int __devexit mpc512x_psc_spi_of_remove(struct platform_device *op) |
543 | { |
544 | return mpc512x_psc_spi_do_remove(&op->dev); |
545 | } |
546 | |
547 | static struct of_device_id mpc512x_psc_spi_of_match[] = { |
548 | { .compatible = "fsl,mpc5121-psc-spi", }, |
549 | {}, |
550 | }; |
551 | |
552 | MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match); |
553 | |
554 | static struct of_platform_driver mpc512x_psc_spi_of_driver = { |
555 | .probe = mpc512x_psc_spi_of_probe, |
556 | .remove = __devexit_p(mpc512x_psc_spi_of_remove), |
557 | .driver = { |
558 | .name = "mpc512x-psc-spi", |
559 | .owner = THIS_MODULE, |
560 | .of_match_table = mpc512x_psc_spi_of_match, |
561 | }, |
562 | }; |
563 | |
564 | static int __init mpc512x_psc_spi_init(void) |
565 | { |
566 | return of_register_platform_driver(&mpc512x_psc_spi_of_driver); |
567 | } |
568 | module_init(mpc512x_psc_spi_init); |
569 | |
570 | static void __exit mpc512x_psc_spi_exit(void) |
571 | { |
572 | of_unregister_platform_driver(&mpc512x_psc_spi_of_driver); |
573 | } |
574 | module_exit(mpc512x_psc_spi_exit); |
575 | |
576 | MODULE_AUTHOR("John Rigby"); |
577 | MODULE_DESCRIPTION("MPC512x PSC SPI Driver"); |
578 | MODULE_LICENSE("GPL"); |
579 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9