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Source at commit 6c17a31f1fc515425221067cb3ece599c09dbc5d created 12 years 8 months ago. By Werner Almesberger, atusb, atben: moved from spi/ to ieee802154/; renamed atusb to spi_atusb | |
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1 | /* |
2 | * OMAP2 McSPI controller driver |
3 | * |
4 | * Copyright (C) 2005, 2006 Nokia Corporation |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and |
6 | * Juha Yrjölä <juha.yrjola@nokia.com> |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; either version 2 of the License, or |
11 | * (at your option) any later version. |
12 | * |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | * GNU General Public License for more details. |
17 | * |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program; if not, write to the Free Software |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
21 | * |
22 | */ |
23 | |
24 | #include <linux/kernel.h> |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> |
27 | #include <linux/module.h> |
28 | #include <linux/device.h> |
29 | #include <linux/delay.h> |
30 | #include <linux/dma-mapping.h> |
31 | #include <linux/platform_device.h> |
32 | #include <linux/err.h> |
33 | #include <linux/clk.h> |
34 | #include <linux/io.h> |
35 | #include <linux/slab.h> |
36 | |
37 | #include <linux/spi/spi.h> |
38 | |
39 | #include <plat/dma.h> |
40 | #include <plat/clock.h> |
41 | #include <plat/mcspi.h> |
42 | |
43 | #define OMAP2_MCSPI_MAX_FREQ 48000000 |
44 | |
45 | /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */ |
46 | #define OMAP2_MCSPI_MAX_CTRL 4 |
47 | |
48 | #define OMAP2_MCSPI_REVISION 0x00 |
49 | #define OMAP2_MCSPI_SYSCONFIG 0x10 |
50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
51 | #define OMAP2_MCSPI_IRQSTATUS 0x18 |
52 | #define OMAP2_MCSPI_IRQENABLE 0x1c |
53 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 |
54 | #define OMAP2_MCSPI_SYST 0x24 |
55 | #define OMAP2_MCSPI_MODULCTRL 0x28 |
56 | |
57 | /* per-channel banks, 0x14 bytes each, first is: */ |
58 | #define OMAP2_MCSPI_CHCONF0 0x2c |
59 | #define OMAP2_MCSPI_CHSTAT0 0x30 |
60 | #define OMAP2_MCSPI_CHCTRL0 0x34 |
61 | #define OMAP2_MCSPI_TX0 0x38 |
62 | #define OMAP2_MCSPI_RX0 0x3c |
63 | |
64 | /* per-register bitmasks: */ |
65 | |
66 | #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4) |
67 | #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) |
68 | #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) |
69 | #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1) |
70 | |
71 | #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0) |
72 | |
73 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
74 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) |
75 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) |
76 | |
77 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
78 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) |
79 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
80 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
81 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
82 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
83 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) |
84 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
85 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
86 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) |
87 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) |
88 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) |
89 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) |
90 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) |
91 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) |
92 | |
93 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
94 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) |
95 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) |
96 | |
97 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
98 | |
99 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
100 | |
101 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
102 | struct omap2_mcspi_dma { |
103 | int dma_tx_channel; |
104 | int dma_rx_channel; |
105 | |
106 | int dma_tx_sync_dev; |
107 | int dma_rx_sync_dev; |
108 | |
109 | struct completion dma_tx_completion; |
110 | struct completion dma_rx_completion; |
111 | }; |
112 | |
113 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
114 | * cache operations; better heuristics consider wordsize and bitrate. |
115 | */ |
116 | #define DMA_MIN_BYTES 160 |
117 | |
118 | |
119 | struct omap2_mcspi { |
120 | struct work_struct work; |
121 | /* lock protects queue and registers */ |
122 | spinlock_t lock; |
123 | struct list_head msg_queue; |
124 | struct spi_master *master; |
125 | struct clk *ick; |
126 | struct clk *fck; |
127 | /* Virtual base address of the controller */ |
128 | void __iomem *base; |
129 | unsigned long phys; |
130 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
131 | struct omap2_mcspi_dma *dma_channels; |
132 | }; |
133 | |
134 | struct omap2_mcspi_cs { |
135 | void __iomem *base; |
136 | unsigned long phys; |
137 | int word_len; |
138 | struct list_head node; |
139 | /* Context save and restore shadow register */ |
140 | u32 chconf0; |
141 | }; |
142 | |
143 | /* used for context save and restore, structure members to be updated whenever |
144 | * corresponding registers are modified. |
145 | */ |
146 | struct omap2_mcspi_regs { |
147 | u32 sysconfig; |
148 | u32 modulctrl; |
149 | u32 wakeupenable; |
150 | struct list_head cs; |
151 | }; |
152 | |
153 | static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL]; |
154 | |
155 | static struct workqueue_struct *omap2_mcspi_wq; |
156 | |
157 | #define MOD_REG_BIT(val, mask, set) do { \ |
158 | if (set) \ |
159 | val |= mask; \ |
160 | else \ |
161 | val &= ~mask; \ |
162 | } while (0) |
163 | |
164 | static inline void mcspi_write_reg(struct spi_master *master, |
165 | int idx, u32 val) |
166 | { |
167 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
168 | |
169 | __raw_writel(val, mcspi->base + idx); |
170 | } |
171 | |
172 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) |
173 | { |
174 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
175 | |
176 | return __raw_readl(mcspi->base + idx); |
177 | } |
178 | |
179 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, |
180 | int idx, u32 val) |
181 | { |
182 | struct omap2_mcspi_cs *cs = spi->controller_state; |
183 | |
184 | __raw_writel(val, cs->base + idx); |
185 | } |
186 | |
187 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) |
188 | { |
189 | struct omap2_mcspi_cs *cs = spi->controller_state; |
190 | |
191 | return __raw_readl(cs->base + idx); |
192 | } |
193 | |
194 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
195 | { |
196 | struct omap2_mcspi_cs *cs = spi->controller_state; |
197 | |
198 | return cs->chconf0; |
199 | } |
200 | |
201 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) |
202 | { |
203 | struct omap2_mcspi_cs *cs = spi->controller_state; |
204 | |
205 | cs->chconf0 = val; |
206 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); |
207 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
208 | } |
209 | |
210 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
211 | int is_read, int enable) |
212 | { |
213 | u32 l, rw; |
214 | |
215 | l = mcspi_cached_chconf0(spi); |
216 | |
217 | if (is_read) /* 1 is read, 0 write */ |
218 | rw = OMAP2_MCSPI_CHCONF_DMAR; |
219 | else |
220 | rw = OMAP2_MCSPI_CHCONF_DMAW; |
221 | |
222 | MOD_REG_BIT(l, rw, enable); |
223 | mcspi_write_chconf0(spi, l); |
224 | } |
225 | |
226 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) |
227 | { |
228 | u32 l; |
229 | |
230 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; |
231 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); |
232 | /* Flash post-writes */ |
233 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); |
234 | } |
235 | |
236 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) |
237 | { |
238 | u32 l; |
239 | |
240 | l = mcspi_cached_chconf0(spi); |
241 | MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); |
242 | mcspi_write_chconf0(spi, l); |
243 | } |
244 | |
245 | static void omap2_mcspi_set_master_mode(struct spi_master *master) |
246 | { |
247 | u32 l; |
248 | |
249 | /* setup when switching from (reset default) slave mode |
250 | * to single-channel master mode |
251 | */ |
252 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); |
253 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0); |
254 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); |
255 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); |
256 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
257 | |
258 | omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l; |
259 | } |
260 | |
261 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
262 | { |
263 | struct spi_master *spi_cntrl; |
264 | struct omap2_mcspi_cs *cs; |
265 | spi_cntrl = mcspi->master; |
266 | |
267 | /* McSPI: context restore */ |
268 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, |
269 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); |
270 | |
271 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG, |
272 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig); |
273 | |
274 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, |
275 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); |
276 | |
277 | list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs, |
278 | node) |
279 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
280 | } |
281 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) |
282 | { |
283 | clk_disable(mcspi->ick); |
284 | clk_disable(mcspi->fck); |
285 | } |
286 | |
287 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) |
288 | { |
289 | if (clk_enable(mcspi->ick)) |
290 | return -ENODEV; |
291 | if (clk_enable(mcspi->fck)) |
292 | return -ENODEV; |
293 | |
294 | omap2_mcspi_restore_ctx(mcspi); |
295 | |
296 | return 0; |
297 | } |
298 | |
299 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
300 | { |
301 | unsigned long timeout; |
302 | |
303 | timeout = jiffies + msecs_to_jiffies(1000); |
304 | while (!(__raw_readl(reg) & bit)) { |
305 | if (time_after(jiffies, timeout)) |
306 | return -1; |
307 | cpu_relax(); |
308 | } |
309 | return 0; |
310 | } |
311 | |
312 | static unsigned |
313 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) |
314 | { |
315 | struct omap2_mcspi *mcspi; |
316 | struct omap2_mcspi_cs *cs = spi->controller_state; |
317 | struct omap2_mcspi_dma *mcspi_dma; |
318 | unsigned int count, c; |
319 | unsigned long base, tx_reg, rx_reg; |
320 | int word_len, data_type, element_count; |
321 | int elements; |
322 | u32 l; |
323 | u8 * rx; |
324 | const u8 * tx; |
325 | void __iomem *chstat_reg; |
326 | |
327 | mcspi = spi_master_get_devdata(spi->master); |
328 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
329 | l = mcspi_cached_chconf0(spi); |
330 | |
331 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
332 | |
333 | count = xfer->len; |
334 | c = count; |
335 | word_len = cs->word_len; |
336 | |
337 | base = cs->phys; |
338 | tx_reg = base + OMAP2_MCSPI_TX0; |
339 | rx_reg = base + OMAP2_MCSPI_RX0; |
340 | rx = xfer->rx_buf; |
341 | tx = xfer->tx_buf; |
342 | |
343 | if (word_len <= 8) { |
344 | data_type = OMAP_DMA_DATA_TYPE_S8; |
345 | element_count = count; |
346 | } else if (word_len <= 16) { |
347 | data_type = OMAP_DMA_DATA_TYPE_S16; |
348 | element_count = count >> 1; |
349 | } else /* word_len <= 32 */ { |
350 | data_type = OMAP_DMA_DATA_TYPE_S32; |
351 | element_count = count >> 2; |
352 | } |
353 | |
354 | if (tx != NULL) { |
355 | omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel, |
356 | data_type, element_count, 1, |
357 | OMAP_DMA_SYNC_ELEMENT, |
358 | mcspi_dma->dma_tx_sync_dev, 0); |
359 | |
360 | omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0, |
361 | OMAP_DMA_AMODE_CONSTANT, |
362 | tx_reg, 0, 0); |
363 | |
364 | omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0, |
365 | OMAP_DMA_AMODE_POST_INC, |
366 | xfer->tx_dma, 0, 0); |
367 | } |
368 | |
369 | if (rx != NULL) { |
370 | elements = element_count - 1; |
371 | if (l & OMAP2_MCSPI_CHCONF_TURBO) |
372 | elements--; |
373 | |
374 | omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, |
375 | data_type, elements, 1, |
376 | OMAP_DMA_SYNC_ELEMENT, |
377 | mcspi_dma->dma_rx_sync_dev, 1); |
378 | |
379 | omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0, |
380 | OMAP_DMA_AMODE_CONSTANT, |
381 | rx_reg, 0, 0); |
382 | |
383 | omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0, |
384 | OMAP_DMA_AMODE_POST_INC, |
385 | xfer->rx_dma, 0, 0); |
386 | } |
387 | |
388 | if (tx != NULL) { |
389 | omap_start_dma(mcspi_dma->dma_tx_channel); |
390 | omap2_mcspi_set_dma_req(spi, 0, 1); |
391 | } |
392 | |
393 | if (rx != NULL) { |
394 | omap_start_dma(mcspi_dma->dma_rx_channel); |
395 | omap2_mcspi_set_dma_req(spi, 1, 1); |
396 | } |
397 | |
398 | if (tx != NULL) { |
399 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
400 | dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE); |
401 | |
402 | /* for TX_ONLY mode, be sure all words have shifted out */ |
403 | if (rx == NULL) { |
404 | if (mcspi_wait_for_reg_bit(chstat_reg, |
405 | OMAP2_MCSPI_CHSTAT_TXS) < 0) |
406 | dev_err(&spi->dev, "TXS timed out\n"); |
407 | else if (mcspi_wait_for_reg_bit(chstat_reg, |
408 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
409 | dev_err(&spi->dev, "EOT timed out\n"); |
410 | } |
411 | } |
412 | |
413 | if (rx != NULL) { |
414 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
415 | dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE); |
416 | omap2_mcspi_set_enable(spi, 0); |
417 | |
418 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
419 | |
420 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
421 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
422 | u32 w; |
423 | |
424 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
425 | if (word_len <= 8) |
426 | ((u8 *)xfer->rx_buf)[elements++] = w; |
427 | else if (word_len <= 16) |
428 | ((u16 *)xfer->rx_buf)[elements++] = w; |
429 | else /* word_len <= 32 */ |
430 | ((u32 *)xfer->rx_buf)[elements++] = w; |
431 | } else { |
432 | dev_err(&spi->dev, |
433 | "DMA RX penultimate word empty"); |
434 | count -= (word_len <= 8) ? 2 : |
435 | (word_len <= 16) ? 4 : |
436 | /* word_len <= 32 */ 8; |
437 | omap2_mcspi_set_enable(spi, 1); |
438 | return count; |
439 | } |
440 | } |
441 | |
442 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
443 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
444 | u32 w; |
445 | |
446 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
447 | if (word_len <= 8) |
448 | ((u8 *)xfer->rx_buf)[elements] = w; |
449 | else if (word_len <= 16) |
450 | ((u16 *)xfer->rx_buf)[elements] = w; |
451 | else /* word_len <= 32 */ |
452 | ((u32 *)xfer->rx_buf)[elements] = w; |
453 | } else { |
454 | dev_err(&spi->dev, "DMA RX last word empty"); |
455 | count -= (word_len <= 8) ? 1 : |
456 | (word_len <= 16) ? 2 : |
457 | /* word_len <= 32 */ 4; |
458 | } |
459 | omap2_mcspi_set_enable(spi, 1); |
460 | } |
461 | return count; |
462 | } |
463 | |
464 | static unsigned |
465 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) |
466 | { |
467 | struct omap2_mcspi *mcspi; |
468 | struct omap2_mcspi_cs *cs = spi->controller_state; |
469 | unsigned int count, c; |
470 | u32 l; |
471 | void __iomem *base = cs->base; |
472 | void __iomem *tx_reg; |
473 | void __iomem *rx_reg; |
474 | void __iomem *chstat_reg; |
475 | int word_len; |
476 | |
477 | mcspi = spi_master_get_devdata(spi->master); |
478 | count = xfer->len; |
479 | c = count; |
480 | word_len = cs->word_len; |
481 | |
482 | l = mcspi_cached_chconf0(spi); |
483 | |
484 | /* We store the pre-calculated register addresses on stack to speed |
485 | * up the transfer loop. */ |
486 | tx_reg = base + OMAP2_MCSPI_TX0; |
487 | rx_reg = base + OMAP2_MCSPI_RX0; |
488 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; |
489 | |
490 | if (word_len <= 8) { |
491 | u8 *rx; |
492 | const u8 *tx; |
493 | |
494 | rx = xfer->rx_buf; |
495 | tx = xfer->tx_buf; |
496 | |
497 | do { |
498 | c -= 1; |
499 | if (tx != NULL) { |
500 | if (mcspi_wait_for_reg_bit(chstat_reg, |
501 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
502 | dev_err(&spi->dev, "TXS timed out\n"); |
503 | goto out; |
504 | } |
505 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
506 | word_len, *tx); |
507 | __raw_writel(*tx++, tx_reg); |
508 | } |
509 | if (rx != NULL) { |
510 | if (mcspi_wait_for_reg_bit(chstat_reg, |
511 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
512 | dev_err(&spi->dev, "RXS timed out\n"); |
513 | goto out; |
514 | } |
515 | |
516 | if (c == 1 && tx == NULL && |
517 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
518 | omap2_mcspi_set_enable(spi, 0); |
519 | *rx++ = __raw_readl(rx_reg); |
520 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
521 | word_len, *(rx - 1)); |
522 | if (mcspi_wait_for_reg_bit(chstat_reg, |
523 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
524 | dev_err(&spi->dev, |
525 | "RXS timed out\n"); |
526 | goto out; |
527 | } |
528 | c = 0; |
529 | } else if (c == 0 && tx == NULL) { |
530 | omap2_mcspi_set_enable(spi, 0); |
531 | } |
532 | |
533 | *rx++ = __raw_readl(rx_reg); |
534 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
535 | word_len, *(rx - 1)); |
536 | } |
537 | } while (c); |
538 | } else if (word_len <= 16) { |
539 | u16 *rx; |
540 | const u16 *tx; |
541 | |
542 | rx = xfer->rx_buf; |
543 | tx = xfer->tx_buf; |
544 | do { |
545 | c -= 2; |
546 | if (tx != NULL) { |
547 | if (mcspi_wait_for_reg_bit(chstat_reg, |
548 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
549 | dev_err(&spi->dev, "TXS timed out\n"); |
550 | goto out; |
551 | } |
552 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
553 | word_len, *tx); |
554 | __raw_writel(*tx++, tx_reg); |
555 | } |
556 | if (rx != NULL) { |
557 | if (mcspi_wait_for_reg_bit(chstat_reg, |
558 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
559 | dev_err(&spi->dev, "RXS timed out\n"); |
560 | goto out; |
561 | } |
562 | |
563 | if (c == 2 && tx == NULL && |
564 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
565 | omap2_mcspi_set_enable(spi, 0); |
566 | *rx++ = __raw_readl(rx_reg); |
567 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
568 | word_len, *(rx - 1)); |
569 | if (mcspi_wait_for_reg_bit(chstat_reg, |
570 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
571 | dev_err(&spi->dev, |
572 | "RXS timed out\n"); |
573 | goto out; |
574 | } |
575 | c = 0; |
576 | } else if (c == 0 && tx == NULL) { |
577 | omap2_mcspi_set_enable(spi, 0); |
578 | } |
579 | |
580 | *rx++ = __raw_readl(rx_reg); |
581 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
582 | word_len, *(rx - 1)); |
583 | } |
584 | } while (c); |
585 | } else if (word_len <= 32) { |
586 | u32 *rx; |
587 | const u32 *tx; |
588 | |
589 | rx = xfer->rx_buf; |
590 | tx = xfer->tx_buf; |
591 | do { |
592 | c -= 4; |
593 | if (tx != NULL) { |
594 | if (mcspi_wait_for_reg_bit(chstat_reg, |
595 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
596 | dev_err(&spi->dev, "TXS timed out\n"); |
597 | goto out; |
598 | } |
599 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
600 | word_len, *tx); |
601 | __raw_writel(*tx++, tx_reg); |
602 | } |
603 | if (rx != NULL) { |
604 | if (mcspi_wait_for_reg_bit(chstat_reg, |
605 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
606 | dev_err(&spi->dev, "RXS timed out\n"); |
607 | goto out; |
608 | } |
609 | |
610 | if (c == 4 && tx == NULL && |
611 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
612 | omap2_mcspi_set_enable(spi, 0); |
613 | *rx++ = __raw_readl(rx_reg); |
614 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
615 | word_len, *(rx - 1)); |
616 | if (mcspi_wait_for_reg_bit(chstat_reg, |
617 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
618 | dev_err(&spi->dev, |
619 | "RXS timed out\n"); |
620 | goto out; |
621 | } |
622 | c = 0; |
623 | } else if (c == 0 && tx == NULL) { |
624 | omap2_mcspi_set_enable(spi, 0); |
625 | } |
626 | |
627 | *rx++ = __raw_readl(rx_reg); |
628 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
629 | word_len, *(rx - 1)); |
630 | } |
631 | } while (c); |
632 | } |
633 | |
634 | /* for TX_ONLY mode, be sure all words have shifted out */ |
635 | if (xfer->rx_buf == NULL) { |
636 | if (mcspi_wait_for_reg_bit(chstat_reg, |
637 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
638 | dev_err(&spi->dev, "TXS timed out\n"); |
639 | } else if (mcspi_wait_for_reg_bit(chstat_reg, |
640 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
641 | dev_err(&spi->dev, "EOT timed out\n"); |
642 | |
643 | /* disable chan to purge rx datas received in TX_ONLY transfer, |
644 | * otherwise these rx datas will affect the direct following |
645 | * RX_ONLY transfer. |
646 | */ |
647 | omap2_mcspi_set_enable(spi, 0); |
648 | } |
649 | out: |
650 | omap2_mcspi_set_enable(spi, 1); |
651 | return count - c; |
652 | } |
653 | |
654 | /* called only when no transfer is active to this device */ |
655 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, |
656 | struct spi_transfer *t) |
657 | { |
658 | struct omap2_mcspi_cs *cs = spi->controller_state; |
659 | struct omap2_mcspi *mcspi; |
660 | struct spi_master *spi_cntrl; |
661 | u32 l = 0, div = 0; |
662 | u8 word_len = spi->bits_per_word; |
663 | u32 speed_hz = spi->max_speed_hz; |
664 | |
665 | mcspi = spi_master_get_devdata(spi->master); |
666 | spi_cntrl = mcspi->master; |
667 | |
668 | if (t != NULL && t->bits_per_word) |
669 | word_len = t->bits_per_word; |
670 | |
671 | cs->word_len = word_len; |
672 | |
673 | if (t && t->speed_hz) |
674 | speed_hz = t->speed_hz; |
675 | |
676 | if (speed_hz) { |
677 | while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div)) |
678 | > speed_hz) |
679 | div++; |
680 | } else |
681 | div = 15; |
682 | |
683 | l = mcspi_cached_chconf0(spi); |
684 | |
685 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS |
686 | * REVISIT: this controller could support SPI_3WIRE mode. |
687 | */ |
688 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); |
689 | l |= OMAP2_MCSPI_CHCONF_DPE0; |
690 | |
691 | /* wordlength */ |
692 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; |
693 | l |= (word_len - 1) << 7; |
694 | |
695 | /* set chipselect polarity; manage with FORCE */ |
696 | if (!(spi->mode & SPI_CS_HIGH)) |
697 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ |
698 | else |
699 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; |
700 | |
701 | /* set clock divisor */ |
702 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; |
703 | l |= div << 2; |
704 | |
705 | /* set SPI mode 0..3 */ |
706 | if (spi->mode & SPI_CPOL) |
707 | l |= OMAP2_MCSPI_CHCONF_POL; |
708 | else |
709 | l &= ~OMAP2_MCSPI_CHCONF_POL; |
710 | if (spi->mode & SPI_CPHA) |
711 | l |= OMAP2_MCSPI_CHCONF_PHA; |
712 | else |
713 | l &= ~OMAP2_MCSPI_CHCONF_PHA; |
714 | |
715 | mcspi_write_chconf0(spi, l); |
716 | |
717 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
718 | OMAP2_MCSPI_MAX_FREQ / (1 << div), |
719 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
720 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); |
721 | |
722 | return 0; |
723 | } |
724 | |
725 | static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data) |
726 | { |
727 | struct spi_device *spi = data; |
728 | struct omap2_mcspi *mcspi; |
729 | struct omap2_mcspi_dma *mcspi_dma; |
730 | |
731 | mcspi = spi_master_get_devdata(spi->master); |
732 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); |
733 | |
734 | complete(&mcspi_dma->dma_rx_completion); |
735 | |
736 | /* We must disable the DMA RX request */ |
737 | omap2_mcspi_set_dma_req(spi, 1, 0); |
738 | } |
739 | |
740 | static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data) |
741 | { |
742 | struct spi_device *spi = data; |
743 | struct omap2_mcspi *mcspi; |
744 | struct omap2_mcspi_dma *mcspi_dma; |
745 | |
746 | mcspi = spi_master_get_devdata(spi->master); |
747 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); |
748 | |
749 | complete(&mcspi_dma->dma_tx_completion); |
750 | |
751 | /* We must disable the DMA TX request */ |
752 | omap2_mcspi_set_dma_req(spi, 0, 0); |
753 | } |
754 | |
755 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
756 | { |
757 | struct spi_master *master = spi->master; |
758 | struct omap2_mcspi *mcspi; |
759 | struct omap2_mcspi_dma *mcspi_dma; |
760 | |
761 | mcspi = spi_master_get_devdata(master); |
762 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
763 | |
764 | if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX", |
765 | omap2_mcspi_dma_rx_callback, spi, |
766 | &mcspi_dma->dma_rx_channel)) { |
767 | dev_err(&spi->dev, "no RX DMA channel for McSPI\n"); |
768 | return -EAGAIN; |
769 | } |
770 | |
771 | if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX", |
772 | omap2_mcspi_dma_tx_callback, spi, |
773 | &mcspi_dma->dma_tx_channel)) { |
774 | omap_free_dma(mcspi_dma->dma_rx_channel); |
775 | mcspi_dma->dma_rx_channel = -1; |
776 | dev_err(&spi->dev, "no TX DMA channel for McSPI\n"); |
777 | return -EAGAIN; |
778 | } |
779 | |
780 | init_completion(&mcspi_dma->dma_rx_completion); |
781 | init_completion(&mcspi_dma->dma_tx_completion); |
782 | |
783 | return 0; |
784 | } |
785 | |
786 | static int omap2_mcspi_setup(struct spi_device *spi) |
787 | { |
788 | int ret; |
789 | struct omap2_mcspi *mcspi; |
790 | struct omap2_mcspi_dma *mcspi_dma; |
791 | struct omap2_mcspi_cs *cs = spi->controller_state; |
792 | |
793 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
794 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
795 | spi->bits_per_word); |
796 | return -EINVAL; |
797 | } |
798 | |
799 | mcspi = spi_master_get_devdata(spi->master); |
800 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
801 | |
802 | if (!cs) { |
803 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
804 | if (!cs) |
805 | return -ENOMEM; |
806 | cs->base = mcspi->base + spi->chip_select * 0x14; |
807 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
808 | cs->chconf0 = 0; |
809 | spi->controller_state = cs; |
810 | /* Link this to context save list */ |
811 | list_add_tail(&cs->node, |
812 | &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs); |
813 | } |
814 | |
815 | if (mcspi_dma->dma_rx_channel == -1 |
816 | || mcspi_dma->dma_tx_channel == -1) { |
817 | ret = omap2_mcspi_request_dma(spi); |
818 | if (ret < 0) |
819 | return ret; |
820 | } |
821 | |
822 | if (omap2_mcspi_enable_clocks(mcspi)) |
823 | return -ENODEV; |
824 | |
825 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
826 | omap2_mcspi_disable_clocks(mcspi); |
827 | |
828 | return ret; |
829 | } |
830 | |
831 | static void omap2_mcspi_cleanup(struct spi_device *spi) |
832 | { |
833 | struct omap2_mcspi *mcspi; |
834 | struct omap2_mcspi_dma *mcspi_dma; |
835 | struct omap2_mcspi_cs *cs; |
836 | |
837 | mcspi = spi_master_get_devdata(spi->master); |
838 | |
839 | if (spi->controller_state) { |
840 | /* Unlink controller state from context save list */ |
841 | cs = spi->controller_state; |
842 | list_del(&cs->node); |
843 | |
844 | kfree(spi->controller_state); |
845 | } |
846 | |
847 | if (spi->chip_select < spi->master->num_chipselect) { |
848 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
849 | |
850 | if (mcspi_dma->dma_rx_channel != -1) { |
851 | omap_free_dma(mcspi_dma->dma_rx_channel); |
852 | mcspi_dma->dma_rx_channel = -1; |
853 | } |
854 | if (mcspi_dma->dma_tx_channel != -1) { |
855 | omap_free_dma(mcspi_dma->dma_tx_channel); |
856 | mcspi_dma->dma_tx_channel = -1; |
857 | } |
858 | } |
859 | } |
860 | |
861 | static void omap2_mcspi_work(struct work_struct *work) |
862 | { |
863 | struct omap2_mcspi *mcspi; |
864 | |
865 | mcspi = container_of(work, struct omap2_mcspi, work); |
866 | spin_lock_irq(&mcspi->lock); |
867 | |
868 | if (omap2_mcspi_enable_clocks(mcspi)) |
869 | goto out; |
870 | |
871 | /* We only enable one channel at a time -- the one whose message is |
872 | * at the head of the queue -- although this controller would gladly |
873 | * arbitrate among multiple channels. This corresponds to "single |
874 | * channel" master mode. As a side effect, we need to manage the |
875 | * chipselect with the FORCE bit ... CS != channel enable. |
876 | */ |
877 | while (!list_empty(&mcspi->msg_queue)) { |
878 | struct spi_message *m; |
879 | struct spi_device *spi; |
880 | struct spi_transfer *t = NULL; |
881 | int cs_active = 0; |
882 | struct omap2_mcspi_cs *cs; |
883 | struct omap2_mcspi_device_config *cd; |
884 | int par_override = 0; |
885 | int status = 0; |
886 | u32 chconf; |
887 | |
888 | m = container_of(mcspi->msg_queue.next, struct spi_message, |
889 | queue); |
890 | |
891 | list_del_init(&m->queue); |
892 | spin_unlock_irq(&mcspi->lock); |
893 | |
894 | spi = m->spi; |
895 | cs = spi->controller_state; |
896 | cd = spi->controller_data; |
897 | |
898 | omap2_mcspi_set_enable(spi, 1); |
899 | list_for_each_entry(t, &m->transfers, transfer_list) { |
900 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { |
901 | status = -EINVAL; |
902 | break; |
903 | } |
904 | if (par_override || t->speed_hz || t->bits_per_word) { |
905 | par_override = 1; |
906 | status = omap2_mcspi_setup_transfer(spi, t); |
907 | if (status < 0) |
908 | break; |
909 | if (!t->speed_hz && !t->bits_per_word) |
910 | par_override = 0; |
911 | } |
912 | |
913 | if (!cs_active) { |
914 | omap2_mcspi_force_cs(spi, 1); |
915 | cs_active = 1; |
916 | } |
917 | |
918 | chconf = mcspi_cached_chconf0(spi); |
919 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
920 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; |
921 | |
922 | if (t->tx_buf == NULL) |
923 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; |
924 | else if (t->rx_buf == NULL) |
925 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; |
926 | |
927 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
928 | /* Turbo mode is for more than one word */ |
929 | if (t->len > ((cs->word_len + 7) >> 3)) |
930 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; |
931 | } |
932 | |
933 | mcspi_write_chconf0(spi, chconf); |
934 | |
935 | if (t->len) { |
936 | unsigned count; |
937 | |
938 | /* RX_ONLY mode needs dummy data in TX reg */ |
939 | if (t->tx_buf == NULL) |
940 | __raw_writel(0, cs->base |
941 | + OMAP2_MCSPI_TX0); |
942 | |
943 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
944 | count = omap2_mcspi_txrx_dma(spi, t); |
945 | else |
946 | count = omap2_mcspi_txrx_pio(spi, t); |
947 | m->actual_length += count; |
948 | |
949 | if (count != t->len) { |
950 | status = -EIO; |
951 | break; |
952 | } |
953 | } |
954 | |
955 | if (t->delay_usecs) |
956 | udelay(t->delay_usecs); |
957 | |
958 | /* ignore the "leave it on after last xfer" hint */ |
959 | if (t->cs_change) { |
960 | omap2_mcspi_force_cs(spi, 0); |
961 | cs_active = 0; |
962 | } |
963 | } |
964 | |
965 | /* Restore defaults if they were overriden */ |
966 | if (par_override) { |
967 | par_override = 0; |
968 | status = omap2_mcspi_setup_transfer(spi, NULL); |
969 | } |
970 | |
971 | if (cs_active) |
972 | omap2_mcspi_force_cs(spi, 0); |
973 | |
974 | omap2_mcspi_set_enable(spi, 0); |
975 | |
976 | m->status = status; |
977 | m->complete(m->context); |
978 | |
979 | spin_lock_irq(&mcspi->lock); |
980 | } |
981 | |
982 | omap2_mcspi_disable_clocks(mcspi); |
983 | |
984 | out: |
985 | spin_unlock_irq(&mcspi->lock); |
986 | } |
987 | |
988 | static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) |
989 | { |
990 | struct omap2_mcspi *mcspi; |
991 | unsigned long flags; |
992 | struct spi_transfer *t; |
993 | |
994 | m->actual_length = 0; |
995 | m->status = 0; |
996 | |
997 | /* reject invalid messages and transfers */ |
998 | if (list_empty(&m->transfers) || !m->complete) |
999 | return -EINVAL; |
1000 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1001 | const void *tx_buf = t->tx_buf; |
1002 | void *rx_buf = t->rx_buf; |
1003 | unsigned len = t->len; |
1004 | |
1005 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ |
1006 | || (len && !(rx_buf || tx_buf)) |
1007 | || (t->bits_per_word && |
1008 | ( t->bits_per_word < 4 |
1009 | || t->bits_per_word > 32))) { |
1010 | dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
1011 | t->speed_hz, |
1012 | len, |
1013 | tx_buf ? "tx" : "", |
1014 | rx_buf ? "rx" : "", |
1015 | t->bits_per_word); |
1016 | return -EINVAL; |
1017 | } |
1018 | if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) { |
1019 | dev_dbg(&spi->dev, "%d Hz max exceeds %d\n", |
1020 | t->speed_hz, |
1021 | OMAP2_MCSPI_MAX_FREQ/(1<<16)); |
1022 | return -EINVAL; |
1023 | } |
1024 | |
1025 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) |
1026 | continue; |
1027 | |
1028 | if (tx_buf != NULL) { |
1029 | t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf, |
1030 | len, DMA_TO_DEVICE); |
1031 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
1032 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
1033 | 'T', len); |
1034 | return -EINVAL; |
1035 | } |
1036 | } |
1037 | if (rx_buf != NULL) { |
1038 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len, |
1039 | DMA_FROM_DEVICE); |
1040 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { |
1041 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
1042 | 'R', len); |
1043 | if (tx_buf != NULL) |
1044 | dma_unmap_single(&spi->dev, t->tx_dma, |
1045 | len, DMA_TO_DEVICE); |
1046 | return -EINVAL; |
1047 | } |
1048 | } |
1049 | } |
1050 | |
1051 | mcspi = spi_master_get_devdata(spi->master); |
1052 | |
1053 | spin_lock_irqsave(&mcspi->lock, flags); |
1054 | list_add_tail(&m->queue, &mcspi->msg_queue); |
1055 | queue_work(omap2_mcspi_wq, &mcspi->work); |
1056 | spin_unlock_irqrestore(&mcspi->lock, flags); |
1057 | |
1058 | return 0; |
1059 | } |
1060 | |
1061 | static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) |
1062 | { |
1063 | struct spi_master *master = mcspi->master; |
1064 | u32 tmp; |
1065 | |
1066 | if (omap2_mcspi_enable_clocks(mcspi)) |
1067 | return -1; |
1068 | |
1069 | mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, |
1070 | OMAP2_MCSPI_SYSCONFIG_SOFTRESET); |
1071 | do { |
1072 | tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS); |
1073 | } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE)); |
1074 | |
1075 | tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE | |
1076 | OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP | |
1077 | OMAP2_MCSPI_SYSCONFIG_SMARTIDLE; |
1078 | mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp); |
1079 | omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp; |
1080 | |
1081 | tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
1082 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); |
1083 | omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp; |
1084 | |
1085 | omap2_mcspi_set_master_mode(master); |
1086 | omap2_mcspi_disable_clocks(mcspi); |
1087 | return 0; |
1088 | } |
1089 | |
1090 | static u8 __initdata spi1_rxdma_id [] = { |
1091 | OMAP24XX_DMA_SPI1_RX0, |
1092 | OMAP24XX_DMA_SPI1_RX1, |
1093 | OMAP24XX_DMA_SPI1_RX2, |
1094 | OMAP24XX_DMA_SPI1_RX3, |
1095 | }; |
1096 | |
1097 | static u8 __initdata spi1_txdma_id [] = { |
1098 | OMAP24XX_DMA_SPI1_TX0, |
1099 | OMAP24XX_DMA_SPI1_TX1, |
1100 | OMAP24XX_DMA_SPI1_TX2, |
1101 | OMAP24XX_DMA_SPI1_TX3, |
1102 | }; |
1103 | |
1104 | static u8 __initdata spi2_rxdma_id[] = { |
1105 | OMAP24XX_DMA_SPI2_RX0, |
1106 | OMAP24XX_DMA_SPI2_RX1, |
1107 | }; |
1108 | |
1109 | static u8 __initdata spi2_txdma_id[] = { |
1110 | OMAP24XX_DMA_SPI2_TX0, |
1111 | OMAP24XX_DMA_SPI2_TX1, |
1112 | }; |
1113 | |
1114 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ |
1115 | || defined(CONFIG_ARCH_OMAP4) |
1116 | static u8 __initdata spi3_rxdma_id[] = { |
1117 | OMAP24XX_DMA_SPI3_RX0, |
1118 | OMAP24XX_DMA_SPI3_RX1, |
1119 | }; |
1120 | |
1121 | static u8 __initdata spi3_txdma_id[] = { |
1122 | OMAP24XX_DMA_SPI3_TX0, |
1123 | OMAP24XX_DMA_SPI3_TX1, |
1124 | }; |
1125 | #endif |
1126 | |
1127 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
1128 | static u8 __initdata spi4_rxdma_id[] = { |
1129 | OMAP34XX_DMA_SPI4_RX0, |
1130 | }; |
1131 | |
1132 | static u8 __initdata spi4_txdma_id[] = { |
1133 | OMAP34XX_DMA_SPI4_TX0, |
1134 | }; |
1135 | #endif |
1136 | |
1137 | static int __init omap2_mcspi_probe(struct platform_device *pdev) |
1138 | { |
1139 | struct spi_master *master; |
1140 | struct omap2_mcspi *mcspi; |
1141 | struct resource *r; |
1142 | int status = 0, i; |
1143 | const u8 *rxdma_id, *txdma_id; |
1144 | unsigned num_chipselect; |
1145 | |
1146 | switch (pdev->id) { |
1147 | case 1: |
1148 | rxdma_id = spi1_rxdma_id; |
1149 | txdma_id = spi1_txdma_id; |
1150 | num_chipselect = 4; |
1151 | break; |
1152 | case 2: |
1153 | rxdma_id = spi2_rxdma_id; |
1154 | txdma_id = spi2_txdma_id; |
1155 | num_chipselect = 2; |
1156 | break; |
1157 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ |
1158 | || defined(CONFIG_ARCH_OMAP4) |
1159 | case 3: |
1160 | rxdma_id = spi3_rxdma_id; |
1161 | txdma_id = spi3_txdma_id; |
1162 | num_chipselect = 2; |
1163 | break; |
1164 | #endif |
1165 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
1166 | case 4: |
1167 | rxdma_id = spi4_rxdma_id; |
1168 | txdma_id = spi4_txdma_id; |
1169 | num_chipselect = 1; |
1170 | break; |
1171 | #endif |
1172 | default: |
1173 | return -EINVAL; |
1174 | } |
1175 | |
1176 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); |
1177 | if (master == NULL) { |
1178 | dev_dbg(&pdev->dev, "master allocation failed\n"); |
1179 | return -ENOMEM; |
1180 | } |
1181 | |
1182 | /* the spi->mode bits understood by this driver: */ |
1183 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1184 | |
1185 | if (pdev->id != -1) |
1186 | master->bus_num = pdev->id; |
1187 | |
1188 | master->setup = omap2_mcspi_setup; |
1189 | master->transfer = omap2_mcspi_transfer; |
1190 | master->cleanup = omap2_mcspi_cleanup; |
1191 | master->num_chipselect = num_chipselect; |
1192 | |
1193 | dev_set_drvdata(&pdev->dev, master); |
1194 | |
1195 | mcspi = spi_master_get_devdata(master); |
1196 | mcspi->master = master; |
1197 | |
1198 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1199 | if (r == NULL) { |
1200 | status = -ENODEV; |
1201 | goto err1; |
1202 | } |
1203 | if (!request_mem_region(r->start, (r->end - r->start) + 1, |
1204 | dev_name(&pdev->dev))) { |
1205 | status = -EBUSY; |
1206 | goto err1; |
1207 | } |
1208 | |
1209 | mcspi->phys = r->start; |
1210 | mcspi->base = ioremap(r->start, r->end - r->start + 1); |
1211 | if (!mcspi->base) { |
1212 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); |
1213 | status = -ENOMEM; |
1214 | goto err1aa; |
1215 | } |
1216 | |
1217 | INIT_WORK(&mcspi->work, omap2_mcspi_work); |
1218 | |
1219 | spin_lock_init(&mcspi->lock); |
1220 | INIT_LIST_HEAD(&mcspi->msg_queue); |
1221 | INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); |
1222 | |
1223 | mcspi->ick = clk_get(&pdev->dev, "ick"); |
1224 | if (IS_ERR(mcspi->ick)) { |
1225 | dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); |
1226 | status = PTR_ERR(mcspi->ick); |
1227 | goto err1a; |
1228 | } |
1229 | mcspi->fck = clk_get(&pdev->dev, "fck"); |
1230 | if (IS_ERR(mcspi->fck)) { |
1231 | dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); |
1232 | status = PTR_ERR(mcspi->fck); |
1233 | goto err2; |
1234 | } |
1235 | |
1236 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
1237 | sizeof(struct omap2_mcspi_dma), |
1238 | GFP_KERNEL); |
1239 | |
1240 | if (mcspi->dma_channels == NULL) |
1241 | goto err3; |
1242 | |
1243 | for (i = 0; i < num_chipselect; i++) { |
1244 | mcspi->dma_channels[i].dma_rx_channel = -1; |
1245 | mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i]; |
1246 | mcspi->dma_channels[i].dma_tx_channel = -1; |
1247 | mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i]; |
1248 | } |
1249 | |
1250 | if (omap2_mcspi_reset(mcspi) < 0) |
1251 | goto err4; |
1252 | |
1253 | status = spi_register_master(master); |
1254 | if (status < 0) |
1255 | goto err4; |
1256 | |
1257 | return status; |
1258 | |
1259 | err4: |
1260 | kfree(mcspi->dma_channels); |
1261 | err3: |
1262 | clk_put(mcspi->fck); |
1263 | err2: |
1264 | clk_put(mcspi->ick); |
1265 | err1a: |
1266 | iounmap(mcspi->base); |
1267 | err1aa: |
1268 | release_mem_region(r->start, (r->end - r->start) + 1); |
1269 | err1: |
1270 | spi_master_put(master); |
1271 | return status; |
1272 | } |
1273 | |
1274 | static int __exit omap2_mcspi_remove(struct platform_device *pdev) |
1275 | { |
1276 | struct spi_master *master; |
1277 | struct omap2_mcspi *mcspi; |
1278 | struct omap2_mcspi_dma *dma_channels; |
1279 | struct resource *r; |
1280 | void __iomem *base; |
1281 | |
1282 | master = dev_get_drvdata(&pdev->dev); |
1283 | mcspi = spi_master_get_devdata(master); |
1284 | dma_channels = mcspi->dma_channels; |
1285 | |
1286 | clk_put(mcspi->fck); |
1287 | clk_put(mcspi->ick); |
1288 | |
1289 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1290 | release_mem_region(r->start, (r->end - r->start) + 1); |
1291 | |
1292 | base = mcspi->base; |
1293 | spi_unregister_master(master); |
1294 | iounmap(base); |
1295 | kfree(dma_channels); |
1296 | |
1297 | return 0; |
1298 | } |
1299 | |
1300 | /* work with hotplug and coldplug */ |
1301 | MODULE_ALIAS("platform:omap2_mcspi"); |
1302 | |
1303 | #ifdef CONFIG_SUSPEND |
1304 | /* |
1305 | * When SPI wake up from off-mode, CS is in activate state. If it was in |
1306 | * unactive state when driver was suspend, then force it to unactive state at |
1307 | * wake up. |
1308 | */ |
1309 | static int omap2_mcspi_resume(struct device *dev) |
1310 | { |
1311 | struct spi_master *master = dev_get_drvdata(dev); |
1312 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
1313 | struct omap2_mcspi_cs *cs; |
1314 | |
1315 | omap2_mcspi_enable_clocks(mcspi); |
1316 | list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs, |
1317 | node) { |
1318 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
1319 | |
1320 | /* |
1321 | * We need to toggle CS state for OMAP take this |
1322 | * change in account. |
1323 | */ |
1324 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1); |
1325 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1326 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0); |
1327 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1328 | } |
1329 | } |
1330 | omap2_mcspi_disable_clocks(mcspi); |
1331 | return 0; |
1332 | } |
1333 | #else |
1334 | #define omap2_mcspi_resume NULL |
1335 | #endif |
1336 | |
1337 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { |
1338 | .resume = omap2_mcspi_resume, |
1339 | }; |
1340 | |
1341 | static struct platform_driver omap2_mcspi_driver = { |
1342 | .driver = { |
1343 | .name = "omap2_mcspi", |
1344 | .owner = THIS_MODULE, |
1345 | .pm = &omap2_mcspi_pm_ops |
1346 | }, |
1347 | .remove = __exit_p(omap2_mcspi_remove), |
1348 | }; |
1349 | |
1350 | |
1351 | static int __init omap2_mcspi_init(void) |
1352 | { |
1353 | omap2_mcspi_wq = create_singlethread_workqueue( |
1354 | omap2_mcspi_driver.driver.name); |
1355 | if (omap2_mcspi_wq == NULL) |
1356 | return -1; |
1357 | return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe); |
1358 | } |
1359 | subsys_initcall(omap2_mcspi_init); |
1360 | |
1361 | static void __exit omap2_mcspi_exit(void) |
1362 | { |
1363 | platform_driver_unregister(&omap2_mcspi_driver); |
1364 | |
1365 | destroy_workqueue(omap2_mcspi_wq); |
1366 | } |
1367 | module_exit(omap2_mcspi_exit); |
1368 | |
1369 | MODULE_LICENSE("GPL"); |
1370 |
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