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Source at commit 6c17a31f1fc515425221067cb3ece599c09dbc5d created 12 years 8 months ago. By Werner Almesberger, atusb, atben: moved from spi/ to ieee802154/; renamed atusb to spi_atusb | |
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1 | /* |
2 | * spi_txx9.c - TXx9 SPI controller driver. |
3 | * |
4 | * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c |
5 | * Copyright (C) 2000-2001 Toshiba Corporation |
6 | * |
7 | * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the |
8 | * terms of the GNU General Public License version 2. This program is |
9 | * licensed "as is" without any warranty of any kind, whether express |
10 | * or implied. |
11 | * |
12 | * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) |
13 | * |
14 | * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp) |
15 | */ |
16 | #include <linux/init.h> |
17 | #include <linux/delay.h> |
18 | #include <linux/errno.h> |
19 | #include <linux/interrupt.h> |
20 | #include <linux/platform_device.h> |
21 | #include <linux/sched.h> |
22 | #include <linux/spinlock.h> |
23 | #include <linux/workqueue.h> |
24 | #include <linux/spi/spi.h> |
25 | #include <linux/err.h> |
26 | #include <linux/clk.h> |
27 | #include <linux/io.h> |
28 | #include <asm/gpio.h> |
29 | |
30 | |
31 | #define SPI_FIFO_SIZE 4 |
32 | #define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */ |
33 | #define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */ |
34 | |
35 | #define TXx9_SPMCR 0x00 |
36 | #define TXx9_SPCR0 0x04 |
37 | #define TXx9_SPCR1 0x08 |
38 | #define TXx9_SPFS 0x0c |
39 | #define TXx9_SPSR 0x14 |
40 | #define TXx9_SPDR 0x18 |
41 | |
42 | /* SPMCR : SPI Master Control */ |
43 | #define TXx9_SPMCR_OPMODE 0xc0 |
44 | #define TXx9_SPMCR_CONFIG 0x40 |
45 | #define TXx9_SPMCR_ACTIVE 0x80 |
46 | #define TXx9_SPMCR_SPSTP 0x02 |
47 | #define TXx9_SPMCR_BCLR 0x01 |
48 | |
49 | /* SPCR0 : SPI Control 0 */ |
50 | #define TXx9_SPCR0_TXIFL_MASK 0xc000 |
51 | #define TXx9_SPCR0_RXIFL_MASK 0x3000 |
52 | #define TXx9_SPCR0_SIDIE 0x0800 |
53 | #define TXx9_SPCR0_SOEIE 0x0400 |
54 | #define TXx9_SPCR0_RBSIE 0x0200 |
55 | #define TXx9_SPCR0_TBSIE 0x0100 |
56 | #define TXx9_SPCR0_IFSPSE 0x0010 |
57 | #define TXx9_SPCR0_SBOS 0x0004 |
58 | #define TXx9_SPCR0_SPHA 0x0002 |
59 | #define TXx9_SPCR0_SPOL 0x0001 |
60 | |
61 | /* SPSR : SPI Status */ |
62 | #define TXx9_SPSR_TBSI 0x8000 |
63 | #define TXx9_SPSR_RBSI 0x4000 |
64 | #define TXx9_SPSR_TBS_MASK 0x3800 |
65 | #define TXx9_SPSR_RBS_MASK 0x0700 |
66 | #define TXx9_SPSR_SPOE 0x0080 |
67 | #define TXx9_SPSR_IFSD 0x0008 |
68 | #define TXx9_SPSR_SIDLE 0x0004 |
69 | #define TXx9_SPSR_STRDY 0x0002 |
70 | #define TXx9_SPSR_SRRDY 0x0001 |
71 | |
72 | |
73 | struct txx9spi { |
74 | struct workqueue_struct *workqueue; |
75 | struct work_struct work; |
76 | spinlock_t lock; /* protect 'queue' */ |
77 | struct list_head queue; |
78 | wait_queue_head_t waitq; |
79 | void __iomem *membase; |
80 | int baseclk; |
81 | struct clk *clk; |
82 | u32 max_speed_hz, min_speed_hz; |
83 | int last_chipselect; |
84 | int last_chipselect_val; |
85 | }; |
86 | |
87 | static u32 txx9spi_rd(struct txx9spi *c, int reg) |
88 | { |
89 | return __raw_readl(c->membase + reg); |
90 | } |
91 | static void txx9spi_wr(struct txx9spi *c, u32 val, int reg) |
92 | { |
93 | __raw_writel(val, c->membase + reg); |
94 | } |
95 | |
96 | static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c, |
97 | int on, unsigned int cs_delay) |
98 | { |
99 | int val = (spi->mode & SPI_CS_HIGH) ? on : !on; |
100 | if (on) { |
101 | /* deselect the chip with cs_change hint in last transfer */ |
102 | if (c->last_chipselect >= 0) |
103 | gpio_set_value(c->last_chipselect, |
104 | !c->last_chipselect_val); |
105 | c->last_chipselect = spi->chip_select; |
106 | c->last_chipselect_val = val; |
107 | } else { |
108 | c->last_chipselect = -1; |
109 | ndelay(cs_delay); /* CS Hold Time */ |
110 | } |
111 | gpio_set_value(spi->chip_select, val); |
112 | ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */ |
113 | } |
114 | |
115 | static int txx9spi_setup(struct spi_device *spi) |
116 | { |
117 | struct txx9spi *c = spi_master_get_devdata(spi->master); |
118 | u8 bits_per_word; |
119 | |
120 | if (!spi->max_speed_hz |
121 | || spi->max_speed_hz > c->max_speed_hz |
122 | || spi->max_speed_hz < c->min_speed_hz) |
123 | return -EINVAL; |
124 | |
125 | bits_per_word = spi->bits_per_word; |
126 | if (bits_per_word != 8 && bits_per_word != 16) |
127 | return -EINVAL; |
128 | |
129 | if (gpio_direction_output(spi->chip_select, |
130 | !(spi->mode & SPI_CS_HIGH))) { |
131 | dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n"); |
132 | return -EINVAL; |
133 | } |
134 | |
135 | /* deselect chip */ |
136 | spin_lock(&c->lock); |
137 | txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz); |
138 | spin_unlock(&c->lock); |
139 | |
140 | return 0; |
141 | } |
142 | |
143 | static irqreturn_t txx9spi_interrupt(int irq, void *dev_id) |
144 | { |
145 | struct txx9spi *c = dev_id; |
146 | |
147 | /* disable rx intr */ |
148 | txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE, |
149 | TXx9_SPCR0); |
150 | wake_up(&c->waitq); |
151 | return IRQ_HANDLED; |
152 | } |
153 | |
154 | static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m) |
155 | { |
156 | struct spi_device *spi = m->spi; |
157 | struct spi_transfer *t; |
158 | unsigned int cs_delay; |
159 | unsigned int cs_change = 1; |
160 | int status = 0; |
161 | u32 mcr; |
162 | u32 prev_speed_hz = 0; |
163 | u8 prev_bits_per_word = 0; |
164 | |
165 | /* CS setup/hold/recovery time in nsec */ |
166 | cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz; |
167 | |
168 | mcr = txx9spi_rd(c, TXx9_SPMCR); |
169 | if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) { |
170 | dev_err(&spi->dev, "Bad mode.\n"); |
171 | status = -EIO; |
172 | goto exit; |
173 | } |
174 | mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR); |
175 | |
176 | /* enter config mode */ |
177 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); |
178 | txx9spi_wr(c, TXx9_SPCR0_SBOS |
179 | | ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0) |
180 | | ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0) |
181 | | 0x08, |
182 | TXx9_SPCR0); |
183 | |
184 | list_for_each_entry (t, &m->transfers, transfer_list) { |
185 | const void *txbuf = t->tx_buf; |
186 | void *rxbuf = t->rx_buf; |
187 | u32 data; |
188 | unsigned int len = t->len; |
189 | unsigned int wsize; |
190 | u32 speed_hz = t->speed_hz ? : spi->max_speed_hz; |
191 | u8 bits_per_word = t->bits_per_word ? : spi->bits_per_word; |
192 | |
193 | bits_per_word = bits_per_word ? : 8; |
194 | wsize = bits_per_word >> 3; /* in bytes */ |
195 | |
196 | if (prev_speed_hz != speed_hz |
197 | || prev_bits_per_word != bits_per_word) { |
198 | int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1; |
199 | n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER); |
200 | /* enter config mode */ |
201 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, |
202 | TXx9_SPMCR); |
203 | txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1); |
204 | /* enter active mode */ |
205 | txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR); |
206 | |
207 | prev_speed_hz = speed_hz; |
208 | prev_bits_per_word = bits_per_word; |
209 | } |
210 | |
211 | if (cs_change) |
212 | txx9spi_cs_func(spi, c, 1, cs_delay); |
213 | cs_change = t->cs_change; |
214 | while (len) { |
215 | unsigned int count = SPI_FIFO_SIZE; |
216 | int i; |
217 | u32 cr0; |
218 | |
219 | if (len < count * wsize) |
220 | count = len / wsize; |
221 | /* now tx must be idle... */ |
222 | while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE)) |
223 | cpu_relax(); |
224 | cr0 = txx9spi_rd(c, TXx9_SPCR0); |
225 | cr0 &= ~TXx9_SPCR0_RXIFL_MASK; |
226 | cr0 |= (count - 1) << 12; |
227 | /* enable rx intr */ |
228 | cr0 |= TXx9_SPCR0_RBSIE; |
229 | txx9spi_wr(c, cr0, TXx9_SPCR0); |
230 | /* send */ |
231 | for (i = 0; i < count; i++) { |
232 | if (txbuf) { |
233 | data = (wsize == 1) |
234 | ? *(const u8 *)txbuf |
235 | : *(const u16 *)txbuf; |
236 | txx9spi_wr(c, data, TXx9_SPDR); |
237 | txbuf += wsize; |
238 | } else |
239 | txx9spi_wr(c, 0, TXx9_SPDR); |
240 | } |
241 | /* wait all rx data */ |
242 | wait_event(c->waitq, |
243 | txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI); |
244 | /* receive */ |
245 | for (i = 0; i < count; i++) { |
246 | data = txx9spi_rd(c, TXx9_SPDR); |
247 | if (rxbuf) { |
248 | if (wsize == 1) |
249 | *(u8 *)rxbuf = data; |
250 | else |
251 | *(u16 *)rxbuf = data; |
252 | rxbuf += wsize; |
253 | } |
254 | } |
255 | len -= count * wsize; |
256 | } |
257 | m->actual_length += t->len; |
258 | if (t->delay_usecs) |
259 | udelay(t->delay_usecs); |
260 | |
261 | if (!cs_change) |
262 | continue; |
263 | if (t->transfer_list.next == &m->transfers) |
264 | break; |
265 | /* sometimes a short mid-message deselect of the chip |
266 | * may be needed to terminate a mode or command |
267 | */ |
268 | txx9spi_cs_func(spi, c, 0, cs_delay); |
269 | } |
270 | |
271 | exit: |
272 | m->status = status; |
273 | m->complete(m->context); |
274 | |
275 | /* normally deactivate chipselect ... unless no error and |
276 | * cs_change has hinted that the next message will probably |
277 | * be for this chip too. |
278 | */ |
279 | if (!(status == 0 && cs_change)) |
280 | txx9spi_cs_func(spi, c, 0, cs_delay); |
281 | |
282 | /* enter config mode */ |
283 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); |
284 | } |
285 | |
286 | static void txx9spi_work(struct work_struct *work) |
287 | { |
288 | struct txx9spi *c = container_of(work, struct txx9spi, work); |
289 | unsigned long flags; |
290 | |
291 | spin_lock_irqsave(&c->lock, flags); |
292 | while (!list_empty(&c->queue)) { |
293 | struct spi_message *m; |
294 | |
295 | m = container_of(c->queue.next, struct spi_message, queue); |
296 | list_del_init(&m->queue); |
297 | spin_unlock_irqrestore(&c->lock, flags); |
298 | |
299 | txx9spi_work_one(c, m); |
300 | |
301 | spin_lock_irqsave(&c->lock, flags); |
302 | } |
303 | spin_unlock_irqrestore(&c->lock, flags); |
304 | } |
305 | |
306 | static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m) |
307 | { |
308 | struct spi_master *master = spi->master; |
309 | struct txx9spi *c = spi_master_get_devdata(master); |
310 | struct spi_transfer *t; |
311 | unsigned long flags; |
312 | |
313 | m->actual_length = 0; |
314 | |
315 | /* check each transfer's parameters */ |
316 | list_for_each_entry (t, &m->transfers, transfer_list) { |
317 | u32 speed_hz = t->speed_hz ? : spi->max_speed_hz; |
318 | u8 bits_per_word = t->bits_per_word ? : spi->bits_per_word; |
319 | |
320 | bits_per_word = bits_per_word ? : 8; |
321 | if (!t->tx_buf && !t->rx_buf && t->len) |
322 | return -EINVAL; |
323 | if (bits_per_word != 8 && bits_per_word != 16) |
324 | return -EINVAL; |
325 | if (t->len & ((bits_per_word >> 3) - 1)) |
326 | return -EINVAL; |
327 | if (speed_hz < c->min_speed_hz || speed_hz > c->max_speed_hz) |
328 | return -EINVAL; |
329 | } |
330 | |
331 | spin_lock_irqsave(&c->lock, flags); |
332 | list_add_tail(&m->queue, &c->queue); |
333 | queue_work(c->workqueue, &c->work); |
334 | spin_unlock_irqrestore(&c->lock, flags); |
335 | |
336 | return 0; |
337 | } |
338 | |
339 | static int __init txx9spi_probe(struct platform_device *dev) |
340 | { |
341 | struct spi_master *master; |
342 | struct txx9spi *c; |
343 | struct resource *res; |
344 | int ret = -ENODEV; |
345 | u32 mcr; |
346 | int irq; |
347 | |
348 | master = spi_alloc_master(&dev->dev, sizeof(*c)); |
349 | if (!master) |
350 | return ret; |
351 | c = spi_master_get_devdata(master); |
352 | platform_set_drvdata(dev, master); |
353 | |
354 | INIT_WORK(&c->work, txx9spi_work); |
355 | spin_lock_init(&c->lock); |
356 | INIT_LIST_HEAD(&c->queue); |
357 | init_waitqueue_head(&c->waitq); |
358 | |
359 | c->clk = clk_get(&dev->dev, "spi-baseclk"); |
360 | if (IS_ERR(c->clk)) { |
361 | ret = PTR_ERR(c->clk); |
362 | c->clk = NULL; |
363 | goto exit; |
364 | } |
365 | ret = clk_enable(c->clk); |
366 | if (ret) { |
367 | clk_put(c->clk); |
368 | c->clk = NULL; |
369 | goto exit; |
370 | } |
371 | c->baseclk = clk_get_rate(c->clk); |
372 | c->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1); |
373 | c->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1); |
374 | |
375 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
376 | if (!res) |
377 | goto exit_busy; |
378 | if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res), |
379 | "spi_txx9")) |
380 | goto exit_busy; |
381 | c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res)); |
382 | if (!c->membase) |
383 | goto exit_busy; |
384 | |
385 | /* enter config mode */ |
386 | mcr = txx9spi_rd(c, TXx9_SPMCR); |
387 | mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR); |
388 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); |
389 | |
390 | irq = platform_get_irq(dev, 0); |
391 | if (irq < 0) |
392 | goto exit_busy; |
393 | ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0, |
394 | "spi_txx9", c); |
395 | if (ret) |
396 | goto exit; |
397 | |
398 | c->workqueue = create_singlethread_workqueue( |
399 | dev_name(master->dev.parent)); |
400 | if (!c->workqueue) |
401 | goto exit_busy; |
402 | c->last_chipselect = -1; |
403 | |
404 | dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n", |
405 | (unsigned long long)res->start, irq, |
406 | (c->baseclk + 500000) / 1000000); |
407 | |
408 | /* the spi->mode bits understood by this driver: */ |
409 | master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; |
410 | |
411 | master->bus_num = dev->id; |
412 | master->setup = txx9spi_setup; |
413 | master->transfer = txx9spi_transfer; |
414 | master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */ |
415 | |
416 | ret = spi_register_master(master); |
417 | if (ret) |
418 | goto exit; |
419 | return 0; |
420 | exit_busy: |
421 | ret = -EBUSY; |
422 | exit: |
423 | if (c->workqueue) |
424 | destroy_workqueue(c->workqueue); |
425 | if (c->clk) { |
426 | clk_disable(c->clk); |
427 | clk_put(c->clk); |
428 | } |
429 | platform_set_drvdata(dev, NULL); |
430 | spi_master_put(master); |
431 | return ret; |
432 | } |
433 | |
434 | static int __exit txx9spi_remove(struct platform_device *dev) |
435 | { |
436 | struct spi_master *master = spi_master_get(platform_get_drvdata(dev)); |
437 | struct txx9spi *c = spi_master_get_devdata(master); |
438 | |
439 | spi_unregister_master(master); |
440 | platform_set_drvdata(dev, NULL); |
441 | destroy_workqueue(c->workqueue); |
442 | clk_disable(c->clk); |
443 | clk_put(c->clk); |
444 | spi_master_put(master); |
445 | return 0; |
446 | } |
447 | |
448 | /* work with hotplug and coldplug */ |
449 | MODULE_ALIAS("platform:spi_txx9"); |
450 | |
451 | static struct platform_driver txx9spi_driver = { |
452 | .remove = __exit_p(txx9spi_remove), |
453 | .driver = { |
454 | .name = "spi_txx9", |
455 | .owner = THIS_MODULE, |
456 | }, |
457 | }; |
458 | |
459 | static int __init txx9spi_init(void) |
460 | { |
461 | return platform_driver_probe(&txx9spi_driver, txx9spi_probe); |
462 | } |
463 | subsys_initcall(txx9spi_init); |
464 | |
465 | static void __exit txx9spi_exit(void) |
466 | { |
467 | platform_driver_unregister(&txx9spi_driver); |
468 | } |
469 | module_exit(txx9spi_exit); |
470 | |
471 | MODULE_DESCRIPTION("TXx9 SPI Driver"); |
472 | MODULE_LICENSE("GPL"); |
473 |
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